WO2022155914A1 - 显示面板、显示装置及控制方法 - Google Patents

显示面板、显示装置及控制方法 Download PDF

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Publication number
WO2022155914A1
WO2022155914A1 PCT/CN2021/073374 CN2021073374W WO2022155914A1 WO 2022155914 A1 WO2022155914 A1 WO 2022155914A1 CN 2021073374 W CN2021073374 W CN 2021073374W WO 2022155914 A1 WO2022155914 A1 WO 2022155914A1
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WO
WIPO (PCT)
Prior art keywords
light
sub
electrically connected
pixels
data line
Prior art date
Application number
PCT/CN2021/073374
Other languages
English (en)
French (fr)
Inventor
黄耀
邱远游
王倩
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/627,794 priority Critical patent/US11793057B2/en
Priority to CN202180000060.1A priority patent/CN115669279A/zh
Priority to PCT/CN2021/073374 priority patent/WO2022155914A1/zh
Publication of WO2022155914A1 publication Critical patent/WO2022155914A1/zh
Priority to US18/240,877 priority patent/US20240008350A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a display device, and a control method.
  • the under-screen camera is to set the camera of the electronic device under the display screen to take pictures, and the under-screen camera can display the corresponding area on the display screen, so as to achieve a full-screen display.
  • a display panel which has a display area, the display area includes a light-transmitting area, at least one first area and a second area, and the at least one first area is located at least on one side of the light-transmitting area.
  • the display panel includes a plurality of sub-pixels arranged in the at least one first area and the second area, a plurality of second light-emitting devices arranged in the light-transmitting area, a plurality of data lines and a first transistor .
  • the plurality of sub-pixels are arranged in multiple rows and columns; the plurality of sub-pixels include a plurality of effective sub-pixels and a plurality of dummy sub-pixels, and the plurality of dummy sub-pixels are arranged in the at least one first area; each Each sub-pixel includes a pixel driving circuit, and each effective sub-pixel further includes a first light-emitting device electrically connected to the pixel driving circuit; the plurality of second light-emitting devices are arranged in a plurality of columns of second light-emitting devices, and each column has a second light-emitting device. The light emitting devices are aligned with a column of sub-pixels.
  • a pixel driving circuit in a column of sub-pixels is electrically connected to a data line; the plurality of data lines include a first data line and a second data line; the first data line is connected to a column of sub-pixels including dummy sub-pixels.
  • the pixel driving circuit is electrically connected; the second data line is electrically connected with a pixel driving circuit in a column of sub-pixels located in the same column as a column of second light-emitting devices; a second light-emitting device in the column of second light-emitting devices is connected to the
  • the pixel driving circuit in one dummy sub-pixel connected to the first data line is electrically connected.
  • the first data line and the second data line are electrically connected through the first transistor.
  • the sub-pixels located in the first region are all dummy sub-pixels.
  • the effective sub-pixels located in the first region among the plurality of effective sub-pixels are uniformly arranged.
  • the display panel further includes: a first connection line and/or a second connection line.
  • the first connecting line is arranged on the side of the first area away from the signal input end of the first data line; one end of the first connecting line is electrically connected to the first electrode of the first transistor, and the first The other end of the connection line is electrically connected to the first data line; the second connection line is arranged on the side of the first area away from the signal input end of the first data line; one end of the second connection line is connected to the first data line.
  • the second electrode of a transistor is electrically connected, and the other end of the second connection line is electrically connected to the second data line.
  • the display panel further includes at least one second transistor; the at least one second transistor is configured to connect the first data lines as a whole when turned on; and to connect the first data line when turned off
  • the part of the data line located in the first area is disconnected from the part located in the second area, and is electrically connected to the second data line.
  • the light-transmitting area is located in the middle of the display area;
  • the first data line includes a first part, and a second part and a third part located on both sides of the first part, the first part is located in the first area, the second part and the third part are located in the second area; the second part is closer to the signal input end of the first data line than the third part;
  • the The at least one second transistor includes one second transistor; the first part and the second part are electrically connected through the second transistor; or the at least one second transistor includes two second transistors, the first part and the second part are electrically connected through the second transistor; One part and the second part are electrically connected through one of the second transistors, and the first part and the third part are electrically connected through the other second transistor.
  • the display panel further includes a capacitor; a first storage electrode of the capacitor is electrically connected to a first electrode of the first transistor, and a second storage electrode of the capacitor is electrically connected to a second electrode of the first transistor pole electrical connection.
  • the spacing between any two adjacent second light emitting devices in each row of second light emitting devices is equal; in a row of subpixels including dummy subpixels and effective subpixels, between any two adjacent effective subpixels The spacing is equal to the spacing between the two adjacent second light emitting devices.
  • three of the virtual sub-pixels are disposed between any two adjacent valid sub-pixels.
  • the at least one first region includes a first region located on one side of the light-transmitting region along a direction perpendicular to the data line.
  • the at least one first region includes two first regions, and the two first regions are respectively located on two sides of the light-transmitting region along a direction perpendicular to the data lines.
  • the at least one first region includes two first regions, one first region is located on one side of the light-transmitting region along a direction perpendicular to the data line, and the other first region is located on the light-transmitting region One side of the area in the direction of the data line.
  • the display panel further includes a plurality of gate lines and a plurality of scan signal connection lines. At least effective sub-pixels in a row of pixels are electrically connected to a gate line; one end of the scan signal connection line is electrically connected to a gate line electrically connected to an effective sub-pixel located in the same row with a second light-emitting device, the scan signal connection line The other end is electrically connected to the pixel data driving circuit of the dummy sub-pixel electrically connected to the second light-emitting device, and the pixel data driving circuit of the dummy sub-pixel is electrically connected to the gate line of the valid sub-pixel in the same row with the dummy sub-pixel insulation.
  • the first light emitting device and the second light emitting device are both OLEDs.
  • a display device comprising the display panel of any of the above embodiments and an image sensor located in the light-transmitting area.
  • a method for controlling a display panel comprising: inputting gate scanning signals to sub-pixels in multiple rows row by row; When a gate scan signal is input, a control signal is also input to the first transistor to turn on the first transistor; a data signal is input to each row of sub-pixels through the plurality of data lines; when the first transistor is turned on, The second data signal from the signal input terminal of the second data line is transmitted to the pixel driving circuit electrically connected to the second light emitting device through the first data line.
  • FIG. 1 is a schematic diagram of a display device according to some embodiments.
  • 2A is a schematic plan view of a display panel according to some embodiments.
  • 2B is another schematic plan view of a display panel according to some embodiments.
  • 3A is a schematic diagram of a display panel according to some embodiments.
  • 3B is another schematic diagram of a display panel according to some embodiments.
  • 4A is yet another schematic diagram of a display panel according to some embodiments.
  • 4B is yet another schematic diagram of a display panel according to some embodiments.
  • 4C is yet another schematic diagram of a display panel according to some embodiments.
  • 5A is a signal timing diagram of a display panel according to some embodiments.
  • 5B is another signal timing diagram of a display panel according to some embodiments.
  • 6A is yet another signal timing diagram of a display panel according to some embodiments.
  • 6B is yet another signal timing diagram of a display panel according to some embodiments.
  • FIG. 7 is a simulation waveform diagram of a second data signal according to some embodiments.
  • FIG. 8 is yet another schematic diagram of a display panel according to some embodiments.
  • FIG. 9 is yet another schematic diagram of a display panel according to some embodiments.
  • 10A is an equivalent circuit diagram of a pixel driving circuit according to some embodiments.
  • 10B is an equivalent circuit diagram of another pixel driving circuit according to some embodiments.
  • Figure 11 is a cross-sectional view along the direction B-B' in Figure 8, according to some embodiments.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • the expression “connected” and its derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact.
  • the term “connected” may also mean that two or more components are not in direct contact with each other, but yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by this context.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C”, and both include the following combinations of A, B, and C: A only, B only, C only, A and B , A and C, B and C, and A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if a [statement or event] is detected” are optionally interpreted to mean “in determining" or “in response to determining" or “on the detection of [the stated condition or event]” or “in response to the detection of the [ stated condition or event]”.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity.
  • Exemplary embodiments of the present disclosure should not be construed as limited to the shapes of the regions illustrated herein, but rather include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • Some embodiments of the present disclosure provide a display device, which can be used as a mobile phone, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, etc.
  • the embodiments of the present disclosure do not make special use of the display device limit.
  • the display device includes a display panel 100 , a frame 200 , a cover 300 , a circuit board 400 , and other electronic accessories including an image sensor 500 and the like.
  • the longitudinal section of the frame 200 is U-shaped, and the display panel 100 , the circuit board 400 , the image sensor 500 and the like are arranged in the cavity enclosed by the frame 200 and the cover plate 300 .
  • the circuit board 400 is disposed on the side of the display panel 100 away from the cover plate 300 .
  • image sensor 500 is a camera.
  • the camera is disposed on the side of the display panel 100 away from the cover plate 300 .
  • the circuit board 400 is configured to provide the display panel 100 with signals required for display.
  • the circuit board 400 is a printed circuit board assembly (Printed Circuit Board Assembly, PCBA)
  • the PCBA includes a printed circuit board (Printed Circuit Board, PCB) and a timing controller (Timing Controller, TCON) disposed on the PCB, power management Integrated circuits (Power Management IC, PMIC) and other ICs or circuits, etc.
  • Some embodiments of the present disclosure provide a display panel 100 , as shown in FIGS. 2A and 2B , the display panel has a display area 1 , and the display area 1 includes a light-transmitting area 11 , at least one first area 12 and a second area 13 .
  • the first area 12 is disposed on one side of the light-transmitting area 11 .
  • the first region 12 is disposed around the light-transmitting region 11 .
  • the light-transmitting area 11 is an area corresponding to the installation position of the image sensor in a direction perpendicular to the thickness of the display device. On the basis of realizing the image captured by the camera, the light-transmitting area 11 can also display an image, so that the display panel 100 can realize a full-screen display.
  • the shape of the light-transmitting area 11 is a circle.
  • the shape of the light-transmitting area 11 is a rectangle.
  • the shape of the first region 12 is a rectangle.
  • the shapes of the light-transmitting area 11 and the first area 12 in the embodiment of the present disclosure are not limited, and can be adjusted reasonably according to the actual situation.
  • the display panel 100 includes a plurality of sub-pixels disposed in the first area 12 and the second area 13, and the plurality of sub-pixels are arranged in multiple rows and columns.
  • a plurality of sub-pixels are arranged in 8 rows and 24 columns, which are from the 1st column to the 24th column along the X direction, and the 1st row to the 8th row along the Y direction.
  • the number of sub-pixels in each column of sub-pixels is equal, and the number of sub-pixels in each row of sub-pixels is also equal.
  • the number of sub-pixels in the display panel 100 the number of rows and columns in which the plurality of sub-pixels are arranged in rows, the number of sub-pixels in each row of sub-pixels, and the number of sub-pixels in each column of sub-pixels
  • the plurality of sub-pixels shown in FIG. 3A and FIG. 3B are part of the sub-pixels in the display panel 100, which is only an arrangement in which the plurality of sub-pixels are arranged in multiple rows and columns.
  • the embodiment of the present disclosure does not limit the number of sub-pixels and the specific manner in which the plurality of sub-pixels are arranged in multiple rows and multiple columns, as long as the multiple sub-pixels can be arranged in multiple rows and multiple columns.
  • the multiple sub-pixels include multiple effective sub-pixels P and multiple virtual sub-pixels D; the multiple effective sub-pixels P are arranged in the first area 12 and the second area 12, and multiple virtual sub-pixels The pixel D is arranged in the first area 12 .
  • Each effective sub-pixel P includes a pixel driving circuit and a first light emitting device electrically connected to the pixel driving circuit, and each dummy sub-pixel D only includes a pixel driving circuit.
  • the circuit structures of the pixel driving circuit in each effective sub-pixel P and the pixel driving circuit in each dummy sub-pixel D are the same.
  • the display panel further includes a plurality of second light-emitting devices A disposed in the light-transmitting area 11 , and the plurality of second light-emitting devices A are arranged in a plurality of columns of second light-emitting devices A, and each column of second light-emitting devices A emits light.
  • Device A is aligned with a column of subpixels.
  • a plurality of sub-pixels electrically connected to one signal line is defined as a column of sub-pixels, and here, the signal line is the data line in the present disclosure.
  • a plurality of second light-emitting devices A arranged in the same direction as at least some of the sub-pixels in a column of sub-pixels is defined as a column of second light-emitting devices A.
  • a plurality of sub-pixels arranged along the extending direction of another signal line is defined as a row of sub-pixels, and here, the other signal line is a gate line hereinafter.
  • a plurality of second light emitting devices A arranged in the same direction as at least some of the subpixels in a row of subpixels is defined as a row of second light emitting devices A.
  • the plurality of second light emitting devices A are arranged in 4 rows and 3 columns as shown in FIGS. 2A and 2B , the first to third columns along the X direction, and the first row to the fourth along the Y direction.
  • the number of second light emitting devices A in each column of second light emitting devices A is equal, and the number of second light emitting devices A in each row of second light emitting devices A is also equal.
  • the number of the second light-emitting devices A in the light-transmitting area 11 , the number of rows and columns of the plurality of second light-emitting devices A arranged in rows, and the number of second light-emitting devices A in each row of the second light-emitting devices A The number of devices A and the number of second light-emitting devices A in each column of second light-emitting devices A are related to the size and resolution of the light-transmitting region 11, and the plurality of second light-emitting devices A shown in FIG. 3A and FIG. 3B
  • the arrangement manner of the second light emitting devices A is only an illustration, and the embodiment of the present disclosure does not limit the number of the second light emitting devices A and the manner in which the plurality of second light emitting devices A are arranged in multiple columns.
  • the second light-emitting devices A in the first column in the light-transmitting area 11 are arranged in a column with the sub-pixels in the 13th column in the display area 1 .
  • the second light-emitting device A in the second column and the sub-pixels in the 15th column in the light-transmitting area 11 are arranged in a column.
  • the plurality of first light emitting devices includes a plurality of first light emitting devices configured to emit red light, a plurality of first light emitting devices configured to emit green light, and a plurality of first light emitting devices emitting blue light.
  • the plurality of second light emitting devices A include a plurality of second light emitting devices A configured to emit red light, a plurality of second light emitting devices A configured to emit green light, and a plurality of second light emitting devices A configured to emit blue light Light-emitting device A.
  • the plurality of first light emitting devices may further include first light emitting devices that emit white light.
  • the plurality of second light emitting devices A may also include second light emitting devices A that emit white light.
  • the first light-emitting device is an organic light-emitting diode (Organic Light-Emitting Diode, OLED).
  • OLED Organic Light-Emitting Diode
  • the second light emitting device A is an OLED.
  • the display panel 100 further includes a plurality of data lines 14 , and the pixel driving circuit in a column of sub-pixels is electrically connected to one data line 14 .
  • the plurality of data lines 14 include a first data line 141 and a second data line 142 .
  • the first data lines 141 are a plurality of first data lines 141
  • the second data lines 142 are a plurality of second data lines 142 .
  • a plurality of data lines 14 are arranged on the same layer.
  • the plurality of data lines 14 are at least partially disposed in the same layer.
  • a plurality of data lines 14 disposed on the same layer are formed synchronously through a patterning process.
  • FIG. 3A and FIG. 3B only show part of the data lines. In essence, each column of sub-pixels is electrically connected to one data line.
  • the first data line 141 is electrically connected to a pixel driving circuit in a column of sub-pixels including the dummy sub-pixel D.
  • the sub-pixels in the first column include dummy sub-pixels D
  • the first data line 141 - 1 is electrically connected to the pixel driving circuit in the sub-pixels in the first column.
  • the sub-pixels in the second column include dummy sub-pixels D and effective sub-pixels P
  • the first data line 141-2 is electrically connected to the pixel driving circuit in the sub-pixels in the second column. .
  • the second data line 142 is electrically connected to a pixel driving circuit in a column of sub-pixels located in the same column as a column of second light-emitting devices A; a second light-emitting device A in the column of second light-emitting devices A is connected to the first data line
  • the pixel driving circuit in one of the dummy sub-pixels D is electrically connected.
  • the second light-emitting device A in the first column in the light-transmitting area 11 is located in the same column as the sub-pixels in the thirteenth column, and the second data line 142 - 1 is located in the sub-pixels in the thirteenth column.
  • the pixel drive circuit is electrically connected.
  • FIG. 3A the second light-emitting device A in the first column in the light-transmitting area 11 is located in the same column as the sub-pixels in the thirteenth column, and the second data line 142 - 1 is located in the sub-pixels in the thirteenth column.
  • the pixel drive circuit is
  • the second light emitting device A in the second column and the sub-pixels in the 15th column in the light-transmitting area 11 are located in the same column, and the second data line 142 - 2 and the sub-pixels in the 15th column are located in the same column.
  • the pixel drive circuit in the circuit is electrically connected.
  • Each second data line 142 has a section of a first winding portion, and the first winding portion is routed around the light-transmitting area 11, so that the second data line 142 does not pass through the light-transmitting area 11, so as to avoid the second data line The influence of 142 on the light transmittance of the light-transmitting area 11 .
  • the plurality of data lines 14 further includes a third data line 143 .
  • the third data lines 143 are a plurality of third data lines 143 .
  • the third data line 143 is only electrically connected to the pixel driving circuit in the sub-pixels that are located in different columns from the second light-emitting devices A of any column, and each column is an effective sub-pixel P. That is, the third data line 143 is only electrically connected to the pixel driving circuit of a column of effective sub-pixels P located in a different column from the second light emitting device A of any column in the second region 13 .
  • the effective sub-pixels P in the 24th column are located in different columns from the second light-emitting device A in any column, and the plurality of effective sub-pixels P in the 24th column are all located in the second region 13, and the third The data line 143-1 is electrically connected to the pixel driving circuit of the effective sub-pixel P located in the 24th column.
  • the effective sub-pixels P in the 22nd column and the second light-emitting devices A in any column are located in different columns, and the plurality of effective sub-pixels P in the 22nd column are all located in the second region 13, and the The three data lines 143-2 are electrically connected to the pixel driving circuits of the effective sub-pixels P located in the 22nd column.
  • the third data line 143-2 has a second winding portion, and the second winding portion is arranged around the light-transmitting area 11, so that the third data line 143-2 does not pass through the light-transmitting area 11, so as to avoid the third data line 143-2.
  • the influence of the data line 143 - 1 on the light transmittance of the light transmitting area 11 that is to say, if the effective sub-pixel P electrically connected to the third data line 143 is located on one side of the light-transmitting area along the direction of the data line 14, the third data line needs to be provided with a second winding portion.
  • the second light emitting device A located in the first column and the first row in the light-transmitting region 11 is electrically connected to the pixel driving circuit in the dummy sub-pixel D located in the first column and the third row.
  • a second light-emitting device A is connected to a pixel driving circuit in a dummy sub-pixel D through an auxiliary connection line 15 .
  • FIGS. 3A and 3B are only for illustration. Although only part of the second light-emitting device A and the pixel driving circuit in the dummy sub-pixel D are connected through the auxiliary connecting line 15 in FIGS. 3A and 3B , they do not represent the light-transmitting area 11 Only part of the second light emitting device A is electrically connected to the pixel driving circuit in the dummy sub-pixel D. In essence, each second light-emitting device A in the light-transmitting area 11 is electrically connected to the pixel driving circuit in the corresponding dummy sub-pixel D.
  • the material of the auxiliary connection line 15 is indium tin oxide (Indium tin oxide, ITO).
  • ITO Indium tin oxide
  • ITO is transparent when it is in the form of a film, therefore, the auxiliary connecting line made of ITO is in a transparent state, so that the auxiliary connecting line has little influence on the light transmittance of the light-transmitting area 11 .
  • a plurality of auxiliary connecting lines 15 are arranged on the same layer.
  • the plurality of auxiliary connection lines 15 and the plurality of data lines 14 are at least partially disposed in the same layer.
  • a plurality of auxiliary connecting lines 15 arranged on the same layer are formed simultaneously through a patterning process.
  • the pixel driving circuit 30 includes a driving transistor Td, a third transistor T3 and a first storage capacitor Cst.
  • the width to length ratio of the channel of the driving transistor Td is larger than the width to length ratio of the channels of other switching transistors (eg, the third transistor T3). That is, the circuit structure of the pixel driving circuit 30 is a 2T1C circuit structure.
  • the gate of the third transistor T3 is electrically connected to the scanning signal line GL, and the first electrode of the third transistor T3 is electrically connected to the data line DL (ie, the data line 14 in the display panel 100 ).
  • the second pole of the three transistors T3 is electrically connected to the gate of the driving transistor Td.
  • the first electrode of the driving transistor Td is electrically connected to the first power supply line VDD, and the second electrode of the driving transistor Td is electrically connected to the anode of the light emitting device L (ie, the first light emitting device or the second light emitting device A of the display panel).
  • the cathode of the light emitting device L is electrically connected to the second power supply line VSS.
  • first storage capacitor Cst is electrically connected to the gate of the driving transistor Td, and the other end of the first storage capacitor Cst is electrically connected to the second electrode of the driving transistor Td.
  • first power line VDD is configured to provide a high voltage signal
  • second power line VSS is configured to provide a low voltage signal.
  • the pixel driving circuit 30 includes a driving transistor Td, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9 , and the first storage capacitor Cst. That is, the circuit structure of the pixel driving circuit is a 7T1C circuit structure.
  • the gate of the eighth transistor T8 is electrically connected to the scan signal line GL, and the first electrode of the eighth transistor T8 is electrically connected to the data signal line DL (ie, the data line 14 in the above-mentioned display panel).
  • the second electrode of the eight transistor T8 is electrically connected to the first electrode of the driving transistor Td.
  • the gate of the ninth transistor T9 is electrically connected to the scan signal line GL, and the first and second electrodes of the ninth transistor T9 are electrically connected to the second and gate of the driving transistor Td, respectively.
  • the gate of the fourth transistor T4 is electrically connected to the enable signal line EM, the first pole of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second pole of the fourth transistor T4 is electrically connected to the first pole of the driving transistor Td. connect.
  • the gate of the fifth transistor T5 is electrically connected to the enable signal line EM, the first electrode of the fifth transistor T5 is electrically connected to the second electrode of the driving transistor Td, and the second electrode of the fifth transistor T5 is electrically connected to the anode of the light emitting device L. connect.
  • the gate of the sixth transistor T6 is electrically connected to the reset signal line RST(N), the first pole of the sixth transistor T6 is electrically connected to the initialization signal line VIN, and the second pole of the sixth transistor T6 is electrically connected to the gate of the driving transistor Td. connect.
  • the gate of the seventh transistor T7 is electrically connected to the reset signal line RST(N+1) connected to the sixth transistor T6 in the next row of pixel driving circuits 30, and the first pole of the seventh transistor T7 is electrically connected to the initialization signal line VIN,
  • the second electrode of the seventh transistor T7 is electrically connected to the anode of the light emitting device L (ie, the first light emitting device or the second light emitting device A of the above-mentioned display panel).
  • One end of the first storage capacitor Cst is electrically connected to the gate of the driving transistor Td, and the other end of the first storage capacitor Cst is electrically connected to the first power supply line VDD.
  • the cathode of the light emitting device L is electrically connected to the second power supply line VSS.
  • the first power line VDD is configured to provide a high voltage signal
  • the second power line VSS is configured to provide a low voltage signal.
  • the circuit structure of the pixel driving circuit 30 is not limited to the above two structures, and may also be other types of circuit structures, which will not be listed one by one here. However, it should be understood that no matter what kind of circuit structure the pixel driving circuit 30 is, it at least includes a driving transistor, a transistor that functions as a switch, and a first storage capacitor.
  • the first pole is one of the source and drain of the transistor
  • the second pole is the other of the source and the drain of the transistor. Since the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be indistinguishable in structure. That is, the first pole and the second pole of the transistor in the embodiments of the present disclosure may be indistinguishable in structure.
  • the second electrode is referred to as the drain electrode
  • the first electrode is referred to as the source electrode.
  • the first electrode is referred to as the drain electrode
  • the second electrode is referred to as the source electrode.
  • transistors can be classified into enhancement-mode transistors and depletion-mode transistors according to different conduction modes of transistors.
  • Each transistor in the embodiment of the present disclosure may be an enhancement mode transistor or a depletion mode transistor, which is not limited thereto.
  • the pixel driving circuits 30 in each sub-pixel are the same.
  • the pixel driving circuits 30 in the plurality of sub-pixels are formed synchronously through a patterning process.
  • the display panel 100 also includes a plurality of first transistors. Referring to FIGS. 3A, 3B, and 4A, a first data line 141 and a second data line 142 are connected through a first transistor T1, and the first transistor T1 is configured to enable the first data line 141 when turned on It is connected with the second data line 142 as a whole; when it is turned off, the first data line 141 and the second data line 142 are not connected.
  • the plurality of first transistors T1 are simultaneously formed through a patterning process.
  • the gate of the first transistor T1 is connected to the first control terminal through the first control line 16, and the first control signal from the first control terminal is transmitted to the first transistor T1 through the first control line 16 to control the first control terminal.
  • a transistor T1 is turned on or off.
  • the first transistor T1 is an N-type transistor, and in response to the first control signal from the first control terminal being a high level signal, the first transistor T1 is turned on.
  • the first transistor T1 is a P-type transistor, and in response to the first control signal from the first control terminal being a low level signal, the first transistor T1 is turned off.
  • the first data line 141 and the second data line 142 are connected as one, and the second data signal from the signal input terminal of the second data line 142 passes through the second data line 142 connected as one.
  • the data lines 142 and the first data lines 141 are transmitted to the pixel driving circuit electrically connected to the second light-emitting device A to control the second light-emitting device A to emit light, so that the light-transmitting area 11 of the display panel displays an image.
  • the first signal line 141 may not transmit the first data signal to the pixel driving circuit in the dummy sub-pixel D electrically connected to the second light-emitting device A, so as to prevent the A data signal and a second data signal interfere with each other.
  • the signal input terminal of the first data line 141 may not output the first data signal, or not output the data signal that enables the second light emitting device A to emit light, that is, the processor
  • the signal input terminal of the first signal line 141 may be controlled to output a virtual first data signal; The first data signal at the signal input terminal is transmitted to the pixel driving circuit electrically connected to the second light-emitting device A.
  • the first transistor T1 When the first transistor T1 is turned off, the first data line 141 and the second data line 142 are not connected, and the first data signal from the signal input terminal of the first data line 141 is transmitted to the pixel electrically connected to the first data line 141 In the data circuit, a column of valid sub-pixels P electrically connected to the first data line 141 can be displayed normally.
  • the embodiment of the present disclosure can make the light-transmitting area 11 located at the top of the display area 1. Any position in the area 1, and does not affect the normal display of the second area 13.
  • the sub-pixels in each row of the display panel 100 are equally spaced, and the sub-pixels in each column are equally spaced, so that the display panel 100 has a good display effect.
  • the spacing between the sub-pixels in the second row and the sub-pixels in the third row, the spacing between the sixth row and the seventh row, and the spacing between the 23rd column and the 24th column in FIGS. 3A and 3B are only for illustration. , in order to more clearly illustrate the connection between the first data line 141 and the second data line 142 and the wiring mode of each data line, it does not represent the actual spacing between sub-pixels in the display panel.
  • the first transistor T1 is a thin film transistor (Thin Film Transistor, TFT for short).
  • the display panel 100 includes a substrate 101 on which a pixel driving circuit in each sub-pixel is disposed.
  • the substrate 101 is a glass substrate.
  • the driving transistor Td in each pixel driving circuit includes an active layer, a source electrode, a drain electrode, a gate electrode and a gate insulating layer, and the source electrode and the drain electrode are respectively in contact with the active layer.
  • the material of the active layer 2113 includes amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p One of -Si), hexathiophene, polythiophene, etc.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p One of -Si hexathiophene
  • polythiophene etc.
  • the first light emitting device 210 in each effective sub-pixel P includes an anode 212 , a light emitting functional layer 213 and a cathode 214 .
  • Each of the second light emitting devices A also includes an anode 212 , a light emitting functional layer 213 and a cathode 214 .
  • the light-emitting functional layer 213 includes only the light-emitting layer.
  • the light-emitting functional layer 213 includes, in addition to the light-emitting layer, an electron transport layer (election transporting layer, referred to as ETL), an electron injection layer (election injection layer, abbreviated as EIL), and a hole transport layer (hole transporting layer, abbreviated as ETL) HTL) and one or more of the hole injection layer (HIL for short).
  • ETL electron transport layer
  • EIL electron injection layer
  • HTL hole transport layer
  • HIL hole transporting layer
  • the anodes 212 of the first light emitting device 210 and the second light emitting device A near the substrate 101 are opaque, and the cathodes 214 away from the substrate 101 are transparent or translucent.
  • the anodes 212 of the first light emitting device 210 and the second light emitting device A close to the substrate 101 are transparent or translucent, and the cathodes 214 away from the substrate 101 are opaque.
  • the display panel 100 further includes a pixel defining layer 215, the pixel defining layer 215 includes a plurality of opening areas, a first light emitting device 210 is disposed in one opening area, and a second light emitting device A set in an open area.
  • the display panel 100 further includes a flat layer 216 disposed between the pixel driving circuit and the anode 212 of the first light emitting device corresponding to the pixel driving circuit.
  • the anode of the first light emitting device 210 is electrically connected to the second electrode of the driving transistor Td in the pixel driving circuit through a via hole provided on the flat layer 216 .
  • the anode of the second light emitting device A is connected to the auxiliary connection line 15 (not shown in FIG. 11 ) through a via hole provided on the flat layer 216 .
  • the material of the flat layer 50 includes, but is not limited to, polysiloxane-based, acrylic-based or polyimide-based materials.
  • the display panel 100 further includes an encapsulation layer 217 .
  • the sub-pixels located in the first region 12 are all dummy sub-pixels D.
  • the pixel driving circuits in each row of sub-pixels are scanned row by row. That is, starting from the pixel driving circuit located in the first row of sub-pixels in the display area 1 to scan row by row, input the corresponding data signal to each pixel driving circuit in each row of sub-pixels in turn, until the data signal is input in the display area 1.
  • the first transistor T1 can be continuously turned on until it is connected to the last row of the second light-emitting device A in the light-transmitting area 11 .
  • the scanning of all the electrically connected pixel driving circuits is completed.
  • a first control signal is also input to the first transistor to turn on the first transistor T1.
  • the first data line 141 and the second data line 142 are connected together through the turned-on first transistor T1, and the second data signal is transmitted to the pixel driver of the dummy sub-pixel D in the third row electrically connected to the first data line 141
  • the second light-emitting device A located in the first row in the light-transmitting area 11, which is electrically connected to the dummy sub-pixel D emits light; when the processor receives the scan signal from the pixel driving circuit in the fourth row, the second light-emitting device A emits light.
  • the data signal is transmitted to the pixel driving circuit of the dummy sub-pixel D in the fourth row, which is electrically connected to the first data line 141, so that the dummy sub-pixel D is electrically connected to the dummy sub-pixel D in the second row of the light-transmitting area 11.
  • the second light emitting device A emits light. Until the second data signal is transmitted to the pixel driving circuit of the dummy sub-pixel D in the sixth row electrically connected to the first data line 141, so that the dummy sub-pixel D is electrically connected to the dummy sub-pixel D and is located in the light-transmitting area 11.
  • the second light-emitting devices A in 4 rows (that is, the pixel row located in the same row as the second light-emitting device A in the last row in the light-transmitting area 11 ) emit light, that is, the pixel row where each second light-emitting device A is located in the light-transmitting area 11 All scans are complete.
  • the processor inputs the first control signal to the gate of the first transistor T1 to turn off the first transistor T1.
  • the sub-pixels located in the first region 12 include dummy sub-pixels D and effective sub-pixels P.
  • the sub-pixel electrically connected to the first data line 141 is an effective sub-pixel P, the sub-pixel connected to the first data line 141 is turned off.
  • a data line 141 is electrically connected to the first transistor T1.
  • the sub-pixel electrically connected to the first data line 141 is a dummy sub-pixel P, and the dummy sub-pixel D is electrically connected to a second light-emitting device A in the second row in the light-transmitting area 11, the first data line 141 is turned on and the first light-emitting device A is electrically connected The first transistor T1 to which the data line 141 is electrically connected.
  • a first control signal is also input to the first transistor T1 electrically connected to the first data line 141-2 to turn off the first transistor T1.
  • the processor Since the sub-pixel in the fourth row of sub-pixels electrically connected to the first data line 141-2 is a dummy sub-pixel D, and the dummy sub-pixel D is electrically connected to a second light-emitting device A in the second row of the light-transmitting area 11 Therefore, when the processor inputs the gate scan signal to the pixel driving circuit in the fourth row (ie, the pixel row located in the same row as the second light-emitting device A in the second row in the light-transmitting area 11), the processor also A first control signal is input to the first transistor T1 electrically connected to the first data line 141-2 to turn on the first transistor T1.
  • the effective sub-pixels P located in the first region 12 among the plurality of effective sub-pixels P are uniformly arranged. In this way, the first region 12 can have a good display effect.
  • the display panel 100 further includes a first connection line.
  • the first connection line is disposed on a side of the first region 12 away from the signal input end of the data line 14 .
  • One end of the first connection line is electrically connected to the first pole of the first transistor T1
  • the other end of the first connection line is electrically connected to the first data line 141
  • the second pole of the first transistor T1 is electrically connected to the second data line 142 .
  • the display panel 100 further includes a second connection line.
  • the second connecting line is disposed on the side of the first region 12 away from the signal input end of the data line 14; one end of the second connecting line is electrically connected to the second pole of the first transistor T1, and the first pole of the first transistor T1 is connected to the first
  • the data lines 141 are electrically connected.
  • the display panel 100 further includes a first connection line 17 and a second connection line 18 .
  • Both the first connection line 17 and the second connection line 18 are disposed on a side of the first region 12 away from the signal input end of the data line 14 .
  • both the first connection line 17 and the second connection line 18 are disposed in the pixel row where the dummy sub-pixel D electrically connected to the first row of the second light emitting device A in the light-transmitting area 11 is located.
  • both the first connection line 17 and the second connection line 18 are arranged in the region corresponding to the sub-pixels in the third row in FIG. 3B .
  • first connection line 17 and the second connection line 18 are arranged at the same layer.
  • first connection line 17 and the second connection line 18 and the plurality of data lines 14 are at least partially disposed in the same layer.
  • first connection line 17 and the second connection line 18 electrically connected to a first transistor T1 are provided in the same layer as the first transistor T1.
  • One end of the first connection line 17 is electrically connected to the first electrode of the first transistor T1 , and the other end of the first connection line 17 is electrically connected to the first data line 141 .
  • One end of the second connection line 18 is electrically connected to the second electrode of the first transistor T1 , and the other end of the second connection line 18 is electrically connected to the second data line 142 .
  • the display panel 100 further includes at least one second transistor T2; the at least one second transistor T2 is configured to connect the first data lines 141 together when turned on; When turned off, the part of the first data line 141 located in the first area 12 is disconnected from the part located in the second area 13 and electrically connected to the second data line 142 .
  • the second transistor T2 is a thin film transistor TFT.
  • the plurality of second transistors T2 are disposed at least partially in the same layer.
  • the plurality of second transistors T2 are disposed at least partially in the same layer as the first data line 141 .
  • the second transistors T2 disposed in the same layer are simultaneously formed through a patterning process.
  • the light-transmitting area 11 is located in the middle of the display area 1 ;
  • the first data line 141 includes a first part 1411 , and a second part 1412 and a third part 1413 on both sides of the first part 1411 .
  • the first part 1411 is located in the first area 12
  • the second part 1412 and the third part 1413 are located in the second area 13 ;
  • the second part 1412 is closer to the signal input end of the first data line 141 than the third part 1413 .
  • the display panel 100 includes a second transistor T2; the first part 1411 and the second part 1412 of the first data line 141 are electrically connected through the second transistor T2. That is, the first electrode of the second transistor T2 is electrically connected to the first portion 1411 of the first data line 141 , and the second electrode of the second transistor T2 is electrically connected to the second portion 1412 of the first data line 141 .
  • the gate of the second transistor T2 is connected to the second control terminal through the second control signal line 21 to control the turn-on or turn-off of the second transistor T2.
  • the second transistor T2 is disposed on a side close to the signal input terminal of the first data line 141 , for example, in a region of the last pixel row of the display area 1 .
  • the first transistor T1 , the second transistor T2 and each transistor in the pixel driving circuit are P-type transistors as an example.
  • the processor when the processor inputs the gate scan signal G1 to the pixel driving circuit electrically connected to any second light-emitting device A in the light-transmitting area 11 , it also inputs the gate scan signal G1 to the first transistor T1
  • the first control signal K1 the first control signal K1 is a low-level signal
  • the first transistor T1 is turned on
  • the first data line 141 and the second data line 142 are connected as a whole
  • the data signal input terminal from the second data signal line 142 is connected.
  • the second data signal is transmitted to the pixel driving circuit electrically connected to the second light emitting device A through the first data line 141, so that the pixel driving circuit drives the second light emitting device A to emit light according to the second data signal.
  • the second control signal K2 is a high level signal, and the second transistor T2 is turned off, so that the first part 1411 and the second part 1412 of the first data line 141 are disconnected, so as to prevent the signal input from the first data line 141.
  • the first data signal is transmitted to the pixel driving circuit electrically connected to the second light emitting device A.
  • the processor when the processor inputs the gate scanning signal G2 to any row of pixel driving circuits located in the second area 13 , the processor inputs the first control signal K1 to the first transistor T1 , and the first control The signal K1 is a high level signal, the first transistor T1 is turned off, and the first data line 141 and the second data line 142 are not connected.
  • the second control signal K2 is a low-level signal, the second transistor T2 is turned on, and the first part 1411 and the second part 1412 of the first data line 141 are connected as a whole, so that the first part 1411 and the second part 1412 from the signal input end of the first data line 141 are connected together.
  • a data signal is transmitted to the pixel driving circuit of the row through the first data line 141, so that the first light-emitting device in the effective sub-pixel P of the row that is electrically connected to the pixel driving circuit emits light; from the second data line 142
  • the second data signal of the signal input terminal of 1 is transmitted to the pixel driving circuit of the row through the second data line 142, so that the first light emitting device in the effective sub-pixel P electrically connected to the pixel driving circuit of the row emits light.
  • the light-transmitting area 11 is located in the middle of the display area 1 .
  • the display panel includes two second transistors T2, the first part 1411 and the second part 1412 are electrically connected through one of the second transistors T21, and the first part 1411 and the third part 1413 are electrically connected through the other second transistor T22.
  • the second transistor T22 is disposed on a side close to the signal input end of the first data line 141 , for example, in the region of the last pixel row of the display area 1 .
  • the second transistor T21 is disposed at a position of the second region 13 closest to a row of sub-pixels in the first region 12 .
  • the second transistor T2 connecting the first part 1411 and the second part 1412 is turned off to prevent the first data signal from the signal input terminal of the first data line 141 from being transmitted to and the second light-emitting
  • the device A is electrically connected to the pixel drive circuit. Turning off the second transistor T2 connecting the first part 1411 and the third part 1413 can prevent the second data signal from the second data line 142 from being transmitted to the first part 1411 of the first data line 141 and also being transmitted to the first data Third portion 1413 of line 141 .
  • the processor when the processor inputs the gate scan signal G1 to the pixel driving circuit electrically connected to any second light-emitting device A in the light-transmitting area 11 , it also inputs the gate scan signal G1 to the first transistor T1
  • the first control signal K1 the first control signal K1 is a low-level signal
  • the first transistor T1 is turned on
  • the first data line 141 and the second data line 142 are connected as a whole
  • the data signal input terminal from the second data signal line 142 is connected.
  • the second data signal is transmitted to the pixel driving circuit electrically connected to the second light emitting device A through the first data line 141, so that the pixel driving circuit drives the second light emitting device A to emit light according to the second data signal.
  • the second control signals K21 and K22 are both high-level signals, the second transistor T21 and the second transistor T22 are both turned off, so that the first part 1411 and the second part 1412 of the first data line 141 are disconnected to prevent the
  • the first data signal of the signal input end of the first data line 141 is transmitted to the pixel driving circuit electrically connected to the second light emitting device A.
  • the processor when the processor sends pixels to any row of sub-pixels in the second area 12 (ie, the first row, the second row, the seventh row or the eighth row in FIG. 2B )
  • the gate scanning signal G1 is input to the driving circuit
  • the first control signal K1 is input to the first transistor T1
  • the first control signal K1 is a high level signal
  • the first transistor T1 is turned off, the first data line 141 and the second data line 142 not connected.
  • the second control signals K21 and K22 are both low-level signals, the second transistor T21 and the second transistor T22 are turned on, and the first part 1411 , the second part 1412 and the third part 1413 of the first data line 141 are connected as one , so that the first data signal from the signal input terminal of the first data line 141 is transmitted to the pixel driving circuit of the row through the first data line 141, so that the effective sub-pixel P of the row is electrically connected to the pixel driving circuit.
  • the first light-emitting device emits light; the second data signal from the signal input end of the second data line 142 is transmitted to the pixel driving circuit of the row through the second data line 142, so that the pixel driving circuit of the row is electrically connected to the pixel driving circuit.
  • the first light emitting device in the effective sub-pixel P emits light.
  • the display panel further includes a capacitor C, as shown in FIG. 4C .
  • the capacitor C is hereinafter referred to as a second storage capacitor C2.
  • the first storage electrode of the second storage capacitor C2 is electrically connected to the first electrode of the first transistor T1
  • the second storage electrode of the second storage capacitor C2 is electrically connected to the second electrode of the first transistor T1.
  • the second data signal from the signal input terminal of the second data line 142 is transmitted to the second storage electrode of the second storage capacitor C2, so that the voltage of the second storage electrode of the second storage capacitor C2 is the voltage of the second data signal ( Denoted as V2)
  • the voltage of the first storage electrode of the second storage capacitor C2 is the voltage of the first data signal from the signal input terminal of the first data line 141 (denoted as V1).
  • the first transistor T1 is turned on, and according to the charge retention law of the capacitor, the voltage of the first storage electrode of the second storage capacitor C2 jumps from V1 to V2, so that the voltages of the first and second electrodes of the first transistor T1 are between The same can be achieved in a short time, reducing the voltage drop, which can reduce the influence of the first transistor T1 on the transmission of the second data signal (refer to FIG. 7 ), and improve the uniformity of the brightness of the display panel.
  • FIG. 7 shows a signal simulation waveform diagram of the second data signal transmitted from the second data line to the first data line, wherein Q1 is the second storage device electrically connected between the first pole and the second pole of the first transistor T1 After the capacitor C2, the second data signal is transmitted from the second data line to the signal simulation waveform diagram of the first data line; Q2 is the second storage capacitor C2 that is not electrically connected between the first pole and the second pole of the first transistor T1 The signal simulation waveform diagram of the second data signal transmitted from the second data line to the first data line.
  • the spacing between any two adjacent second light emitting devices A in each row of second light emitting devices A is equal, and in a row of sub pixels including the dummy sub pixels D sum, the distance between any two adjacent effective sub pixels P is equal. The distance between them is equal to the distance between two adjacent second light emitting devices A. In this way, the display resolutions of the light-transmitting area 11 and the first area 12 are made equal, and the display effect of the display panel is improved.
  • three virtual sub-pixels D are disposed between any two adjacent effective sub-pixels P.
  • the resolution of the second region 13 is higher than that of the first region 12 and the light-transmitting region 11 .
  • the display area 1 includes a first area 12 , and the first area 12 is located on one side of the light-transmitting area 11 along the vertical data line direction.
  • the display area 1 includes two first areas 12 , and the two first areas 12 are respectively located on two sides of the light-transmitting area 11 along the vertical data line direction.
  • the light-transmitting area 11 is located in the middle of the display area 1 .
  • the plurality of dummy sub-pixels D in the first region 12 on both sides of the light-transmitting region 11 are electrically connected to the second light-emitting device A in the light-transmitting region 11, respectively, so that a plurality of auxiliary connection lines 15 and a plurality of data Lines are routed more evenly in the display panel.
  • the display area 1 includes two first areas 12 , one first area 12 is located on one side of the light-transmitting area 11 along the vertical data line direction, and the other first area 12 is located One side of the light-transmitting area 11 along the data line direction.
  • the light-transmitting area 11 is located in the middle of the display area 1 .
  • the plurality of sub-pixels shown in FIG. 7 are arranged in 12 rows and 18 columns, the first column to the 18th column along the X direction, and the first row to the 12th row along the Y direction.
  • the display panel 100 further includes a plurality of gate lines 19 and a plurality of scan signal connection lines 20 . At least the effective sub-pixels P in a row of pixels are electrically connected to one gate line.
  • a gate line 19 is electrically connected to the sub-pixels in the pixels in the ninth row, and the sub-pixels in this row include effective sub-pixels P and dummy sub-pixels D.
  • one gate line 19 is electrically connected to the sub-pixels in the pixels in the second row, and only the effective sub-pixels P are included in the sub-pixels in this row.
  • each scan signal connection line 20 is electrically connected to the gate line 19 electrically connected to the effective sub-pixel P located in the same row as a second light emitting device A, and the other end of the scan signal connection line 20 is electrically connected to the second light emitting device A
  • the pixel data driving circuit of the electrically connected dummy sub-pixel D is electrically connected, and the pixel data driving circuit of the dummy sub-pixel D is electrically connected to the gate line 20 which is electrically connected to the effective sub-pixel P in the same line with the dummy sub-pixel D.
  • the first data line 141 - 3 is electrically connected to the pixel driving circuit in the sub-pixel located in the fourth column, and the second light-emitting device A in the first column in the light-transmitting area 11 is connected to the eighth column.
  • the sub-pixels are located in the same column, and the second data line 142-3 is electrically connected to the pixel driving circuit in the sub-pixel located in the 8th column; the second light-emitting device A in the first column and the 1st row in the light-transmitting area 11 is located in the same row.
  • the pixel data driving circuit of the dummy sub-pixel D is electrically connected through the auxiliary connection line 15; the first data line 141-3 and the second data line 142-3 are electrically connected through the first transistor T1.
  • the first transistor T1 when the first transistor T1 is turned on, the first data line 141-3 and the second data line 142-3 are connected as a whole, and the second data signal from the signal input terminal of the second data line 142-3 passes through the first
  • the data line 141-3 is transmitted to the pixel data driving circuit of the dummy sub-pixel D electrically connected to the second light emitting device A, so that the second light emitting device A emits light.
  • the first data line 141-3 and the second data line 142-3 are not connected, and the first data signal from the signal input terminal of the first data line 141-3 is transmitted to the first data line 141-3.
  • the valid sub-pixels P in a row electrically connected to the first data line 141-3 can be displayed normally.
  • the second light-emitting device A in the third column and the sub-pixels in the twelfth column in the light-transmitting area 11 are located in the same column, and the second data line 142-4 and the sub-pixels in the twelfth column are located in the same column.
  • the first data line 141-4 is electrically connected to the pixel driving circuit in the sub-pixel in the 11th column; the second light-emitting device A in the 3rd column and 3rd row in the light-transmitting area 11 is electrically connected to
  • the pixel data driving circuits of the virtual sub-pixels D in the same column are electrically connected through the auxiliary connecting line 15; the first data line 141-4 and the second data line 142-4 are electrically connected through the first transistor T1;
  • One end is electrically connected to the gate line 19-1 electrically connected to the effective sub-pixel P in the same row (ie, the ninth row) with the second light-emitting device A, and the other end of the scanning signal connection line 20 is electrically connected to the second light-emitting device
  • the pixel data driving circuit of the dummy sub-pixel D that is electrically connected to A is electrically connected, and the pixel data driving circuit of the dummy sub-pixel D is electrically connected to the effective sub-pixel P in the same row (ie, the
  • the first transistor T1 when the first transistor T1 is turned on, the first data line 141-2 and the second data line 142-4 are connected together, and the second data signal from the signal input terminal of the second data line 142-4 passes through the first
  • the data line 141-4 is transmitted to the pixel data driving circuit of the dummy sub-pixel D electrically connected to the second light emitting device A, and the gate line scan signal from the gate line 19-1 is transmitted to the second light emitting device A through the scan signal connection line 20 to the pixel data driving circuit of the dummy sub-pixel D.
  • the two light-emitting devices A are electrically connected to the pixel data driving circuit of the dummy sub-pixel D, so that the second light-emitting device A can emit light normally.
  • the first data line 141-4 and the second data line 142-4 are not connected, and the first data signal from the signal input terminal of the first data line 141-4 is transmitted to the first data line 141-4.
  • the pixel data circuit electrically connected to the line 142 so that a column of valid sub-pixels P electrically connected to the first data line 141-4 can be displayed normally; the second data signal transmission from the signal input end of the second data line 142-4 into the pixel data circuit electrically connected to the second data line 142-4, so that a row of valid sub-pixels P electrically connected to the second data line 142-4 can be displayed normally.
  • the first area 12 is arranged on one side of the light-transmitting area 11 along the direction of the data line, and the number of dummy sub-pixels D is increased, so that the number of the second light-emitting devices A in the light-transmitting area increases accordingly. Increase, the area of the light-transmitting region 11 is enlarged.
  • Some embodiments of the present disclosure provide a control method of a display panel, including S100-S300.
  • the processor inputs gate scanning signals to the sub-pixels in the plurality of rows row by row.
  • the processor When the processor inputs a gate scan signal to the pixel driving circuit electrically connected to any second light-emitting device A in the light-transmitting area 11, it also inputs a control signal to the first transistor T1, so that the first transistor turns on T1 .
  • the processor inputs data signals to each row of sub-pixels through the plurality of data lines 14; when the first transistor T1 is turned on, the second data signal from the signal input terminal of the second data line 142 is transmitted to the sub-pixel through the first data line 141. in the pixel driving circuit to which the second light-emitting device A is electrically connected.

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Abstract

一种显示面板，具有显示区，显示区包括透光区、至少一个第一区和第二区。显示面板包括设置于至少一个第一区和第二区中的多个子像素、设置于透光区的多个第二发光器件、多根数据线以及第一晶体管。多根数据线包括第一数据线和第二数据线；第一数据线与包含虚拟子像素的一列子像素中的像素驱动电路电连接；第二数据线和与一列第二发光器件位于同一列的一列子像素中的像素驱动电路电连接；该列第二发光器件中的一个第二发光器件和与第一数据线连接的一个虚拟子像素中的像素驱动电路电连接。第一数据线与第二数据线通过第一晶体管电连接。

Description

显示面板、显示装置及控制方法 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、显示装置及控制方法。
背景技术
目前，用于电子装置的显示屏正往大屏化、全屏化方向发展，以使用户具有更好的视觉体验。随着技术的发展和进步，人们对屏下摄像头技术的研究越来越多。屏下摄像头是将电子设备摄像头设于显示屏之下实现拍照，并且屏下摄像头在显示屏上对应的区域能够进行显示，从而实现全面屏显示。
发明内容
一方面，提供一种显示面板，具有显示区，所述显示区包括透光区、至少一个第一区和第二区，所述至少一个第一区至少位于所述透光区的一侧。所述显示面板，包括设置于所述至少一个第一区和所述第二区中的多个子像素、设置于所述透光区的多个第二发光器件、多根数据线以及第一晶体管。所述多个子像素排布成多行多列；所述多个子像素包括多个有效子像素和多个虚拟子像素，所述多个虚拟子像素设置于所述至少一个第一区中；每个子像素均包括像素驱动电路，且每个有效子像素还包括与该像素驱动电路电连接的第一发光器件；所述多个第二发光器件排成多列第二发光器件，每列第二发光器件与一列子像素排成一列。一列子像素中的像素驱动电路与一根数据线电连接；所述多根数据线包括第一数据线和第二数据线；所述第一数据线与包含虚拟子像素的一列子像素中的像素驱动电路电连接；所述第二数据线和与一列第二发光器件位于同一列的一列子像素中的像素驱动电路电连接；该列第二发光器件中的一个第二发光器件和与所述第一数据线连接的一个虚拟子像素中的像素驱动电路电连接。所述第一数据线与所述第二数据线通过所述第一晶体管电连接。
在一些实施例中，与所述第一数据线电连接的一列子像素中，位于第一区的子像素均为虚拟子像素。
在一些实施例中，所述多个有效子像素中位于第一区中的有效子像素均匀排布。
在一些实施例中，显示面板还包括：第一连接线和/或第二连接线。第一连接线设置于所述第一区远离所述第一数据线的信号输入端的一侧；所述第一连接线的一端与所述第一晶体管的第一极电连接，所述第一连接线的另一 端与所述第一数据线电连接；第二连接线设置于第一区远离所述第一数据线的信号输入端的一侧；所述第二连接线的一端与所述第一晶体管的第二极电连接，所述第二连接线的另一端与所述第二数据线电连接。
在一些实施例中，显示面板还包括至少一个第二晶体管；所述至少一个第二晶体管被配置为在开启时，使所述第一数据线连为一体；在关闭时，使所述第一数据线中位于第一区的部分与位于第二区中的部分断开，且与所述第二数据线电连接。
在一些实施例中，所述透光区位于所述显示区的中部；所述第一数据线包括第一部分、和位于所述第一部分两侧的第二部分和第三部分，所述第一部分位于所述第一区，所述第二部分和所述第三部分位于所述第二区；所述第二部分相对所述第三部分更靠近所述第一数据线的信号输入端；所述至少一个第二晶体管包括一个第二晶体管；所述第一部分和所述第二部分通过所述第二晶体管电连接；或者，所述至少一个第二晶体管包括两个第二晶体管，所述第一部分和所述第二部分通过其中一个第二晶体管电连接，所述第一部分和所述第三部分通过另一个第二晶体管电连接。
在一些实施例中，显示面板还包括电容器；所述电容器的第一存储电极与所述第一晶体管的第一极电连接，所述电容器的第二存储电极与所述第一晶体管的第二极电连接。
在一些实施例中，每行第二发光器件中任意相邻两个第二发光器件的间距相等；包含虚拟子像素和有效子像素的一行子像素中，任意相邻两个有效子像素之间的间距等于所述相邻两个第二发光器件之间的间距。
在一些实施例中，包含虚拟子像素和有效子像素的一行子像素中，任意相邻两个有效子像素之间设置有三个所述虚拟子像素。
在一些实施例中，所述至少一个第一区包括一个第一区，该第一区位于所述透光区的沿垂直数据线方向的一侧。
在一些实施例中，所述至少一个第一区包括两个第一区，该两个第一区分别位于所述透光区的沿垂直数据线方向的两侧。
在一些实施例中，所述至少一个第一区包括两个第一区，一个第一区位于所述透光区的沿垂直数据线方向的一侧，另一个第一区位于所述透光区的沿数据线方向的一侧。
在一些实施例中，显示面板还包括多根栅线和多根扫描信号连接线。一行像素中的至少有效子像素与一根栅线电连接；扫描信号连接线的一端和与一个第二发光器件位于同一行的有效子像素电连接的栅线电连接，所述扫描 信号连接线的另一端和与该第二发光器件电连接的虚拟子像素的像素数据驱动电路电连接，且该虚拟子像素的像素数据驱动电路和与该虚拟子像素同行的有效子像素电连接的栅线绝缘。
在一些实施例中，所述第一发光器件和所述第二发光器件均为OLED。
另一方面，提供一种显示装置，包括上述任一实施例的显示面板和位于所述透光区的图像传感器。
又一方面，提供一种显示面板的控制方法，包括：逐行向多行子像素输入栅极扫描信号；当向与所述透光区中任一的第二发光器件电连接的像素驱动电路输入栅极扫描信号时，还向所述第一晶体管输入控制信号，以使所述第一晶体管开启；通过所述多根数据线向每行子像素输入数据信号；在第一晶体管开启时，来自所述第二数据线的信号输入端的第二数据信号通过所述第一数据线传输至与所述第二发光器件电连接的像素驱动电路中。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的示意图；
图2A为根据一些实施例的显示面板的一种平面示意图；
图2B为根据一些实施例的显示面板的另一种平面示意图；
图3A为根据一些实施例的显示面板的一种示意图；
图3B为根据一些实施例的显示面板的另一种示意图；
图4A为根据一些实施例的显示面板的又一种示意图；
图4B为根据一些实施例的显示面板的又一种示意图；
图4C为根据一些实施例的显示面板的又一种示意图；
图5A为根据一些实施例的显示面板的一种信号时序图；
图5B为根据一些实施例的显示面板的另一种信号时序图；
图6A为根据一些实施例的显示面板的又一种信号时序图；
图6B为根据一些实施例的显示面板的又一种信号时序图；
图7为根据一些实施例的第二数据信号的一种仿真波形图；
图8为根据一些实施例的显示面板的又一种示意图；
图9为根据一些实施例的显示面板的又一种示意图；
图10A为根据一些实施例的一种像素驱动电路的等效电路图；
图10B为根据一些实施例的另一种像素驱动电路的等效电路图；
图11为根据一些实施例的一种基于图8中B-B’方向的剖视图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
如本文所使用的，单数形式“一个”也包括复数形式，除非上下文另外明确指出。除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语““连接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。本公开示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开一些实施例提供一种显示装置，该显示装置可以用作手机、平板电脑、个人数字助理(personal digital assistant，PDA)、车载电脑等，本公开的实施例对显示装置的用途不做特殊限制。
如图1所示，显示装置包括显示面板100、框架200、盖板300、电路板400、以及包括图像传感器500等的其他电子配件。示例的，框架200的纵截面呈U型，显示面板100、电路板400和图像传感器500等设置于框架200和盖板300围成的腔体内。电路板400设置于显示面板100背离盖板300的一侧。
在一些示例中，图像传感器500为摄像头。示例的，摄像头设置于显示面板100背离盖板300的一侧。
在一些示例中，电路板400被配置为向显示面板100提供显示所需的信号。示例的，电路板400为印刷电路板组件(Printed Circuit Board Assembly， PCBA)，PCBA包括印刷电路板(Printed Circuit Board，PCB)和设置于PCB上的时序控制器(Timing Controller，TCON)、电源管理集成电路(Power Management IC，PMIC)以及其它IC或电路等。
本公开一些实施例提供一种显示面板100，如图2A和图2B所示，该显示面板具有显示区1，显示区1包括透光区11、至少一个第一区12和第二区13。示例的，如图2A所示，第一区12设置于透光区11的一侧。又示例的，如图2B所示，第一区12围绕透光区11设置。
在一些示例中，如图1所示，透光区11为与图像传感器的安装位置在垂直于显示装置厚度的方向上相对应的区域。透光区11在实现摄像头采集图像的基础上，还可以显示图像，以使显示面板100实现全面屏显示。
示例的，如图2A和图2B所示，透光区11的形状为圆形。另示例的，透光区11的形状为矩形。又示例的，第一区12的形状为矩形。当然，本公开实施例透光区11和第一区12的形状不做限定，可根据实际情况合理调整。
显示面板100包括设置于第一区12和第二区13中的多个子像素，多个子像素排布成多行多列。示例的，如图3A和图3B所示，多个子像素排布成8行24列，沿X方向依次为第1列至第24列，沿Y方向依次为第1行至第8行。每列子像素中的子像素的数量相等，每行子像素中的子像素的数量也相等。当然，显示面板100中子像素的数量、多个子像素排布成行的行数和排布成列的列数、以及每行子像素中的子像素的数量、每列子像素中的子像素的数量与该显示面板的分辨率等有关，图3A和图3B所示的多个子像素为显示面板100中的一部分子像素，其仅为多个子像素排布成多行多列的一种排布方式的示意，本公开实施例对子像素的数量以及多个子像素排布成多行多列的具体方式不进行限定，只要多个子像素可以排布为多行多列即可。
如图3A和图3B所示，多个子像素包括多个有效子像素P和多个虚拟子像素D；多个有效子像素P设置于第一区12和第二区12中，多个虚拟子像素D设置于第一区12中。
每个有效子像素P包括像素驱动电路以及与该像素驱动电路电连接的第一发光器件，每个虚拟子像素D仅包括像素驱动电路。示例的，每个有效子像素P中的像素驱动电路和每个虚拟子像素D中的像素驱动电路的电路结构相同。
如图3A和图3B所示，显示面板还包括设置于透光区11的多个第二发光器件A，多个第二发光器件A排成多列第二发光器件A，每列第二发光器件A与一列子像素排成一列。
本公开中，将与一根信号线电连接的多个子像素定义为一列子像素，这里，信号线为本公开中的数据线。将与一列子像素中的至少部分子像素沿同一方向排列的多个第二发光器件A定义为一列第二发光器件A。将沿另一根信号线的延伸方向排布的多个子像素定义为一行子像素，这里，另一根信号线为下文中的栅线。将与一行子像素中的至少部分子像素沿同一方向排列的多个第二发光器件A定义为一行第二发光器件A。
示例的，多个第二发光器件A排布成如图2A和2B所示的4行3列，沿X方向依次为第1列至第3列，沿Y方向依次为第1行至第4行，每列第二发光器件A中的第二发光器件A的数量相等，每行第二发光器件A中的第二发光器件A的数量也相等。当然，透光区11中第二发光器件A的数量、多个第二发光器件A排布成行的行数和排布成列的列数、以及每行第二发光器件A中的第二发光器件A的数量、每列第二发光器件A中的第二发光器件A的数量与该透光区11的尺寸以及分辨率等有关，图3A和图3B所示的多个第二发光器件A的排布方式仅为一种示意，本公开实施例对第二发光器件A的数量以及多个第二发光器件A排布成多列的方式不进行限定。
这里，透光区11仅设置多个第二发光器件A，且多个第二发光器件A间隔均匀排布，可增大透光区11的透光率，并使透光区具有良好的显示效果。
示例的，参考图3A和图3B，透光区11中的第1列第二发光器件A与显示区1中的第13列子像素排成一列。又示例的，透光区11中的第2列第二发光器件A与第15列子像素排成一列。
在一些示例中，多个第一发光器件包括多个被配置为发红光的第一发光器件、多个被配置为发绿光的第一发光器件以及多个发蓝光的第一发光器件。
在一些示例中，多个第二发光器件A包括多个被配置为发红光的第二发光器件A、多个被配置为发绿光的第二发光器件A以及多个发蓝光的第二发光器件A。
当然，多个第一发光器件还可包括发白光的第一发光器件。多个第二发光器件A也可以包括发白光的第二发光器件A。
在一些示例中，第一发光器件为有机发光二极管(Organic Light-Emitting Diode，OLED)。
在一些示例中，第二发光器件A为OLED。
如图3A和图3B所示，显示面板100还包括多根数据线14，一列子像素中的像素驱动电路与一根数据线14电连接。多根数据线14包括第一数据线141和第二数据线142。示例的，第一数据线141为多条第一数据线141，第 二数据线142为多条第二数据线142。
示例的，多根数据线14同层设置。又示例的，多根数据线14至少部分同层设置。同层设置的多根数据线14通过构图工艺同步形成。
本公开中，图3A和图3B仅示出了部分数据线，实质上，每列子像素均电连接一根数据线。
第一数据线141与包含虚拟子像素D的一列子像素中的像素驱动电路电连接。示例的，如图3A所示，第1列子像素中包含虚拟子像素D，第一数据线141-1与位于第1列的子像素中的像素驱动电路电连接。又示例的，如图3A所示，第2列的子像素中包含虚拟子像素D和有效子像素P，第一数据线141-2与位于第2列的子像素中的像素驱动电路电连接。
第二数据线142和与一列第二发光器件A位于同一列的一列子像素中的像素驱动电路电连接；该列第二发光器件A中的一个第二发光器件A和与第一数据线连接的一个虚拟子像素D中的像素驱动电路电连接。示例的，如图3A所示，透光区11中的第1列第二发光器件A与第13列的子像素位于同一列，第二数据线142-1和位于第13列的子像素中的像素驱动电路电连接。又示例的，如图3A所示，透光区11中的第2列第二发光器件A与第15列的子像素位于同一列，第二数据线142-2和位于第15列的子像素中的像素驱动电路电连接。
每个第二数据线142具有一段第一绕线部，该第一绕线部绕过透光区11布线，可使第二数据线142不穿过透光区11，以避免第二数据线142对透光区11的透光率的影响。
在一些示例中，如图3A所示，多根数据线14还包括第三数据线143。示例的，第三数据线143为多根第三数据线143。第三数据线143仅和与任意列的第二发光器件A位于不同列，且一列均为有效子像素P的子像素中的像素驱动电路电连接。即，第三数据线143仅与位于第二区13中的与任意列的第二发光器件A位于不同列的一列有效子像素P的像素驱动电路电连接。
示例的，如图3A所示，第24列的有效子像素P与任意列的第二发光器件A位于不同列，且第24列的多个有效子像素P均位于第二区13，第三数据线143-1与位于第24列的有效子像素P的像素驱动电路电连接。
又示例的，如图3A所示，第22列的有效子像素P与任意列的第二发光器件A位于不同列，且第22列的多个有效子像素P均位于第二区13，第三数据线143-2与位于第22列中的有效子像素P的像素驱动电路电连接。第三数据线143-2具有一段第二绕线部，该第二绕线部绕过透光区11设置，可使 第三数据线143-2不穿过透光区11，以避免第三数据线143-1对透光区11的透光率的影响。也就是说，若与第三数据线143电连接的有效子像素P在沿数据线14的方向上位于透光区的一侧，则第三数据线需设置一段第二绕线部。
在一些示例中，位于透光区11中第1列第1行的第二发光器件A与位于第1列第3行的虚拟子像素D中的像素驱动电路电连接。例如，如图3A和图3B所示，一个第二发光器件A与一个虚拟子像素D中的像素驱动电路通过一根辅助连接线15连接。
这里，图3A和图3B仅为示意，虽然图3A和图3B中仅部分第二发光器件A与虚拟子像素D中的像素驱动电路通过辅助连接线15连接，但并不代表透光区11中仅部分第二发光器件A与虚拟子像素D中的像素驱动电路电连接。实质上，透光区11中的每个第二发光器件A均与对应的虚拟子像素D中的像素驱动电路电连接。
示例的，该辅助连接线15的材料为氧化铟锡(Indium tin oxide，ITO)。ITO在薄膜状时呈透明，因此，采用ITO制作的辅助连接线呈透明态，因此，使得辅助连接线对透光区11的透光率几乎不产生影响。示例的，多根辅助连接线15同层设置。又示例的，多根辅助连接线15与多根数据线14至少部分同层设置。同层设置的多根辅助连接线15通过构图工艺同步形成。
在一些示例中，如图10A所示，像素驱动电路30包括驱动晶体管Td、第三晶体管T3和第一存储电容器Cst。本领域技术人员应当明白，在像素驱动电路30中，驱动晶体管Td的沟道的宽长比大于其它起开关作用的晶体管(例如第三晶体管T3)的沟道的宽长比。即，该像素驱动电路30的电路结构为2T1C电路结构。
如图10A所示，第三晶体管T3的栅极与扫描信号线GL电连接，第三晶体管T3的第一极与数据线DL(即，上述显示面板100中的数据线14)电连接，第三晶体管T3的第二极与驱动晶体管Td的栅极电连接。驱动晶体管Td的第一极与第一电源线VDD电连接，驱动晶体管Td的第二极与发光器件L(即，上述显示面板的第一发光器件或第二发光器件A)的阳极电连接。发光器件L的阴极与第二电源线VSS电连接。第一存储电容器Cst的一端与驱动晶体管Td的栅极电连接，第一存储电容器Cst的另一端与驱动晶体管Td的第二极电连接。示例的，第一电源线VDD被配置为提供高电压信号，第二电源线VSS被配置为提供低电压信号。
在另一些示例中，如图10B所示，像素驱动电路30包括驱动晶体管Td、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体 管T8、第九晶体管T9、和第一存储电容器Cst。即，该像素驱动电路的电路结构为7T1C电路结构。
如图10B所示，第八晶体管T8的栅极与扫描信号线GL电连接，第八晶体管T8的第一极与数据信号线DL(即，上述显示面板中的数据线14)电连接，第八晶体管T8的第二极与驱动晶体管Td的第一极电连接。第九晶体管T9的栅极与扫描信号线GL电连接，第九晶体管T9的第一极和第二极分别与驱动晶体管Td的第二极和栅极电连接。第四晶体管T4的栅极与使能信号线EM电连接，第四晶体管T4的第一极与第一电源线VDD电连接，第四晶体管T4的第二极与驱动晶体管Td的第一极电连接。第五晶体管T5的栅极与使能信号线EM电连接，第五晶体管T5的第一极与驱动晶体管Td的第二极电连接，第五晶体管T5的第二极与发光器件L的阳极电连接。第六晶体管T6的栅极与复位信号线RST(N)电连接，第六晶体管T6的第一极与初始化信号线VIN电连接，第六晶体管T6的第二极与驱动晶体管Td的栅极电连接。第七晶体管T7的栅极与下一行像素驱动电路30中的第六晶体管T6连接的复位信号线RST(N+1)电连接，第七晶体管T7的第一极与初始化信号线VIN电连接，第七晶体管T7的第二极与发光器件L(即，上述显示面板的第一发光器件或第二发光器件A)的阳极电连接。第一存储电容器Cst的一端与驱动晶体管Td的栅极电连接，第一存储电容器Cst的另一端与第一电源线VDD电连接。发光器件L的阴极与第二电源线VSS电连接。示例的，第一电源线VDD被配置为提供高电压信号，第二电源线VSS被配置为提供低电压信号。
上述仅仅是对像素驱动电路30的举例说明，关于像素驱动电路30的电路结构不限于上述两种结构，其还可以是其它类型的电路结构，这里不再一一列举。但应理解，不管像素驱动电路30是哪种电路结构，其至少包括一个驱动晶体管、一个起开关作用的晶体管以及一个第一存储电容器。
在本公开中，第一极为晶体管的源极和漏极中的一者，第二极为晶体管的源极和漏极中的另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例的，对于P型晶体管，将第二极称为漏极，将第一极称为源极。又示例的，对于N型晶体管，将第一极称为漏极，将第二极称为源极。
此外，根据晶体管导电方式的不同，可以将晶体管分为增强型晶体管和耗尽型晶体管。本公开实施例中的各个晶体管可以为增强型晶体管，也可以为耗尽型晶体管，对此不作限制。
示例的，每个子像素中的像素驱动电路30相同。多个子像素中的像素驱动电路30通过构图工艺同步形成。
显示面板100还包括多个第一晶体管。参考图3A、3B、以及图4A，一条第一数据线141和一条第二数据线142之间通过一个第一晶体管T1连接，第一晶体管T1被配置为在开启时，使第一数据线141和第二数据线142连为一体；在关闭时，使第一数据线141和第二数据线142不连接。
示例的，多个第一晶体管T1通过构图工艺同步形成。
在一些示例中，第一晶体管T1的栅极通过第一控制线16连接到第一控制端，来自第一控制端的第一控制信号通过第一控制线16传输至第一晶体管T1，以控制第一晶体管T1的开启或关闭。例如，第一晶体管T1为N型晶体管，响应于来自第一控制端的第一控制信号为高电平信号，第一晶体管T1开启。又例如，第一晶体管T1为P型晶体管，响应于来自第一控制端的第一控制信号为低电平信号，第一晶体管T1关闭。
本公开中，在第一晶体管T1开启的情况下，第一数据线141和第二数据线142连为一体，来自第二数据线142的信号输入端的第二数据信号通过连为一体的第二数据线142和第一数据线141传输至与第二发光器件A电连接的像素驱动电路中，以控制该第二发光器件A发光，以使显示面板的透光区11显示图像。
需要说明的是，在第一晶体管T1开启的情况下，第一信号线141可不向与第二发光器件A电连接的虚拟子像素D中的像素驱动电路中传输第一数据信号，以防止第一数据信号和第二数据信号相互干扰。例如，可通过处理器控制在第一晶体管T1开启时，第一数据线141的信号输入端不输出第一数据信号，或不输出可使第二发光器件A发光的数据信号，即，处理器可控制第一信号线141的信号输入端输出虚拟的第一数据信号；或者，通过控制开关(例如下文中的第二晶体管T2)断开第一数据线141，阻止来自第一数据线141的信号输入端的第一数据信号传输至与第二发光器件A电连接的像素驱动电路中。
在第一晶体管T1关闭的情况下，第一数据线141和第二数据线142不连接，来自第一数据线141的信号输入端的第一数据信号传输至与第一数据线141电连接的像素数据电路中，以使与第一数据线141电连接的一列有效子像素P均可正常显示。
这样，与第一数据线141与第二数据线142直接通过连接线电连接，只能将透光区位于显示区1的最顶端相比，本公开的实施例可使透光区11位于 显示区1的任意位置，且不影响第二区13的正常显示。
本公开中，显示面板100中的各行子像素之间的间距相等，各列子像素之间的间距也相等，以使显示面板100具有良好的显示效果。图3A和3B中第2行子像素和第三行子像素之间的间距、第6行与第7行之间的间距、以及第23列和第24列之间的间距仅为一种示意，为了更清楚的示意第一数据线141和第二数据线142之间的连接，以及各数据线的布线方式，其并不代表显示面板中子像素之间的实际间距。
在一些实施例中，第一晶体管T1为薄膜晶体管(Thin Film Transistor，简称TFT)。
在一些示例中，参考图11，显示面板100包括衬底101，每个子像素中的像素驱动电路设置于衬底101上。示例的，衬底101为玻璃衬底。
每个像素驱动电路中的驱动晶体管Td包括有源层、源极、漏极、栅极及栅绝缘层，源极和漏极分别与有源层接触。
示例的，有源层2113的材料包含非晶铟镓锌氧(a-IGZO)、氮氧化锌(ZnON)、铟锌锡氧化物(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等中的一种。
参考图11，每个有效子像素P中的第一发光器件210包括阳极212、发光功能层213以及阴极214。每个第二发光器件A也包括阳极212、发光功能层213以及阴极214。
示例的，发光功能层213仅包括发光层。又示例的，发光功能层213除包括发光层外，还包括电子传输层(election transporting layer，简称ETL)、电子注入层(election injection layer，简称EIL)、空穴传输层(hole transporting layer，简称HTL)以及空穴注入层(hole injection layer，简称HIL)中的一层或多层。
在一些示例中，第一发光器件210和第二发光器件A的靠近衬底101的阳极212呈不透明，远离衬底101的阴极214呈透明或半透明。
在另一些示例中，第一发光器件210和第二发光器件A的靠近衬底101的阳极212呈透明或半透明，远离衬底101的阴极214呈不透明。
在一些示例中，如图11所示，显示面板100还包括像素界定层215，像素界定层215包括多个开口区，一个第一发光器件210设置于一个开口区中，一个第二发光器件A设置于一个开口区中。
在又一些示例中，如图11所示，显示面板100还包括设置在像素驱动电路和与该像素驱动电路对应的第一发光器件的阳极212之间的平坦层216。第 一发光器件210的阳极通过设置于平坦层216上的过孔与像素驱动电路中驱动晶体管Td的第二极电连接。第二发光器件A的阳极通过设置于平坦层216上的过孔与辅助连接线15连接(图11中未示出)。
示例的，平坦层50的材料包含但不限于聚硅氧烷系、亚克力系或聚酰亚胺系材料。
在又一些示例中，如图11所示，显示面板100还包括封装层217。
在一些实施例中，如图3B所示，与第一数据线141电连接的一列子像素中，位于第一区12的子像素均为虚拟子像素D。
在一个帧周期的扫描阶段中，对各行子像素中的像素驱动电路逐行进行扫描。即，从位于显示区1的第一行子像素中的像素驱动电路开始逐行扫描，依次向各行子像素中的每个像素驱动电路输入对应的数据信号，直至将数据信号输入位于显示区1的最后一行子像素中的各像素驱动电路。
基于此，在对透光区11中各第二发光器件A所在的像素行进行扫描的过程中，可使第一晶体管T1持续开启，直至与透光区11中的最后一行第二发光器件A电连接的像素驱动电路全部扫描结束。
示例的，参考图3B，当处理器向第3行(即，与透光区11中第1行的第二发光器件A位于同一行的像素行)的像素驱动电路输入栅极扫描信号时，还向第一晶体管输入第一控制信号，使第一晶体管T1开启。第一数据线141和第二数据线142通过开启的第一晶体管T1连为一体，第二数据信号被传输至与第一数据线141电连接的位于第3行的虚拟子像素D的像素驱动电路中，以使与该虚拟子像素D电连接的位于透光区11中第1行的第二发光器件A发光；当处理器向第4行的像素驱动电路接收到的扫描信号，第二数据信号被传输至与第一数据线141电连接的位于第4行的虚拟子像素D的像素驱动电路中，以使与该虚拟子像素D电连接的位于透光区11中第2行的第二发光器件A发光。直至第二数据信号被传输至与第一数据线141电连接的位于第6行的虚拟子像素D的像素驱动电路中，以使与该虚拟子像素D电连接的位于透光区11中第4行(即，与透光区11中最后一行的第二发光器件A位于同一行的像素行)的第二发光器件A发光，即透光区11中各第二发光器件A所在的像素行全部扫描结束。处理器向第一晶体管T1的栅极输入第一控制信号，使第一晶体管T1关闭。
在另一些实施例中，如图3A所示，与第一数据线141电连接的一列子像素中，位于第一区12的子像素包括虚拟子像素D和有效子像素P。
基于此，在对透光区11中的一个第二发光器件A所在的像素行进行扫描的过程中，若与第一数据线141电连接的子像素为有效子像素P，则关闭与该第一数据线141电连接的第一晶体管T1。若与第一数据线141电连接的子像素为虚拟子像素P，且该虚拟子像素D与透光区11中的第二行的一个第二发光器件A电连接，则开启与该第一数据线141电连接的第一晶体管T1。
示例的，参考图3A，当处理器向第3行(即，与透光区11中第1行的第二发光器件A位于同一行的像素行)的像素驱动电路输入栅极扫描信号时，还向与第一数据线141-2电连接的第一晶体管T1输入第一控制信号，以使第一晶体管T1关闭。由于第4行子像素中与第一数据线141-2电连接的子像素为虚拟子像素D，且该虚拟子像素D与透光区11中的第二行的一个第二发光器件A电连接，因此，当处理器向第4行(即，与透光区11中第2行的第二发光器件A位于同一行的像素行)的像素驱动电路输入栅极扫描信号时，处理器还向与第一数据线141-2电连接的第一晶体管T1输入第一控制信号，以使第一晶体管T1开启。
在一些实施例中，如图3A和3B所示，多个有效子像素P中位于第一区12中的有效子像素P均匀排布。这样，可使第一区12具有良好的显示效果。
在一些实施例中，显示面板100还包括第一连接线。第一连接线设置于第一区12远离数据线14的信号输入端的一侧。第一连接线的一端与第一晶体管T1的第一极电连接，第一连接线的另一端与第一数据线141电连接，第一晶体管T1的第二极与第二数据线142电连接。
在另一些实施例中，显示面板100还包括第二连接线。第二连接线设置于第一区12远离数据线14的信号输入端的一侧；第二连接线的一端与第一晶体管T1的第二极电连接，第一晶体管T1的第一极与第一数据线141电连接。
在又一些实施例中，如图3A和3B、以及图4A-图4C所示，显示面板100还包括第一连接线17和第二连接线18。第一连接线17和第二连接线18均设置于第一区12远离数据线14的信号输入端的一侧。示例的，第一连接线17和第二连接线18均设置于与透光区11中的第一行第二发光器件A电连接的虚拟子像素D所在的像素行。例如第一连接线17和第二连接线18均设置于图3B中的第3行子像素所对应的区域。示例的，第一连接线17和第二连接线18同层设置。另示例的，第一连接线17和第二连接线18与多根数据线14至少部分同层设置。又示例的，与一个第一晶体管T1电连接的第一连接线17和第二连接线18与该第一晶体管T1同层设置。
第一连接线17的一端与第一晶体管T1的第一极电连接，第一连接线17的另一端与第一数据线141电连接。第二连接线18的一端与第一晶体管T1的第二极电连接，第二连接线18的另一端与第二数据线142电连接。
在一些实施例中，如图4B和图4C所示，显示面板100还包括至少一个第二晶体管T2；至少一个第二晶体管T2被配置为在开启时，使第一数据线141连为一体；在关闭时，使第一数据线141中位于第一区12的部分与位于第二区13中的部分断开，且与第二数据线142电连接。
示例的，第二晶体管T2为薄膜晶体管TFT。
示例的，多个第二晶体管T2至少部分同层设置。又示例的，多个第二晶体管T2至少部分与第一数据线141同层设置。同层设置的第二晶体管T2通过构图工艺同步形成。
在一些示例中，如图4B所示，透光区11位于显示区1的中部；第一数据线141包括第一部分1411、和位于第一部分1411两侧的第二部分1412和第三部分1413。第一部分1411位于第一区12，第二部分1412和第三部分1413位于第二区13；第二部分1412相对第三部分1413更靠近第一数据线141的信号输入端。
显示面板100包括一个第二晶体管T2；第一数据线141的第一部分1411和第二部分1412通过第二晶体管T2电连接。即，第二晶体管T2的第一极与第一数据线141的第一部分1411电连接，第二晶体管T2的第二极与第一数据线141的第二部分1412电连接。第二晶体管T2的栅极通过第二控制信号线21连接到第二控制端，以控制第二晶体管T2的开启或关闭。
示例的，第二晶体管T2设置于靠近第一数据线141的信号输入端的一侧，例如，位于显示区1的最后一行像素行的区域。
参考图3B、图4B、图5A以及图5B，以第一晶体管T1、第二晶体管T2以及像素驱动电路中的各个晶体管均为P型晶体管为例。
如图3B、图4B以及图5A所示，当处理器向与透光区11中任一个第二发光器件A电连接的像素驱动电路输入栅极扫描信号G1时，还向第一晶体管T1输入第一控制信号K1，第一控制信号K1为低电平信号，第一晶体管T1开启，第一数据线141和第二数据线142连为一体，来自第二数据信号线142的数据信号输入端的第二数据信号通过第一数据线141传输至与该第二发光器件A电连接的像素驱动电路中，以使该像素驱动电路根据第二数据信号驱动该第二发光器件A发光。此时，第二控制信号K2为高电平信号，第二晶体管T2关闭，使第一数据线141的第一部分1411和第二部分1412断开， 以阻止来自第一数据线141的信号输入端的第一数据信号传输至与该第二发光器件A电连接的像素驱动电路中。
如图3B、图4C以及图5B所示，当处理器向位于第二区13的任意一行像素驱动电路输入栅极扫描信号G2时，向第一晶体管T1输入第一控制信号K1，第一控制信号K1为高电平信号，第一晶体管T1关闭，第一数据线141和第二数据线142不连接。此时，第二控制信号K2为低电平信号，第二晶体管T2开启，第一数据线141的第一部分1411和第二部分1412连为一体，使得来自第一数据线141的信号输入端的第一数据信号通过第一数据线141传输至该行的像素驱动电路中，以使该行的与该像素驱动电路电连接的有效子像素P中的第一发光器件发光；来自第二数据线142的信号输入端的第二数据信号通过第二数据线142传输至该行的像素驱动电路中，以使该行的与该像素驱动电路电连接的有效子像素P中的第一发光器件发光。
在另一些示例中，如图4C所示，透光区11位于显示区1的中部。显示面板包括两个第二晶体管T2，第一部分1411和第二部分1412通过其中一个第二晶体管T21电连接，第一部分1411和第三部分1413通过另一个第二晶体管T22电连接。
示例的，第二晶体管T22设置于靠近第一数据线141的信号输入端的一侧，例如，位于显示区1的最后一行像素行的区域。第二晶体管T21设置于第二区13最靠近第一区12的一行子像素的位置。
这样，在第一晶体管T1开启的情况下，关闭连接第一部分1411和第二部分1412的第二晶体管T2，以阻止来自第一数据线141的信号输入端的第一数据信号传输至与第二发光器件A电连接的像素驱动电路中。关闭连接第一部分1411和第三部分1413的第二晶体管T2，可阻止来自第二数据线142的第二数据信号在传输至第一数据线141的第一部分1411的同时，还传输至第一数据线141的第三部分1413。
以第一晶体管T1、第二晶体管T2以及像素驱动电路中的各个晶体管均为P型晶体管为例。
如图3B、图4B以及图6A所示，当处理器向与透光区11中任一个第二发光器件A电连接的像素驱动电路输入栅极扫描信号G1时，还向第一晶体管T1输入第一控制信号K1，第一控制信号K1为低电平信号，第一晶体管T1开启，第一数据线141和第二数据线142连为一体，来自第二数据信号线142的数据信号输入端的第二数据信号通过第一数据线141传输至与该第二发光器件A电连接的像素驱动电路中，以使该像素驱动电路根据第二数据信号 驱动该第二发光器件A发光。此时，第二控制信号K21和K22均为高电平信号，第二晶体管T21和第二晶体管T22均关闭，使第一数据线141的第一部分1411和第二部分1412断开，以阻止来自第一数据线141的信号输入端的第一数据信号传输至与该第二发光器件A电连接的像素驱动电路中。
如图3B、图4B以及图6B所示，当处理器向第二区12的任意一行子像素(即，图2B中的第1行、第2行、第7行或第8行)的像素驱动电路输入栅极扫描信号G1时，向第一晶体管T1输入第一控制信号K1，第一控制信号K1为高电平信号，第一晶体管T1关闭，第一数据线141和第二数据线142不连接。此时，第二控制信号K21和K22均为低电平信号，第二晶体管T21和第二晶体管T22开启，第一数据线141的第一部分1411、第二部分1412和第三部分1413连为一体，使得来自第一数据线141的信号输入端的第一数据信号通过第一数据线141传输至该行的像素驱动电路中，以使该行的与该像素驱动电路电连接的有效子像素P中的第一发光器件发光；来自第二数据线142的信号输入端的第二数据信号通过第二数据线142传输至该行的像素驱动电路中，以使该行的与该像素驱动电路电连接的有效子像素P中的第一发光器件发光。
在一些实施例中，如图4C所示，显示面板还包括电容器C。为了与上述驱动电路中的第一存储电容器Cst区分，以下将该电容器C称为第二存储电容器C2。
第二存储电容器C2的第一存储电极与第一晶体管T1的第一极电连接，第二存储电容器C2的第二存储电极与第一晶体管T1的第二极电连接。这样，来自第二数据线142的信号输入端的第二数据信号传输至第二存储电容器C2的第二存储电极，使得第二存储电容器C2的第二存储电极的电压为第二数据信号的电压(记为V2)，第二存储电容器C2的第一存储电极的电压为来自第一数据线141的信号输入端的第一数据信号的电压(记为V1)。这样，第一晶体管T1开启，根据电容器的电荷保持定律，第二存储电容器C2的第一存储电极的电压由V1跳变为V2，使得第一晶体管T1的第一极和第二极的电压在短时间内达到相同，减小压降，可减小第一晶体管T1对第二数据信号传输的影响(参考图7)，提高显示面板亮度的均匀性。图7所示为第二数据信号由第二数据线传输至第一数据线的信号仿真波形图，其中，Q1为在第一晶体管T1的第一极和第二极之间电连接第二存储电容器C2后，第二数据信号由第二数据线传输至第一数据线的信号仿真波形图；Q2为在第一晶体管T1的第一极和第二极之间未电连接第二存储电容器C2的第二数据信号由第二 数据线传输至第一数据线的信号仿真波形图。
在一些实施例中，每行第二发光器件A中任意相邻两个第二发光器件A的间距相等，包含虚拟子像素D和的一行子像素中，任意相邻两个有效子像素P之间的间距等于相邻两个第二发光器件A之间的间距。这样，使得透光区11和第一区12的显示分辨率相等，提高显示面板的显示效果。
在一些示例中，如图3A和图3B所示，包含虚拟子像素D和有效子像素的一行子像素P中，任意相邻两个有效子像素P之间设置有三个虚拟子像素D。这里，由于第二区13中仅包括有效子像素P，因此，第二区13的分辨率高于第一区12和透光区11的分辨率。
在一些实施例中，如图3A和图3B所示，显示区1包括一个第一区12，该第一区12位于透光区11的沿垂直数据线方向的一侧。
在一些实施例中，如图8所示，显示区1包括两个第一区12，该两个第一区12分别位于透光区11的沿垂直数据线方向的两侧。透光区11位于显示区1的中部。这样，位于透光区11两侧的第一区12中的多个虚拟子像素D分别与透光区11中的第二发光器件A电连接，可使多根辅助连接线15和多跟数据线在显示面板中的布线位置更均匀。
在一些实施例中，如图9所示，显示区1包括两个第一区12，一个第一区12位于透光区11的沿垂直数据线方向的一侧，另一个第一区12位于透光区11的沿数据线方向的一侧。透光区11位于显示区1的中部。图7所示的多个子像素排布成12行18列，沿X方向依次为第1列至第18列，沿Y方向依次为第1行至第12行。
在一些示例中，显示面板100还包括多根栅线19和多根扫描信号连接线20。一行像素中的至少有效子像素P与一根栅线电连接。示例的，如图9所示，一根栅线19与第9行的像素中的子像素电连接，该行子像素中包括有效子像素P和虚拟子像素D。又示例的，如图7所示，一根栅线19与第2行的像素中的子像素电连接，该行子像素中仅包括有效子像素P。
每根扫描信号连接线20的一端和与一个第二发光器件A位于同一行的有效子像素P电连接的栅线19电连接，扫描信号连接线20的另一端和与该第二发光器件A电连接的虚拟子像素D的像素数据驱动电路电连接，且该虚拟子像素D的像素数据驱动电路和与该虚拟子像素D同行的有效子像素P电连接的栅线绝缘20。
示例的，如图9所示，第一数据线141-3与位于第4列的子像素中的像素驱动电路电连接，透光区11中的第1列第二发光器件A与第8列的子像素 位于同一列，第二数据线142-3和位于第8列的子像素中的像素驱动电路电连接；透光区11中第1列第1行的第二发光器件A与位于同行的虚拟子像素D的像素数据驱动电路通过辅助连接线15电连接；第一数据线141-3与第二数据线142-3之间通过第一晶体管T1电连接。
这样，在第一晶体管T1开启的情况下，第一数据线141-3和第二数据线142-3连为一体，来自第二数据线142-3的信号输入端的第二数据信号通过第一数据线141-3传输至与该第二发光器件A电连接的虚拟子像素D的像素数据驱动电路中，以使该第二发光器件A发光。
在第一晶体管T1关闭的情况下，第一数据线141-3和第二数据线142-3不连接，来自第一数据线141-3的信号输入端的第一数据信号传输至与第一数据线141-3电连接的像素数据电路中，以使与第一数据线141-3电连接的一列有效子像素P均可正常显示。
又示例的，如图9所示，透光区11中的第3列第二发光器件A与第12列的子像素位于同一列，第二数据线142-4和位于第12列的子像素中的像素驱动电路电连接；第一数据线141-4与位于第11列的子像素中的像素驱动电路电连接；透光区11中第3列第3行的第二发光器件A与位于同列的虚拟子像素D的像素数据驱动电路通过辅助连接线15电连接；第一数据线141-4与第二数据线142-4之间通过第一晶体管T1电连接；扫描信号连接线20的一端和与该第二发光器件A位于同一行(即，第9行)的有效子像素P电连接的栅线19-1电连接，扫描信号连接线20的另一端和与该第二发光器件A电连接的虚拟子像素D的像素数据驱动电路电连接，且该虚拟子像素D的像素数据驱动电路和与该虚拟子像素D同行(即，第5行)的有效子像素P电连接的栅线19-2绝缘。
这样，在第一晶体管T1开启的情况下，第一数据线141-2和第二数据线142-4连为一体，来自第二数据线142-4的信号输入端的第二数据信号通过第一数据线141-4传输至与该第二发光器件A电连接的虚拟子像素D的像素数据驱动电路中，来自栅线19-1的栅线扫描信号通过扫描信号连接线20传输至与该第二发光器件A电连接的虚拟子像素D的像素数据驱动电路中，以使该第二发光器件A正常发光。
在第一晶体管T1关闭的情况下，第一数据线141-4和第二数据线142-4不连接，来自第一数据线141-4的信号输入端的第一数据信号传输至与第一数据线142电连接的像素数据电路中，以使与第一数据线141-4电连接的一列有效子像素P均可正常显示；来自第二数据线142-4的信号输入端的第二数据信 号传输至与第二数据线142-4电连接的像素数据电路中，以使与第二数据线142-4电连接的一列有效子像素P均可正常显示。
此外，如图9所示，在透光区11沿数据线方向的一侧设置第一区12，增加了虚拟子像素D的数量，使得透光区中的第二发光器件A的数量随之增加，扩大了透光区11的面积。
本公开一些实施例提供一种显示面板的控制方法，包括S100-S300。
S100、处理器逐行向多行子像素输入栅极扫描信号。
S200、当处理器向与透光区11中任一的第二发光器件A电连接的像素驱动电路输入栅极扫描信号时，还向第一晶体管T1输入控制信号，以使第一晶体管开启T1。
S300、处理器通过多根数据线14向每行子像素输入数据信号；在第一晶体管T1开启时，来自第二数据线142的信号输入端的第二数据信号通过第一数据线141传输至与第二发光器件A电连接的像素驱动电路中。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种显示面板，具有显示区，所述显示区包括透光区、至少一个第一区和第二区，所述至少一个第一区至少位于所述透光区的一侧；
    所述显示面板，包括：
    设置于所述至少一个第一区和所述第二区中的多个子像素，所述多个子像素排布成多行多列；所述多个子像素包括多个有效子像素和多个虚拟子像素，所述多个虚拟子像素设置于所述至少一个第一区中；每个子像素均包括像素驱动电路，且每个有效子像素还包括与该像素驱动电路电连接的第一发光器件；
    设置于所述透光区的多个第二发光器件，所述多个第二发光器件排成多列第二发光器件，每列第二发光器件与一列子像素排成一列；
    多根数据线，一列子像素中的像素驱动电路与一根数据线电连接；所述多根数据线包括第一数据线和第二数据线；所述第一数据线与包含虚拟子像素的一列子像素中的像素驱动电路电连接；所述第二数据线和与一列第二发光器件位于同一列的一列子像素中的像素驱动电路电连接；该列第二发光器件中的一个第二发光器件和与所述第一数据线连接的一个虚拟子像素中的像素驱动电路电连接；
    第一晶体管，所述第一数据线与所述第二数据线通过所述第一晶体管电连接。
  2. 根据权利要求1所述的显示面板，其中，与所述第一数据线电连接的一列子像素中，位于第一区的子像素均为虚拟子像素。
  3. 根据权利要求1或2所述的显示面板，其中，所述多个有效子像素中位于第一区中的有效子像素均匀排布。
  4. 根据权利要求1-3任一项所述的显示面板，还包括：
    第一连接线，设置于所述第一区远离所述第一数据线的信号输入端的一侧；所述第一连接线的一端与所述第一晶体管的第一极电连接，所述第一连接线的另一端与所述第一数据线电连接；和/或，
    第二连接线，设置于第一区远离所述第一数据线的信号输入端的一侧；所述第二连接线的一端与所述第一晶体管的第二极电连接，所述第二连接线的另一端与所述第二数据线电连接。
  5. 根据权利要求1-4任一项所述的显示面板，还包括：
    至少一个第二晶体管；所述至少一个第二晶体管被配置为在开启时，使所述第一数据线连为一体；在关闭时，使所述第一数据线中位于第一区的部分与位于第二区中的部分断开，且与所述第二数据线电连接。
  6. 根据权利要求5所述的显示面板，其中，所述透光区位于所述显示区的中部；
    所述第一数据线包括第一部分、和位于所述第一部分两侧的第二部分和第三部分，所述第一部分位于所述第一区，所述第二部分和所述第三部分位于所述第二区；所述第二部分相对所述第三部分更靠近所述第一数据线的信号输入端；
    所述至少一个第二晶体管包括一个第二晶体管；所述第一部分和所述第二部分通过所述第二晶体管电连接；或者，所述至少一个第二晶体管包括两个第二晶体管，所述第一部分和所述第二部分通过其中一个第二晶体管电连接，所述第一部分和所述第三部分通过另一个第二晶体管电连接。
  7. 根据权利要求1-6任一项所述的显示面板，还包括：
    电容器；所述电容器的第一存储电极与所述第一晶体管的第一极电连接，所述电容器的第二存储电极与所述第一晶体管的第二极电连接。
  8. 根据权利要求1所述的显示面板，其中，每行第二发光器件中任意相邻两个第二发光器件的间距相等；
    包含虚拟子像素和有效子像素的一行子像素中，任意相邻两个有效子像素之间的间距等于所述相邻两个第二发光器件之间的间距。
  9. 根据权利要求8所述的显示面板，其中，包含虚拟子像素和有效子像素的一行子像素中，任意相邻两个有效子像素之间设置有三个所述虚拟子像素。
  10. 根据权利要求1-9任一项所述的显示面板，其中，所述至少一个第一区包括一个第一区，该第一区位于所述透光区的沿垂直数据线方向的一侧。
  11. 根据权利要求1-9任一项所述的显示面板，其中，所述至少一个第一区包括两个第一区，该两个第一区分别位于所述透光区的沿垂直数据线方向的两侧。
  12. 根据权利要求1-9任一项所述的显示面板，其中，所述至少一个第一区包括两个第一区，一个第一区位于所述透光区的沿垂直数据线方向的一侧，另一个第一区位于所述透光区的沿数据线方向的一侧。
  13. 根据权利要求12所述的显示面板，还包括：
    多根栅线，一行像素中的至少有效子像素与一根栅线电连接；
    多根扫描信号连接线；扫描信号连接线的一端和与一个第二发光器件位于同一行的有效子像素电连接的栅线电连接，所述扫描信号连接线的另一端和与该第二发光器件电连接的虚拟子像素的像素数据驱动电路电连接，且该 虚拟子像素的像素数据驱动电路和与该虚拟子像素同行的有效子像素电连接的栅线绝缘。
  14. 根据权利要求1-13任一项所述的显示面板，其中，所述第一发光器件和所述第二发光器件均为OLED。
  15. 一种显示装置，包括：
    权利要求1-15任一项所述的显示面板；
    位于所述透光区的图像传感器。
  16. 一种如权利要求1所述的显示面板的控制方法，包括：
    逐行向多行子像素输入栅极扫描信号；
    当向与所述透光区中任一的第二发光器件电连接的像素驱动电路输入栅极扫描信号时，还向所述第一晶体管输入控制信号，以使所述第一晶体管开启；
    通过所述多根数据线向每行子像素输入数据信号；在第一晶体管开启时，来自所述第二数据线的信号输入端的第二数据信号通过所述第一数据线传输至与所述第二发光器件电连接的像素驱动电路中。
PCT/CN2021/073374 2021-01-22 2021-01-22 显示面板、显示装置及控制方法 WO2022155914A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108364957A (zh) * 2017-09-30 2018-08-03 云谷（固安）科技有限公司 显示屏及显示装置
CN109585519A (zh) * 2018-12-19 2019-04-05 上海天马微电子有限公司 一种显示面板和显示装置
US20200043406A1 (en) * 2018-07-31 2020-02-06 Samsung Display Co., Ltd. Display device
CN111326560A (zh) * 2020-01-23 2020-06-23 京东方科技集团股份有限公司 显示基板和显示装置
CN111462695A (zh) * 2020-04-22 2020-07-28 昆山国显光电有限公司 显示面板、第一像素电路及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10707281B2 (en) * 2018-08-10 2020-07-07 Au Optronics Corporation Display apparatus
CN110942746B (zh) * 2018-09-21 2022-07-01 北京小米移动软件有限公司 有机发光二极管显示屏、显示控制方法和电子设备
KR20200097371A (ko) * 2019-02-07 2020-08-19 삼성디스플레이 주식회사 표시 장치
US11074856B2 (en) * 2019-08-09 2021-07-27 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel and display device
KR20210081568A (ko) * 2019-12-24 2021-07-02 엘지디스플레이 주식회사 유기발광 표시장치
KR20210081571A (ko) * 2019-12-24 2021-07-02 엘지디스플레이 주식회사 유기발광 표시장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108364957A (zh) * 2017-09-30 2018-08-03 云谷（固安）科技有限公司 显示屏及显示装置
US20200043406A1 (en) * 2018-07-31 2020-02-06 Samsung Display Co., Ltd. Display device
CN109585519A (zh) * 2018-12-19 2019-04-05 上海天马微电子有限公司 一种显示面板和显示装置
CN111326560A (zh) * 2020-01-23 2020-06-23 京东方科技集团股份有限公司 显示基板和显示装置
CN111462695A (zh) * 2020-04-22 2020-07-28 昆山国显光电有限公司 显示面板、第一像素电路及显示装置

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