WO2021013181A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2021013181A1
WO2021013181A1 PCT/CN2020/103541 CN2020103541W WO2021013181A1 WO 2021013181 A1 WO2021013181 A1 WO 2021013181A1 CN 2020103541 W CN2020103541 W CN 2020103541W WO 2021013181 A1 WO2021013181 A1 WO 2021013181A1
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WIPO (PCT)
Prior art keywords
goa
circuit
sub
area
goa unit
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PCT/CN2020/103541
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English (en)
French (fr)
Inventor
郝学光
乔勇
吴新银
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2021538325A priority Critical patent/JP2022541693A/ja
Priority to US17/271,319 priority patent/US11495179B2/en
Priority to EP20844705.2A priority patent/EP4006886A4/en
Publication of WO2021013181A1 publication Critical patent/WO2021013181A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/87—Arrangements for heating or cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8794—Arrangements for heating and cooling

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device.
  • the gate drive circuit also called GOA circuit
  • the gate driving circuit includes a plurality of GOA units (also referred to as shift registers) connected in a one-to-one correspondence with a plurality of driving signal lines such as gate lines in the display panel.
  • an array substrate has a display area and a peripheral area located outside the display area; the display area includes two substantially parallel first sides and an arc side connected to at least one end of each of the first sides.
  • the array substrate includes a plurality of sub-pixels arranged in the display area and at least one gate driving circuit arranged in the peripheral area.
  • Each gate driving circuit includes: a plurality of GOA units sequentially distributed along at least one of the arc edges and a plurality of effective GOA units sequentially distributed along one of the first sides connected to the arc edges;
  • the plurality of GOA units includes at least one valid GOA unit and at least one virtual GOA unit; each valid GOA unit is configured to provide a driving signal to at least one of the sub-pixels, and the at least one virtual GOA unit is the plurality of GOA units other than the effective GOA units in the GOA unit; wherein the distance between two adjacent GOA units in the plurality of GOA units sequentially distributed along at least one of the arc edges is connected to the arc edge The distance between two adjacent effective GOA units among the multiple effective GOA units sequentially distributed on one of the first side edges is approximately the same.
  • At least one virtual GOA unit is arranged between two adjacent effective GOA units among the plurality of GOA units sequentially distributed along at least one side of the arc.
  • any effective GOA unit among the plurality of GOA units sequentially distributed along at least one of the arc edges is close to the plurality of effective GOA units sequentially distributed along the first side relative to all virtual GOA units.
  • the effective GOA cell includes a plurality of transistors; the at least one virtual GOA cell includes a plurality of transistors; the number of transistors in the at least one virtual GOA cell is less than the number of transistors in the effective GOA cell .
  • the area occupied by each GOA unit includes: a first area and a second area; the effective GOA unit includes a first sub-circuit disposed in the first area of the effective GOA unit and The second sub-circuit in the second region of the effective GOA cell, the first sub-circuit includes a plurality of transistors, the second sub-circuit includes at least one transistor; at least one virtual GOA cell includes a first sub-circuit provided in each virtual GOA cell The first sub-circuit in a region does not include the second sub-circuit, and the second region of the virtual GOA unit is located in a half region close to the outer edge of the peripheral region in the region occupied by the virtual GOA unit.
  • each of the effective GOA cells includes a plurality of transistors coupled through a plurality of signal transmission paths; at least one virtual GOA cell includes a plurality of transistors, and the plurality of transistors in each virtual GOA cell are connected to the The positions of the plurality of transistors in the effective GOA unit correspond; in the at least one dummy GOA unit, at least one of the plurality of signal transmission paths coupled to the plurality of transistors is compared to the position at the corresponding position of the effective GOA unit The signal transmission path is disconnected.
  • the area occupied by each GOA unit includes: a first area and a second area; the GOA unit includes at least one transistor disposed in the first area and at least one transistor disposed in the second area Transistor; in the at least one dummy GOA unit, at least one of the signal transmission paths coupled to the transistor located in the second area is disconnected compared to the signal transmission path at the corresponding position of the effective GOA unit
  • the second area of the virtual GOA unit is located in a half area close to the outer edge of the peripheral area in the area occupied by the virtual GOA unit.
  • the second area of the virtual GOA unit is closer to the outer edge of the peripheral area than the first area.
  • the effective GOA unit includes an input sub-circuit, a pull-down sub-circuit, a pull-up control sub-circuit, a pull-up sub-circuit, an output control sub-circuit, and an output sub-circuit; the input sub-circuit and the signal input terminal, The first node and the second clock signal terminal are connected; the input sub-circuit is configured to output the voltage of the signal input terminal to the first node under the control of the voltage of the second clock signal terminal; the pull-down sub The circuit is connected to the first voltage terminal, the second node, and the second clock signal terminal; the pull-down sub-circuit is configured to output the voltage of the first voltage terminal to the second clock signal terminal under the control of the voltage of the second clock signal terminal.
  • the pull-up control sub-circuit is connected to the first clock signal terminal, the first node, the second node, and the second voltage terminal; the pull-up control sub-circuit is configured to Under the control of the voltages of the first clock signal terminal and the second node, the voltage of the second voltage terminal is output to the first node; the pull-up sub-circuit and the second node, the second node The voltage terminal is connected to the signal output terminal; the pull-up sub-circuit is configured to output the voltage of the second voltage terminal to the signal output terminal under the control of the voltage of the second node; the output control sub-circuit Connected to the first node, the first voltage terminal, and the output sub-circuit; the output control sub-circuit is configured to control the voltage between the output sub-circuit and the first node through the voltage of the first voltage terminal On and off; the output sub-circuit is connected to the output control sub-circuit, the first clock signal terminal, the signal output terminal; the output sub-circuit is configured to be when
  • each GOA unit when the area occupied by each GOA unit includes a first area and a second area, in the effective GOA unit, at least part of the transistors in the input sub-circuit and/or the pull-down At least part of the transistors in the sub-circuit are located in the second area of the effective GOA unit.
  • the pull-up control sub-circuit includes a first control unit and a second control unit; the first control unit and the second node, the second voltage terminal, and the second control unit Connected; the second control unit is also connected to the first node and the first clock signal terminal; in the effective GOA unit, at least part of the transistors in the first control unit and/or the first At least part of the transistors in the second control unit are located in the second area of the effective GOA unit.
  • the array substrate includes two GOA circuits; the two GOA circuits are respectively located on two of the first sides and an arc side connected to at least one end of each of the first sides. In the outer peripheral zone.
  • the display panel includes: the array substrate as described in any of the above embodiments.
  • embodiments of the present disclosure also provide a display device.
  • the display device includes: the display panel as described in any of the above embodiments.
  • FIG. 1 is a structural diagram of a special-shaped display panel provided by the present disclosure
  • FIG. 2 is a structural diagram of a display panel (array substrate) provided by some embodiments of the present disclosure
  • FIG. 3 is a structural diagram of an OLED provided by some embodiments of the present disclosure.
  • Fig. 4A is an enlarged structural view of A1 in Fig. 2;
  • Fig. 4B is another enlarged structural view of A1 in Fig. 2;
  • Fig. 4C is another enlarged structural diagram at A1 in Fig. 2;
  • FIG. 5 is a partial structure diagram of an array substrate provided by related art
  • Fig. 6 is a region division diagram of a virtual GOA circuit and an effective GOA circuit according to some embodiments of the present disclosure
  • FIG. 7 is another area division diagram of a virtual GOA circuit and an effective GOA circuit provided by some embodiments of the present disclosure.
  • FIG. 8 is a structural diagram of an effective GOA unit provided by some embodiments of the disclosure.
  • FIG. 9 is a circuit structure diagram of an effective GOA unit provided by some embodiments of the disclosure.
  • FIG. 10 is a circuit structure diagram of a virtual GOA unit provided by some embodiments of the present disclosure.
  • FIG. 11 is a structural diagram of a virtual GOA unit provided by some embodiments of the present disclosure.
  • FIG. 12 is a circuit structure diagram of another virtual GOA unit provided by some embodiments of the present disclosure.
  • first, second and similar words are only used to distinguish different components, and cannot be understood as indicating or implying any order, relative importance, or implicitly indicating the number of indicated technical features.
  • the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “when” or “in response to determination” or “in response to detection.”
  • the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [the stated condition or event] is detected” or “in response to the detection of [stated condition or event]”.
  • azimuth terms such as “upper”, “lower”, “left”, “right”, “horizontal” and “vertical” are defined relative to the directions in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, and they are used for relative description and clarification, which can be changed correspondingly according to the changes in the orientation of the components in the drawings.
  • the embodiments of the present disclosure provide a display device, which may be a TV, a mobile phone, a desktop computer, a notebook computer, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, and the like.
  • a display device which may be a TV, a mobile phone, a desktop computer, a notebook computer, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, and the like.
  • PDA personal digital assistant
  • Fig. 1 illustrates an example in which the display device is a mobile phone.
  • the display device at least includes a display panel.
  • the display panel includes an array substrate, a gate drive circuit, a source drive circuit, a timing control circuit (TCON), a printed circuit board (Printed Circuit Board, PCB), a flexible printed circuit board (Flexible Printed Circuit Board, FPC) and other electronic accessories Wait.
  • TCON timing control circuit
  • PCB printed circuit board
  • FPC Flexible Printed Circuit Board
  • the above-mentioned display panel may be an Organic Light Emitting Diode (OLED) display panel, Quantum Dot Light Emitting Diodes (QLED) display panel, or Micro Light Emitting Diodes (Micro LED) display panel, etc. This disclosure does not specifically limit this.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro LED Micro Light Emitting Diodes
  • OLED display panels have received widespread attention due to their self-luminous, light and thin, low power consumption, high contrast, high color gamut, and flexible display.
  • the OLED display panel is also known as a new generation of display technology.
  • the following embodiments of the present disclosure are all taking the above-mentioned display panel as an OLED display panel as an example to illustrate the present disclosure.
  • FIG. 2 is a structural diagram of a display panel provided by some embodiments of the present disclosure.
  • the display panel 001 includes: an active area (referred to as an AA area; also referred to as an effective display area) 1 and a peripheral area 2 located outside the display area 1.
  • AA area an active area
  • Fig. 2 illustrates an example in which the peripheral area 2 surrounds the display area 1 as an example.
  • a plurality of gate lines (Gate Line) GL and a plurality of data lines (Data Line) DL are provided in the above-mentioned display panel 001, and a plurality of gate lines GL and a plurality of data lines DL cross in the display area 1.
  • a number of sub pixels P are defined.
  • the multiple sub-pixels P located in the display area 1 at least include: first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels.
  • the first color, the second color, and the third color are three primary colors (for example, red, green, and blue).
  • the multiple sub-pixels P are arranged in a matrix as an example.
  • the gate line GL extends in the horizontal direction X
  • the data line DL extends in the vertical direction Y
  • the sub-pixels P arranged in a row along the horizontal direction X are called sub-pixels in the same row
  • the sub-pixels P arranged in a row are called sub-pixels in the same column.
  • each sub-pixel P is provided with a pixel circuit S (also referred to as a pixel driving circuit), and the pixel circuit S includes a driving unit and a light emitting unit.
  • a pixel driving circuit also referred to as a pixel driving circuit
  • the above-mentioned driving unit includes a transistor and a capacitor.
  • the driving unit in the pixel circuit S is only a 2T1C (that is, including a driving transistor Md, a switching transistor Ms, and a storage capacitor Cst) structure as an example.
  • the present disclosure is not limited to this.
  • the driving unit may also adopt 3T1C, 4T1C, and other circuit structures.
  • the aforementioned light emitting unit includes an organic light emitting diode OLED.
  • the OLED includes a cathode 11 and an anode 12, and a light-emitting function layer 13 located between the cathode 11 and the anode 12.
  • the light-emitting functional layer 13 may include an organic light-emitting layer (Emission layer, EML), and may also include a hole transport layer (HTL) located between the organic light-emitting layer EML and the anode 12 and/or a hole transport layer (HTL) located on the organic light-emitting layer.
  • EML Electron Transport Layer
  • a hole injection layer (Hole Injection Layer, HIL) can also be provided between the hole transport layer HTL and the anode 12, and/or, between the electron transport layer ETL and the cathode 11
  • An electron injection layer (Electron Injection Layer, EIL), etc. are provided in between, which is not limited in the present disclosure.
  • the anode 12 is used to inject holes and the cathode 11 injects electrons.
  • the formed electrons and holes meet in the organic light-emitting layer EML to generate excitons, thereby exciting the organic
  • the light-emitting layer EML emits light;
  • the driving sub-circuit in the pixel circuit S of the sub-pixel P controls the size of the driving current in the current path formed by the cathode 11 and the anode 12, so that the light-emitting brightness of the organic light-emitting layer EML is different to achieve different gray levels. Order display.
  • the display panel 001 is also provided with a gate driving circuit (also referred to as a GOA circuit) 10 connected to a driving signal line such as a gate line GL in the peripheral area 2 (attached to the embodiment of the present disclosure).
  • a gate driving circuit also referred to as a GOA circuit
  • the figures all take the connection of the gate line GL and the gate driving circuit 10 as an example), and the data driving circuit 20 connected to the data line DL.
  • the above-mentioned driving signal line may be, for example, a gate line or an emission control line.
  • the gate driving circuit 10 described above may be disposed in the peripheral area 2 along the extending direction of the gate line GL, and the data driving circuit 20 may be disposed in the peripheral area 2 along the extending direction of the data line DL.
  • the pixel circuits S are turned on row by row by the gate driving circuit 10, and when a row of pixel circuits S is turned on, the pixel data voltage is written into each pixel circuit S of the row by the data driving circuit 20 to perform screen display.
  • the above-mentioned gate driving circuit 10 is directly integrated on the array substrate in the display panel 001.
  • the structure diagram of the array substrate in the display panel 001 is basically the same as the structure diagram of the display panel 001 shown in FIG. 2 (but does not mean that the structures of the two are the same), the following describes the array substrate 100 in the present disclosure with reference to FIG. And the arrangement of the GOA circuit 10 on the base substrate of the array substrate 100 will be further explained.
  • the display area 1 includes two substantially parallel first sides L1 and two substantially parallel The second side L2, the first side L1 and the second side L2 are substantially perpendicular, and at least one end of each first side L passes through an arc edge R (also called a rounded corner, a rounded corner, or an R corner ) Connect with the second side L2. That is, the display area 1 of the display panel 001 in the present disclosure is provided with at least two R angles.
  • the display area 1 may include multiple R angles.
  • the display area 1 may include two substantially parallel first sides (L1 and L1'), and two substantially parallel second sides (L2 and L2). '), the first side L1 and the second side L2 are approximately perpendicular, and the two ends of each first side (L1 and L1') are connected with the two second sides (L2 and L2') respectively through an R angle .
  • the display area 1 includes 4 R angles.
  • the display area 1 may include two substantially parallel first side edges (L1 and L1'), and two substantially parallel second side edges (L2 and L2').
  • the side L1 and the second side L2 are substantially perpendicular, and the two first sides (L1 and L1') and a second side (L2) are respectively connected by an R angle.
  • the display area 1 includes 2 R angles.
  • the following embodiments all take the display area 1 shown in FIG. 2 including 4 R angles as an example to further illustrate the present disclosure.
  • the array substrate 100 is respectively provided with GOA circuits 10 in the peripheral area 2 of the display area 1 located on both sides in the extending direction of the gate line GL.
  • the GOA circuit may be provided only in the peripheral area 2 of the display area 1 located on one side along the extending direction of the gate line GL.
  • FIG. 4A, FIG. 4B and FIG. 4C are a part of the A1 area in FIG.
  • the GOA circuit 10 includes: a plurality of GOA units sequentially distributed along at least one arc edge R and a plurality of effective GOA units sequentially distributed along a first side L1 connected to the arc edge R 101; Multiple GOA units include at least one valid GOA unit 101 and at least one dummy GOA unit 102; each valid GOA unit 101 is configured to provide at least one sub-pixel P with a driving signal (ie, scan signal or light emission control signal), At least one virtual GOA unit 102 is a GOA unit other than the valid GOA unit 101 among the plurality of GOA units.
  • a driving signal ie, scan signal or light emission control signal
  • the spacing between two adjacent GOA units among the plurality of GOA units sequentially distributed along at least one arc side R and the multiple effective GOAs sequentially distributed along a first side L1 connected to the arc side R is approximately the same.
  • the number of effective GOA units 101 and virtual GOA units 102 among the multiple GOA units sequentially distributed along the arc edge R is not limited, and the number of effective GOA units 101 and virtual GOA units 102 can be determined according to the space at the position close to the arc edge R in the peripheral area 2 The size selects the number of effective GOA units 101 and virtual GOA units 102 set.
  • the virtual GOA unit 102 may provide a driving signal to at least one virtual sub-pixel located in the peripheral area 2.
  • the virtual GOA unit 102 may not output a signal, that is, it may not provide a signal to any sub-pixel P.
  • the distribution mode of the effective GOA unit 101 and the virtual GOA unit 102 among the multiple GOA units sequentially distributed along the arc edge R is not limited.
  • Two specific examples are provided below.
  • the embodiments of the present disclosure include but are not limited to the following two examples.
  • At least one virtual GOA unit 102 is provided between two adjacent effective GOA units 101 among a plurality of GOA units sequentially distributed along at least one arc edge R.
  • one virtual GOA unit 102 can be set between two adjacent effective GOA units 101; two or more virtual GOA units 102 can also be set between two adjacent effective GOA units 101, which is not limited .
  • the number of virtual GOA units 102 can be selected according to the distance between two adjacent effective GOA units 101.
  • FIGS. 4A and 4B both take a virtual GOA unit 102 between two adjacent effective GOA units 101 as an example for illustration.
  • the GOA units at the two ends may all be valid GOA units 101 as shown in FIG. 4A; they may all be virtual GOA units 102 as shown in FIG. 4B; One end of the multiple GOA units sequentially distributed along the arc edge R is the effective GOA unit 101, and the other end is the virtual GOA unit 102.
  • any effective GOA unit 101 among the multiple GOA units sequentially distributed along at least one arc edge R is close to the multiple effective GOA units sequentially distributed along the first side edge L1 relative to all virtual GOA units 102 101.
  • the multiple GOA units sequentially distributed along at least one arc edge R include multiple effective GOA units 101
  • the multiple effective GOA units 101 are continuously arranged (that is, there is no difference between two adjacent effective GOA units 101.
  • a virtual GOA unit 102) is set, and the multiple effective GOA units 101 are close to the multiple effective GOA units sequentially distributed along the first side edge L1 relative to the virtual GOA unit 102 of the multiple GOA units sequentially distributed along at least one arc edge R Unit 101.
  • the multiple GOA units sequentially distributed along at least one arc edge R include multiple virtual GOA units 102
  • the multiple virtual GOA units 102 are continuously arranged (that is, no valid GOA is set between two adjacent virtual GOA units 102 Unit 101)
  • the multiple virtual GOA units 102 are far away from the multiple effective GOA units 101 sequentially distributed along the first side edge L1 relative to the effective GOA units 101 of the multiple GOA units sequentially distributed along at least one arc edge R.
  • any effective GOA unit 101 among the multiple GOA units distributed in sequence along at least one arc edge R is close to multiple effective GOA units 101 sequentially distributed along the first side edge L1, so that the signal can be reduced.
  • the length of the wire is conducive to the layout of the wire.
  • the GOA circuit 10 includes a plurality of effective GOA units 101 sequentially distributed along a first side L1. If the spacing between every two adjacent effective GOA units 101 is approximately the same, the surrounding A large blank area (that is, no wiring or device is provided) at a position close to the arc edge R in area 2 (that is, the position marked by the dashed circle in FIG. 5).
  • the concentration of the etching solution in the peripheral area 2 near the arc edge R and the peripheral area 2 except near the arc edge R will be significantly different, resulting in
  • the etching uniformity at the position close to the arc edge R in zone 2 is not good.
  • the position close to the arc edge R in the peripheral zone 2 will have problems such as over-etching, which will lead to close to the arc edge in the peripheral zone 2.
  • the effective GOA circuit 101 provided at the position of R has poor electrical performance (ie, poor electrical stability).
  • the GOA circuit 10 includes a plurality of effective GOAs sequentially distributed along a first side L1 and at least one arc side R connected to it.
  • Unit 101 the distance a between two adjacent effective GOA units 101 arranged at a position close to the arc edge R in the peripheral area 2 is greater than the phase set at other positions except the arc edge R in the peripheral area 2
  • the distance b between two adjacent effective GOA units 101 is greater than the phase set at other positions except the arc edge R in the peripheral area 2 The distance b between two adjacent effective GOA units 101.
  • the effective GOA unit 101 occupies a part of the space near the arc edge R in the peripheral area 2 to reduce the area of the blank area, thereby improving the etching uniformity at the position near the arc edge R in the peripheral area 2 It is not good and the electrical performance of the effective GOA circuit 101 arranged at a position close to the arc side R in the peripheral area 2 is poor.
  • An embodiment of the present disclosure provides an array substrate 100.
  • the GOA circuit 10 in the array substrate 100 includes: a plurality of GOA units sequentially distributed along at least one arc edge R and a first side edge connected to the arc edge R L1 multiple effective GOA units 101 distributed in sequence; multiple GOA units including at least one effective GOA unit 101 and at least one virtual GOA unit 102; two adjacent GOA units in multiple GOA units sequentially distributed along at least one arc edge R The distance between the units is approximately the same as the distance between two adjacent effective GOA units 101 among the plurality of effective GOA units 101 sequentially distributed along a first side L1 connected to the arc side R.
  • the GOA circuit 10 provided by the embodiment of the present disclosure includes not only the effective GOA unit 101, but also the virtual GOA unit 102, and the virtual GOA unit 102 occupies a part of the space near the arc edge R in the peripheral area 2, thereby reducing The area of the small blank area.
  • the spacing between two adjacent GOA units in the plurality of GOA units sequentially distributed along at least one circular arc side R and the multiple effective ones sequentially distributed along a first side L1 connected to the circular arc side R The spacing between two adjacent effective GOA units 101 in the GOA unit 101 is approximately the same, so the size of the blank area between any adjacent GOA units 101 is approximately the same.
  • peripheral area 2 is close to the arc edge
  • the problem of poor etching uniformity at the position of R, and the problem of poor electrical performance of the effective GOA circuit 101 arranged at a position close to the arc edge R in the peripheral area 2 is avoided.
  • both the effective GOA unit 101 and the virtual GOA unit 102 are mainly composed of transistors.
  • the specific settings of the effective GOA unit 101 and the virtual GOA unit 102 are not limited, and several possible implementation manners are provided below.
  • the effective GOA cell 101 includes multiple transistors, and at least one virtual GOA cell 102 includes multiple transistors; the number of transistors in at least one virtual GOA cell 102 is less than that in the effective GOA cell 101. Quantity.
  • the number of transistors in one virtual GOA unit 102 is less than the number of transistors in the effective GOA unit 101; it can also be part of a plurality of virtual GOA units 102 in each virtual GOA unit 102.
  • the number of transistors is less than the number of transistors in the effective GOA cell 101; of course, it is also possible that the number of transistors in each virtual GOA cell 102 in the plurality of virtual GOA cells 102 is less than the number of transistors in the effective GOA cell 101. This is not limited.
  • the present disclosure by setting the number of transistors in at least one dummy GOA cell 102 to be less than the number of transistors in the effective GOA cell 102, that is, compared with the effective GOA cell 101, the present disclosure reduces
  • the number of transistors in at least one virtual GOA unit 102 can free up part of the layout space in the peripheral area 2 near the arc edge R, which is beneficial to set the routing space in the peripheral area 2 near the arc edge R. This avoids problems such as short-circuiting of the traces set near the arc edge R in the peripheral area 2 due to the small space.
  • the area occupied by each GOA unit includes: a first area a1 and a second area a2; the effective GOA unit 101 includes a first area a1 arranged in the effective GOA unit 101 The first sub-circuit and the second sub-circuit disposed in the second area a2 of the effective GOA unit 102, the first sub-circuit includes a plurality of transistors, the second sub-circuit includes at least one transistor; at least one dummy GOA unit 102 includes The first sub-circuit of the first area a1 of each virtual GOA cell 102 does not include the second sub-circuit (that is, the second area a2 of at least one virtual GOA cell 102 is not provided with a transistor), and the second area of the virtual GOA cell 102 a2 is located in a half area close to the outer edge of the peripheral area 2 in the area occupied by the virtual GOA unit 102.
  • the center line M in FIGS. 6 and 7 divides the area occupied by the virtual GOA unit 102 into two areas of equal area.
  • the center line M to the left is half of the area occupied by the virtual GOA unit 102, and the center The line M to the right is half of the area occupied by the virtual GOA unit 102.
  • the areas other than the marked second area a2 in FIG. 6 and FIG. 7 are all the first area a1.
  • the peripheral area 2 includes two edges, an inner edge and an outer edge. Wherein, the inner edge overlaps with the edge of the display area 2.
  • the at least one virtual GOA unit 102 since at least one virtual GOA unit 102 does not include the second sub-circuit, compared to the effective GOA unit 101, the at least one virtual GOA unit 102 removes the transistors included in the second sub-circuit.
  • the first sub-circuit provided in the first area a1 of the effective GOA unit 101 has the same circuit structure as the first sub-circuit provided in the first area a1 of the virtual GOA unit 102.
  • the structure and connection relationship of the transistors (transistor M3 to transistor M7) provided in the first region a1 of the dummy GOA unit 102 are similar to the transistors provided in the first region a1 of the effective GOA unit 101 (transistor M3).
  • ⁇ Transistor M7) has the same structure and connection relationship.
  • the second area a2 of the virtual GOA unit 102 is located in the area occupied by the virtual GOA unit 102
  • the second sub-circuit that is, removing the transistors in the second area of the dummy GOA unit 102, which is close to the half area of the outer edge of the peripheral area 2
  • part of the space near the outer edge of the peripheral area 2 in the peripheral area 2 can be released. This is helpful for setting up wiring.
  • the setting position of the first area a1 in the virtual GOA unit 102 is not limited. As shown in FIG. 6, at least part of the first area a1 in the virtual GOA unit 102 is also close to the outer edge of the peripheral area 2, that is, at least part of the transistors in the first sub-circuit are close to the outer edge of the peripheral area 2. Of course, as shown in FIG. 7, the second area a2 of the virtual GOA unit 102 is closer to the outer edge of the peripheral area 2 than the first area a1.
  • the second area a2 of the virtual GOA unit 102 does not include the second sub-circuit, when the second area a2 of the virtual GOA unit 102 is closer to the outer edge of the peripheral area 2 than the first area a1, the virtual GOA unit 102 In the occupied area, the area close to the peripheral area 2 is completely free of transistors, so that a larger layout space can be released, thereby facilitating wiring.
  • the effective GOA unit 101 may include an input sub-circuit 201, a pull-down sub-circuit 202, a pull-up control sub-circuit 203, a pull-up sub-circuit 204, an output control sub-circuit 205, and an output sub-circuit 206.
  • the input sub-circuit 201 is connected to the signal input terminal Input, the first node N1, and the second clock signal terminal CK2.
  • the input sub-circuit 201 is configured to output the voltage of the signal input terminal Input to the first node N1 under the control of the voltage of the second clock signal terminal CK2.
  • the aforementioned input sub-circuit 201 may include a first transistor M1.
  • the gate of the first transistor M1 is connected to the second clock signal terminal CK2, the first electrode of the first transistor M1 is connected to the signal input terminal Input, and the second electrode of the first transistor M1 is connected to the first node N1.
  • the pull-down sub-circuit 202 is connected to the first voltage terminal VGL, the second node N2, and the second clock signal terminal CK2.
  • the pull-down sub-circuit 202 is configured to output the voltage of the first voltage terminal VGL to the second node N2 under the control of the voltage of the second clock signal terminal CK2.
  • the pull-down sub-circuit 202 described above may include a second transistor M2.
  • the gate of the second transistor M2 is connected to the second clock signal terminal CK2, the first electrode of the second transistor M2 is connected to the first voltage terminal VGL, and the second electrode of the second transistor M2 is connected to the second node N2.
  • the pull-up control sub-circuit 203 is connected to the first clock signal terminal CK1, the first node N1, the second node N2, and the second voltage terminal VGH.
  • the pull-up control sub-circuit 203 is configured to output the voltage of the second voltage terminal VGH to the first node N1 under the control of the voltage of the first clock signal terminal CK1 and the second node N2.
  • the above-mentioned pull-up control sub-circuit 203 may include a third transistor M3 and a fourth transistor M4.
  • the gate of the third transistor M3 is connected to the second node N2
  • the first electrode of the third transistor M3 is connected to the second voltage terminal VGH
  • the second electrode of the third transistor M3 is connected to the second electrode of the fourth transistor M4
  • the first pole of the fourth transistor M4 is connected to the first node N1
  • the gate of the fourth transistor M4 is connected to the first clock signal terminal CK1.
  • the pull-up sub-circuit 204 is connected to the second node N2, the second voltage terminal VGH, and the signal output terminal Output.
  • the pull-up sub-circuit 204 is configured to output the voltage of the second voltage terminal VGH to the signal output terminal Output under the control of the voltage of the second node N2.
  • the above-mentioned pull-up sub-circuit 204 may include a fifth transistor M5.
  • the gate of the fifth transistor M5 is connected to the second node N2, the first electrode of the fifth transistor M5 is connected to the second voltage terminal VGH, and the second electrode of the fifth transistor M5 is connected to the signal output terminal Output.
  • the above-mentioned output control sub-circuit 205 is connected to the first node N1, the first voltage terminal VGL, and the output sub-circuit 206.
  • the output control sub-circuit 205 is configured to control the on-off between the output sub-circuit 206 and the first node N1 through the voltage of the first voltage terminal VGL.
  • the aforementioned output control sub-circuit 205 may include a sixth transistor M6.
  • the gate of the sixth transistor M6 is connected to the first voltage terminal VGL, the first electrode of the sixth transistor M6 is connected to the first node N1, and the second electrode of the sixth transistor M6 is connected to the output sub-circuit 206.
  • the output sub-circuit 206 is connected to the output control sub-circuit 205, the first clock signal terminal CK1, and the signal output terminal Output.
  • the output sub-circuit 206 is configured to output the voltage of the first clock signal terminal CK1 to the signal output terminal Output under the control of the voltage of the first node N1 when the output sub-circuit 205 is turned on.
  • the above-mentioned output sub-circuit 206 may include a seventh transistor M7.
  • the gate of the seventh transistor M7 is connected to the output control sub-circuit 205 (the second pole of the sixth transistor M6), the first pole of the seventh transistor M7 is connected to the first clock signal terminal CK1, and the first pole of the seventh transistor M7 The two poles are connected to the signal output terminal Output.
  • the transistors in the present disclosure may be enhancement type transistors or depletion type transistors.
  • the source and drain in a transistor are usually symmetrical in structure and composition, there is no difference between the source and drain.
  • one of the electrodes is called the source and the other is called the drain. Based on this, it can be the source of the first electrode and the drain of the second electrode; it can also be the drain of the first electrode and the source of the second electrode.
  • the effective GOA unit 101 in the effective GOA unit 101, at least some of the transistors in the input sub-circuit 201 and/or the pull-down sub-circuit 202 are At least part of the transistors in are located in the second area of the effective GOA cell 101.
  • the effective GOA unit 101 includes the second sub-circuit provided in the second area of the effective GOA unit 101, the second sub-circuit includes at least part of the transistors in the input sub-circuit 201 and/or at least part of the pull-down sub-circuit 202. Transistor.
  • the virtual GOA unit described above includes the first sub-circuit provided in the first area of each virtual GOA unit, and does not include the second sub-circuit, that is to say, the virtual GOA unit does not include the aforementioned input sub-circuit 201
  • At least part of the transistors and/or at least part of the transistors in the aforementioned pull-down sub-circuit 202 that is, the virtual GOA unit deletes at least part of the transistors in the aforementioned input sub-circuit 201 and/or at least part of the transistors in the aforementioned pull-down sub-circuit 202, so As a result, part of the space can be released, which is conducive to wiring.
  • the pull-down sub-circuit 202 includes the second transistor M2; the input sub-circuit 201 and the pull-down sub-circuit 202 are both located in the second area a2.
  • the dummy GOA unit 102 since the second area a2 of the dummy GOA unit 102 is not provided with the second sub-circuit, the dummy GOA unit 102 does not include the first transistor M1 and the second transistor M2. That is, the dummy GOA unit 102 removes the first transistor M1 and the second transistor M2 from the effective GOA unit 101.
  • the pull-up control sub-circuit 203 in the effective GOA unit 101 may include: a first control unit 2031 and a second control unit 2032.
  • the first control unit 2031 is connected to the second node N2, the second voltage terminal VGH, and the second control unit 2032; the second control unit 2032 is also connected to the first node N1 and the first clock signal terminal CK1.
  • the first control unit 2031 includes a third transistor M3, and the second control unit 2032 includes a fourth transistor M4.
  • the pull-up control sub-circuit 203 includes a first control unit 2031 and a second control unit 2032
  • the effective GOA unit 101 at least part of the transistors and/or transistors in the above-mentioned first control unit 2031 At least part of the transistors in the second control unit 2032 are located in the second area of the effective GOA unit 101. Since the second area a2 of the virtual GOA unit 101 does not include the second sub-circuit, that is to say, the virtual GOA unit 101 does not include at least part of the transistors in the first control unit 2031 and/or at least part of the second control unit 2032. The transistor, that is, the virtual GOA unit 101 deletes at least part of the transistors in the first control unit 2031 and/or at least part of the transistors in the second control unit 2032.
  • each effective GOA unit 101 includes multiple transistors coupled through multiple signal transmission paths; at least one virtual GOA unit 102 includes multiple transistors, and each virtual GOA unit 102 includes multiple transistors.
  • Transistors correspond to the positions of the plurality of transistors in the effective GOA unit 101; in at least one dummy GOA unit 102, at least one of the plurality of signal transmission paths coupled to the plurality of transistors is compared to the corresponding position of the effective GOA unit 101 The signal transmission path is disconnected.
  • At least one of the multiple signal transmission paths coupled to multiple transistors is off compared to the signal transmission path at the corresponding position of the effective GOA unit.
  • the signal transmission path that is open and disconnected does not generate heat because there is no current flow, so the heat dissipation effect is improved.
  • the positions of the multiple transistors in each virtual GOA unit 102 correspond to the multiple transistors in the effective GOA unit 101" means that if the first transistor M1 in the virtual GOA unit 102 is located in the area occupied by the virtual GOA unit 102 In the upper left corner, the first transistor M1 in the effective GOA unit 101 is also located in the upper left corner of the area occupied by the effective GOA unit 101.
  • each effective GOA unit 101 is coupled together through multiple signal transmission paths.
  • the second transistor M2 and the third transistor M3 are coupled through the signal transmission path bc.
  • the second transistor M2 and the fifth transistor M5 are coupled through the signal transmission path bd.
  • the first transistor M1 and the sixth transistor M6 are coupled through the signal transmission path ef.
  • the disconnection position of the signal transmission path is not limited. Taking the structure of the effective GOA unit 101 as shown in FIG. 9 as an example, with respect to FIG. 9, as shown in FIG. 12, for example, the signal transmission path bc between the second transistor M2 and the third transistor M3 can be disconnected . For another example, the signal transmission path bd between the second transistor M2 and the fifth transistor M5 may be disconnected. For another example, the signal transmission path ef between the first transistor M1 and the sixth transistor M6 may be used.
  • the area occupied by each GOA unit includes: a first area a1 and a second area a2; the GOA unit includes at least one transistor disposed in the first area a1 and at least one transistor disposed in the second area a2;
  • the at least one virtual GOA unit 102 at least one of the signal transmission paths coupled to the transistor located in the second region a2 is disconnected compared to the signal transmission path at the corresponding position of the effective GOA unit 101; the virtual GOA unit 102
  • the second area of is located in a half area close to the outer edge of the peripheral area 2 in the area occupied by the virtual GOA unit 102.
  • first area a1 of the virtual GOA unit 102 are consistent with the structure and connection relationship of the first area a1 of the effective GOA unit 101.
  • the structure and connection relationship of the transistors (transistor M3 to transistor M7) provided in the first area a1 of the virtual GOA unit 102 are similar to the transistors provided in the first area a1 of the effective GOA unit 101 (transistor M3).
  • ⁇ Transistor M7) has the same structure and connection relationship.
  • At least one of the signal transmission paths coupled to the transistor located in the second area a2 is disconnected compared to the signal transmission path at the corresponding position of the effective GOA unit 101, that is, The broken signal transmission path is located in a half area close to the outer edge of the peripheral area 2 in the area occupied by the virtual GOA unit 102.
  • the effective GOA unit 101 in the effective GOA unit 101, at least some of the transistors in the input sub-circuit 201 and/or at least some of the transistors in the pull-down sub-circuit 202 are located The second area a2 of the effective GOA unit 101.
  • the second area a2 of the virtual GOA cell 102 includes at least part of the transistors and/or pull-down sub-circuits in the input sub-circuit 201 At least part of the transistors in 202, and at least one of the signal transmission paths coupled to the transistors located in the second area a2 is disconnected compared to the signal transmission path at the corresponding position of the effective GOA unit 101, so as shown in FIG.
  • the signal transmission path coupled to the input sub-circuit 201 and/or the pull-up sub-circuit 202 is disconnected, that is, with at least part of the transistors in the input sub-circuit 201 and/or with the pull-up sub-circuit 202 At least part of the signal transmission paths coupled to the transistors are disconnected.
  • the input sub-circuit 201 includes a first transistor M1
  • the pull-up sub-circuit 202 includes a second transistor M2.
  • the signal transmission path ef coupled to the first transistor M1 is disconnected, and/or is connected to the second transistor M2.
  • the coupled signal transmission path bd and signal transmission path bc are disconnected.
  • the pull-up control sub-circuit 203 includes a first control unit 2031 and a second control unit 2032, at least some of the transistors in the first control unit 2031 and/or the transistors in the second control unit 2032 are At least part of the transistors are located in the second area a2 of the effective GOA cell 101.
  • the second area a2 of the virtual GOA cell 102 includes the first At least part of the transistors in a control unit 2031 and/or at least part of the transistors in the above-mentioned second control unit 2032, and at least one of the signal transmission paths coupled to the transistors located in the second area a2 is compared with the effective GOA unit 101
  • the signal transmission path at the corresponding position is disconnected, so as shown in FIG. 11, the signal transmission path coupled to the first control unit 2031 and/or the second control unit 2032 is disconnected, that is, as shown in FIG. 12
  • the signal transmission path coupled to at least part of the transistors in the first control unit 2031 and/or to at least part of the transistors in the second control unit 2032 is disconnected.
  • the signal transmission path coupled to the third transistor M3 and the signal transmission path coupled to the fourth transistor M4 are disconnected.
  • the broken signal transmission path is located near the area occupied by the virtual GOA unit 102
  • the half area of the outer edge of the peripheral area 2 can reduce the heat generated by the current flow of the signal transmission path and improve the heat dissipation effect, thereby avoiding the influence on the wiring arranged on the side of the GOA unit near the outer edge of the peripheral area 2.
  • the second area a2 of the virtual GOA unit 102 is closer to the outer edge of the peripheral area 2 than the first area a1.
  • the second area a2 of the virtual GOA unit 102 is closer to the outer edge of the peripheral area 2 than the first area a1
  • the position where the signal transmission path is disconnected is close to the outer edge of the peripheral area 2
  • the wiring on the array substrate 100 is usually It will pass the GOA unit on the side close to the outer edge of the peripheral area 2, so it is possible to further avoid affecting the wiring arranged on the side of the GOA unit close to the outer edge of the peripheral area 2.
  • the virtual GOA unit 102 includes multiple transistors
  • the effective GOA unit 101 includes multiple transistors
  • the multiple transistors in each virtual GOA unit 102 correspond to the positions of the multiple transistors in the effective GOA unit 101 , And the connection relationship of the corresponding transistors is the same.
  • a gate signal may be input to the gate of at least one transistor in the dummy GOA unit 102, so that the at least one transistor is always in an off state.
  • a high-level signal may be input to the gate of the N-type transistor to make the N-type transistor in an off state.
  • no gate signal may be input to the gate of at least one transistor in the dummy GOA unit 102, so that the at least one transistor is always in an off state.
  • the structure of the virtual GOA unit 102 is the same as the structure of the effective GOA unit 101, and both have the structure shown in FIG. 9.
  • first clock signal terminal CK1 and the second clock signal terminal CK2 can be connected to the clock signal line. In this way, the transistors whose gates are connected to the first clock signal terminal CK1 and the second clock signal terminal CK2 will always be in an off state because the gates of the transistors are not input with a strobe signal. Referring to FIG. 9, if the first clock signal terminal CK1 and the second clock signal terminal CK2 are not connected to the clock signal line, the first transistor M1, the second transistor M2, and the fourth transistor M4 will always be in an off state.
  • each GOA unit includes: a first area a1 and a second area a2.
  • the transistors arranged in the second area a2 of the dummy GOA unit 102 are in an off state.
  • the second area a2 of the virtual GOA unit 102 is closer to the outer edge of the peripheral area 2 than the first area a1. Further, in some embodiments, the second area a2 of the virtual GOA unit 102 is closer to the outer edge of the peripheral area 2 than the first area a1.
  • the second area a2 of the dummy GOA unit 102 Since the transistors in the second area a2 of the dummy GOA unit 102 are in an off state, the second area a2 of the dummy GOA unit 102 does not generate heat, so that the heat dissipation effect can be improved.
  • the array substrate 100 is also provided with other related signal lines, such as clock signal line CLK, power supply voltage signal line VDD, etc. You can refer to related technologies, which will not be repeated here.

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Abstract

一种阵列基板(100),具有显示区(1)以及位于显示区(1)外侧的周边区(2)；显示区(1)包括两条大致平行的第一侧边(L1和L1')和与每条第一侧边(L1和L1')的至少一端连接的圆弧边(R)。阵列基板(100)包括至少一个栅极驱动电路(10)。每个栅极驱动电路(10)包括沿至少一条圆弧边(R)依次分布的多个GOA单元以及沿与该圆弧边(R)连接的一条第一侧边(L1)依次分布的多个有效GOA单元(101)；多个GOA单元包括至少一个有效GOA单元(101)和至少一个虚拟GOA单元(102)；每个有效GOA单元(101)被配置为给至少一个亚像素（P）提供驱动信号，至少一个虚拟GOA单元(102)为多个GOA单元中除多个有效GOA单元(101)以外的GOA单元；沿至少一条圆弧边(R)依次分布的多个GOA单元中相邻两个GOA单元之间的间距和沿与该圆弧边(R)连接的一条第一侧边(L1)依次分布的多个有效GOA单元(101)中相邻两个有效GOA单元(101)之间的间距大致相同。

Description

阵列基板、显示面板及显示装置
本申请要求于2019年7月23日提交的、申请号为201921162475.5的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
背景技术
如图1所示，近年来，具有R角(也即圆角或者倒圆角)的显示面板迎来了广泛的应用，为了窄化边框，显示面板一般多采用GOA(Gate Driver on Array)技术，即将栅极驱动电路(也可以称为GOA电路)制作于显示面板中阵列基板的衬底基板上。其中，栅极驱动电路包括多个与显示面板中的多条驱动信号线如栅线一一对应连接的GOA单元(也可以称为移位寄存器)。
公开内容
一方面，提供一种阵列基板。该阵列基板具有显示区以及位于所述显示区外侧的周边区；所述显示区包括两条大致平行的第一侧边和与每条所述第一侧边的至少一端连接的圆弧边。所述阵列基板包括：设置于所述显示区的多个亚像素以及设置于所述周边区的至少一个栅极驱动电路。每个栅极驱动电路包括：沿至少一条所述圆弧边依次分布的多个GOA单元以及沿与该所述圆弧边连接的一条所述第一侧边依次分布的多个有效GOA单元；所述多个GOA单元包括至少一个有效GOA单元和至少一个虚拟GOA单元；每个有效GOA单元被配置为给至少一个所述亚像素提供驱动信号，所述至少一个虚拟GOA单元为所述多个GOA单元中除有效GOA单元以外的GOA单元；其中，沿至少一条所述圆弧边依次分布的多个GOA单元中相邻两个GOA单元之间的间距和沿与该所述圆弧边连接的一条所述第一侧边依次分布的多个有效GOA单元中相邻两个有效GOA单元之间的间距大致相同。
在一些实施例中，沿至少一条所述圆弧边依次分布的多个GOA单元中相邻两个有效GOA单元之间设置至少一个虚拟GOA单元。
在一些实施例中，沿至少一条所述圆弧边依次分布的多个GOA单元中任一个有效GOA单元相对于所有的虚拟GOA单元靠近沿第一侧 边依次分布的多个有效GOA单元。
在一些实施例中，所述有效GOA单元包括多个晶体管；所述至少一个虚拟GOA单元包括多个晶体管；所述至少一个虚拟GOA单元中晶体管的数量少于所述有效GOA单元中晶体管的数量。
在一些实施例中，每个GOA单元所占区域包括：第一区域和第二区域；所述有效GOA单元包括设置在所述有效GOA单元的第一区域的第一子电路和设置于所述有效GOA单元的第二区域的第二子电路，所述第一子电路包括多个晶体管，所述第二子电路包括至少一个晶体管；至少一个虚拟GOA单元包括设置在每个虚拟GOA单元的第一区域的第一子电路，且不包含所述第二子电路，所述虚拟GOA单元的第二区域位于所述虚拟GOA单元所占区域中的靠近所述周边区的外边缘的一半区域。
在一些实施例中，每个所述有效GOA单元包括通过多个信号传输通路相耦接的多个晶体管；至少一个虚拟GOA单元包括多个晶体管，每个虚拟GOA单元中多个晶体管与所述有效GOA单元中多个晶体管的位置对应；在所述至少一个虚拟GOA单元中，与多个晶体管耦接的多个信号传输通路中的至少一个相比于所述有效GOA单元的相应位置处的信号传输通路是断开的。
在一些实施例中，每个GOA单元所占区域包括：第一区域和第二区域；所述GOA单元包括设置于所述第一区域的至少一个晶体管和设置于所述第二区域的至少一个晶体管；所述至少一个虚拟GOA单元中，与位于所述第二区域的晶体管耦接的信号传输通路中的至少一个相比于所述有效GOA单元的相应位置处的信号传输通路是断开的；所述虚拟GOA单元的第二区域位于所述虚拟GOA单元所占区域中的靠近所述周边区的外边缘的一半区域。
在一些实施例中，所述虚拟GOA单元的第二区域相比于第一区域靠近所述周边区的外边缘。
在一些实施例中，所述有效GOA单元包括输入子电路、下拉子电路、上拉控制子电路、上拉子电路、输出控制子电路、输出子电路；所述输入子电路与信号输入端、第一节点、第二时钟信号端连接；所述输入子电路配置为在所述第二时钟信号端的电压的控制下，将所述信号输入端的电压输出至所述第一节点；所述下拉子电路与第一电压端、第二 节点、所述第二时钟信号端连接；所述下拉子电路配置为在所述第二时钟信号端的电压的控制下，将所述第一电压端的电压输出至所述第二节点；所述上拉控制子电路与第一时钟信号端、所述第一节点、所述第二节点、第二电压端连接；所述上拉控制子电路配置为在所述第一时钟信号端和所述第二节点的电压的控制下，将所述第二电压端的电压输出至所述第一节点；所述上拉子电路与所述第二节点、所述第二电压端、信号输出端连接；所述上拉子电路配置为在所述第二节点的电压的控制下，将所述第二电压端的电压输出至所述信号输出端；所述输出控制子电路与所述第一节点、所述第一电压端、所述输出子电路连接；所述输出控制子电路配置为通过第一电压端的电压控制所述输出子电路与所述第一节点之间的通断；所述输出子电路与所述输出控制子电路、所述第一时钟信号端、所述信号输出端连接；所述输出子电路配置为在所述输出子电路导通时，在所述第一节点的电压的控制下，将所述第一时钟信号端的电压输出至所述信号输出端。
在一些实施例中，在每个GOA单元所占区域包括第一区域和第二区域的情况下，在所述有效GOA单元中，所述输入子电路中的至少部分晶体管和/或所述下拉子电路中的至少部分晶体管位于所述有效GOA单元的第二区域。
在一些实施例中，所述上拉控制子电路包括第一控制单元和第二控制单元；所述第一控制单元与所述第二节点、所述第二电压端、所述第二控制单元连接；所述第二控制单元还与所述第一节点和所述第一时钟信号端连接；在所述有效GOA单元中，所述第一控制单元中的至少部分晶体管和/或所述第二控制单元中的至少部分晶体管位于所述有效GOA单元的第二区域。
在一些实施例中，所述阵列基板包括两个GOA电路；两个所述GOA电路分别位于两条所述第一侧边和与每条所述第一侧边的至少一端连接的圆弧边的外侧的周边区中。
另一方面，提供一种显示面板。所述显示面板包括：如上述任一实施例所述的阵列基板。
再一方面，本公开实施例还提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开或相关技术中的技术方案，下面将对本公开的一些实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图。对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为本公开提供的一种异型显示面板的结构图；
图2为本公开的一些实施例提供的一种显示面板(阵列基板)的结构图；
图3为本公开的一些实施例提供的一种OLED的结构图；
图4A为图2中一种A1处的放大结构图；
图4B为图2中另一种A1处的放大结构图；
图4C为图2中又一种A1处的放大结构图；
图5为相关技术提供的一种阵列基板的局部结构图；
图6本公开的一些实施例提供的一种虚拟GOA电路和有效GOA电路的区域划分图；
图7本公开的一些实施例提供的另一种虚拟GOA电路和有效GOA电路的区域划分图；
图8为本公开的一些实施例提供的一种有效GOA单元的结构图；
图9为本公开的一些实施例提供的一种有效GOA单元的电路结构图；
图10本公开的一些实施例提供的一种虚拟GOA单元的电路结构图；
图11本公开的一些实施例提供的一种虚拟GOA单元的结构图；
图12本公开的一些实施例提供的另一种虚拟GOA单元的电路结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包 括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”以及类似的词语仅用于区分不同的组成部分，而不能理解为指示或暗示任何顺序、相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于 额外条件或超出所述的值。
如本文所使用的那样，“约”、“近似”或“大致”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
此外，本申请中，“上”、“下”、“左”、“右”、“水平”以及“竖直”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
本公开实施例提供一种显示装置，该显示装置可以为电视、手机、台式电脑、笔记本电脑、平板电脑、个人数字助理(personal digital assistant，PDA)、车载电脑等。本公开实施例对上述显示装置的具体形式不做特殊限定。附图1以显示装置为手机为例进行示意。
本公开实施例提供的显示装置至少包括显示面板。该显示面板包括阵列基板、栅极驱动电路、源极驱动电路、时序控制电路(TCON)、印刷电路版(Printed Circuit Board，PCB)、柔性电路板(Flexible Printed Circuit Board，FPC)以及其他电子配件等。
上述显示面板可以为有机发光二极管(Organic Light Emitting Diode，OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示面板或微发光二极管(Micro Light Emitting Diodes，Micro LED)显示面板等，本公开对此不做具体限定。
OLED显示面板因其具有自发光、轻薄、功耗低、高对比度、高色域、可实现柔性显示等优点，受到广泛的关注，OLED显示面板也被誉为新一代显示技术。为了方便说明，本公开以下实施例均是以上述显示面板为OLED显示面板为例，对本公开进行说明。
图2为本公开的一些实施例提供的一种显示面板的结构图。参考图2，该显示面板001包括：显示区(active area，称为AA区；也可称为有效显示区)1和位于显示区1外侧的周边区2。附图2以周边区2围绕显示区1设置一圈为例进行示意。
参考图2所示，上述显示面板001中设置有多条栅线(Gate Line)GL和多条数据线(Data Line)DL，并且多条栅线GL和多条数据线DL在显示区1交叉界定出多个亚像素(sub pixel)P。
上述位于显示区1的多个亚像素P至少包括：第一颜色亚像素、第二颜色亚像素和第三颜色亚像素。其中，第一颜色、第二颜色和第三颜色为三基色(例如红色、绿色和蓝色)。
为了方便说明，本申请中，上述多个亚像素P是以矩阵形式排列为例进行的说明。在此情况下，栅线GL沿水平方向X延伸，数据线DL沿竖直方向Y延伸；并将沿水平方向X排列成一排的亚像素P称为同一行亚像素；将沿竖直方向Y排列成一排的亚像素P称为同一列亚像素。
另外，如图2所示，每个亚像素P中均设置有像素电路S(也可称为像素驱动电路)，该像素电路S包括驱动单元和发光单元。
上述驱动单元包括晶体管和电容，图2中仅是示意的以该像素电路S中的驱动单元为2T1C(即包括一个驱动晶体管Md、一个开关晶体管Ms和一个存储电容Cst)结构为例说明的，但本公开并不限制于此，在一些实施例中驱动单元还可以采用3T1C、4T1C等电路结构。
上述发光单元包括有机发光二极管OLED。参考图3所示，OLED包括阴极11和阳极12，以及位于阴极11和阳极12之间的发光功能层13。其中，发光功能层13可以包括有机发光层(Emission layer，EML)，还可以包括位于有机发光层EML和阳极12之间的空穴传输层(Hole Transport Layer，HTL)和/或位于有机发光层EML和阴极11之间的电子传输层(Electron Transport Layer，ETL)。当然，根据需要，在一些实施例中，还可以在空穴传输层HTL和阳极12之间设置空穴注入层(Hole Injection Layer，HIL)，和/或，在电子传输层ETL和阴极11之间设置电子注入层(Electron Injection Layer，EIL)等，本公开对此不做限定。
在显示时，通过控制施加在阴极11和阳极12上的电压，利用阳极12注入空穴，阴极11注入电子，所形成的电子和空穴在有机发光层EML相遇而产生激子，从而激发有机发光层EML发光；通过亚像素P的像素电路S中的驱动子电路控制阴极11和阳极12形成的电流通路中驱动电流的大小，进而使得有机发光层EML的发光亮度不同，以实现不同的灰阶显示。
在此基础上，如图2所示，显示面板001在周边区2还设置有与驱动信号线如栅线GL连接的栅极驱动电路(也可以称为GOA电路) 10(本公开实施例附图均以栅线GL与栅极驱动电路10连接为例示意)，以及与数据线DL连接的数据驱动电路20。上述驱动信号线例如可以为栅线或发光控制线。
在一些实施例中，上述栅极驱动电路10可以设置在沿栅线GL的延伸方向上的周边区2，数据驱动电路20可以设置在沿数据线DL的延伸方向上的周边区2。通过栅极驱动电路10逐行开启像素电路S，并在一行像素电路S开启时，通过数据驱动电路20将像素数据电压写入至该行的各像素电路S中，以进行画面显示。
本公开的实施例中，为了窄化显示装置的边框宽度，降低制作成本，将上述栅极驱动电路10直接集成在显示面板001中的阵列基板上。
由于显示面板001中的阵列基板的结构图，与图2中示出的显示面板001的结构图基本一致(但不代表两者的结构相同)，以下结合图2，对本公开中的阵列基板100以及位于阵列基板100的衬底基板上的GOA电路10的设置做进一步的说明。
对于本公开实施例提供的异型显示面板001(也可以是显示装置或阵列基板)而言，如图2所示，显示区1包括两条大致平行的第一侧边L1和两条大致平行的第二侧边L2，第一侧边L1和第二侧边L2大致垂直，且每条第一侧边L的至少一端通过圆弧边R(也可以称为圆角、倒圆角或R角)与第二侧边L2连接。也即本公开中显示面板001的显示区1至少设置有两个R角。
在一些实施例中，显示区1可以包括多个R角。
示例的，如图2所示，在一些实施例中，显示区1可以包括两条大致平行的第一侧边(L1和L1’)，以及两条大致平行的第二侧边(L2和L2’)，第一侧边L1和第二侧边L2大致垂直，每条第一侧边(L1和L1’)的两端与两条第二侧边(L2和L2’)分别通过R角连接。在此情况下，显示区1包括4个R角。
示例的，在另一些实施例中，显示区1可以包括两条大致平行的第一侧边(L1和L1’)，以及两条大致平行的第二侧边(L2和L2’)，第一侧边L1和第二侧边L2大致垂直，两条第一侧边(L1和L1’)与一条第二侧边(L2)分别通过R角连接。在此情况下，显示区1包括2个R角。
以下实施例均是以图2中示出的显示区1包括4个R角为例，对 本公开作进一步的说明。
在一些实施例中，如图2所示，阵列基板100在显示区1位于栅线GL延伸方向上两侧的周边区2分别设置有GOA电路10。当然，在一些实施例中，也可以仅在显示区1位于沿栅线GL延伸方向上的一侧的周边区2设置GOA电路。
在此情况下，对于设置于阵列基板100的衬底基板上的单个GOA电路10而言，如图4A、图4B和图4C(图4A、图4B和图4C为图2中A1区域的局部放大图)所示，该GOA电路10包括：沿至少一条圆弧边R依次分布的多个GOA单元以及沿与该圆弧边R连接的一条第一侧边L1依次分布的多个有效GOA单元101；多个GOA单元包括至少一个有效GOA单元101和至少一个虚拟GOA单元102；每个有效GOA单元101被配置为给至少一个亚像素P提供驱动信号(即，扫描信号或发光控制信号)，至少一个虚拟GOA单元102为多个GOA单元中除有效GOA单元101以外的GOA单元。
其中，沿至少一条圆弧边R依次分布的多个GOA单元中相邻两个GOA单元之间的间距和沿与该圆弧边R连接的一条第一侧边L1依次分布的多个有效GOA单元101中相邻两个有效GOA单元101之间的间距大致相同。
需要说明的是，对于沿圆弧边R依次分布的多个GOA单元中有效GOA单元101和虚拟GOA单元102的数量不进行限定，可以根据周边区2中靠近圆弧边R的位置处的空间大小选择设置的有效GOA单元101和虚拟GOA单元102的数量。
此处，虚拟GOA单元102可以给位于周边区2的至少一个虚拟亚像素提供驱动信号，当然，虚拟GOA单元102也可以不输出信号，即不给任何亚像素P提供信号。
在此基础上，对于沿圆弧边R依次分布的多个GOA单元中有效GOA单元101和虚拟GOA单元102的分布方式不做限定。以下提供两种具体的示例。本公开实施例包括但不限于以下两种示例。
示例一
如图4A和图4B所示，沿至少一条圆弧边R依次分布的多个GOA单元中相邻两个有效GOA单元101之间设置至少一个虚拟GOA单元102。
此处，相邻两个有效GOA单元101之间可以设置一个虚拟GOA单元102；相邻两个有效GOA单元101之间也可以设置两个或两个以上虚拟GOA单元102，对此不做限定。可以根据相邻两个有效GOA单元101之间的间距选择设置的虚拟GOA单元102的数量。附图4A和图4B均以相邻两个有效GOA单元101之间设置一个虚拟GOA单元102为例进行示意。
此外，沿圆弧边R依次分布的多个GOA单元中位于两端的GOA单元可以如图4A所示均是有效GOA单元101；也可以如图4B所示均是虚拟GOA单元102；当然还可以是沿圆弧边R依次分布的多个GOA单元中的一端是有效GOA单元101，另一端是虚拟GOA单元102。
示例二
如图4C所示，沿至少一条圆弧边R依次分布的多个GOA单元中任一个有效GOA单元101相对于所有的虚拟GOA单元102靠近沿第一侧边L1依次分布的多个有效GOA单元101。
此处，在沿至少一条圆弧边R依次分布的多个GOA单元包括多个有效GOA单元101的情况下，多个有效GOA单元101连续设置(即相邻两个有效GOA单元101之间不设置虚拟GOA单元102)，且多个有效GOA单元101相对于沿至少一条圆弧边R依次分布的多个GOA单元中的虚拟GOA单元102靠近沿第一侧边L1依次分布的多个有效GOA单元101。在沿至少一条圆弧边R依次分布的多个GOA单元包括多个虚拟GOA单元102的情况下，多个虚拟GOA单元102连续设置(即相邻两个虚拟GOA单元102之间不设置有效GOA单元101)，多个虚拟GOA单元102相对于沿至少一条圆弧边R依次分布的多个GOA单元中的有效GOA单元101远离沿第一侧边L1依次分布的多个有效GOA单元101。
本公开实施例中，由于有效GOA单元101被配置为给位于显示区1的亚像素P提供驱动信号，因而有效GOA单元101与显示区1的亚像素P之间需要设置信号线，而若沿至少一条圆弧边R依次分布的多个GOA单元中任一个有效GOA单元101相对于所有的虚拟GOA单元102靠近沿第一侧边L1依次分布的多个有效GOA单元101，则可以减小信号线的长度，有利于布置走线。
对于上述显示面板1，由于显示区1的每条第一侧边L的至少一端 通过圆弧边R与第二侧边L2连接，因而周边区2中靠近圆弧边R的位置处的空间会较大。相关技术中的GOA电路在设计时，GOA电路10包括沿一条第一侧边L1依次分布的多个有效GOA单元101，若每相邻两个有效GOA单元101之间的间距大致相同，则周边区2中靠近圆弧边R的位置处(即图5虚线圈所标示的位置)会空出的较大的空白区域(即不设置任何走线或器件)。这样一来，在构图过程中，刻蚀液在周边区2中靠近圆弧边R的位置处和周边区2中除靠近圆弧边R以外的其它位置处的浓度会明显不同，从而导致周边区2中靠近圆弧边R的位置处的刻蚀均一性不好，例如周边区2中靠近圆弧边R的位置处会出现过刻等问题，进而导致在周边区2中靠近圆弧边R的位置处设置的有效GOA电路101的电性能差(即电学稳定性差)。
为了解决上述问题，相关技术在改进GOA电路10的设计时，如图5所示，GOA电路10包括沿一条第一侧边L1和与其连接的至少一条圆弧边R依次分布的多个有效GOA单元101，在周边区2中靠近圆弧边R的位置处设置的相邻两个有效GOA单元101之间的间距a大于周边区2中除靠近圆弧边R以外的其它位置处设置的相邻两个有效GOA单元101之间的间距b。这样有效GOA单元101会占据周边区2中靠近圆弧边R的位置处的部分空间，减小空白区域的面积，从而可以改善周边区2中靠近圆弧边R的位置处的刻蚀均一性不好以及在周边区2中靠近圆弧边R的位置处设置的有效GOA电路101的电性能差的问题。
然而，由于在周边区2中靠近圆弧边R的位置处设置的相邻有效GOA单元101之间的间距a和在周边区2中除靠近圆弧边R以外的其它位置处设置的相邻两个有效GOA单元101之间的间距b不同，从而在周边区2中靠近圆弧边R的位置处设置的相邻有效GOA单元101之间的空白区域和在周边区2中除靠近圆弧边R以外的其它位置处设置的相邻两个有效GOA单元101之间的空白区域的大小就会不同，因而还是会存在周边区2中靠近圆弧边R的位置处刻蚀均一性不好以及在周边区2中靠近圆弧边R的位置处设置的有效GOA电路101的电性能差的问题。
本公开实施例提供一种阵列基板100，阵列基板100中的GOA电路10包括：沿至少一条圆弧边R依次分布的多个GOA单元以及沿与 该圆弧边R连接的一条第一侧边L1依次分布的多个有效GOA单元101；多个GOA单元包括至少一个有效GOA单元101和至少一个虚拟GOA单元102；沿至少一条圆弧边R依次分布的多个GOA单元中相邻两个GOA单元之间的间距和沿与该圆弧边R连接的一条第一侧边L1依次分布的多个有效GOA单元101中相邻两个有效GOA单元101之间的间距大致相同。由于本公开实施例提供的GOA电路10不仅包括有效GOA单元101，还包括虚拟GOA单元102，而虚拟GOA单元102会占据周边区2中靠近圆弧边R的位置处的部分空间，从而可以减小空白区域的面积。此外，由于沿至少一条圆弧边R依次分布的多个GOA单元中相邻两个GOA单元之间的间距和沿与该圆弧边R连接的一条第一侧边L1依次分布的多个有效GOA单元101中相邻两个有效GOA单元101之间的间距大致相同，因而任意相邻GOA单元101之间的空白区域的大小大致相同，这样一来，避免了周边区2中靠近圆弧边R的位置刻蚀均一性不好的问题，且避免了在周边区2中靠近圆弧边R的位置处设置的有效GOA电路101的电性能差的问题。
可以理解的是，无论对于有效GOA单元101，还是虚拟GOA单元102，其均主要由晶体管构成。对于有效GOA单元101和虚拟GOA单元102的具体设置不进行限定，以下提供几种可能的实现方式。
在第一种可能的实现方式中，有效GOA单元101中包括多个晶体管，至少一个虚拟GOA单元102包括多个晶体管；至少一个虚拟GOA单元102中晶体管的数量少于有效GOA单元101中晶体管的数量。
此处，可以是一个虚拟GOA单元102中晶体管的数量少于有效GOA单元101中晶体管的数量；也可以是多个虚拟GOA单元102中的部分虚拟GOA单元102中的每个虚拟GOA单元102中晶体管的数量少于有效GOA单元101中晶体管的数量；当然还可以是，多个虚拟GOA单元102中的每个虚拟GOA单元102中晶体管的数量均少于有效GOA单元101中晶体管的数量，对此不做限定。
综上所述，本公开中，通过设置至少一个虚拟GOA单元102中晶体管的数量少于有效GOA单元102中晶体管的数量，也就是说，相比于有效GOA单元101，本公开中通过减小至少一个虚拟GOA单元102中晶体管的数量，从而能够释放周边区2中靠近圆弧边R的位置处的部分布图空间，因而有利于在周边区2中靠近圆弧边R的位置处设置 走线，避免了因空间较小导致的在周边区2中靠近圆弧边R的位置处设置的走线出现短路等问题。
以下对于上述至少一个虚拟GOA单元102中晶体管的数量少于有效GOA单元101中晶体管的数量的具体设置情况做进一步的说明。
在一些实施例中，如图6和图7所示，每个GOA单元所占区域包括：第一区域a1和第二区域a2；有效GOA单元101包括设置在有效GOA单元101的第一区域a1的第一子电路和设置于有效GOA单元102的第二区域a2的第二子电路，第一子电路包括多个晶体管，第二子电路包括至少一个晶体管；至少一个虚拟GOA单元102包括设置在每个虚拟GOA单元102的第一区域a1的第一子电路，且不包含第二子电路(即至少一个虚拟GOA单元102的第二区域a2不设置晶体管)，虚拟GOA单元102的第二区域a2位于虚拟GOA单元102所占区域中的靠近周边区2的外边缘的一半区域。
需要说明的是，附图6和图7中的中心线M将虚拟GOA单元102所占区域分成面积相等的两个区域，中心线M以左为虚拟GOA单元102所占区域的一半区域，中心线M以右为虚拟GOA单元102所占区域的一半区域。附图6和图7中除标示的第二区域a2以外的其它区域都为第一区域a1。
此处，周边区2包括两个边缘，一个内边缘，一个外边缘。其中，内边缘与显示区2的边缘重叠。
基于上述可知，由于至少一个虚拟GOA单元102不包含第二子电路，因此至少一个虚拟GOA单元102相对于有效GOA单元101而言，去除了第二子电路包括的晶体管。
应当理解到，设置在有效GOA单元101的第一区域a1的第一子电路与设置在虚拟GOA单元102的第一区域a1的第一子电路的电路结构相同。
例如，参考图10所示，虚拟GOA单元102的第一区域a1设置的晶体管(晶体管M3～晶体管M7)的结构和连接关系，与有效GOA单元101的第一区域a1的设置的晶体管(晶体管M3～晶体管M7)的结构和连接关系相一致。
由于阵列基板100上的多条走线通常会经过GOA单元靠近周边区2的边缘的一侧，因而本公开实施例中，虚拟GOA单元102的第二区 域a2位于虚拟GOA单元102所占区域中的靠近周边区2的外边缘的一半区域，通过去除第二子电路，即去除虚拟GOA单元102的第二区域中的晶体管，因而可以释放周边区2中靠近周边区2外边缘的部分空间，从而有利于设置走线。
在此基础上，对于上述虚拟GOA单元102中第一区域a1的设置位置不进行限定。可以是如图6所示，上述虚拟GOA单元102中第一区域a1的至少部分也靠近周边区2的外边缘，即第一子电路中的至少部分晶体管靠近周边区2的外边缘。当然还可以是如图7所示，虚拟GOA单元102的第二区域a2相比于第一区域a1靠近周边区2的外边缘。
由于虚拟GOA单元102的第二区域a2不包括第二子电路，在虚拟GOA单元102的第二区域a2相比于第一区域a1靠近周边区2的外边缘的情况下，因此虚拟GOA单元102所占的区域中靠近周边区2的区域完全不设置晶体管，从而可以释放更大的布图空间，进而有利于布线。
对于上述有效GOA单元101和虚拟GOA单元102的具体结构不做限定。以下示例性地介绍一种有效GOA单元101的结构，本领域技术人员应该明白，本公开实施例包括但不限于下述介绍的有效GOA单元101的结构。
在一些实施例中，如图8所示，有效GOA单元101可以包括输入子电路201、下拉子电路202、上拉控制子电路203、上拉子电路204、输出控制子电路205、输出子电路206。
如图8所示，上述输入子电路201与信号输入端Input、第一节点N1、第二时钟信号端CK2连接。该输入子电路201配置为在第二时钟信号端CK2的电压的控制下，将信号输入端Input的电压输出至第一节点N1。
示例的，在一些实施例中，如图9所示，上述输入子电路201可以包括第一晶体管M1。其中，第一晶体管M1的栅极与第二时钟信号端CK2连接，第一晶体管M1的第一极与信号输入端Input连接，第一晶体管M1的第二极与第一节点N1连接。
如图8所示，上述下拉子电路202与第一电压端VGL、第二节点N2、第二时钟信号端CK2连接。该下拉子电路202配置为在第二时钟 信号端CK2的电压的控制下，将第一电压端VGL的电压输出至第二节点N2。
示例的，在一些实施例中，如图9所示，上述下拉子电路202可以包括第二晶体管M2。第二晶体管M2的栅极与第二时钟信号端CK2连接，第二晶体管M2的第一极与第一电压端VGL连接，第二晶体管M2的第二极与第二节点N2连接。
如图8所示，上述上拉控制子电路203与第一时钟信号端CK1、第一节点N1、第二节点N2、第二电压端VGH连接。该上拉控制子电路203配置为在第一时钟信号端CK1和第二节点N2的电压的控制下，将第二电压端VGH的电压输出至第一节点N1。
示例的，在一些实施例中，如图9所示，上述上拉控制子电路203可以包括第三晶体管M3和第四晶体管M4。其中，第三晶体管M3的栅极与第二节点N2连接，第三晶体管M3的第一极与第二电压端VGH连接，第三晶体管M3的第二极与第四晶体管M4的第二极连接，第四晶体管M4的第一极与第一节点N1连接，第四晶体管M4的栅极与第一时钟信号端CK1连接。
如图8所示，上述上拉子电路204与第二节点N2、第二电压端VGH、信号输出端Output连接。上拉子电路204配置为在第二节点N2的电压的控制下，将第二电压端VGH的电压输出至信号输出端Output。
示例的，在一些实施例中，如图9所示，上述上拉子电路204可以包括第五晶体管M5。其中，第五晶体管M5的栅极与第二节点N2连接，第五晶体管M5的第一极与第二电压端VGH连接，第五晶体管M5的第二极与信号输出端Output连接。
如图8所示，上述输出控制子电路205与第一节点N1、第一电压端VGL、输出子电路206连接。该输出控制子电路205配置为通过第一电压端VGL的电压控制输出子电路206与第一节点N1之间的通断。
示例的，在一些实施例中，如图9所示，上述输出控制子电路205可以包括第六晶体管M6。第六晶体管M6的栅极与第一电压端VGL连接，第六晶体管M6的第一极与第一节点N1连接，第六晶体管M6的第二极与输出子电路206连接。
如图8所示，上述输出子电路206与输出控制子电路205、第一时钟信号端CK1、信号输出端Output连接。该输出子电路206配置为在 输出子电路205导通时，在第一节点N1的电压的控制下，将第一时钟信号端CK1的电压输出至信号输出端Output。
示例的，在一些实施例中，如图9所示，上述输出子电路206可以包括第七晶体管M7。其中，第七晶体管M7的栅极与输出控制子电路205(第六晶体管M6的第二极)连接，第七晶体管M7的第一极与第一时钟信号端CK1连接，第七晶体管M7的第二极与信号输出端Output连接。
需要说明的是，本公开中的晶体管可以为增强型晶体管，也可以为耗尽型晶体管。另外，由于晶体管中的源极、漏极在结构和组成上通常是对称的，所以其源极、漏极是没有区别的。在本公开一些实施例中，为区分一个晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。基于此，可以是上述第一极为源极，第二极为漏极；也可以是上述第一极为漏极，第二极为源极。
基于上述，对于位于阵列基板100上的GOA电路的实际电路分布而言，在一些实施例中，在有效GOA单元101中，上述输入子电路201中的至少部分晶体管和/或上述下拉子电路202中的至少部分晶体管位于有效GOA单元101的第二区域。
由于有效GOA单元101包括设置于有效GOA单元101的第二区域的第二子电路，因此第二子电路包括上述输入子电路201中的至少部分晶体管和/或上述下拉子电路202中的至少部分晶体管。在上述至少一个虚拟GOA单元包括设置在每个虚拟GOA单元的第一区域的第一子电路，且不包含第二子电路的情况下，也就是说虚拟GOA单元不包括上述输入子电路201中的至少部分晶体管和/或上述下拉子电路202中的至少部分晶体管，也即虚拟GOA单元删除了上述输入子电路201中的至少部分晶体管和/或上述下拉子电路202中的至少部分晶体管，这样一来，可以释放部分空间，从而有利于布线。
示例的，相比于有效GOA单元101中的输入子电路201包括第一晶体管M1，下拉子电路202包括第二晶体管M2；输入子电路201和下拉子电路202均位于第二区域a2。参考图10，由于虚拟GOA单元102的第二区域a2不设置第二子电路，因此虚拟GOA单元102不包括第一晶体管M1和第二晶体管M2。即，虚拟GOA单元102相对于有效GOA单元101去除了第一晶体管M1和第二晶体管M2。
在一些示例中，参考图9所示，有效GOA单元101中的上拉控制子电路203可以包括：第一控制单元2031和第二控制单元2032。其中，第一控制单元2031与第二节点N2、第二电压端VGH、第二控制单元2032连接；第二控制单元2032还与第一节点N1和第一时钟信号端CK1连接。
示例的，在一些实施例中，如图9所示，第一控制单元2031包括第三晶体管M3，第二控制单元2032包括第四晶体管M4。
在一些实施例中，在上拉控制子电路203包括第一控制单元2031和第二控制单元2032的情况下，在有效GOA单元101中，上述第一控制单元2031中的至少部分晶体管和/或上述第二控制单元2032中的至少部分晶体管位于有效GOA单元101的第二区域。由于虚拟GOA单元101的第二区域a2不包括第二子电路，也就是说虚拟GOA单元101不包括上述第一控制单元2031中的至少部分晶体管和/或上述第二控制单元2032中的至少部分晶体管，也即虚拟GOA单元101删除了上述第一控制单元2031中的至少部分晶体管和/或上述第二控制单元2032中的至少部分晶体管。
在第二种可能的实现方式中，每个有效GOA单元101包括通过多个信号传输通路相耦接的多个晶体管；至少一个虚拟GOA单元102包括多个晶体管，每个虚拟GOA单元102中多个晶体管与有效GOA单元101中多个晶体管的位置对应；在至少一个虚拟GOA单元102中，与多个晶体管耦接的多个信号传输通路中的至少一个相比于有效GOA单元101的相应位置处的信号传输通路是断开的。
本公开实施例中，由于在至少一个虚拟GOA单元102中，与多个晶体管耦接的多个信号传输通路中的至少一个相比于所述有效GOA单元的相应位置处的信号传输通路是断开的，而断开的信号传输通路因没有电流流通是不发热的，因此提高了散热效果。
此处，“每个虚拟GOA单元102中多个晶体管与有效GOA单元101中多个晶体管的位置对应”指的是若虚拟GOA单元102中的第一晶体管M1位于虚拟GOA单元102所占区域的左上角，则有效GOA单元101中的第一晶体管M1也位于有效GOA单元101所占区域的左上角。
应当理解到，每个有效GOA单元101中的多个晶体管都是通过多个信号传输通路相耦接在一起的。以有效GOA单元101的结构为如图9所示的结构为例，例如，第二晶体管M2和第三晶体管M3通过信号传输通路bc相耦接。又例如，第二晶体管M2和第五晶体管M5通过信号传输通路bd相耦接。再例如，第一晶体管M1和第六晶体管M6通过信号传输通路ef相耦接。
另外，对于一个虚拟GOA单元102，对于信号传输通路的断开位置不进行限定。以有效GOA单元101的结构为图9所示的结构为例，相对于图9，如图12所示，例如，可以将第二晶体管M2和第三晶体管M3之间的信号传输通路bc断开。又例如，可以将第二晶体管M2和第五晶体管M5之间的信号传输通路bd断开。再例如，可以将第一晶体管M1和第六晶体管M6之间的信号传输通路ef。
在一些实施例中，每个GOA单元所占区域包括：第一区域a1和第二区域a2；GOA单元包括设置于第一区域a1的至少一个晶体管和设置于第二区域a2的至少一个晶体管；至少一个虚拟GOA单元102中，与位于第二区域a2的晶体管耦接的信号传输通路中的至少一个相比于有效GOA单元101的相应位置处的信号传输通路是断开的；虚拟GOA单元102的第二区域位于虚拟GOA单元102所占区域中的靠近周边区2的外边缘的一半区域。
应当理解到，虚拟GOA单元102的第一区域a1的结构和连接关系与有效GOA单元101的第一区域a1的结构和连接关系是一致的。
例如，参考图12所示，虚拟GOA单元102的第一区域a1设置的晶体管(晶体管M3～晶体管M7)的结构和连接关系，与有效GOA单元101的第一区域a1的设置的晶体管(晶体管M3～晶体管M7)的结构和连接关系相一致。
上述至少一个虚拟GOA单元102中，与位于第二区域a2的晶体管耦接的信号传输通路中的至少一个相比于有效GOA单元101的相应位置处的信号传输通路是断开的，也即，断开的信号传输通路位于虚拟GOA单元102所占区域中的靠近周边区2的外边缘的一半区域。
以有效GOA单元101的结构为如图8和图9所示的结构为例，在有效GOA单元101中，输入子电路201中的至少部分晶体管和/或下拉子电路202中的至少部分晶体管位于有效GOA单元101的第二区域a2。 由于每个虚拟GOA单元102中多个晶体管与有效GOA单元101中多个晶体管的位置对应，因而虚拟GOA单元102的第二区域a2包括输入子电路201中的至少部分晶体管和/或下拉子电路202中的至少部分晶体管，而与位于第二区域a2的晶体管耦接的信号传输通路中的至少一个相比于有效GOA单元101的相应位置处的信号传输通路是断开的，因此如图11所示，与输入子电路201和/或与上拉子电路202耦接的信号传输通路断开，也即，与输入子电路201中的至少部分晶体管和/或与上拉子电路202中的至少部分晶体管耦接的信号传输通路断开。如图12所示，输入子电路201包括第一晶体管M1，上拉子电路202包括第二晶体管M2，与第一晶体管M1耦接的信号传输通路ef断开，和/或与第二晶体管M2耦接的信号传输通路bd和信号传输通路bc断开。
在此基础上，在上拉控制子电路203包括第一控制单元2031和第二控制单元2032的情况下，上述第一控制单元2031中的至少部分晶体管和/或上述第二控制单元2032中的至少部分晶体管位于有效GOA单元101的第二区域a2，由于每个虚拟GOA单元102中多个晶体管与有效GOA单元101中多个晶体管的位置对应，因而虚拟GOA单元102的第二区域a2包括第一控制单元2031中的至少部分晶体管和/或上述第二控制单元2032中的至少部分晶体管，而与位于第二区域a2的晶体管耦接的信号传输通路中的至少一个相比于有效GOA单元101的相应位置处的信号传输通路是断开的，因此如图11所示，与第一控制单元2031和/或第二控制单元2032耦接的信号传输通路断开，也即，如图12所示，与第一控制单元2031中的至少部分晶体管，和/或，与上述第二控制单元2032中的至少部分晶体管耦接的信号传输通路断开。
示例的，如图12所示，与第三晶体管M3耦接的信号传输通路和与第四晶体管M4耦接的信号传输通路断开。
由于阵列基板100上的多条走线通常会经过GOA单元靠近周边区2的外边缘的一侧，而本公开实施例中，断开的信号传输通路位于虚拟GOA单元102所占区域中的靠近周边区2的外边缘的一半区域，因而可以降低因信号传输通路电流流通产生的热量，提高散热效果，从而避免了对设置在GOA单元靠近周边区2外边缘的一侧的走线的影响。
在一些实施例中，虚拟GOA单元102的第二区域a2相比于第一 区域a1靠近周边区2的外边缘。
由于虚拟GOA单元102的第二区域a2相比于第一区域a1靠近周边区2的外边缘，因此信号传输通路断开的位置靠近周边区2的外边缘，而阵列基板100上的走线通常会经过GOA单元靠近周边区2的外边缘的一侧，因此可以进一步避免对设置在GOA单元靠近周边区2外边缘的一侧的走线产生影响。
在第三种可能的实现方式中，虚拟GOA单元102包括多个晶体管，有效GOA单元101包括多个晶体管，每个虚拟GOA单元102中多个晶体管与有效GOA单元101中多个晶体管的位置对应，且位置对应的晶体管的连接关系相同。
在此基础上，在一些实施例中，可以向虚拟GOA单元102中的至少一个晶体管的栅极输入选通信号，以使至少一个晶体管一直处于截止状态。例如，在虚拟GOA单元102中的至少一个晶体管为N型晶体管的情况下，可以向该N型晶体管的栅极输入高电平信号，以使该N型晶体管处于截止状态。或者，可以向虚拟GOA单元102中的至少一个晶体管的栅极不输入选通信号，以使至少一个晶体管一直处于截止状态。例如，虚拟GOA单元102的结构和有效GOA单元101的结构相同，都是如图9所示的结构，可以将第一时钟信号端CK1和第二时钟信号端CK2均不与时钟信号线连接，这样一来，栅极与第一时钟信号端CK1和第二时钟信号端CK2连接的晶体管，由于其栅极不输入选通信号，因而会一直处于截止状态。参考图9，若第一时钟信号端CK1和第二时钟信号端CK2均不与时钟信号线连接，则第一晶体管M1、第二晶体管M2以及第四晶体管M4会一直处于截止状态。
由于处于截止状态的晶体管中不会有电流经过，因而可以降低发热，提高散热效果。
此外，每个GOA单元所占区域包括：第一区域a1和第二区域a2。有效GOA单元101在工作时，对于虚拟GOA单元102，设置于虚拟GOA单元102的第二区域a2的晶体管处于截止状态。虚拟GOA单元102的第二区域a2相比于第一区域a1靠近周边区2的外边缘。进一步地，在一些实施例中，虚拟GOA单元102的第二区域a2相比于第一区域a1靠近周边区2的外边缘。
由于虚拟GOA单元102的第二区域a2的晶体管处于截止状态， 因而虚拟GOA单元102的第二区域a2不发热，从而可以提高散热效果。
另外，还需要说明的是，阵列基板100上除了设置前述的虚拟GOA单元102和有效GOA单元101以外，还设置有其他相关的信号线，例如时钟信号线CLK、电源电压信号线VDD等等，可以参考相关技术，此处不再一一赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种阵列基板，具有显示区以及位于所述显示区外侧的周边区；所述显示区包括两条大致平行的第一侧边和与每条所述第一侧边的至少一端连接的圆弧边；
    所述阵列基板包括：
    设置于所述显示区的多个亚像素；
    设置于所述周边区的至少一个栅极驱动电路；每个栅极驱动电路包括：沿至少一条所述圆弧边依次分布的多个GOA单元以及沿与该所述圆弧边连接的一条所述第一侧边依次分布的多个有效GOA单元；所述多个GOA单元包括至少一个有效GOA单元和至少一个虚拟GOA单元；每个有效GOA单元被配置为给至少一个所述亚像素提供驱动信号，所述至少一个虚拟GOA单元为所述多个GOA单元中除有效GOA单元以外的GOA单元；
    其中，沿至少一条所述圆弧边依次分布的多个GOA单元中相邻两个GOA单元之间的间距和沿与该所述圆弧边连接的一条所述第一侧边依次分布的多个有效GOA单元中相邻两个有效GOA单元之间的间距大致相同。
  2. 根据权利要求1所述的阵列基板，其中，沿至少一条所述圆弧边依次分布的多个GOA单元中相邻两个有效GOA单元之间设置至少一个虚拟GOA单元。
  3. 根据权利要求1所述的阵列基板，其中，沿至少一条所述圆弧边依次分布的多个GOA单元中任一个有效GOA单元相对于所有的虚拟GOA单元靠近沿第一侧边依次分布的多个有效GOA单元。
  4. 根据权利要求1所述的阵列基板，其中，所述有效GOA单元包括多个晶体管；所述至少一个虚拟GOA单元包括多个晶体管；
    所述至少一个虚拟GOA单元中晶体管的数量少于所述有效GOA单元中晶体管的数量。
  5. 根据权利要求4所述的阵列基板，其中，每个GOA单元所占区域包括：第一区域和第二区域；
    所述有效GOA单元包括设置在所述有效GOA单元的第一区域的第一子电路和设置于所述有效GOA单元的第二区域的第二子电路，所述第一子电路包括多个晶体管，所述第二子电路包括至少一个晶体管；
    至少一个虚拟GOA单元包括设置在每个虚拟GOA单元的第一区域的第一子电路，且不包含所述第二子电路，所述虚拟GOA单元的第 二区域位于所述虚拟GOA单元所占区域中的靠近所述周边区的外边缘的一半区域。
  6. 根据权利要求1所述的阵列基板，其中，每个所述有效GOA单元包括通过多个信号传输通路相耦接的多个晶体管；至少一个虚拟GOA单元包括多个晶体管，每个虚拟GOA单元中多个晶体管与所述有效GOA单元中多个晶体管的位置对应；
    在所述至少一个虚拟GOA单元中，与多个晶体管耦接的多个信号传输通路中的至少一个相比于所述有效GOA单元的相应位置处的信号传输通路是断开的。
  7. 根据权利要求6所述的阵列基板，其中，每个GOA单元所占区域包括：第一区域和第二区域；所述GOA单元包括设置于所述第一区域的至少一个晶体管和设置于所述第二区域的至少一个晶体管；
    所述至少一个虚拟GOA单元中，与位于所述第二区域的晶体管耦接的信号传输通路中的至少一个相比于所述有效GOA单元的相应位置处的信号传输通路是断开的；
    所述虚拟GOA单元的第二区域位于所述虚拟GOA单元所占区域中的靠近所述周边区的外边缘的一半区域。
  8. 根据权利要求5或7所述的阵列基板，其中，所述虚拟GOA单元的第二区域相比于第一区域靠近所述周边区的外边缘。
  9. 根据权利要求1～8任一项所述的阵列基板，其中，所述有效GOA单元包括输入子电路、下拉子电路、上拉控制子电路、上拉子电路、输出控制子电路、输出子电路；
    所述输入子电路与信号输入端、第一节点、第二时钟信号端连接；所述输入子电路配置为在所述第二时钟信号端的电压的控制下，将所述信号输入端的电压输出至所述第一节点；
    所述下拉子电路与第一电压端、第二节点、所述第二时钟信号端连接；所述下拉子电路配置为在所述第二时钟信号端的电压的控制下，将所述第一电压端的电压输出至所述第二节点；
    所述上拉控制子电路与第一时钟信号端、所述第一节点、所述第二节点、第二电压端连接；所述上拉控制子电路配置为在所述第一时钟信号端和所述第二节点的电压的控制下，将所述第二电压端的电压输出至所述第一节点；
    所述上拉子电路与所述第二节点、所述第二电压端、信号输出端连 接；所述上拉子电路配置为在所述第二节点的电压的控制下，将所述第二电压端的电压输出至所述信号输出端；
    所述输出控制子电路与所述第一节点、所述第一电压端、所述输出子电路连接；所述输出控制子电路配置为通过第一电压端的电压控制所述输出子电路与所述第一节点之间的通断；
    所述输出子电路与所述输出控制子电路、所述第一时钟信号端、所述信号输出端连接；所述输出子电路配置为在所述输出子电路导通时，在所述第一节点的电压的控制下，将所述第一时钟信号端的电压输出至所述信号输出端。
  10. 根据权利要求9所述的阵列基板，其中，在每个GOA单元所占区域包括第一区域和第二区域的情况下，在所述有效GOA单元中，所述输入子电路中的至少部分晶体管和/或所述下拉子电路中的至少部分晶体管位于所述有效GOA单元的第二区域。
  11. 根据权利要求9所述的阵列基板，其特征在于，
    所述上拉控制子电路包括第一控制单元和第二控制单元；所述第一控制单元与所述第二节点、所述第二电压端、所述第二控制单元连接；所述第二控制单元还与所述第一节点和所述第一时钟信号端连接；
    在所述有效GOA单元中，所述第一控制单元中的至少部分晶体管和/或所述第二控制单元中的至少部分晶体管位于所述有效GOA单元的第二区域。
  12. 根据权利要求1所述的阵列基板，其特征在于，所述阵列基板包括两个GOA电路；
    两个所述GOA电路分别位于两条所述第一侧边和与每条所述第一侧边的至少一端连接的圆弧边的外侧的周边区中。
  13. 一种显示面板，其特征在于，包括权利要求1～12任一项所述的阵列基板。
  14. 一种显示装置，其特征在于，包括权利要求13所述的显示面板。
PCT/CN2020/103541 2019-07-23 2020-07-22 阵列基板、显示面板及显示装置 WO2021013181A1 (zh)

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