WO2023155091A1 - 金属氧化物薄膜晶体管、阵列基板及显示装置 - Google Patents

金属氧化物薄膜晶体管、阵列基板及显示装置 Download PDF

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WO2023155091A1
WO2023155091A1 PCT/CN2022/076578 CN2022076578W WO2023155091A1 WO 2023155091 A1 WO2023155091 A1 WO 2023155091A1 CN 2022076578 W CN2022076578 W CN 2022076578W WO 2023155091 A1 WO2023155091 A1 WO 2023155091A1
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Prior art keywords
metal oxide
semiconductor layer
oxide semiconductor
thin film
film transistor
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PCT/CN2022/076578
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English (en)
French (fr)
Inventor
贺家煜
赵坤
曲燕
雷利平
宁策
李正亮
胡合合
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京东方科技集团股份有限公司
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Priority to PCT/CN2022/076578 priority Critical patent/WO2023155091A1/zh
Priority to CN202280000203.3A priority patent/CN117355947A/zh
Publication of WO2023155091A1 publication Critical patent/WO2023155091A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the disclosure belongs to the field of display technology, and in particular relates to a metal oxide thin film transistor, an array substrate and a display device.
  • metal oxide thin film transistors Due to its higher mobility, metal oxide thin film transistors have gradually increased their share in the high-end display market, and metal oxide technology is also considered to be the most likely way to replace the existing low-temperature polysilicon technology. With the upgrading of display products, the development of metal oxide thin film transistors with ultra-high mobility (mobility greater than 20cm2/V.s or even 30cm2/V.s or 50cm2/V.s) has become the research and development focus of various panel manufacturers.
  • the current metal oxide thin film transistor can form its metal oxide semiconductor layer by using metal oxide materials with higher mobility. Although the mobility of metal oxide thin film transistors has been greatly improved, the current metal oxide thin film As a device in a product, transistors are easily affected by factors such as light, manufacturing process, and external water and oxygen during production or use. The stability is not high enough and needs to be further improved.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a metal oxide thin film transistor, an array substrate and a display device.
  • an embodiment of the present disclosure provides a metal oxide thin film transistor, including: a substrate, a first metal oxide semiconductor layer on the substrate, and a metal oxide semiconductor layer on the first metal oxide semiconductor layer. a second metal oxide semiconductor layer on a side away from the substrate; the carrier mobility of the first metal oxide semiconductor layer is higher than the carrier mobility of the second metal oxide semiconductor layer;
  • the material of the first metal oxide semiconductor layer includes: a first metal oxide doped with a rare earth element; wherein, the difference between the electronegativity of the rare earth element and the electronegativity of oxygen is greater than or equal to the The electronegativity difference between the metal element and oxygen element in the first metal oxide.
  • the rare earth elements include: at least one of tantalum, niobium, neodymium and zirconium.
  • the metal element in the first metal oxide includes: at least one of indium, gallium, zinc, and tin.
  • the atomic percentage of the rare earth element in the first metal oxide semiconductor layer is 0.01% to 5%.
  • the atomic percentage of the rare earth element in the first metal oxide semiconductor layer is 0.15% or 0.2%.
  • the Hall mobility in the first metal oxide semiconductor layer is greater than or equal to 31 cm2/V.s.
  • the concentration of carriers in the first metal oxide semiconductor layer is greater than or equal to 3.5 ⁇ E18cm-3.
  • the etching slope angle of the first metal oxide semiconductor layer is 40 degrees to 60 degrees.
  • the first metal oxide semiconductor layer is in contact with the etched side of the second metal oxide semiconductor layer, and the etching slope angle of the first metal oxide semiconductor layer is the same as that of the second metal oxide semiconductor layer.
  • the etching slope angles of the metal oxide semiconductor layers are equal.
  • the metal element in the second metal oxide includes: at least one of indium, gallium, zinc, and tin.
  • an embodiment of the present disclosure provides an array substrate, which includes a plurality of metal oxide thin film transistors as provided above.
  • an embodiment of the present disclosure provides a display device, which includes the array substrate provided above.
  • FIG. 1 is a schematic structural diagram of a metal oxide thin film transistor provided by at least one embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another metal oxide thin film transistor provided by at least one embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another metal oxide thin film transistor provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another metal oxide thin film transistor provided by at least one embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of an array substrate provided by at least one embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another array substrate provided by at least one embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another array substrate provided by at least one embodiment of the present disclosure.
  • FIG 8 to 10 are schematic structural views of other three array substrates provided by at least one embodiment of the present disclosure.
  • metal oxide thin film transistors can be applied to liquid crystal display panels (Liquid Crystal Display, LCD), organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panels, mini light-emitting diodes (Mini Light-Emitting Diode) Emitting Diode) backlight or display panel, quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display panel and other technologies.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • mini light-emitting diodes Mini Light-Emitting Diode) Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • the higher mobility of current metal oxide thin film transistors is mainly determined by the material properties of the metal oxide semiconductor layer.
  • indium gallium zinc oxide IGZO wherein Oxygen (O) elements and metal elements indium (In), gallium (Ga) and zinc (Zn) can form compounds, and provide or trap carriers (oxygen vacancies) according to the chemical bond formation.
  • indium (In) can provide electron transmission path, so that IGZO has higher mobility.
  • Gallium (Ga) has high ionization energy, which can suppress electron mobility, suppress the formation of oxygen vacancies, and generate new mobile electrons.
  • Zinc (Zn) can be used as a stabilizer, has a strong chemical bond that can bind oxygen ions, and can form a stable tetrahedral structure to form a relatively stable amorphous grain boundary.
  • the metal oxide thin film transistor composed of IGZO can have higher mobility, but the metal oxide in the higher mobility metal oxide thin film transistor
  • the material of the semiconductor layer is easily affected by factors such as light, manufacturing process, and external water and oxygen.
  • metal oxide semiconductor layers can be stacked, but also due to the material properties of metal oxides, in the process of patterning the multi-layer metal oxide semiconductor layers, it is easy to appear The smearing phenomenon and the small etching slope angle formed further affect the stability of the metal oxide thin film transistor.
  • embodiments of the present disclosure provide a metal oxide thin film transistor, an array substrate, and a display device.
  • the metal oxide thin film transistors and arrays provided in the disclosure will be compared below in conjunction with the drawings and specific embodiments.
  • the substrate and display device are described in further detail.
  • FIG. 1 is a schematic structural diagram of a metal oxide thin film transistor provided by at least one embodiment of the present disclosure. As shown in FIG. 1 , the metal oxide thin film transistor includes: a substrate 101.
  • the carrier mobility is higher than that of the second metal oxide semiconductor layer 103;
  • the material of the first metal oxide semiconductor layer 102 includes: a first metal oxide doped with a rare earth element; wherein, the rare earth element
  • the difference between the electronegativity of the metal element and the electronegativity of the oxygen element is greater than or equal to the difference between the electronegativity of the metal element in the first metal oxide and the oxygen element.
  • the substrate 101 can be made of rigid materials such as glass, which can improve the bearing capacity of the substrate 101 on other film layers thereon.
  • the substrate 101 can also be made of flexible materials such as polyimide (PI), which can improve the overall bending resistance and stretching resistance of the metal oxide thin film transistor, and avoid bending, stretching, and twisting during bending, stretching, and twisting.
  • PI polyimide
  • the stress generated in the substrate 101 breaks, resulting in poor disconnection.
  • the material of the substrate 101 can be reasonably selected according to actual needs, so as to ensure good performance of the metal oxide thin film transistor.
  • the metal oxide semiconductor layer of the metal oxide thin film transistor can be composed of a single-layer structure, that is, only one layer of the first metal oxide semiconductor layer 102 is provided in the metal oxide thin film transistor, and its structure is simple, which can reduce the cost of the metal oxide thin film transistor. Preparation difficulty, saving preparation cost.
  • the first metal oxide semiconductor layer 102 in the metal oxide thin film transistor can be formed using metal oxide, specifically, the material of the first metal oxide semiconductor layer 102 includes the first metal oxide doped with rare earth elements.
  • the first metal oxide may be a metal oxide with high mobility, which can ensure the high mobility of the metal oxide thin film transistor, thereby improving the electrical performance of the metal oxide thin film transistor.
  • the first metal oxide semiconductor layer 102 is also doped with rare earth elements. According to the limit of the electronegativity difference of 1.7, the greater the electronegativity difference, the stronger the bond energy of the ionic bond formed.
  • the difference between the electronegativity and the electronegativity of the oxygen (O) element is large, and generally greater than or equal to the difference between the electronegativity of the metal element in the first metal oxide and the oxygen (O) element.
  • the electronegativity of oxygen (O) element is 3.5, and the rare earth element with electronegativity less than 1.8 can be selected to dope the first metal oxide, so that the rare earth element and oxygen (O) element can form
  • the ionic bond with stronger bond energy is far greater than the bond energy between the metal element and the oxygen (O) element in the original first metal oxide semiconductor layer, so that the first metal oxide semiconductor layer
  • the performance of the material 102 is more stable, avoiding the influence of light, manufacturing process, external water and oxygen, etc., so as to ensure the stability of the structure of the first metal oxide semiconductor layer 102, thereby improving the stability of the metal oxide thin film transistor.
  • the metal oxide semiconductor layer of the metal oxide thin film transistor can also be formed by a double-layer structure.
  • the second metal oxide semiconductor layer 103 may be disposed on the semiconductor layer 102. Since the first metal oxide semiconductor layer 102 is doped with rare earth elements, the structure of the first metal oxide semiconductor layer 102 formed by it is relatively stable. It is not easily affected by the etching process. When the second metal oxide semiconductor layer 103 is stacked with the first metal oxide semiconductor layer 102, the tailing phenomenon can be avoided to ensure that the first metal oxide semiconductor layer 102 and the stability of the second metal oxide semiconductor layer 103 .
  • the second metal oxide semiconductor layer 103 can be made of a material with better stability, although the mobility of the second metal oxide semiconductor layer 103 is not as high as that of the first metal oxide semiconductor layer 102, but During the application process, carriers can mainly migrate through the first metal oxide semiconductor layer 102 to ensure that the overall metal oxide thin film transistor has a high mobility, and the second metal oxide semiconductor layer 103 can further improve the mobility of the metal oxide thin film transistor.
  • the thin film transistor as a whole has high mobility.
  • the second metal oxide semiconductor layer 103 is disposed on the first metal oxide semiconductor layer 102, which can play a certain light-shielding effect and prevent ambient light or light from the light emitting device from directly shining on the first metal oxide semiconductor layer 102. , so as to play a good protective effect on the first metal oxide semiconductor layer 102 and ensure good stability of the metal oxide thin film transistor as a whole.
  • the second metal oxide semiconductor layer 103 and the first metal oxide semiconductor layer 102 can be etched using the same mask, which does not increase the process steps and thus does not increase the manufacturing cost.
  • the rare earth element includes: at least one of tantalum (Ta), niobium (Nb), neodymium (Nd), and zirconium (Zr); the metal element in the first metal oxide includes: indium (In) , gallium (Ga), zinc (Zn), tin (Sn) at least one.
  • the first metal oxide may be indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc oxide (IZO), indium tin oxide (ITO) and indium tin zinc oxide (ITZO). At least one of them is a metal oxide with relatively high mobility, so as to ensure that the metal oxide thin film transistor has relatively high mobility as a whole.
  • the rare earth element may be at least one of tantalum (Ta), niobium (Nb), neodymium (Nd), and zirconium (Zr).
  • the electronegativity of the tantalum (Ta) element is 1.5
  • the electronegativity of the oxygen (O) element is 3.5
  • the bond energy of the ionic bond formed by two elements with electronegativity difference greater than 1.7 is stronger, so the bond energy of the ionic bond formed by tantalum (Ta) element and oxygen (O) element
  • tantalum (Ta) is 0.07 nanometers (nm)
  • tantalum (Ta) ) can replace zinc (Zn) in it with little or no change in the lattice structure of the metal oxide.
  • the electron orbits will overlap, so that the bonding structure will rarely be set without relatively weak ionic bonds , which has nothing to do with its crystalline or amorphous state, so the stability of the first metal oxide can be further improved, so as to further improve the stability of the metal oxide thin film transistor.
  • rare earth elements whose electronegativity is other values can also be selected, for example, niobium (Nb), neodymium (Nd), zirconium (Zr), etc., of course, can also be a mixture of the above-mentioned multiple metal elements, as long as It only needs to ensure that the electronegativity difference between its electronegativity and that of oxygen is large, so as to ensure that an ionic bond with strong bond energy can be formed between the two, thereby improving the overall stability of the metal oxide thin film transistor.
  • Nb niobium
  • Nd neodymium
  • Zr zirconium
  • the atomic percentage of the rare earth element in the first metal oxide semiconductor layer 102 is 0.01% to 5%.
  • the rare earth element in the first metal oxide semiconductor layer 102 is tantalum (Ta) as an example, and the atomic percentage of tantalum (Ta) in it is 0.01% to 5%, which can ensure the relationship between tantalum (Ta) and oxygen (O).
  • Forming ionic bonds with strong bond energy can make the material properties of the first metal oxide more stable and avoid being affected by factors such as light, manufacturing process, and external water and oxygen, thereby ensuring the stability of the first metal oxide semiconductor layer 102. Stability, and thus can improve the overall stability of the metal oxide thin film transistor.
  • the rare earth elements are the above-mentioned niobium (Nb), neodymium (Nd), zirconium (Zr), or more of tantalum (Ta), niobium (Nb), neodymium (Nd), and zirconium (Zr).
  • the atomic percentage can also be 0.01% to 5%, and the specific value can be set according to actual needs.
  • the atomic percentage of rare earth elements in the first metal oxide semiconductor layer 102 is 0.15% or 0.2%.
  • the carrier trapping defects can be effectively reduced by suppressing the formation of oxygen vacancies and reducing impurities in the IGZO film, thereby ensuring the strong stability of the first metal oxide and improving the overall performance of the metal oxide thin film transistor. stability.
  • the Hall mobility in the first MOS layer 102 is greater than or equal to 31 cm2/V.s.
  • the concentration of carriers in the first metal oxide semiconductor layer 102 is greater than or equal to 3.5 ⁇ E18 cm ⁇ 3 .
  • the Hall mobility of carriers in the first metal oxide semiconductor layer 102 and the concentration of carriers are relatively high, which can ensure that the first metal oxide semiconductor layer 102 has a relatively high mobility, so as to ensure that the metal oxide thin film
  • the transistor as a whole has high mobility.
  • the etching slope angle of the first metal oxide semiconductor layer 102 is 40 degrees to 60 degrees, which can ensure that when multiple film layers are stacked, the first metal oxide semiconductor layer 102 can be guaranteed The film layer can be effectively supported, avoiding that the etching slope angle is too large or small to affect the bonding stability between the multi-layer film layers. At the same time, the tailing phenomenon can be avoided to ensure the stability of the first metal oxide semiconductor layer 102 and the second metal oxide semiconductor layer 103 .
  • the first metal oxide semiconductor layer 102 is in contact with the etched side of the second metal oxide semiconductor layer 103, and the etching slope angle of the first metal oxide semiconductor layer 102 is the same as that of the second metal oxide semiconductor layer 103.
  • the etching slope angles of the semiconductor layer 103 are equal.
  • the area of the second metal oxide semiconductor layer 103 may be approximately equal to the area of the first metal oxide semiconductor layer 102, and the orthographic projection of the second metal oxide semiconductor layer 103 on the substrate 101 is located The material semiconductor layer 102 is within the orthographic projection of the substrate 101 on the substrate 101.
  • the first metal oxide semiconductor layer 102 and the second metal oxide semiconductor layer 103 can form a relatively flat etching side surface, so that the second metal oxide semiconductor layer
  • the layer 103 can cover the first metal oxide semiconductor layer 102, so as to play a good light-shielding effect, and prevent ambient light or light from the light emitting device from directly shining on the first metal oxide semiconductor layer 102, so that the first metal oxide semiconductor layer 102
  • the layer 102 plays a good protective role, and can avoid the tailing phenomenon during the manufacturing process, so as to ensure the overall stability of the metal oxide thin film transistor.
  • the metal oxide thin film transistor further includes: a gate 104 located on the side of the first metal oxide semiconductor layer 102 close to the substrate 101 ;
  • the orthographic projection is located within the orthographic projection of the first metal oxide semiconductor layer 102 on the substrate 101 .
  • the gate 104 may be located on the side of the first metal oxide semiconductor layer 102 close to the substrate 101, and the gate 104 and A gate insulating layer may be provided between the first metal oxide semiconductor layers 102 to avoid a short circuit between the first metal oxide semiconductor layer 102 and the gate 104, so as to form a bottom gate type thin film metal oxide thin film transistor.
  • the gate 104 receives a turn-on control signal, the first metal oxide semiconductor layer 102 and the second metal oxide semiconductor layer 103 can be in a conduction state.
  • the thin film transistor metal oxide thin film transistor is an N-type transistor, when the gate 104 inputs a high-level signal, the first active layer metal oxide semiconductor layer 102 and the second metal oxide semiconductor layer 103 can be in a conduction state, If the metal oxide thin film transistor is a P-type transistor, when the gate 104 inputs a low level signal, the first metal oxide semiconductor layer 102 and the second metal oxide semiconductor layer 103 may be in a conduction state.
  • the gate 104 may be located on the first metal oxide semiconductor layer 102
  • a gate insulating layer may be disposed between the gate 104 and the first metal oxide semiconductor layer 102 on the side close to the substrate 101, so as to avoid a short circuit between the first active layer metal oxide semiconductor layer 102 and the gate 104 , to form a bottom-gate metal oxide thin film transistor, when the gate 104 is input with a turn-on control signal, the first metal oxide semiconductor layer 102 can be turned on.
  • the metal oxide thin film transistor is an N-type transistor, when the gate 104 inputs a high-level signal, the first metal oxide semiconductor layer 102 can be in a conduction state; if the metal oxide thin film transistor is a P-type transistor, the gate When 104 inputs a low-level signal, the first metal oxide semiconductor layer 102 may be in a conduction state.
  • the gate 104 can play a certain light-shielding function.
  • the grid 104 can block the light emitted by the backlight from directly irradiating the first metal oxide semiconductor layer 102, so as to play a good role in protecting the first metal oxide semiconductor layer 102 and ensure the oxidation of the metal.
  • the physical thin film transistor has good stability as a whole.
  • FIG. 3 is a schematic structural diagram of another thin film transistor metal oxide thin film transistor provided by at least one embodiment of the present disclosure.
  • the metal oxide thin film transistor further includes: The gate 104 on the side of 101 ; the orthographic projection of the gate 104 on the substrate 101 is located within the orthographic projection of the first metal oxide semiconductor layer 102 on the substrate 102 .
  • the gate 104 may be located on the side of the first metal oxide semiconductor layer 102 away from the substrate 101, and the gate 104 and the first metal oxide semiconductor A gate insulating layer may be provided between the layers 102 to avoid a short circuit between the first metal oxide semiconductor layer 102 and the gate 104, so as to form a top-gate thin-film metal oxide thin film transistor, and the gate 104 is input to turn on the control signal, the first metal-oxide-semiconductor layer 102 may be in a conduction state.
  • the metal oxide thin film transistor is an N-type transistor, when the gate 104 inputs a high-level signal, the first metal oxide semiconductor layer 102 can be in a conduction state; if the metal oxide thin film transistor is a P-type transistor, the gate When 104 inputs a low-level signal, the first metal oxide semiconductor layer 102 may be in a conduction state.
  • FIG. 4 is a schematic structural diagram of another metal oxide thin film transistor provided by at least one embodiment of the present disclosure. As shown in FIG. 4 , the metal oxide thin film transistor further includes: The gate 104 on the side; the orthographic projection of the gate 104 on the substrate 101 is located within the orthographic projection of the first metal oxide semiconductor layer 102 on the substrate 101 .
  • the gate 104 may be located on the side of the second metal oxide semiconductor layer 102 away from the substrate 101 , a gate insulating layer may be provided between the gate 104 and the second metal oxide semiconductor layer 103 to avoid a short circuit between the second metal oxide semiconductor layer 103 and the gate 104 to form a top-gate metal oxide
  • the thin film transistor can make the first metal-oxide-semiconductor layer 102 and the second metal-oxide-semiconductor layer 103 be in a conduction state when a turn-on control signal is input to the gate 104 .
  • the metal oxide thin film transistor is an N-type transistor, when the gate 104 inputs a high-level signal, the first metal oxide semiconductor layer 102 and the second metal oxide semiconductor layer 103 can be in a conduction state.
  • the thin film transistor is a P-type transistor, and when a low level signal is input to the gate 104, the first metal oxide semiconductor layer 102 and the second metal oxide semiconductor layer 103 may be in a conduction state.
  • the gate 104 can play a certain light-shielding function.
  • the gate 104 can prevent the light emitted by the light emitting device from directly irradiating the first metal oxide semiconductor layer 101, so as to play a good role in protecting the first metal oxide semiconductor layer 102, ensuring The overall metal oxide thin film transistor has good stability.
  • the metal oxide thin film transistor further includes: a source electrode 105 and a drain electrode 106 located on the side of the first metal oxide semiconductor layer 102 away from the substrate 101;
  • the object semiconductor layer 102 has a first channel region 1020 and a first source contact region 1021 and a first drain contact region 1022 located at both ends of the first channel region 1020; the source 105 is electrically connected to the first source contact region 1021 , the drain 106 is electrically connected to the first drain contact region 1022 .
  • first metal oxide semiconductor layer 102 In the metal oxide thin film transistor shown in Figure 1 and Figure 3, only one layer of the first metal oxide semiconductor layer 102 is provided.
  • the first metal oxide semiconductor Both ends of the layer 102 are conductorized to form a first channel region 1020 and a first source contact region 1021 and a first drain contact region 1022 at both ends of the first channel region 1020 .
  • An ohmic contact is formed between the source 105 and the first source contact region 1021
  • an ohmic contact is also formed between the drain 106 and the first drain contact region 1022 .
  • the gate 104 When the gate 104 receives a turn-on control signal, the first metal oxide semiconductor layer 102 can be turned on, so that data signals and the like are transmitted from the source 105 to the drain 106 of the metal oxide thin film transistor, realizing the function of controlling signal transmission.
  • the metal oxide thin film transistor further includes a source 105 and a drain 106 located on the side of the second metal oxide semiconductor layer 103 away from the substrate 101; the second metal oxide The semiconductor layer 103 has a second channel region 1030 and a second source contact region 1031 and a second drain contact region 1032 located at both ends of the second channel region 1030; the source 105 is electrically connected to the second source contact region 1031, The drain 106 is electrically connected to the second drain contact region 1032 .
  • a heavy doping or particle implantation process can be used to conduct conductive treatment on both ends of the first metal oxide semiconductor layer 102 and the second metal oxide semiconductor layer 103 to form the first channel region 1020 and the first channel region 1020.
  • An ohmic contact is formed between the source 105 and the first source contact region 1021 and the second source contact region 1031, and an ohmic contact is also formed between the drain 106 and the first drain contact region 1022 and the second drain contact region 1032.
  • the gate 104 inputs a turn-on control signal, the first metal oxide semiconductor layer 102 and the second metal oxide semiconductor layer 103 can be turned on, so that data signals and the like are transmitted from the source 105 of the metal oxide thin film transistor to the drain 106 , to realize the function of controlling signal transmission.
  • the embodiment of the present disclosure also provides an array substrate.
  • the bottom-gate metal oxide layer with only one layer of the first metal oxide semiconductor layer 102 shown in FIG. 1 will be used.
  • a thin film transistor will be described as an example.
  • the array substrate can be a liquid crystal array substrate, which can be applied to a liquid crystal display device, or an organic light emitting diode array substrate, which can be applied to an organic light emitting diode display device, and will be used as an array substrate in the following description In order to explain the liquid crystal display device.
  • the array substrate is an organic light-emitting diode array substrate, its realization principle and beneficial effects are the same as those of a liquid crystal array substrate, and will not be repeated here.
  • Fig. 5 is a schematic structural diagram of an array substrate provided by at least one embodiment of the present disclosure.
  • the array substrate includes a plurality of metal oxide thin film transistors provided in any of the above embodiments (only the One), the array substrate also includes: a first protective layer 107, an organic insulating layer 108 and a second protective layer 109; the first protective layer 107 is located on the side where the source electrode 105 and the drain electrode 106 are located away from the substrate 101; The second protection layer 108 is located on the side of the first protection layer 107 facing away from the substrate 101 ; the organic insulating layer 109 is located between the first protection layer 107 and the second protection layer 108 .
  • the first protective layer 107 and the second protective layer 109 are generally made of inorganic materials, and the first protective layer 107 and the second protective layer 109 protect the first metal oxide semiconductor layer 102 to prevent the subsequent etching process from damaging the first A metal oxide semiconductor layer 102 is damaged.
  • the organic insulating layer 108 can be arranged between the first protective layer 107 and the second protective layer 109, so as to improve the flexibility of the first protective layer 107 and the second metal oxide semiconductor layer 109, which can relieve the stress generated during the application process and avoid
  • the first protective layer 107 and the second protective layer 109 made of inorganic materials are broken due to stress. At the same time, it can prevent external gases such as water and oxygen from penetrating into the first metal oxide semiconductor layer 102 , so that the first metal oxide semiconductor layer 102 can be further protected.
  • the first protection layer 107 may include: a plurality of sub-protection layers.
  • the first protection layer 107 can be divided into multiple sub-protection layers.
  • the first protection layer 107 in the array substrate shown in FIG. Alternatively, in the array substrate shown in FIG. 7 , the first protection layer 107 is divided into three sub-protection layers, that is, the first sub-protection layer 1071 , the second sub-protection layer 1072 and the third sub-protection layer 1073 .
  • the multiple sub-protection layers can further protect the first metal oxide semiconductor layer 102, and at the same time, the multiple sub-protection layers can further relieve the stress, preventing the first protection layer 107 and the second protection layer 109 from being cracked due to stress, thereby further improving the metal oxide semiconductor layer 102. Stability of the first metal oxide semiconductor layer 102 in an oxide thin film transistor.
  • the material of at least one sub-protection layer in the first protection layer 107 is silicon oxide; the material of the second protection layer 109 includes silicon nitride.
  • the sub-protective layer made of oxide in the first protective layer 107 is closer to the first metal oxide semiconductor layer, and can supplement oxygen to the first metal oxide semiconductor layer 102, and oxygen can be absorbed when preparing the silicon oxide film layer. Elements are implanted into the first metal oxide semiconductor layer 102 to avoid defects in the first metal oxide semiconductor layer 102 and improve the stability of the first active layer metal oxide semiconductor layer 102 .
  • the second protection layer 109 may be made of silicon nitride, which contains relatively low hydrogen elements, so as to prevent the hydrogen elements from affecting the stability of the first metal oxide semiconductor layer 102 .
  • sub-protection layer made of silicon oxide in the first protection layer 107
  • other sub-protection layers may also be made of silicon nitride, so as to further improve the stability of the first metal oxide semiconductor layer 102 .
  • the array substrate further includes: a common electrode 110 and a pixel electrode 111; the common electrode 110 is located on the side of the second protection layer 109 close to the substrate 101; the pixel electrode 111 is located on the second protective layer 109 The side of the protective layer 109 facing away from the substrate 101 .
  • a common signal can be input into the common electrode 110 in the array substrate, a pixel signal can be input into the pixel electrode 111, and an electric field can be formed between the common electrode 110 and the pixel electrode 111 to drive the deflection of the liquid crystal molecules in the liquid crystal layer to realize Display function.
  • the array substrate can also be used in an organic light emitting diode display device, and structures such as the common electrode 110 and the pixel electrode 111 will not be provided on the array substrate.
  • a light-emitting device can be provided in the structure, and the drain 109 of the metal oxide thin film transistor in the array substrate can be electrically connected to the anode of the light-emitting device to provide a driving signal for the light-emitting device, so that the light-emitting device emits light and realizes a display function.
  • the orthographic projection of the common electrode 110 on the substrate 101 does not overlap with the orthographic projection of the pixel electrode 111 on the substrate 101 .
  • the common electrode 110 does not overlap with the pixel electrode 111 , and an electric field can be formed between the two to drive the liquid crystal molecules in the VA liquid crystal display device to deflect, so as to realize the display function. It can be understood that the common electrode 110 and the pixel electrode 111 can also be arranged facing each other to form a TN display device. Certainly, the common electrode 110 and the pixel electrode 111 may also be arranged in other ways, which will not be listed here.
  • the metal oxide thin film transistors in the array substrates shown in FIG. 5 to FIG. 7 are all bottom-gate metal oxide thin film transistors.
  • the thin film transistor can also be a top-gate metal oxide thin film transistor, and its structure is specifically shown in FIGS. 8 to 10 . The effect is the same, and will not be repeated here.
  • An embodiment of the present disclosure also provides a display device, which includes the array substrate as provided in any one of the above embodiments, and also includes a color filter substrate and a liquid crystal layer; Between the substrate and the color filter substrate.
  • the liquid crystal molecules in the liquid crystal layer can be deflected under the driving signal provided by the array substrate to transmit the light emitted by the backlight, and the color filter substrate can convert the transmitted light into different colors to realize colorful display.
  • the display device can be any product or component with a display function such as a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the implementation principles and beneficial effects of the transistors are the same, and will not be repeated here.

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Abstract

一种金属氧化物薄膜晶体管、阵列基板及显示装置，属于显示技术领域，可解决现有的金属氧化物薄膜晶体管稳定性较差的问题。金属氧化物薄膜晶体管包括：基底（101）、及位于基底（101）上的第一金属氧化物半导体层（102）、及位于第一金属氧化物半导体层（102）背离基底（101）一侧的第二金属氧化物半导体层（103）；第一金属氧化物半导体层（102）的载流子迁移率高于第二金属氧化物半导体层（103）的载流子迁移率；第一金属氧化物半导体层（102）的材料包括：掺杂有稀土元素的第一金属氧化物；其中，稀土元素的电负性与氧元素的电负性的差值大于或等于第一金属氧化物中的金属元素与氧元素的电负性的差值。

Description

金属氧化物薄膜晶体管、阵列基板及显示装置 技术领域
本公开属于显示技术领域，具体涉及一种金属氧化物薄膜晶体管、阵列基板及显示装置。
背景技术
金属氧化物薄膜晶体管由于其更高的迁移率，在高端显示市场份额逐步提升，金属氧化物技术也被认为取代现有低温多晶硅技术最可能的实现方式。随着显示产品的升级换代，超高迁移率(迁移率大于20cm2/V.s甚至到30cm2/V.s或50cm2/V.s)金属氧化物薄膜晶体管的开发成为各面板厂商的研发重点。
目前的金属氧化物薄膜晶体管可以通过采用具有较高迁移率的金属氧化物材料形成其金属氧化物半导体层，虽然金属氧化物薄膜晶体管迁移率得到了较大的提升，但是目前的金属氧化物薄膜晶体管作为产品中的器件，在制作或使用过程中容易受到光照、制作工艺、外界水氧等因素的影响，稳定性不够高，有待进一步提升。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供一种金属氧化物薄膜晶体管、阵列基板及显示装置。
第一方面，本公开实施例提供了一种金属氧化物薄膜晶体管，其中，包括：基底、及位于所述基底上的第一金属氧化物半导体层、及位于所述第一金属氧化物半导体层背离所述基底一侧的第二金属氧化物半导体层；所述第一金属氧化物半导体层的载流子迁移率高于所述第二金属氧化物半导体层 的载流子迁移率；
所述第一金属氧化物半导体层的材料包括：掺杂有稀土元素的第一金属氧化物；其中，所述稀土元素的电负性与氧元素的电负性的差值大于或等于所述第一金属氧化物中的金属元素与氧元素的电负性的差值。
可选地，所述稀土元素包括：钽、铌、钕、锆中的至少一种。
可选地，所述第一金属氧化物中的金属元素包括：铟、镓、锌、锡中的至少一种。
可选地，所述第一金属氧化物半导体层中的所述稀土元素的原子百分比为0.01％至5％。
可选地，所述第一金属氧化物半导体层中的所述稀土元素的原子百分比为0.15％或0.2％。
可选地，所述第一金属氧化物半导体层中的霍尔迁移率大于或等于31cm2/V.s。
可选地，所述第一金属氧化物半导体层中的载流子的浓度大于或等于3.5×E18cm-3。
可选地，所述第一金属氧化物半导体层的刻蚀坡度角为40度至60度。
可选地，所述第一金属氧化物半导体层与所述第二金属氧化物半导体层的刻蚀侧面相接触，且所述第一金属氧化物半导体层的刻蚀坡角度与所述第二金属氧化物半导体层的刻蚀坡角度相等。
可选地，所述第二金属氧化物中的金属元素包括：铟、镓、锌、锡中的至少一种。
第二方面，本公开实施例提供了一种阵列基板，其中，包括多个如上述提供的金属氧化物薄膜晶体管。
第三方面，本公开实施例提供了一种显示装置，其中，包括如上述提供的阵列基板。
附图说明
图1为本公开至少一个实施例提供的一种金属氧化物薄膜晶体管的结构示意图；
图2为本公开至少一个实施例提供的另一种金属氧化物薄膜晶体管的结构示意图；
图3为本公开至少一个实施例提供的又一种金属氧化物薄膜晶体管的结构示意图；
图4为本公开至少一个实施例提供的再一种金属氧化物薄膜晶体管的结构示意图；
图5为本公开至少一个实施例提供的一种阵列基板的结构示意图；
图6为本公开至少一个实施例提供的另一种阵列基板的结构示意图；
图7为本公开至少一个实施例提供的又一种阵列基板的结构示意图；
图8至图10为本公开至少一个实施例提供的另外三种阵列基板的结构示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的 词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
金属氧化物薄膜晶体管作为一种新型的薄膜晶体管，其可以应用于液晶显示面板(Liquid Crystal Display，LCD)，有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，迷你发光二极管(Mini Light-Emitting Diode)背光源或显示面板，量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示面板等技术中。
目前的金属氧化物薄膜晶体管的较高迁移率主要由其中的金属氧化物半导体层的材料特性决定的，以金属氧化物薄膜晶体管中的金属氧化物为铟镓锌氧化物IGZO为例，其中的氧(O)元素与金属元素铟(In)、镓(Ga)锌(Zn)可以形成化合物，并根据化学键成键情况提供或陷落载流子(氧空位)。其中，铟(In)可以提供电子传输路径，使得IGZO具有较高的迁移率。镓(Ga)具有高离化能，可以抑制电子迁移率，抑制氧空位的形成以及产生新的移动电子。锌(Zn)可以作为稳定剂，具有可以结合氧离子的强化学键，可以构成稳定的四面体结构，以形成较为稳定的非晶晶界。
由金属氧化物半导体层中的IGZO中的各个元素的特性可以看出，IGZO构成的金属氧化物薄膜晶体管可以具有较高的迁移率，但是较高迁移率的金属氧化物薄膜晶体管中的金属氧化物半导体层的材料容易受到光照、制作工艺、外界水氧等因素的影响。
另外，为了获得更高的迁移率，可以将多层金属氧化物半导体层进行叠置，但是同样由于金属氧化物的材料特性的原因，在多层金属氧化物半导体层图形化过程中，容易出现拖尾现象，所形成的刻蚀坡角度较小，进一步影响了金属氧化物薄膜晶体管的稳定性。
为了至少解决上述的技术问题之一，本公开实施例提供了一种金属氧 化物薄膜晶体管、阵列基板及显示装置，下面将结合附图和具体实施方式对比公开提供的金属氧化物薄膜晶体管、阵列基板及显示装置进行进一步详细描述。
本公开实施例提供了一种金属氧化物薄膜晶体管，图1为本公开至少一个实施例提供的一种金属氧化物薄膜晶体管的结构示意图，如图1所示，金属氧化物薄膜晶体管包括：基底101、位于基底101上的第一金属氧化物半导体层102、及位于第一金属氧化物半导体层102背离基底101一侧的第二金属氧化物半导体层103；第一金属氧化物半导体层102的载流子迁移率高于第二金属氧化物半导体层103的载流子迁移率；第一金属氧化物半导体层102的材料包括：掺杂有稀土元素的第一金属氧化物；其中，稀土元素的电负性与氧元素的电负性的差值大于或等于第一金属氧化物中的金属元素与氧元素的电负性的差值。
基底101可以采用玻璃等刚性材料制成，可以提高基底101对其上的其他膜层的承载能力。当然，基底101还可以采用聚酰亚胺(polyimide，PI)等柔性材料制成，可以提高金属氧化物薄膜晶体管整体的抗弯折、抗拉伸性能，避免在弯折、拉伸、扭曲过程中产生的应力使得基底101发生断裂，造成断路不良。在实际应用中，可以根据实际需要，合理选择基底101的材料，以保证金属氧化物薄膜晶体管具有良好的性能。
金属氧化物薄膜晶体管的金属氧化物半导体层可以采用单层结构构成，即金属氧化物薄膜晶体管中仅设置有一层第一金属氧化物半导体层102，其结构简单，可以降低金属氧化物薄膜晶体管的制备难度，节约制备成本。金属氧化物薄膜晶体管中的第一金属氧化物半导体层102可以采用金属氧化物形成，具体地，第一金属氧化物半导体层102的材料包括掺杂有稀土元素的第一金属氧化物。其中，第一金属氧化物可以为具有较高的迁移率的金属氧化物，可以保证金属氧化物薄膜晶体管具有较高的迁移率，从而可以提高金 属氧化物薄膜晶体管的电学性能。
并且，第一金属氧化物半导体层102中还掺杂有稀土元素，按照电负性的差值为1.7的界限，电负性差越大所形成的离子键的键能越强，其中稀土元素的电负性与氧(O)元素的电负性的差值较大，且一般要大于或等于第一金属氧化物中的金属元素与氧(O)元素的电负性的差值。例如，氧(O)元素的电负性为3.5，可以选择电负性小于1.8的稀土元素对第一金属氧化物进行掺杂，这样稀土元素元素与氧(O)元素二者之间可以形成键能较强的离子键，其键能要远远大于原来的第一金属氧化物半导体层中的金属元素与氧(O)元素之间的键能，这样可以使得第一金属氧化物半导体层102材料性能更加稳定，避免受到光照、制作工艺、外界水氧等因素的影响，从而可以保证第一金属氧化物半导体层102的结构的稳定性，进而可以提高金属氧化物薄膜晶体管的稳定性。
当然，金属氧化物薄膜晶体管的金属氧化物半导体层也可以采用双层结构构成，如图2所示，金属氧化物薄膜晶体管中设置有一层第一金属氧化物半导体层102，第一金属氧化物半导体层102上可以设置有第二金属氧化物半导体层103，由于第一金属氧化物半导体层102中掺杂有稀土元素，其所形成的的第一金属氧化物半导体层102的结构较为稳定，不容易受到刻蚀工艺的影响，在第二层金属氧化物半导体层103与第一金属氧化物半导体层102叠层设置时，可以避免发生拖尾现象，以保证第一金属氧化物半导体层102和第二金属氧化物半导体层103的稳定性。另一方面，第二金属氧化物半导体层103可以采用稳定性较好的材料制成，虽然第二金属氧化物半导体层103的迁移率不如第一金属氧化物半导体层102的迁移率高，但是在应用过程中，载流子可以主要通过第一金属氧化物半导体层102迁移，以保证金属氧化物薄膜晶体管整体具有较高的迁移率，第二金属氧化物半导体层103可以进一步提高金属氧化物薄膜晶体管整体具有较高的迁移率。
同时，第二金属氧化物半导体层103设置于第一金属氧化物半导体层102上，可以起到一定的遮光作用，避免环境光线或者发光器件的光线直接照射至第一金属氧化物半导体层102上，从而对于第一金属氧化物半导体层102起到良好的保护作用，保证金属氧化物薄膜晶体管整体具有较好的稳定性。
再者，第二金属氧化物半导体层103与第一金属氧化物半导体层102可以采用同一掩膜板进行刻蚀，不会增加工艺步骤，从而不增加制备成本。
在一些实施例中，稀土元素包括：钽(Ta)、铌(Nb)、钕(Nd)、锆(Zr)中的至少一种；第一金属氧化物中的金属元素包括：铟(In)、镓(Ga)、锌(Zn)、锡(Sn)中的至少一种。
第一金属氧化物具体可以为铟镓锌氧化物(IGZO)，铟镓锡氧化物(IGTO)，铟锌氧化物(IZO)，铟锡氧化物(ITO)以及铟锡锌氧化物(ITZO)中的至少一种，其均为具有较高迁移率的金属氧化物，以保证金属氧化物薄膜晶体管整体具有较高的迁移率。稀土元素具体可以为钽(Ta)、铌(Nb)、钕(Nd)、锆(Zr)中的至少一种。以第一金属氧化物为铟镓锌氧化物(IGZO)，稀土元素为钽(Ta)为例，其中钽(Ta)元素的电负性为1.5，氧(O)元素的电负性为3.5，按照一般的电负性差1.7的界限，电负性差大于1.7的两种元素所形成的离子键的键能较强，因此钽(Ta)元素与氧(O)元素所形成的离子键的键能较强，这样可以使得第一金属氧化物的结构更加稳定，避免受到光照、制作工艺、外界水氧等因素的影响，从而可以保证第一金属氧化物半导体层102的稳定性，进而可以提高金属氧化物薄膜晶体管整体的稳定性。
同时，钽(Ta)的离子半径为0.07纳米(nm)，将钽(Ta)掺杂到锌(Zn)的氧化物或者锌(Zn)和铟(In)复合的氧化物中，钽(Ta)可以取代其中的锌(Zn)，而金属氧化物的晶格结构变化很小甚至没有变化。对于离子键 来说，在不考虑氧离子的束缚作用的情况下，由于阳离子具有相对较大的电子云，电子轨道会发生重叠，这样键合结构会很少有设置没有相对较弱的离子键，这与其晶态或者非晶态是无关的，因此可以进一步提高第一金属氧化物的稳定性，以进一步提高金属氧化物薄膜晶体管的稳定性。
可以理解的是，还可以选用电负性为其他数值的稀土元素，例如，铌(Nb)、钕(Nd)、锆(Zr)等，当然，也可以为上述多种金属元素的混合物，只要保证其电负性与氧的电负性差较大即可，以保证二者之间可以形成键能较强的离子键，从而提高金属氧化物薄膜晶体管整体的稳定性。
在一些实施例中，第一金属氧化物半导体层102中的稀土元素的原子百分比为0.01％至5％。
第一金属氧化物半导体层102中的稀土元素以钽(Ta)为例，其中的钽(Ta)的原子百分比为0.01％至5％，其可以保证钽(Ta)与氧(O)之间形成键能较强的离子键，这样可以使得第一金属氧化物的材料性能更加稳定，避免受到光照、制作工艺、外界水氧等因素的影响，从而可以保证第一金属氧化物半导体层102的稳定性，进而可以提高金属氧化物薄膜晶体管整体的稳定性。
在此需要说明的是，稀土元素为上述的铌(Nb)、钕(Nd)、锆(Zr)，或者钽(Ta)、铌(Nb)、钕(Nd)、锆(Zr)中的多种金属元素的混合物时，其原子百分比同样可以为0.01％至5％，具体数值可以根据实际需要进行设置。
优选地，第一金属氧化物半导体层102中的稀土元素的原子百分比为0.15％或0.2％。此时，可以通过抑制氧空位的形成和减少IGZO膜中的杂质而有效地减少载流子俘获缺陷，从而可以保证第一金属氧化物具有较强的稳定性，以提高金属氧化物薄膜晶体管整体的稳定性。
在一些实施例中，第一金属氧化物半导体层102中的霍尔迁移率大于或 等于31cm2/V.s。第一金属氧化物半导体层102中的载流子的浓度大于或等于3.5×E18cm-3。
第一金属氧化物半导体层102中载流子的霍尔迁移率和载流子的浓度较高，可以保证使得第一金属氧化物半导体层102具有较高的迁移率，以保证金属氧化物薄膜晶体管整体具有较高的迁移率。
在一些实施例中，第一金属氧化物半导体层102的刻蚀坡角度为40度至60度，可以保证在多个膜层叠层设置时，可以保证第一金属氧化物半导体层102之上的膜层可以得到有效支撑，避免刻蚀坡度角过大或者或小影响多层膜层之间的贴合稳定性。同时可以避免发生拖尾现象，以保证第一金属氧化物半导体层102和第二金属氧化物半导体层103的稳定性。
在一些实施例中，第一金属氧化物半导体层102与第二金属氧化物半导体层103的刻蚀侧面相接触，且第一金属氧化物半导体层102的刻蚀坡角度与第二金属氧化物半导体层103的刻蚀坡角度相等。
在实际应用中，第二金属氧化物半导体层103的面积可以与第一金属氧化物半导体层102的面积大致相等，第二金属氧化物半导体层103在基底101上的正投影位于第一金属氧化物半导体层102在基底101在基底101的正投影内，同时，第一金属氧化物半导体层102与第二金属氧化物半导体层103可以形成较为平整的刻蚀侧面，这样第二金属氧化物半导体层103可以覆盖第一金属氧化物半导体层102，以起到良好的遮光作用，避免环境光线或者发光器件的光线直接照射至第一金属氧化物半导体层102上，从而对于第一金属氧化物半导体层102起到良好的保护作用，并且可以在制备过程中避免发生拖尾现象，保证金属氧化物薄膜晶体管整体具有较好的稳定性。
在一些实施例中，如图1和图2所示，金属氧化物薄膜晶体管还包括：位于第一金属氧化物半导体层102靠近基底101一侧的栅极104；栅极104在基底101上的正投影位于第一金属氧化物半导体层102在基底101上的正 投影内。
如图1所示，在仅设置有第一金属氧化物半导体层102的金属氧化物薄膜晶体管中，栅极104可以位于第一金属氧化物半导体层102靠近基底101的一侧，栅极104与第一金属氧化物半导体层102之间可以设置有栅极绝缘层，以避免第一金属氧化物半导体层102与栅极104之间发生短路，以构成底栅型薄膜金属氧化物薄膜晶体管，在栅极104输入开启控制信号时，可以使得第一金属氧化物半导体层102和第二金属氧化物半导体层103处于导通状态。如果该薄膜晶体管金属氧化物薄膜晶体管为N型晶体管，栅极104输入高电平信号时，第一有源层金属氧化物半导体层102和第二金属氧化物半导体层103可以处于导通状态，如果该金属氧化物薄膜晶体管为P型晶体管，栅极104输入低电平信号时，第一金属氧化物半导体层102和第二金属氧化物半导体层103可以处于导通状态。
如图2所示，在设置有第一金属氧化物半导体层102和第二金属氧化物半导体层103双层结构的金属氧化物薄膜晶体管中，栅极104可以位于第一金属氧化物半导体层102靠近基底101的一侧，栅极104与第一金属氧化物半导体层102之间可以设置有栅极绝缘层，以避免第一有源层金属氧化物半导体层102与栅极104之间发生短路，以构成底栅型金属氧化物薄膜晶体管，在栅极104输入开启控制信号时，可以使得第一金属氧化物半导体层102处于导通状态。如果该金属氧化物薄膜晶体管为N型晶体管，栅极104输入高电平信号时，第一金属氧化物半导体层102可以处于导通状态，如果该金属氧化物薄膜晶体管为P型晶体管，栅极104输入低电平信号时，第一金属氧化物半导体层102可以处于导通状态。
在底栅型金属氧化物薄膜晶体管中，栅极104可以起到一定的遮光作用。在液晶显示装置中，栅极104可以阻挡由背光源发出的光线直接照射至第一金属氧化物半导体层102上，从而对于第一金属氧化物半导体层102起到良 好的保护作用，保证金属氧化物薄膜晶体管整体具有较好的稳定性。
图3为本公开至少一个实施例提供的又一种薄膜晶体管金属氧化物薄膜晶体管的结构示意图，如图3所示，金属氧化物薄膜晶体管还包括：位于第一金属氧化物半导体层102背离基底101一侧的栅极104；栅极104在基底101上的正投影位于第一金属氧化物半导体层102在基底102上的正投影内。
在仅设置有第一金属氧化物半导体层102的金属氧化物薄膜晶体管中，栅极104可以位于第一金属氧化物半导体层102背离基底101的一侧，栅极104与第一金属氧化物半导体层102之间可以设置有栅极绝缘层，以避免第一金属氧化物半导体层102与栅极104之间发生短路，以构成顶栅型薄膜金属氧化物薄膜晶体管，在栅极104输入开启控制信号时，可以使得第一金属氧化物半导体层102处于导通状态。如果该金属氧化物薄膜晶体管为N型晶体管，栅极104输入高电平信号时，第一金属氧化物半导体层102可以处于导通状态，如果该金属氧化物薄膜晶体管为P型晶体管，栅极104输入低电平信号时，第一金属氧化物半导体层102可以处于导通状态。
图4为本公开至少一个实施例提供的再一种金属氧化物薄膜晶体管的结构示意图，如图4所示，金属氧化物薄膜晶体管还包括：位于第二金属氧化物半导体层103背离基底101一侧的栅极104；栅极104在基底101上的正投影位于第一金属氧化物半导体层102在基底101上的正投影内。
在设置有第一金属氧化物半导体层102和第二金属氧化物半导体层103双层结构的金属氧化物薄膜晶体管中，栅极104可以位于第二金属氧化物半导体层102背离基底101的一侧，栅极104与第二金属氧化物半导体层103之间可以设置有栅极绝缘层，以避免第二金属氧化物半导体层103与栅极104之间发生短路，以构成顶栅型金属氧化物薄膜晶体管，在栅极104输入开启控制信号时，可以使得第一金属氧化物半导体层102和第二金属氧化物半导体层103处于导通状态。如果该金属氧化物薄膜晶体管为N型晶体管，栅极 104输入高电平信号时，第一金属氧化物半导体层102和第二金属氧化物半导体层103可以处于导通状态，如果该金属氧化物薄膜晶体管为P型晶体管，栅极104输入低电平信号时，第一金属氧化物半导体层102和第二金属氧化物半导体层103可以处于导通状态。
在顶栅型金属氧化物薄膜晶体管中，栅极104可以起到一定的遮光作用。在有机发光二极管显示装置中，栅极104可以阻挡由发光器件发出的光线直接照射至第一金属氧化物半导体层101上，从而对于第一金属氧化物半导体层102起到良好的保护作用，保证金属氧化物薄膜晶体管整体具有较好的稳定性。
在一些实施例中，如图1和图3所示，金属氧化物薄膜晶体管还包括：位于第一金属氧化物半导体层102背离基底101一侧的源极105和漏极106；第一金属氧化物半导体层102具有第一沟道区1020及位于第一沟道区1020两端的第一源极接触区1021和第一漏极接触区1022；源极105与第一源极接触区1021电连接，漏极106与第一漏极接触区1022电连接。
如图1和图3所示的金属氧化物薄膜晶体管中仅设置有一层第一金属氧化物半导体层102，在制备过程中，可以采用重掺杂或粒子注入工艺，将第一金属氧化物半导体层102的两端进行导体化处理，形成第一沟道区1020以及第一沟道区1020两端的第一源极接触区1021和第一漏极接触区1022。源极105与第一源极接触区1021之间形成欧姆接触，漏极106与第一漏极接触区1022之间也形成欧姆接触。当栅极104输入开启控制信号时，第一金属氧化物半导体层102可以导通，使得数据信号等由金属氧化物薄膜晶体管的源极105传输至漏极106，实现控制信号传输的功能。
在一些实施例中，如图2和图4所示，金属氧化物薄膜晶体管还包括位于第二金属氧化物半导体层103背离基底101一侧的源极105和漏极106；第二金属氧化物半导体层103具有第二沟道区1030及位于第二沟道区1030 两端的第二源极接触区1031和第二漏极接触区1032；源极105与第二源极接触区1031电连接，漏极106与第二漏极接触区1032电连接。
如图2和图4所示的金属氧化物薄膜晶体管中仅设置有两层金属氧化物半导体层，即叠置的第一金属氧化物半导体层102和第二金属氧化物半导体层103，在制备过程中，可以采用重掺杂或粒子注入工艺，将第一金属氧化物半导体层102和第二金属氧化物半导体层103的两端均进行导体化处理，形成第一沟道区1020、第一沟道区1020两端的第一源极接触区1021和第一漏极接触区1022，以及第二沟道区1030、第二沟道区1030两端的第二源极接触区1031和第二漏极接触区1032。源极105与第一源极接触区1021及第二源极接触区1031之间形成欧姆接触，漏极106与第一漏极接触区1022及第二漏极接触区1032之间也形成欧姆接触。当栅极104输入开启控制信号时，第一金属氧化物半导体层102和第二金属氧化物半导体层103可以导通，使得数据信号等由金属氧化物薄膜晶体管的源极105传输至漏极106，实现控制信号传输的功能。
本公开实施例还提供了一种阵列基板，在本公开实施例及之后的描述中，将以图1中所示的仅设置一层第一金属氧化物半导体层102的底栅型金属氧化物薄膜晶体管为例进行说明。同时，该阵列基板可以为液晶阵列基板，其可以应用于液晶显示装置中，也可以为有机发光二极管阵列基板，其可以应用于有机发光二极管显示装置中，在之后的描述中将以阵列基板应用于液晶显示装置为了进行说明。该阵列基板为有机发光二极管阵列基板时，其实现原理及有益效果与液晶阵列基板的实现原理及有益效果相同，将不再进行赘述。
图5为本公开至少一个实施例提供的一种阵列基板的结构示意图，如图5所示，该阵列基板包括多个如上述任一实施例提供的金属氧化物薄膜晶体管(图中仅示出了一个)，该阵列基板还包括：第一保护层107、有机绝缘层 108和第二保护层109；第一保护层107位于源极105和漏极106所在层背离基底101的一侧；第二保护层108位于第一保护层107背离基底101的一侧；有机绝缘层109位于第一保护层107和第二保护层108之间。
第一保护层107和第二保护层109一般采用无机材料制成，第一保护层107和第二保护层109对第一金属氧化物半导体层102进行保护，防止在之后的刻蚀工艺对第一金属氧化物半导体层102造成损坏。有机绝缘层108可以设置于第一保护层107和第二保护层109之间，以提高第一保护层107和第二金属氧化物半导体层109的柔性，可以缓解在应用过程产生的应力，避免采用无机材料制成的第一保护层107和第二保护层109受到应力而断裂。同时，可以防止外界的水氧等气体渗透至第一金属氧化物半导体层102，从而可以对第一金属氧化物半导体层102可以进一步进行保护。
在一些实施例中，第一保护层107可以包括：多个子保护层。
第一保护层107可以分成多个子保护层，例如，如图6所示的阵列基板中第一保护层107分层两个子保护层，即第一保护层1071和第二子保护层1072。或者，如图7所示的阵列基板中第一保护层107分成三个子保护层，即第一子保护层1071、第二子保护层1072和第三子保护层1073。多个子保护层可以对第一金属氧化物半导体层102进一步进行保护，同时多个子保护层可以进一步缓解应力，避免第一保护层107和第二保护层109受到应力而发生断裂，从而进一步提高金属氧化物薄膜晶体管中的第一金属氧化物半导体层102的稳定性。
在一些实施例中，第一保护层107中的至少一个子保护层的材料为氧化硅；第二保护层109的材料包括氮化硅。
第一保护层107中的由氧化物构成的子保护层离第一金属氧化物半导体层较近，可以对第一金属氧化物半导体层102进行补氧，通过制备氧化硅膜层时可以将氧元素注入至第一金属氧化物半导体层102中，避免第一金属氧 化物半导体层102产生缺陷，以提高第一有源层金属氧化物半导体层102的稳定性。第二保护层109可以采用氮化硅制成，其中含有较低氢元素，以避免氢元素对影响第一金属氧化物半导体层102的稳定性。可以理解的是，第一保护层107中除了氧化硅构成的子保护层之外，其余的子保护层也可以采用氮化硅构成，以进一步提高第一金属氧化物半导体层102的稳定性。
在一些实施例中，如图5至图7所示，阵列基板还包括：公共电极110和像素电极111；公共电极110位于第二保护层109靠近基底101的一侧；像素电极111位于第二保护层109背离基底101的一侧。
在液晶显示装置中，阵列基板中的公共电极110中可以输入公共信号，像素电极111中可以输入像素信号，公共电极110和像素电极111之间可以形成电场驱动液晶层中的液晶分子偏转，实现显示功能。可以理解的是，该阵列基板还可以用于有机发光二极管显示装置中，阵列基板中将不再设置公共电极110及像素电极111等结构。其结构中可以设置发光器件，阵列基板中的金属氧化物薄膜晶体管的漏极109可以与发光器件的阳极电连接，以为发光器件提供驱动信号，使得发光器件发光，实现显示功能。
在一些实施例中，公共电极110在基底101上的正投影与像素电极111在基底101上的正投影不交叠。
公共电极110与像素电极111不交叠，二者之间可以形成电场，以驱动VA型液晶显示装置中的液晶分子发生偏转，以实现显示功能。可以理解的是，公共电极110和像素电极111还可以正对设置，以构成TN型显示装置。当然，公共电极110和像素电极111还可以为其他的设置方式，在此不在一一列举。
在此需要说明的是，图5至图7所示的阵列基板中的金属氧化物薄膜晶体管均为底栅型金属氧化物薄膜晶体管，当然，本公开实施例提供的阵列基板中的金属氧化物薄膜晶体管还可以为顶栅型金属氧化物薄膜晶体管，其结 构具体如图8至图10所示，其实现原理及有益效果与上述的图5至图7所示的阵列基板的实现原理及有益效果相同，在此不在赘述。
本公开实施例还提供了一种显示装置，该显示装置包括如上述任一实施例提供的阵列基板，还包括彩膜基板及液晶层；其中彩膜基板与阵列基板相对设置，液晶层位于阵列基板与彩膜基板之间。液晶层中的液晶分子可以在阵列基板提供的驱动信号下发生偏转，以透过背光源发出的光线，彩膜基板可以将透过的光线转换为不同的颜色，以实现多彩显示。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，其实现原理及有益效果与上述的阵列基板及金属氧化物薄膜晶体管的实现原理及有益效果相同，在此不再进行赘述。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (12)

  1. 一种金属氧化物薄膜晶体管，其中，包括：基底、及位于所述基底上的第一金属氧化物半导体层、及位于所述第一金属氧化物半导体层背离所述基底一侧的第二金属氧化物半导体层；所述第一金属氧化物半导体层的载流子迁移率高于所述第二金属氧化物半导体层的载流子迁移率；
    所述第一金属氧化物半导体层的材料包括：掺杂有稀土元素的第一金属氧化物；其中，所述稀土元素的电负性与氧元素的电负性的差值大于或等于所述第一金属氧化物中的金属元素与氧元素的电负性的差值。
  2. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述稀土元素包括：钽、铌、钕、锆中的至少一种。
  3. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述第一金属氧化物中的金属元素包括：铟、镓、锌、锡中的至少一种。
  4. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述第一金属氧化物半导体层中的所述稀土元素的原子百分比为0.01％至5％。
  5. 根据权利要求4所述的金属氧化物薄膜晶体管，其中，所述第一金属氧化物半导体层中的所述稀土元素的原子百分比为0.15％或0.2％。
  6. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述第一金属氧化物半导体层中的霍尔迁移率大于或等于31cm2/V.s。
  7. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述第一金属氧化物半导体层中的载流子的浓度大于或等于3.5×E18cm-3。
  8. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述第一金属氧化物半导体层的刻蚀坡度角为40度至60度。
  9. 根据权利要求8所述的金属氧化物薄膜晶体管，其中，所述第一金属氧化物半导体层与所述第二金属氧化物半导体层的刻蚀侧面相接触，且所述第一金属氧化物半导体层的刻蚀坡角度与所述第二金属氧化物半导体层的刻蚀坡角度相等。
  10. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述第二金属氧化物中的金属元素包括：铟、镓、锌、锡中的至少一种。
  11. 一种阵列基板，其中，包括多个如权利要求1至10任一项所述的金属氧化物薄膜晶体管。
  12. 一种显示装置，其中，包括如权利要求11所述的阵列基板。
PCT/CN2022/076578 2022-02-17 2022-02-17 金属氧化物薄膜晶体管、阵列基板及显示装置 WO2023155091A1 (zh)

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