WO2023184236A1 - 金属氧化物薄膜晶体管、阵列基板及显示装置 - Google Patents

金属氧化物薄膜晶体管、阵列基板及显示装置 Download PDF

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WO2023184236A1
WO2023184236A1 PCT/CN2022/084064 CN2022084064W WO2023184236A1 WO 2023184236 A1 WO2023184236 A1 WO 2023184236A1 CN 2022084064 W CN2022084064 W CN 2022084064W WO 2023184236 A1 WO2023184236 A1 WO 2023184236A1
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metal oxide
layer
silicon nitride
nitride layer
thin film
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PCT/CN2022/084064
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English (en)
French (fr)
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贺家煜
曲燕
雷利平
宁策
李正亮
胡合合
黄杰
姚念琦
赵坤
李菲菲
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京东方科技集团股份有限公司
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Priority to PCT/CN2022/084064 priority Critical patent/WO2023184236A1/zh
Priority to CN202280000617.6A priority patent/CN117157768A/zh
Priority to US18/028,114 priority patent/US20240304698A1/en
Publication of WO2023184236A1 publication Critical patent/WO2023184236A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to a metal oxide thin film transistor, an array substrate and a display device.
  • metal oxide thin film transistors Due to its higher mobility, metal oxide thin film transistors have gradually increased their share in the high-end display market. Metal oxide technology is also considered to be the most likely way to replace existing low-temperature polysilicon technology. With the upgrading of display products, the development of ultra-high mobility (mobility greater than 25cm 2 /Vs or even 50cm 2 /Vs) metal oxide thin film transistors has become the research and development focus of various panel manufacturers.
  • metal oxide thin film transistors have increasingly higher requirements for stability.
  • different preparation processes are increasingly used, which places higher requirements on the oxygen-supplying and hydrogen-blocking capabilities of the gate insulating layer and passivation layer.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a metal oxide thin film transistor, an array substrate and a display device.
  • embodiments of the present disclosure provide a metal oxide thin film transistor, which includes: a substrate and a metal oxide semiconductor layer located on the substrate; the Hall mobility of the metal oxide semiconductor layer is greater than or Equal to 25cm 2 /Vs; the metal oxide thin film transistor further includes: a gate and a gate insulating layer located between the substrate and the metal oxide semiconductor layer;
  • the gate insulating layer includes: a stacked first silicon nitride layer, a second silicon nitride layer and a first silicon oxide layer; wherein the first silicon oxide layer is in contact with the metal oxide semiconductor layer , two surfaces of the second silicon nitride layer are in contact with the first silicon nitride layer and the first silicon nitride layer respectively;
  • the content of hydrogen atoms in at least part of the second silicon nitride layer is less than 30% of the content of hydrogen atoms in at least part of the first silicon nitride layer.
  • the hydrogen atom content of at least part of the first silicon nitride layer is 6.8 ⁇ 10 20 cm -3 to 1.5 ⁇ 10 21 cm -3 ;
  • the content of hydrogen atoms in at least part of the second silicon nitride layer ranges from 2.2 ⁇ 10 20 cm -3 to 5.8 ⁇ 10 20 cm -3 .
  • the hydrogen atom content in at least part of the first silicon oxide layer is less than 10% of the hydrogen atom content in at least part of the second silicon nitride layer.
  • the hydrogen atom content of at least part of the first silicon oxide layer is 2.2 ⁇ 10 19 cm -3 to 5.8 ⁇ 10 19 cm -3 .
  • the thickness of the second silicon nitride layer is less than 40% of the thickness of the first silicon nitride layer
  • the thickness of the first silicon oxide layer is less than 60% of the thickness of the second silicon nitride layer.
  • the thickness of the first silicon nitride layer is 150 nanometers to 300 nanometers;
  • the thickness of the second silicon nitride layer is 50 nanometers to 180 nanometers;
  • the thickness of the first silicon oxide layer is 30 nanometers to 150 nanometers.
  • the molar ratio of oxygen atoms to silicon atoms in at least part of the first silicon oxide layer is 2.0 to 3.0.
  • the atomic percentage of oxygen atoms in at least part of the first silicon oxide layer is 60% to 70%;
  • the atomic percentage of silicon atoms in at least part of the first silicon oxide layer is 20% to 30%.
  • the molar ratio of nitrogen atoms to silicon atoms in at least part of the first silicon nitride layer and the second silicon nitride layer is 0.8 to 1.0.
  • the atomic percentage of nitrogen atoms in at least part of the first silicon nitride layer and the second silicon nitride layer is both 40% to 50%;
  • the atomic percentage of silicon atoms in at least part of the first silicon nitride layer and the second silicon nitride layer is both 40% to 50%.
  • the atomic percentage of oxygen atoms in at least part of the first silicon nitride layer and the second silicon nitride layer is 2.0% to 5.0%.
  • the metal oxide thin film transistor further includes: a source electrode and a drain electrode located on the metal oxide semiconductor layer, and a first passivation layer located on the source electrode and the drain electrode;
  • the first passivation layer includes: a second silicon oxide layer and a third silicon nitride layer arranged in a stack; the second silicon oxide layer, the metal oxide semiconductor layer, the source electrode and the drain electrode pole contact; the third silicon nitride layer is in contact with the second silicon oxide layer;
  • the content of hydrogen atoms in at least part of the third silicon nitride layer is less than 30% of the content of hydrogen atoms in at least part of the first silicon nitride layer.
  • the metal oxide thin film transistor further includes: a second passivation layer located on the first passivation layer;
  • the second passivation layer includes: a fourth silicon nitride layer;
  • the hydrogen atom content in at least part of the fourth silicon nitride layer is less than 30% of the hydrogen atom content in at least part of the first silicon nitride layer.
  • the metal oxide thin film transistor further includes: an organic insulating layer located between the first passivation layer and the second passivation layer.
  • the metal oxide layer includes: a first metal oxide semiconductor layer or a first metal oxide semiconductor layer and a second metal oxide semiconductor layer arranged in a stack;
  • the Hall mobility of the second metal oxide semiconductor layer is 50% to 60% of the Hall mobility of the first metal oxide semiconductor layer.
  • the thickness of the second metal oxide semiconductor layer is 1 to 5 times the thickness of the first metal oxide semiconductor layer.
  • embodiments of the present disclosure provide an array substrate, which includes the metal oxide thin film transistor provided above.
  • embodiments of the present disclosure provide a display device, which includes the metal oxide thin film transistor provided above or the array substrate provided above.
  • Figure 1 is a schematic structural diagram of a metal oxide thin film transistor provided by at least one embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of another metal oxide thin film transistor provided by at least one embodiment of the present disclosure.
  • Figure 3 is a schematic structural diagram of yet another metal oxide thin film transistor provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of yet another metal oxide thin film transistor provided by at least one embodiment of the present disclosure.
  • metal oxide thin film transistor can be used in liquid crystal display panels (Liquid Crystal Display, LCD), organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panels, mini light-emitting diodes (Mini Light- Emitting Diode) backlight or display panel, Quantum Dot Light Emitting Diode (QLED) display panel and other technologies.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • mini light-emitting diodes Mini Light- Emitting Diode
  • QLED Quantum Dot Light Emitting Diode
  • the metal oxide in the metal oxide thin film transistor is indium gallium zinc oxide IGZO.
  • Oxygen (O) element and metal elements indium (In), gallium (Ga) zinc (Zn) can form compounds, and provide or trap carriers (oxygen vacancies) according to the chemical bond formation.
  • indium (In) can provide an electron transport path, giving IGZO a high mobility.
  • Gallium (Ga) has high ionization energy, which can suppress electron mobility, inhibit the formation of oxygen vacancies, and generate new mobile electrons.
  • Zinc (Zn) can be used as a stabilizer and has strong chemical bonds that can bind oxygen ions. It can form a stable tetrahedral structure to form a relatively stable amorphous grain boundary. It can be seen from the characteristics of each element in IGZO in the metal oxide semiconductor layer that the metal oxide thin film transistor composed of IGZO can have higher mobility.
  • metal oxide thin film transistors in addition to the metal oxide semiconductor layer, there are generally film structures such as gate electrodes, gate insulating layers, source electrodes, drain electrodes, and passivation layers.
  • the gate insulation layer and passivation layer need to have strong oxygen supply and hydrogen blocking capabilities to avoid damage to the metal oxide layer by hydrogen atoms.
  • the current metal oxide thin film transistor The gate insulating layer and passivation layer have low oxygen supply and hydrogen blocking capabilities, which can easily affect the stability of the metal oxide thin film transistor and reduce the life of the metal oxide thin film transistor.
  • embodiments of the present disclosure provide a metal oxide thin film transistor, an array substrate and a display device.
  • the metal oxide thin film transistor and array provided by the disclosure will be compared with the accompanying drawings and specific embodiments below.
  • the substrate and display device are described in further detail.
  • Figure 1 is a schematic structural diagram of a metal oxide thin film transistor provided by at least one embodiment of the present disclosure.
  • the thin film transistor includes: a substrate 101, a metal oxide semiconductor layer 102 located on the substrate 101;
  • the Hall mobility of the physical semiconductor layer 102 is greater than or equal to 25 cm 2 /Vs;
  • the metal oxide thin film transistor also includes: a gate 103 and a gate insulating layer 104 located between the substrate 101 and the metal oxide semiconductor layer; gate insulation
  • the layer 104 includes: a stacked first silicon nitride layer 1041, a second silicon nitride layer 1042 and a first silicon oxide layer 1043; wherein the first silicon oxide layer 1041 is in contact with the metal oxide semiconductor layer 102, and the second silicon nitride layer 1042 is in contact with the metal oxide semiconductor layer 102.
  • Two surfaces of the silicon nitride layer 1042 are in contact with the first silicon nitride layer 1041 and the first silicon nitride layer 1043 respectively; the hydrogen atom content in at least some areas of the second silicon nitride layer 1042 is less than that of the first silicon nitride layer 30% of the hydrogen atom content in at least some areas of 1041.
  • the substrate 101 can be made of rigid materials such as glass, which can improve the carrying capacity of other film layers on the substrate 101 .
  • the substrate 101 can also be made of flexible materials such as polyimide (PI), which can improve the overall bending and tensile resistance of the metal oxide thin film transistor and avoid bending, stretching, and twisting processes.
  • PI polyimide
  • the stress generated in the substrate 101 causes the substrate 101 to break, resulting in poor circuit breaking.
  • the material of the substrate 101 can be reasonably selected according to actual needs to ensure that the metal oxide thin film transistor has good performance.
  • the semiconductor metal oxide layer 102 may be indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc oxide (IZO), indium tin oxide (ITO) and indium tin zinc oxide (ITZO). Made of at least one material, all of which are metal oxides with higher mobility, to ensure that the overall metal oxide thin film transistor has higher mobility.
  • the material of the semiconductor metal oxide layer 102 is IGZO, whose Hall mobility is greater than or equal to 25 cm 2 /Vs.
  • the gate 103 can be made of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), and chromium (Cr). It is made of at least one material, which can form a single-layer structure made of a single material.
  • the gate 103 is a single-layer structure made of aluminum (Al). Of course, it can also be formed of multiple layers made of different materials. Multi-layer structure, for example, a three-layer structure composed of molybdenum (Mo), aluminum (Al), and molybdenum (Mo).
  • the gate 103 can make the metal oxide semiconductor layer 102 conductive when a control signal is input, so as to input a data signal, a reset signal, an initialization signal, etc. It can be understood that other film layers such as buffer layers and barrier layers may also be provided between the substrate 101 and the gate electrode 103, which can prevent water and oxygen from intruding into the metal oxide semiconductor layer 103 on the side of the substrate 101. It is made using techniques and materials in related technologies and will not be described in detail here.
  • the gate insulating layer 104 can be a multi-layer structure, such as a three-layer structure composed of a first silicon nitride layer 1041, a second silicon nitride layer 1042 and a first silicon oxide layer 1043.
  • the first silicon oxide layer 1043 can be combined with a metal
  • the oxide semiconductor layer 102 is in direct contact
  • the first silicon nitride layer 1041 and the second silicon nitride layer 1042 are in direct contact
  • the second silicon nitride layer 1042 is in direct contact with the first silicon oxide layer 1043 .
  • the first silicon oxide layer 1043 can directly protect the metal oxide semiconductor layer 102. However, due to the material characteristics of the first silicon oxide layer 1043, its texture is relatively brittle and generally needs to be used in conjunction with a silicon nitride layer to increase the gate insulating layer. The overall flexibility of 104 prevents the gate insulating layer 104 from breaking during application, causing a short circuit between the metal oxide semiconductor layer 102 and the gate 103 and affecting the performance of the metal oxide thin film transistor.
  • the first silicon nitride layer 1041 can use reactive gases and adopt chemical vapor phase. It is formed by deposition, which can increase the overall flexibility of the gate insulating layer 104. However, during the preparation process, a large number of hydrogen atoms tend to remain in the first silicon nitride layer 1041.
  • a gap is also provided between the first silicon nitride layer 1041 and the first silicon oxide layer 1043.
  • the second silicon nitride layer 1042 can be formed by chemical vapor deposition using a reaction gas that does not contain substantially hydrogen atoms. Wherein, the hydrogen atom content in at least part of the second silicon nitride layer 1042 is less than 30% of the hydrogen atom content in at least part of the first silicon nitride layer 1041 .
  • the second silicon nitride layer 1042 can be prepared using reaction gases such as trisilylamine and nitrogen that basically do not contain hydrogen atoms, so as to avoid a high content of hydrogen remaining in the second silicon nitride layer 1042 atoms, thereby avoiding damage to the metal oxide semiconductor layer 102 by hydrogen atoms, thereby improving the stability of the overall metal oxide thin film transistor and improving the life of the overall metal oxide thin film transistor.
  • reaction gases such as trisilylamine and nitrogen that basically do not contain hydrogen atoms
  • the gate insulating layer 104 of the three-layer structure can be made using the same mask plate, and the mask and etching process will not be increased during the preparation process, and the process steps will not be added, thus the preparation cost will not be increased. It can be understood that the gate insulating layer 104 can also be formed with four-layer, five-layer, or other structures. The implementation principle is similar to the above, and will not be described again here.
  • the hydrogen atom content in at least a part of the first silicon nitride layer 1041 is 6.8 ⁇ 10 20 cm -3 to 1.5 ⁇ 10 21 cm -3 ; the content of hydrogen atoms in at least a part of the second silicon nitride layer 1042 is The hydrogen atom content is 2.2 ⁇ 10 20 cm -3 to 5.8 ⁇ 10 20 cm -3 .
  • the hydrogen atom content in at least a partial region of the second silicon nitride layer 1042 is much smaller than the hydrogen atom content in at least a partial region of the first silicon nitride layer 1041 , wherein the hydrogen atom content in at least a partial region of the second silicon nitride layer 1042
  • the atomic content is generally on the order of 10 20
  • the hydrogen atom content in at least some areas of the first silicon nitride layer 1041 is generally on the order of 10 21 .
  • the hydrogen atom content in at least some areas of the second silicon nitride layer 1042 is less, so that This prevents a large number of hydrogen atoms in the first silicon nitride layer 1041 from being transmitted to the metal oxide semiconductor layer 102 and causes damage to it, thereby improving the stability of the overall metal oxide thin film transistor and improving the performance of the overall metal oxide thin film transistor. life.
  • the hydrogen atom content in at least a portion of the first silicon oxide layer 1043 is less than 10% of the hydrogen atom content in at least a portion of the second silicon nitride layer 1042 .
  • monosilane and nitrous oxide can be used to form the first silicon oxide layer 1043 by chemical vapor deposition.
  • the above reaction gases monosilane and nitrous oxide do not contain hydrogen atoms.
  • hydrogen ions are basically not introduced, and the hydrogen atom content of at least a partial region of the first silicon oxide layer 1043 is smaller than the hydrogen atom content of at least a partial region of the second silicon nitride layer 1042. From the above, it can be seen that the second The content of hydrogen atoms in at least part of the silicon nitride layer 1042 is itself small.
  • the content of hydrogen atoms in at least part of the formed first silicon oxide layer 1043 is less or even almost zero, so that the first nitrogen can be further avoided.
  • a large number of hydrogen atoms in the silicon layer 1041 are conducted to the metal oxide semiconductor layer 102 and cause damage to it, thereby improving the stability of the overall metal oxide thin film transistor and improving the life of the overall metal oxide thin film transistor.
  • the content of hydrogen atoms in at least part of the first silicon oxide layer 1043 may be 2.2 ⁇ 10 19 cm -3 to 5.8 ⁇ 10 19 cm -3 . It can be understood that other reactive gases can be used and new processes can be used to make the hydrogen atom content in at least part of the first silicon oxide layer 1043 lower, or even 0, to protect the metal oxide semiconductor layer 102. By preventing hydrogen atoms from causing damage to the metal oxide semiconductor layer 102, the stability of the overall metal oxide thin film transistor can be improved, and the life of the overall metal oxide thin film transistor can also be improved.
  • the thickness of the second silicon nitride layer 1042 is less than 40% of the thickness of the first silicon nitride layer 1041 ; the thickness of the first silicon oxide layer 1043 is less than 60% of the thickness of the second silicon nitride layer 1042 .
  • the thickness of the first silicon nitride layer 1041 in the metal oxide thin film transistor is relatively thick, which can alleviate the flexibility of the entire gate insulating layer 104 and prevent the gate insulating layer 104 from breaking, causing a gap between the metal oxide layer 102 and the gate 103 A short circuit occurs between them, affecting the performance of the metal oxide thin film transistor.
  • the thickness of the second silicon nitride layer 1042 is smaller than the thickness of the first silicon nitride layer 1041.
  • the content of hydrogen atoms in the second silicon nitride layer 1042 is lower, which can avoid a large amount of hydrogen atoms in the first silicon nitride layer 1041.
  • Hydrogen atoms are conducted into the metal oxide semiconductor layer 102 and cause damage to it, thereby improving the stability of the overall metal oxide thin film transistor and improving the life of the overall metal oxide thin film transistor.
  • the thickness of the first silicon oxide layer 1043 is smaller than the thickness of the second silicon nitride layer 1042. It is in direct contact with the metal oxide semiconductor layer 102 and can protect the metal oxide semiconductor layer 102 from hydrogen atoms attacking the metal oxide.
  • the semiconductor layer 102 is damaged, and at the same time, the overall gate insulating layer 104 can be prevented from being too thick and affecting the performance of the metal oxide thin film transistor.
  • the thickness of the first silicon nitride layer 1041 is 150 nanometers to 300 nanometers; the thickness of the second silicon nitride layer 1042 is 50 nanometers to 180 nanometers; and the thickness of the first silicon oxide layer 1043 is 30 nanometers to 150 nanometers.
  • the thickness of the first silicon nitride layer 1041 may be 218.4 nanometers, the thickness of the second silicon nitride layer 1042 may be 88.45 nanometers, and the thickness of the first silicon oxide layer 1043 The thickness can be 52.88 nm. It can be understood that the thickness of each film layer in the gate insulating layer 104 can also be set according to actual needs, and will not be listed one by one here.
  • the thickness of the metal oxide semiconductor layer 102 is 2 nanometers to 70 nanometers. If the thickness of the metal oxide semiconductor layer 102 is too small, its Hall mobility cannot meet the need for high mobility. If the thickness of the metal oxide semiconductor layer 102 is too large, it will easily become a conductor, affecting the performance of the metal oxide thin film transistor. .
  • the thickness of the metal oxide semiconductor layer 102 in the metal oxide thin film transistor provided by the embodiment of the present disclosure may be 10 nanometers. It can be understood that the thickness of the metal oxide semiconductor layer 102 can also be set reasonably according to the material of the metal oxide semiconductor layer 102 , which will not be listed here.
  • the molar ratio of oxygen atoms to silicon atoms in at least part of the first silicon oxide layer 1043 is 2.0 to 3.0.
  • the content of oxygen atoms in at least some areas of the first silicon oxide layer 1043 is relatively large, and the oxygen atoms in the first silicon oxide layer 1043 can be conducted to the metal oxide semiconductor layer 102 to supplement oxygen to the metal oxide semiconductor layer 102, thereby avoiding the need for preparation and application.
  • the oxygen atoms of the metal oxide semiconductor layer 102 are missing and become conductive, which affects the performance of the metal oxide thin film transistor, thereby improving the performance of the metal oxide thin film transistor and increasing the life of the overall metal oxide thin film transistor.
  • the atomic percentage of oxygen atoms in at least part of the first silicon oxide layer 1043 is 60% to 70%; the atomic percentage of silicon atoms in at least part of the first silicon oxide layer is 20% to 30%.
  • the molar ratio of oxygen atoms to silicon atoms in at least part of the first silicon oxide layer 1043 may be 2.18.
  • the percentage of oxygen atoms in the first silicon oxide layer 1043 is 67.23% and the percentage of silicon atoms is 30.74. % to ensure strong oxygen supplementation ability.
  • the molar ratio of nitrogen atoms to silicon atoms in at least part of the first silicon nitride layer 1041 and the second silicon nitride layer 1042 is both 0.8 to 1.0.
  • the contents of nitrogen atoms and silicon atoms in at least some areas of the first silicon nitride layer 1041 and the second silicon nitride layer 1042 are relatively close. Specifically, at least one of the first silicon nitride layer 1041 and the second silicon nitride layer 1042 has a similar content.
  • the atomic percentages of nitrogen atoms in some areas are both 40% to 50%; the atomic percentages of silicon atoms in at least some areas of the first silicon nitride layer 1041 and the second silicon nitride layer 1042 are both 40% to 50%.
  • the nitrogen atom content in the first silicon nitride layer 1041 and the second silicon nitride layer 1042 can be 48.35%, and the silicon atom content can be 47.2%, to ensure that the first silicon nitride layer 1041 and the second nitrogen atom content
  • the silicon layer 1042 has good insulation properties and good flexibility.
  • the atomic percentage of oxygen atoms in at least part of the first silicon nitride layer 1041 and the second silicon nitride layer 1042 is both 2.0% to 5.0%.
  • the first silicon nitride layer 1041 and the second silicon nitride layer 1042 contain a small amount of oxygen atoms. Specifically, the content of oxygen atoms in the first silicon nitride layer 1041 and the second silicon nitride layer 1042 may be 4.45%. , which can supplement oxygen to the metal oxide semiconductor layer 102 to a certain extent to ensure stable performance of the metal oxide thin film transistor.
  • the metal oxide thin film transistor further includes: a source electrode 105 and a drain electrode 106 located on the metal oxide semiconductor layer 102, and a first passivation layer 107 located on the source electrode 105 and the drain electrode 106;
  • a passivation layer 107 includes: a second silicon oxide layer 1071 and a third silicon nitride layer 1072 arranged in a stack; the second silicon oxide layer 1071 is in contact with the metal oxide semiconductor layer 102, the source electrode 105 and the drain electrode 106;
  • the silicon trinitride layer 1072 is in contact with the second silicon oxide layer 1071; the hydrogen atom content in at least part of the third silicon nitride layer 1072 is less than 30% of the hydrogen atom content in at least part of the first silicon nitride layer 1041.
  • the source electrode 105 and the drain electrode 106 of the metal oxide thin film transistor can be on the metal oxide semiconductor layer 102.
  • the source electrode 105 and the drain electrode 106 can be connected to part of the metal oxide semiconductor layer 102.
  • the control input is at the gate electrode 103. When the signal is generated, the source electrode 105 and the drain electrode 106 can be connected through the metal oxide semiconductor layer 102 to realize the control function of the metal oxide thin film transistor.
  • the first passivation layer 107 may cover the metal oxide semiconductor layer 102, the source electrode 105 and the drain electrode 106, wherein the second silicon oxide layer 1071 in the first passivation layer 107 may be in direct contact with the metal oxide semiconductor layer 102,
  • the third silicon nitride layer 1072 is in contact with the second silicon oxide layer 1071 , and the second silicon oxide layer 1071 can protect the metal oxide layer 102 .
  • the content of hydrogen atoms in the third silicon nitride layer 1072 is relatively low, which can prevent hydrogen atoms from being transmitted to the metal oxide semiconductor layer 102 and cause damage to it, thus improving the stability of the overall metal oxide thin film transistor and improving the overall stability of the metal oxide thin film transistor. Lifetime of metal oxide thin film transistors.
  • the material, thickness and other parameters of the third silicon nitride layer 1072 in the first passivation layer 107 may be the same as the material, thickness and other parameters of the second silicon nitride layer 1042 in the gate insulating layer 104 The same to reduce process difficulty and save preparation costs.
  • FIG. 2 is a schematic structural diagram of another metal oxide thin film transistor provided by at least one embodiment of the present disclosure.
  • the metal oxide thin film transistor further includes: a first passivation layer 107
  • the second passivation layer 108 on the second passivation layer 108 includes: a fourth silicon nitride layer 1081; the hydrogen atom content in at least some areas of the fourth silicon nitride layer 1081 is less than that of at least part of the first silicon nitride layer 1041. Some areas contain 30% hydrogen atoms.
  • the metal oxide thin film transistor may include a double-layer passivation layer, namely a first passivation layer 107 and a second passivation layer 108, and a fourth silicon nitride layer in the second passivation layer 108.
  • the low content of hydrogen atoms in 1081 can prevent hydrogen atoms from being transmitted to the metal oxide semiconductor layer 102 and causing damage to it, thereby improving the stability of the overall metal oxide thin film transistor and improving the life of the overall metal oxide thin film transistor. .
  • the material, thickness and other parameters of the fourth silicon nitride layer 1081 in the second passivation layer 108 may be the same as the material, thickness and other parameters of the second silicon nitride layer 1042 in the gate insulating layer 104 The same to reduce process difficulty and save preparation costs.
  • the metal oxide thin film transistor further includes: an organic insulating layer 109 located between the first passivation layer 107 and the second passivation layer 108 .
  • the organic insulating layer 109 has strong flexibility, which can improve the flexibility of each film layer in the first passivation layer 107 and the second passivation layer 108 and prevent the first passivation layer 107 and the second passivation layer from being damaged during the application process. Each film layer in 108 is broken, thereby improving the performance of the metal oxide thin film transistor.
  • FIG. 3 is a schematic structural diagram of yet another metal oxide thin film transistor provided by at least one embodiment of the present disclosure
  • FIG. 4 is a structural schematic diagram of yet another metal oxide thin film transistor provided by at least one embodiment of the present disclosure.
  • the metal oxide layer 102 includes: a first metal oxide semiconductor layer 1021 (the metal oxide semiconductor layer 102 in the metal oxide thin film transistor shown in Figures 1 and 2 is A single layer arrangement, including only one first metal oxide semiconductor layer 1021) or a stacked first metal oxide semiconductor layer 1021 and a second metal oxide semiconductor layer 1022; the second metal oxide semiconductor layer 1022 has a
  • the Hall mobility is 50% to 60% of the Hall mobility of the first metal oxide semiconductor layer 1021 .
  • the metal oxide semiconductor layer 102 in the metal oxide thin film transistor may have a single-layer structure or a double-layer structure, wherein the Hall mobility of the first metal oxide semiconductor layer 1021 is greater than or equal to 25 cm 2 /Vs to ensure The overall metal oxide semiconductor layer 102 has a larger Hall mobility, and the second metal oxide semiconductor layer 1022 has a smaller Hall mobility than the first metal oxide semiconductor layer 1021, without affecting the overall metal oxide semiconductor layer. While 102 has good Hall mobility, the second metal oxide semiconductor layer 1022 can protect the first metal oxide semiconductor layer 1021 from the influence of light, water and oxygen on the first metal oxide semiconductor layer 1021. This can improve the stability of the metal oxide thin film transistor and increase the life of the metal oxide thin film transistor.
  • the thickness of the second metal oxide semiconductor layer 1022 is 1 to 5 times the thickness of the first metal oxide semiconductor layer 1021.
  • the second metal oxide semiconductor layer 1022 can effectively protect the first metal oxide semiconductor layer 1021, and the thickness of the second metal oxide semiconductor layer 1022 is larger than the thickness of the first metal oxide semiconductor layer 1021 to protect it.
  • the lower first metal oxide semiconductor layer 1021 effectively protects the first metal oxide semiconductor layer 1021 from the effects of light, water, oxygen, etc., thereby improving the stability of the metal oxide thin film transistor and improving the performance of the metal oxide thin film transistor. life span.
  • Embodiments of the present disclosure also provide an array substrate.
  • the array substrate includes the metal oxide thin film transistor provided in any of the above embodiments. Its implementation principle and beneficial effects are the same as those of the above array substrate and metal oxide thin film transistor. The beneficial effects are the same and will not be repeated here.
  • An embodiment of the present disclosure also provides a display device, which includes a metal oxide thin film transistor as provided in any of the above embodiments or an array substrate as provided in any of the above embodiments.
  • the display device can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. Its implementation principle and beneficial effects are the same as those of the above-mentioned metal oxide thin film transistor and array. The implementation principles and beneficial effects of the substrate are the same and will not be described again here.

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Abstract

本公开提供一种金属氧化物薄膜晶体管、阵列基板及显示装置，属于显示技术领域，其可解决现有的金属氧化物薄膜晶体管稳定性较差的问题。本公开的金属氧化物薄膜晶体管包括：基底、位于基底上的金属氧化物半导体层；金属氧化物半导体层的霍尔迁移率大于或等于25cm 2/V.s；金属氧化物薄膜晶体管还包括：位于基底与金属氧化物半导体层之间的栅极及栅极绝缘层；栅极绝缘层包括：叠层设置的第一氮化硅层、第二氮化硅层和第一氧化硅层；其中，第一氧化硅层与金属氧化物半导体层接触，第二氮化硅层的两个表面分别与第一氮化硅层和第一氮化硅层接触；第二氮化硅层中至少部分区域的氢原子含量小于第一氮化硅层中至少部分区域的氢原子含量的30％。

Description

金属氧化物薄膜晶体管、阵列基板及显示装置 技术领域
本公开属于显示技术领域，具体涉及一种金属氧化物薄膜晶体管、阵列基板及显示装置。
背景技术
金属氧化物薄膜晶体管由于其更高的迁移率，在高端显示市场份额逐步提升，金属氧化物技术也被认为取代现有低温多晶硅技术最可能的实现方式。随着显示产品的升级换代，超高迁移率(迁移率大于25cm 2/V.s甚至到50cm 2/V.s)金属氧化物薄膜晶体管的开发成为各面板厂商的研发重点。
然而，随着金属氧化物薄膜晶体管中金属氧化物的载流子迁移率的提升，金属氧化物薄膜晶体管对稳定性的要求也越来越高。为了提升高迁材料金属氧化物薄膜晶体管的稳定性，不同制备工艺的使用也越来越多，对栅极绝缘层、钝化层的补氧阻氢能力提出更高的要求。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供一种金属氧化物薄膜晶体管、阵列基板及显示装置。
第一方面，本公开实施例提供了一种金属氧化物薄膜晶体管，其中，包括：基底、位于所述基底上的金属氧化物半导体层；所述金属氧化物半导体层的霍尔迁移率大于或等于25cm 2/V.s；所述金属氧化物薄膜晶体管还包括：位于所述基底与所述金属氧化物半导体层之间的栅极及栅极绝缘层；
所述栅极绝缘层包括：叠层设置的第一氮化硅层、第二氮化硅层和第一氧化硅层；其中，所述第一氧化硅层与所述金属氧化物半导体层接触，所述 第二氮化硅层的两个表面分别与所述第一氮化硅层和所述第一氮化硅层接触；
所述第二氮化硅层中至少部分区域的氢原子含量小于所述第一氮化硅层中至少部分区域的氢原子含量的30％。
可选地，所述第一氮化硅层中至少部分区域的氢原子含量为6.8×10 20cm -3至1.5×10 21cm -3；
所述第二氮化硅层中至少部分区域的氢原子含量为2.2×10 20cm -3至5.8×10 20cm -3。
可选地，所述第一氧化硅层中至少部分区域的氢原子含量小于所述第二氮化硅层中至少部分区域的氢原子含量的10％。
可选地，所述第一氧化硅层中至少部分区域的氢原子含量为2.2×10 19cm -3至5.8×10 19cm -3。
可选地，所述第二氮化硅层的厚度小于所述第一氮化硅层的厚度的40％；
所述第一氧化硅层的厚度小于所述第二氮化硅层的厚度的60％。
可选地，所述第一氮化硅层的厚度为150纳米至300纳米；
所述第二氮化硅层的厚度为50纳米至180纳米；
所述第一氧化硅层的厚度为30纳米至150纳米。
可选地，所述第一氧化硅层中至少部分区域的氧原子与硅原子的摩尔比为2.0至3.0。
可选地，所述第一氧化硅层中至少部分区域的氧原子的原子百分比为60％至70％；
所述第一氧化硅层中至少部分区域的硅原子的原子百分比为20％至30％。
可选地，所述第一氮化硅层和所述第二氮化硅层中至少部分区域的氮原 子与硅原子的摩尔比均为0.8至1.0。
可选地，所述第一氮化硅层和所述第二氮化硅层中至少部分区域的氮原子的原子百分比均为40％至50％；
所述第一氮化硅层和所述第二氮化硅层中至少部分区域的硅原子的原子百分子均为40％至50％。
可选地，所述第一氮化硅层和所述第二氮化硅层中至少部分区域的氧原子的原子百分比均为2.0％至5.0％。
可选地，金属氧化物薄膜晶体管还包括：位于所述金属氧化物半导体层上的源极和漏极、及位于所述源极和所述漏极上的第一钝化层；
所述第一钝化层包括：叠层设置的第二氧化硅层和第三氮化硅层；所述第二氧化硅层与所述金属氧化物半导体层、所述源极和所述漏极接触；所述第三氮化硅层与所述第二氧化硅层接触；
所述第三氮化硅层中至少部分区域的氢原子含量小于所述第一氮化硅层中至少部分区域的氢原子含量的30％。
可选地，金属氧化物薄膜晶体管还包括：位于所述第一钝化层上的第二钝化层；
所述第二钝化层包括：第四氮化硅层；
所述第四氮化硅层中至少部分区域的氢原子含量小于所述第一氮化硅层中至少部分区域的氢原子含量的30％。
可选地，金属氧化物薄膜晶体管还包括：位于所述第一钝化层和所述第二钝化层之间的有机绝缘层。
可选地，所述金属氧化物层包括：第一金属氧化物半导体层或叠层设置的第一金属氧化物半导体层和第二金属氧化物半导体层；
所述第二金属氧化物半导体层的霍尔迁移率为所述第一金属氧化物半导体层的霍尔迁移率的50％至60％。
可选地，所述第二金属氧化物半导体层的厚度为所述第一金属氧化物半导体层厚度的1倍至5倍。
第二方面，本公开实施例提供了一种阵列基板，其中，包括如上述提供的金属氧化物薄膜晶体管。
第三方面，本公开实施例提供了一种显示装置，其中，包括如上述提供的金属氧化物薄膜晶体管或上述提供的阵列基板。
附图说明
图1为本公开至少一个实施例提供的一种金属氧化物薄膜晶体管的结构示意图；
图2为本公开至少一个实施例提供的另一种金属氧化物薄膜晶体管的结构示意图；
图3为本公开至少一个实施例提供的又一种金属氧化物薄膜晶体管的结构示意图；
图4为本公开至少一个实施例提供的再一种金属氧化物薄膜晶体管的结构示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而 不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
金属氧化物薄膜晶体管作为一种新型的薄膜晶体管，其可以应用于液晶显示面板(Liquid Crystal Display，LCD)，有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，迷你发光二极管(Mini Light-Emitting Diode)背光源或显示面板，量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示面板等技术中。
目前的金属氧化物薄膜晶体管的较高迁移率主要由其中的金属氧化物半导体层的材料特性决定的，以金属氧化物薄膜晶体管中的金属氧化物为铟镓锌氧化物IGZO为例，其中的氧(O)元素与金属元素铟(In)、镓(Ga)锌(Zn)可以形成化合物，并根据化学键成键情况提供或陷落载流子(氧空位)。其中，铟(In)可以提供电子传输路径，使得IGZO具有较高的迁移率。镓(Ga)具有高离化能，可以抑制电子迁移率，抑制氧空位的形成以及产生新的移动电子。锌(Zn)可以作为稳定剂，具有可以结合氧离子的强化学键，可以构成稳定的四面体结构，以形成较为稳定的非晶晶界。由金属氧化物半导体层中的IGZO中的各个元素的特性可以看出，IGZO构成的金属氧化物薄膜晶体管可以具有较高的迁移率。
在金属氧化物薄膜晶体管中，除了金属氧化物半导体层，还一般设置有栅极、栅极绝缘层、源极、漏极、钝化层等膜层结构，为了提升高迁材料金属氧化物薄膜晶体管的稳定性，其中的栅极绝缘层和钝化层等膜层需要具有较强的补氧阻氢能力，以避免氢原子对金属氧化物层造成损坏，然而，目前的金属氧化物薄膜晶体管中的栅极绝缘层、钝化层的补氧阻氢能力较低，容易影响金属氧化物薄膜晶体管的稳定性，降低金属氧化物薄膜晶体管的寿 命。
为了至少解决上述的技术问题之一，本公开实施例提供了一种金属氧化物薄膜晶体管、阵列基板及显示装置，下面将结合附图和具体实施方式对比公开提供的金属氧化物薄膜晶体管、阵列基板及显示装置进行进一步详细描述。
图1为本公开至少一个实施例提供的一种金属氧化物薄膜晶体管的结构示意图，如图1所示，该薄膜晶体管包括：基底101、位于基底101上的金属氧化物半导体层102；金属氧化物半导体层102的霍尔迁移率大于或等于25cm 2/V.s；金属氧化物薄膜晶体管还包括：位于基底101与金属氧化物半导体层之间的栅极103及栅极绝缘层104；栅极绝缘层104包括：叠层设置的第一氮化硅层1041、第二氮化硅层1042和第一氧化硅层1043；其中，第一氧化硅层1041与金属氧化物半导体层102接触，第二氮化硅层1042的两个表面分别与第一氮化硅层1041和第一氮化硅层1043接触；第二氮化硅层1042中至少部分区域的氢原子含量小于第一氮化硅层1041中至少部分区域的氢原子含量的30％。
基底101可以采用玻璃等刚性材料制成，可以提高基底101对其上的其他膜层的承载能力。当然，基底101还可以采用聚酰亚胺(polyimide，PI)等柔性材料制成，可以提高金属氧化物薄膜晶体管整体的抗弯折、抗拉伸性能，避免在弯折、拉伸、扭曲过程中产生的应力使得基底101发生断裂，造成断路不良。在实际应用中，可以根据实际需要，合理选择基底101的材料，以保证金属氧化物薄膜晶体管具有良好的性能。
半导体金属氧化物层102可以采用铟镓锌氧化物(IGZO)，铟镓锡氧化物(IGTO)，铟锌氧化物(IZO)，铟锡氧化物(ITO)以及铟锡锌氧化物(ITZO)中的至少一种材料制成，其均为具有较高迁移率的金属氧化物，以保证金属氧化物薄膜晶体管整体具有较高的迁移率。在本公开实施例中，将以半导体 金属氧化物层102的材料为IGZO为例进行说明，其霍尔迁移率大于或等于25cm 2/V.s。
栅极103可以采用金(Au)、银(Ag)、铜(Cu)、镍(Ni)、铂(Pt)、钯(Pd)、铝(Al)、钼(Mo)以及铬(Cr)中的至少一种材料制成，其可以形成由单一材料制成的单层结构，例如，栅极103为铝(Al)构成的单层结构，当然，其也可以形成有多重不同材料制成的多层结构，例如，钼(Mo)、铝(Al)、钼(Mo)构成的三层结构。栅极103可以在输入控制信号时，使得金属氧化物半导体层102导体化，以输入数据信号、复位信号、初始化信号等。可以理解的是，在基底101与栅极103之间还可以设置有缓冲层、阻挡层等其他膜层，其可以防止水氧等有基底101一侧侵入至金属氧化物半导体层103中，可以采用相关技术中的工艺及材料制成，在此不在赘述。
栅极绝缘层104可以为多层结构，例如由第一氮化硅层1041、第二氮化硅层1042和第一氧化硅层1043构成的三层结构，第一氧化硅层1043可以与金属氧化物半导体层102直接接触，第一氮化硅层1041和第二氮化硅层1042直接接触，并且第二氮化硅层1042与第一氧化硅层1043直接接触。
第一氧化硅层1043可以直接对金属氧化物半导体层102进行保护，然而由于第一氧化硅层1043的材料特性，其质地较脆，一般需要配合氮化硅层使用，以增加栅极绝缘层104整体的柔性，避免在应用过程中栅极绝缘层104发生断裂使得金属氧化物半导体层102与栅极103之间发生短路，影响金属氧化物薄膜晶体管的性能。
由于栅极绝缘层104中各个膜层的材料及制备工艺的限制，其中的各个膜层中均或多或少的残留有氢原子，第一氮化硅层1041可以利用反应气体，采用化学气相沉积的方式形成，其可以增加栅极绝缘层104整体的柔性，然而在制备过程中，第一氮化硅层1041中容易残留有大量的氢原子。
为了避免第一氮化硅层1041中的氢原子侵入金属氧化物半导体层102 并对金属氧化物半导体层102造成损坏，第一氮化硅层1041与第一氧化硅层1043之间还设置有第二氮化硅层1042，第二氮化硅层1042可以利用基本不含有氢原子的反应气体，采用化学气象沉积的方式形成。其中，第二氮化硅层1042中至少部分区域的氢原子含量小于第一氮化硅层1041中至少部分区域的氢原子含量的30％。在实际应用中，具体可以利用三硅胺和氮气等基本不含有氢原子的反应气体，来制备第二氮化硅层1042，以避免第二氮化硅层1042中残留有较高含量的氢原子，从而避免氢原子对金属氧化物半导体层102的损坏，进而可以提高整体金属氧化物薄膜晶体管的稳定性，同时可以提高整体金属氧化物薄膜晶体管的寿命。
同时，三层结构的栅极绝缘层104可以采用同一掩膜板制成，在制备过程中不会增加掩膜及刻蚀工艺，不会增加工艺步骤，从而不增加制备成本。可以理解的是，栅极绝缘层104还可以采用四层、五层等其他数量的结构来形成，其实现原理与上述类似，在此不再赘述。
在一些实施例中，第一氮化硅层1041中至少部分区域的氢原子含量为6.8×10 20cm -3至1.5×10 21cm -3；第二氮化硅层1042中至少部分区域的氢原子含量为2.2×10 20cm -3至5.8×10 20cm -3。
第二氮化硅层1042中至少部分区域的氢原子含量要远远小于第一氮化硅层1041中至少部分区域的氢原子含量，其中，第二氮化硅层1042中至少部分区域的氢原子含量一般为10 20数量级，第一氮化硅层1041中至少部分区域的氢原子含量一般为10 21数量级，可见，第二氮化硅层1042中至少部分区域的氢原子含量较少，从而避免第一氮化硅层1041中大量的氢原子传导至金属氧化物半导体层102中对其造成损坏，进而可以提高整体金属氧化物薄膜晶体管的稳定性，同时可以提高整体金属氧化物薄膜晶体管的寿命。
在一些实施例中，第一氧化硅层1043中至少部分区域的氢原子含量小于第二氮化硅层1042中至少部分区域的氢原子含量的10％。
在实际应用中，可以利用甲硅烷和一氧化二氮，采用化学气象沉积的方式形成第一氧化硅层1043，上述的反应气体甲硅烷和一氧化二氮中不含有氢原子，在制备过程中，也基本不会引入氢离子，所形成的的第一氧化硅层1043中至少部分区域的氢原子含量小于第二氮化硅层1042中至少部分区域的氢原子含量，由上述可知，第二氮化硅层1042中至少部分区域的氢原子含量本身就较少，因此所形成的第一氧化硅层1043中至少部分区域的氢原子含量更少乃至几乎为零，从而可以进一步避免第一氮化硅层1041中大量的氢原子传导至金属氧化物半导体层102中对其造成损坏，进而可以提高整体金属氧化物薄膜晶体管的稳定性，同时可以提高整体金属氧化物薄膜晶体管的寿命。具体地，第一氧化硅层1043中至少部分区域的氢原子含量可以为2.2×10 19cm -3至5.8×10 19cm -3。可以理解的是，可以采用其他的反应气体，利用新的工艺，使得第一氧化硅层1043中至少部分区域的氢原子含量更低，甚至为0，以对金属氧化物半导体层102进行保护，避免氢原子对金属氧化物半导体层102造成损坏，从而可以提高整体金属氧化物薄膜晶体管的稳定性，同时可以提高整体金属氧化物薄膜晶体管的寿命。
在一些实施例中，第二氮化硅层1042的厚度小于第一氮化硅层1041的厚度的40％；第一氧化硅层1043的厚度小于第二氮化硅层1042的厚度的60％。
金属氧化物薄膜晶体管中的第一氮化硅层1041的厚度较厚，其可以缓解整个栅极绝缘层104的柔性，避免栅极绝缘层104断裂，造成金属氧化物层102与栅极103之间发生短路，影响金属氧化物薄膜晶体管的性能。第二氮化硅层1042的厚度较第一氮化硅层1041的厚度较小，第二氮化硅层1042中的氢原子含量较低，其可以避免第一氮化硅层1041中大量的氢原子传导至金属氧化物半导体层102中对其造成损坏，进而可以提高整体金属氧化物薄膜晶体管的稳定性，同时可以提高整体金属氧化物薄膜晶体管的寿命。第 一氧化硅层1043的厚度较第二氮化硅层1042的厚度较小，其与金属氧化物半导体层102直接接触，可以对金属氧化物半导体层102进行保护，避免氢原子对金属氧化物半导体层102造成损坏，同时可以避免整体栅极绝缘层104的厚度过大，影响金属氧化物薄膜晶体管的性能。具体地，第一氮化硅层1041的厚度为150纳米至300纳米；第二氮化硅层1042的厚度为50纳米至180纳米；第一氧化硅层1043的厚度为30纳米至150纳米。优选地，本公开实施例提供的金属氧化物薄膜晶体管中，第一氮化硅层1041的厚度可以为218.4纳米，第二氮化硅层1042的厚度可以为88.45纳米，第一氧化硅层1043的厚度可以为52.88纳米。可以理解的是，栅极绝缘层104中的各个膜层的厚度还可以根据实际需要进行设置，在此不再一一列举。
在此需要说明的是，金属氧化物半导体层102的厚度为2纳米至70纳米。若金属氧化物半导体层102的厚度过小，其霍尔迁移率不能满足高迁移率的需要，若金属氧化物半导体层102的厚度过大，其容易导体化，影响金属氧化物薄膜晶体管的性能。优选地，本公开实施例提供的金属氧化物薄膜晶体管中的金属氧化物半导体层102的厚度可以为10纳米。可以理解的是，还可以根据金属氧化物半导体层102材料的不同，合理设置其厚度，在此不再一一列举。
在一些实施例中，第一氧化硅层1043中至少部分区域的氧原子与硅原子的摩尔比为2.0至3.0。
第一氧化硅层1043中至少部分区域的氧原子的含量较大，其中的氧原子可以传导至金属氧化物半导体层102中，以对金属氧化物半导体层102进行补氧，避免在制备及应用过程中金属氧化物半导体层102氧原子缺失而导体化，影响金属氧化物薄膜晶体管的性能，从而可以提高金属氧化物薄膜晶体管的性能，提高整体金属氧化物薄膜晶体管的寿命。具体地，第一氧化硅层1043中至少部分区域的氧原子的原子百分比为60％至70％；第一氧化硅 层中至少部分区域的硅原子的原子百分比为20％至30％。优选地，第一氧化硅层1043中至少部分区域的氧原子与硅原子的摩尔比可以为2.18，例如，第一氧化硅层1043中的氧原子的百分比为67.23％，硅原子的百分比为30.74％，以保证较强的补氧能力。
在一些实施例中，第一氮化硅层1041和第二氮化硅层1042中至少部分区域的氮原子与硅原子的摩尔比均为0.8至1.0。
第一氮化硅层1041和第二氮化硅层1042中至少部分区域的氮原子和硅原子的含量比较接近，具体地，第一氮化硅层1041和第二氮化硅层1042中至少部分区域的氮原子的原子百分比均为40％至50％；第一氮化硅层1041和第二氮化硅层1042中至少部分区域的硅原子的原子百分子均为40％至50％。优选地，第一氮化硅层1041和第二氮化硅层1042中的氮原子含量可以为48.35％，硅原子的含量可以为47.2％，以保证第一氮化硅层1041和第二氮化硅层1042具有良好的绝缘性能及良好的柔性。
在一些实施例中，第一氮化硅层1041和第二氮化硅层1042中至少部分区域的氧原子的原子百分比均为2.0％至5.0％。
第一氮化硅层1041和第二氮化硅层1042中含有少量的氧原子，具体地，第一氮化硅层1041和第二氮化硅层1042中的氧原子的含量可以为4.45％，其可以在一定程度上为金属氧化物半导体层102进行补氧，以保证金属氧化物薄膜晶体管的性能稳定。
在一些实施例中，金属氧化物薄膜晶体管还包括：位于金属氧化物半导体层102上的源极105和漏极106、及位于源极105和漏极106上的第一钝化层107；第一钝化层107包括：叠层设置的第二氧化硅层1071和第三氮化硅层1072；第二氧化硅层1071与金属氧化物半导体层102、源极105和漏极106接触；第三氮化硅层1072与第二氧化硅层1071接触；第三氮化硅层1072中至少部分区域的氢原子含量小于第一氮化硅层1041中至少部分区域 的氢原子含量的30％。
金属氧化物薄膜晶体管的源极105和漏极106可以在金属氧化物半导体层102上，源极105和漏极106可以与金属氧化物半导体层102的部分区域相连接，在栅极103输入控制信号时，源极105和漏极106可以通过金属氧化物半导体层102导通，实现金属氧化物薄膜晶体管的控制功能。第一钝化层107可以覆盖金属氧化物半导体层102、源极105和漏极106，其中，第一钝化层107中的第二氧化硅层1071可以与金属氧化物半导体层102直接接触，第三氮化硅层1072与第二氧化硅层1071接触，第二氧化硅层1071可以对金属氧化物层102进行保护。同时第三氮化硅层1072中氢原子含量较低，可以避免氢原子传导至金属氧化物半导体层102中对其造成损坏，进而可以提高整体金属氧化物薄膜晶体管的稳定性，同时可以提高整体金属氧化物薄膜晶体管的寿命。在此需要说明的是，第一钝化层107中的第三氮化硅层1072的材料、厚度等参数可以与栅极绝缘层104中的第二氮化硅层1042的材料、厚度等参数相同，以降低工艺难度，节约制备成本。
在一些实施例中，图2为本公开至少一个实施例提供的另一种金属氧化物薄膜晶体管的结构示意图，如图2所示，金属氧化物薄膜晶体管还包括：位于第一钝化层107上的第二钝化层108；第二钝化层108包括：第四氮化硅层1081；第四氮化硅层1081中至少部分区域的氢原子含量小于第一氮化硅层1041中至少部分区域的氢原子含量的30％。
在本公开实施例中，金属氧化物薄膜晶体管中可以包括双层钝化层，即第一钝化层107和第二钝化层108，第二钝化层108中的第四氮化硅层1081中氢原子含量较低，可以避免氢原子传导至金属氧化物半导体层102中对其造成损坏，进而可以提高整体金属氧化物薄膜晶体管的稳定性，同时可以提高整体金属氧化物薄膜晶体管的寿命。在此需要说明的是，第二钝化层108中的第四氮化硅层1081的材料、厚度等参数可以与栅极绝缘层104中的第 二氮化硅层1042的材料、厚度等参数相同，以降低工艺难度，节约制备成本。
在一些实施例中，如图2所示，金属氧化物薄膜晶体管还包括：位于第一钝化层107和第二钝化层108之间的有机绝缘层109。
有机绝缘层109具有较强的柔性，其可以提高第一钝化层107和第二钝化层108中各个膜层的柔性，避免在应用过程中第一钝化层107和第二钝化层108中各个膜层发生断裂，从而可以提高金属氧化物薄膜晶体管的性能。
在一些实施例中，图3为本公开至少一个实施例提供的又一种金属氧化物薄膜晶体管的结构示意图，图4为本公开至少一个实施例提供的再一种金属氧化物薄膜晶体管的结构示意图，如图3和图4所示，金属氧化物层102包括：第一金属氧化物半导体层1021(图1和图2中示出的金属氧化物薄膜晶体管中的金属氧化物半导体层102为单层设置，仅包括一层第一金属氧化物半导体层1021)或叠层设置的第一金属氧化物半导体层1021和第二金属氧化物半导体层1022；第二金属氧化物半导体层1022的霍尔迁移率为第一金属氧化物半导体层1021的霍尔迁移率的50％至60％。
金属氧化物薄膜晶体管中的金属氧化物半导体层102可以为单层结构也可以为双层结构，其中，第一金属氧化物半导体层1021的霍尔迁移率大于或等于25cm 2/V.s，以保证整体金属氧化物半导体层102具有较大的霍尔迁移率，第二金属氧化物半导体层1022的霍尔迁移率较第一金属氧化物半导体层1021较小，在不影响整体金属氧化物半导体层102具有良好的霍尔迁移率的同时，第二金属氧化物半导体层1022可以对第一金属氧化物半导体层1021进行保护，避免光照、水氧等对第一金属氧化物半导体层1021的影响，从而可以提高金属氧化物薄膜晶体管的稳定性，提高金属氧化物薄膜晶体管的寿命。
在一些实施例中，第二金属氧化物半导体层1022的厚度为第一金属氧 化物半导体层1021厚度的1倍至5倍。
第二金属氧化物半导体层1022可以对第一金属氧化物半导体层1021进行有效保护，并且第二金属氧化物半导体层1022的厚度较第一金属氧化物半导体层1021的厚度较大，以对其下层的第一金属氧化物半导体层1021进行有效保护，避免光照、水氧等对第一金属氧化物半导体层1021的影响，从而可以提高金属氧化物薄膜晶体管的稳定性，提高金属氧化物薄膜晶体管的寿命。
本公开实施例还提供了一种阵列基板，该阵列基板包括如上述任一实施例提供的金属氧化物薄膜晶体管，其实现原理及有益效果与上述的阵列基板及金属氧化物薄膜晶体管的实现原理及有益效果相同，在此不再进行赘述。
本公开实施例还提供了一种显示装置，该显示装置包括如上述任一实施例提供的金属氧化物薄膜晶体管或如上述任一实施例提供的阵列基板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，其实现原理及有益效果与上述的金属氧化物薄膜晶体管及阵列基板的实现原理及有益效果相同，在此不再进行赘述。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (18)

  1. 一种金属氧化物薄膜晶体管，其中，包括：基底、位于所述基底上的金属氧化物半导体层；所述金属氧化物半导体层的霍尔迁移率大于或等于25cm 2/V.s；所述金属氧化物薄膜晶体管还包括：位于所述基底与所述金属氧化物半导体层之间的栅极及栅极绝缘层；
    所述栅极绝缘层包括：叠层设置的第一氮化硅层、第二氮化硅层和第一氧化硅层；其中，所述第一氧化硅层与所述金属氧化物半导体层接触，所述第二氮化硅层的两个表面分别与所述第一氮化硅层和所述第一氮化硅层接触；
    所述第二氮化硅层中至少部分区域的氢原子含量小于所述第一氮化硅层中至少部分区域的氢原子含量的30％。
  2. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述第一氮化硅层中至少部分区域的氢原子含量为6.8×10 20cm -3至1.5×10 21cm -3；
    所述第二氮化硅层中至少部分区域的氢原子含量为2.2×10 20cm -3至5.8×10 20cm -3。
  3. 根据权利要求2所述的金属氧化物薄膜晶体管，其中，所述第一氧化硅层中至少部分区域的氢原子含量小于所述第二氮化硅层中至少部分区域的氢原子含量的10％。
  4. 根据权利要求3所述的金属氧化物薄膜晶体管，其中，所述第一氧化硅层中至少部分区域的氢原子含量为2.2×10 19cm -3至5.8×10 19cm -3。
  5. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述第二氮化硅层的厚度小于所述第一氮化硅层的厚度的40％；
    所述第一氧化硅层的厚度小于所述第二氮化硅层的厚度的60％。
  6. 根据权利要求5所述的金属氧化物薄膜晶体管，其中，所述第一氮化硅层的厚度为150纳米至300纳米；
    所述第二氮化硅层的厚度为50纳米至180纳米；
    所述第一氧化硅层的厚度为30纳米至150纳米。
  7. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述第一氧化硅层中至少部分区域的氧原子与硅原子的摩尔比为2.0至3.0。
  8. 根据权利要求7所述的金属氧化物薄膜晶体管，其中，所述第一氧化硅层中至少部分区域的氧原子的原子百分比为60％至70％；
    所述第一氧化硅层中至少部分区域的硅原子的原子百分比为20％至30％。
  9. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述第一氮化硅层和所述第二氮化硅层中至少部分区域的氮原子与硅原子的摩尔比均为0.8至1.0。
  10. 根据权利要求9所述的金属氧化物薄膜晶体管，其中，所述第一氮化硅层和所述第二氮化硅层中至少部分区域的氮原子的原子百分比均为40％至50％；
    所述第一氮化硅层和所述第二氮化硅层中至少部分区域的硅原子的原子百分子均为40％至50％。
  11. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述第一氮化硅层和所述第二氮化硅层中至少部分区域的氧原子的原子百分比均为2.0％至5.0％。
  12. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，还包括：位于所述金属氧化物半导体层上的源极和漏极、及位于所述源极和所述漏极上的第一钝化层；
    所述第一钝化层包括：叠层设置的第二氧化硅层和第三氮化硅层；所述第二氧化硅层与所述金属氧化物半导体层、所述源极和所述漏极接触；所述第三氮化硅层与所述第二氧化硅层接触；
    所述第三氮化硅层中至少部分区域的氢原子含量小于所述第一氮化硅层中至少部分区域的氢原子含量的30％。
  13. 根据权利要求12所述的金属氧化物薄膜晶体管，其中，还包括：位于所述第一钝化层上的第二钝化层；
    所述第二钝化层包括：第四氮化硅层；
    所述第四氮化硅层中至少部分区域的氢原子含量小于所述第一氮化硅层中至少部分区域的氢原子含量的30％。
  14. 根据权利要求13所述的金属氧化物薄膜晶体管，其中，还包括：位于所述第一钝化层和所述第二钝化层之间的有机绝缘层。
  15. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述金属氧化物层包括：第一金属氧化物半导体层或叠层设置的第一金属氧化物半导体层和第二金属氧化物半导体层；
    所述第二金属氧化物半导体层的霍尔迁移率为所述第一金属氧化物半导体层的霍尔迁移率的50％至60％。
  16. 根据权利要求15所述的金属氧化物薄膜晶体管，其中，所述第二金属氧化物半导体层的厚度为所述第一金属氧化物半导体层厚度的1倍至5倍。
  17. 一种阵列基板，其中，包括如权利要求1至16任一项所述的金属氧化物薄膜晶体管。
  18. 一种显示装置，其中，包括如权利要求1至16任一项所述的金属氧化物薄膜晶体管或如权利要求17所述的阵列基板。
PCT/CN2022/084064 2022-03-30 2022-03-30 金属氧化物薄膜晶体管、阵列基板及显示装置 WO2023184236A1 (zh)

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