WO2023151632A1 - 一种adc电路及其控制方法 - Google Patents

一种adc电路及其控制方法 Download PDF

Info

Publication number
WO2023151632A1
WO2023151632A1 PCT/CN2023/075318 CN2023075318W WO2023151632A1 WO 2023151632 A1 WO2023151632 A1 WO 2023151632A1 CN 2023075318 W CN2023075318 W CN 2023075318W WO 2023151632 A1 WO2023151632 A1 WO 2023151632A1
Authority
WO
WIPO (PCT)
Prior art keywords
module
calibration
digital
signal
analog
Prior art date
Application number
PCT/CN2023/075318
Other languages
English (en)
French (fr)
Inventor
刘维辉
陈敏
Original Assignee
芯海科技（深圳）股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 芯海科技（深圳）股份有限公司 filed Critical 芯海科技（深圳）股份有限公司
Publication of WO2023151632A1 publication Critical patent/WO2023151632A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters

Definitions

  • the present application relates to the field of electronic technology, in particular to an ADC circuit and a control method thereof.
  • an analog-to-digital converter (Analog-to-Digital Converter, ADC) circuit can be used for signal measurement to convert an analog signal into a digital signal.
  • ADC Analog-to-Digital Converter
  • the existing ADC cannot continuously operate two working modes. For example, the ADC needs to be reconfigured after the differential signal is processed, and then the single-ended signal is processed. There will be redundant mode switching time in the middle, which cannot be continuously run. And when the requirement for the accuracy of the ADC is relatively high, the ADC needs to be calibrated, and the traditional method cannot satisfy the continuous calibration of the ADC differential mode and single-ended mode.
  • an embodiment of the present application provides an ADC circuit and a control method thereof.
  • the technical solution is as follows:
  • an ADC circuit at least includes: an analog-to-digital conversion module and a calibration module;
  • the analog-to-digital conversion module is configured to output a corresponding first digital signal based on the sampled first signal when the first control signal is at a first level during conversion, and when the first control signal is at a second level Usually, outputting a corresponding second digital signal based on the sampled second signal;
  • the calibration module is connected to the analog-to-digital conversion module, and is configured to determine a calibration code based on the mismatch code obtained during calibration, and perform calibration code compensation on the analog-to-digital conversion module;
  • the level switching of the first control signal is performed during the sampling period.
  • the calibration module includes a calibration digital-to-analog conversion module, a calibration algorithm module, and a calibration control module;
  • the input end of the calibration algorithm module is connected to the analog-to-digital conversion module, and the output end is connected to the calibration control module, which is configured to, when the first control signal is at the first level, based on the mismatch determining a first calibration code corresponding to the first signal; when the first control signal is at the second level, determining a second calibration code corresponding to the second signal based on the mismatch code;
  • the calibration control module is configured to transmit the calibration code currently output by the calibration algorithm module to the calibration digital-to-analog conversion module during the conversion period;
  • the calibration digital-to-analog conversion module is configured to perform voltage compensation on the digital-to-analog conversion module based on the currently received calibration code during the conversion.
  • the calibration algorithm module is further configured to store the mismatch code.
  • the calibration control module is further configured to set the calibration code as a preset intermediate calibration code during the sampling period, and transmit the intermediate calibration code to the calibration digital-to-analog conversion module.
  • the ADC circuit further includes an input preprocessing module, an output terminal of the input preprocessing module is connected to an input terminal of the analog-to-digital conversion module;
  • the input preprocessing module is used to receive an input signal, and is configured to output the first signal based on the input signal when the second control signal is a third level matching the first level; when the When the second control signal is a fourth level matching the second level, outputting the second signal based on the input signal;
  • the level switching of the second control signal is performed during the conversion period.
  • the input preprocessing module includes at least a first switch
  • the first switch is configured to switch the signal output by the input preprocessing module based on the second control signal.
  • one terminal of the first switch is used to connect the negative terminal input voltage to the negative terminal of the input preprocessing module, and the other terminal is connected to the negative terminal of the input preprocessing module.
  • Analog-to-digital conversion module connection
  • one end of the first switch is used to connect the first preset voltage to the negative end of the input pre-processing module, and the other end is connected to the analog-to-digital conversion module connection.
  • the analog-to-digital conversion module includes a digital-to-analog conversion module, a comparison module and a logic module, and the digital-to-analog conversion module is used for sample hold and quantization;
  • the digital-to-analog conversion module is connected to the input preprocessing module, and is configured to perform a first operation corresponding to the first signal when the first control signal is at the first level during the conversion period mode; when the first control signal is at the second level, execute a second working mode corresponding to the second signal;
  • the input end of the comparison module is connected to the digital-to-analog conversion module, and the output end is connected to the logic module;
  • the logic module is configured to output a digital signal corresponding to the input signal.
  • the digital-to-analog conversion module includes a positive-end digital-to-analog conversion module and a negative-end digital-to-analog conversion module, the positive-end digital-to-analog conversion module is adapted to the second switch, and the negative-end digital-to-analog conversion module is matched to the third switch. adaptation;
  • the second switch and the third switch are adapted to the first working mode
  • the second switch When the first control signal is at the second level, the second switch is adapted to the second working mode, and the third switch is used to connect the second preset voltage to the negative terminal digital-to-analog conversion module.
  • the difference between the second preset voltage and the first preset voltage connected to the input pre-processing module is not greater than a difference threshold.
  • the logic module is further configured to quantize the error voltage of the digital-to-analog conversion module during calibration to obtain a mismatch code.
  • a method for controlling an ADC circuit is provided, the ADC circuit at least includes: an analog-to-digital conversion module and a calibration module, and the method includes:
  • the first control signal when the first control signal is at the first level, the first signal based on sampling outputs a corresponding first digital signal, and when the first control signal is at a second level, the second signal based on sampling outputs a corresponding the second digital signal;
  • a calibration code is determined based on the mismatch code obtained during the calibration period, and the calibration code is compensated for the analog-to-digital conversion module;
  • the level switching of the first control signal is performed during the sampling period.
  • the calibration module includes a calibration digital-to-analog conversion module, a calibration algorithm module, and a calibration control module;
  • the said calibration module is used to determine the calibration code based on the mismatch code obtained during calibration, and to perform calibration code compensation on the analog-to-digital conversion module, including:
  • the first control signal When the first control signal is at the first level, determine a first calibration code corresponding to the first signal based on the mismatch code through the calibration algorithm module; when the first control signal is at the first level When the second level is used, the second calibration code corresponding to the second signal is determined based on the mismatch code through the calibration algorithm module;
  • the method also includes:
  • the mismatch code is stored based on the calibration algorithm module.
  • the method also includes:
  • the voltage of the calibration digital-to-analog conversion module is set to a preset intermediate calibration code.
  • the ADC circuit also includes an input preprocessing module, and the method also includes:
  • the first signal is obtained based on the input signal through the input preprocessing module;
  • the second control signal is a fourth level matching the second level
  • the second signal is obtained based on the input signal through the input preprocessing module
  • the level switching of the second control signal is performed during the conversion period.
  • the input preprocessing module includes at least a first switch
  • the method further includes: controlling the first switch based on the second control signal to switch the signal output by the input pre-processing module.
  • controlling the first switch based on the second control signal to switch the signal output by the input preprocessing module includes:
  • control the first switch When the second control signal is at the third level, control the first switch to connect the negative terminal input voltage from the negative terminal of the input preprocessing module to the analog-to-digital conversion module; connect the positive terminal input voltage Accessing the analog-to-digital conversion module from the positive end of the input preprocessing module;
  • control the first switch When the second control signal is at the fourth level, control the first switch to connect the first preset voltage from the negative terminal of the input preprocessing module to the analog-to-digital conversion module; The voltage is connected to the analog-to-digital conversion module from the positive terminal of the input preprocessing module.
  • the analog-to-digital conversion module includes a digital-to-analog conversion module, a comparison module and a logic module, and the digital-to-analog conversion module is used for sample hold and quantization;
  • the outputting the corresponding first digital signal based on the sampling first signal includes: controlling the digital-to-analog conversion module to execute the first working mode corresponding to the first signal; based on the logic module, outputting the first signal a corresponding first digital signal;
  • the outputting the corresponding second digital signal based on the sampling second signal includes: controlling the digital-to-analog conversion module to execute the second working mode corresponding to the second signal; based on the logic module, outputting the second signal corresponding to the second digital signal.
  • the digital-to-analog conversion module includes a positive-end digital-to-analog conversion module and a negative-end digital-to-analog conversion module, the positive-end digital-to-analog conversion module is adapted to the second switch, and the negative-end digital-to-analog conversion module is matched to the third switch. adaptation;
  • the method also includes:
  • control the second switch When the first control signal is at the second level, control the second switch to adapt to the second working mode, and control the third switch to connect the second preset voltage to the negative terminal digital-to-analog conversion module.
  • the difference between the second preset voltage and the first preset voltage connected to the input pre-processing module is not greater than a difference threshold.
  • the method also includes:
  • the logic module is multiplexed to quantify the error voltage of the digital-to-analog conversion module to obtain a mismatch code.
  • a chip including the above-mentioned ADC circuit.
  • an electronic device including:
  • the program includes instructions, and the instructions, when executed by the processor, cause the processor to execute the above-mentioned method for controlling the ADC circuit.
  • a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to make a computer execute the above-mentioned ADC circuit control method.
  • the ADC circuit can realize continuous calibration for two different working modes, and the ADC circuit does not need to be restarted to configure different working modes.
  • FIG. 1 shows a schematic structural diagram of an ADC circuit provided according to an exemplary embodiment of the present application
  • FIG. 2 shows a schematic structural diagram of an ADC circuit provided according to an exemplary embodiment of the present application
  • FIG. 3 shows a schematic diagram of timing control provided according to an exemplary embodiment of the present application
  • FIG. 4 shows a schematic structural diagram of a SAR ADC circuit provided according to an exemplary embodiment of the present application
  • FIG. 5 shows a schematic structural diagram of an ADC circuit provided according to an exemplary embodiment of the present application
  • FIG. 6 shows a schematic diagram of timing control provided according to an exemplary embodiment of the present application.
  • FIG. 7 shows a schematic diagram of an input preprocessing module provided according to an exemplary embodiment of the present application.
  • FIG. 8 shows a schematic structural diagram of an ADC circuit provided according to an exemplary embodiment of the present application.
  • FIG. 9 shows a schematic structural diagram of a SAR ADC circuit provided according to an exemplary embodiment of the present application.
  • FIG. 10 shows a flowchart of a control method of an ADC circuit provided according to an exemplary embodiment of the present application
  • FIG. 11 shows a flowchart of a calibration control method for an ADC circuit provided according to an exemplary embodiment of the present application
  • FIG. 12 shows a flowchart of a control method of an ADC circuit provided according to an exemplary embodiment of the present application
  • FIG. 13 shows a schematic diagram of a switch state during sampling according to an exemplary embodiment of the present application
  • Fig. 14 shows a schematic diagram of switch states during sampling according to an exemplary embodiment of the present application
  • Fig. 15 shows a schematic diagram of switch states during conversion provided according to an exemplary embodiment of the present application
  • Fig. 16 shows a schematic diagram of switch states during conversion according to an exemplary embodiment of the present application
  • FIG. 17 shows a structural block diagram of an exemplary electronic device that can be used to implement the embodiments of the present application.
  • the term “comprise” and its variations are open-ended, ie “including but not limited to”.
  • the term “based on” is “based at least in part on”.
  • the term “one embodiment” means “at least one embodiment”; the term “another embodiment” means “at least one further embodiment”; the term “some embodiments” means “at least some embodiments.”
  • Relevant definitions of other terms will be given in the description below. It should be noted that concepts such as “first” and “second” mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the sequence of functions performed by these devices, modules or units or interdependence.
  • An embodiment of the present application provides an ADC circuit.
  • the ADC circuit at least includes: an analog-to-digital conversion module and a calibration module.
  • the analog-to-digital conversion module is configured to output a corresponding first digital signal based on the sampled first signal when the first control signal is at the first level during conversion, and to output a corresponding first digital signal based on the sampled first signal when the first control signal is at the second level.
  • the second signal output corresponds to the second digital signal;
  • the calibration module is connected to the analog-to-digital conversion module and is configured to determine a calibration code based on a mismatch code obtained during calibration, for The analog-to-digital conversion module performs calibration code compensation;
  • the level of the first control signal is switched during the sampling period.
  • the input signal of the above-mentioned first signal may be a differential signal, and the first signal may be a corresponding differential signal;
  • the input signal of the above-mentioned second signal may be a single-ended signal, and the second signal may be a corresponding pseudo-differential signal.
  • the calibration module may include a calibration digital-to-analog conversion module, a calibration algorithm module, and a calibration control module.
  • the ADC circuit can be controlled by the sequence shown in Figure 3, where sar_clk refers to the clock control signal, sar_sample refers to the sampling control signal, DIFF_EN1 refers to the first control signal, and CALCODE_I ⁇ M:1> refers to the calibration algorithm module
  • the output calibration code, CALCODE_P/N ⁇ M:1> refers to the calibration code output by the calibration control module, and the M digits are determined by the digits of the calibration digital-to-analog conversion module.
  • the input terminal of the calibration algorithm module is connected to the analog-to-digital conversion module, and the output terminal is connected to the calibration control module, configured to determine the first calibration code corresponding to the first signal based on the mismatch code when the first control signal is at the first level; When the first control signal is at the second level, determining a second calibration code corresponding to the second signal based on the mismatch code;
  • the calibration control module is configured to transmit the calibration code currently output by the calibration algorithm module to the calibration digital-to-analog conversion module during the conversion period;
  • the calibration digital-to-analog conversion module is configured to perform voltage compensation on the digital-to-analog conversion module based on the currently received calibration code during conversion.
  • the ADC circuit is a SAR ADC circuit
  • the corresponding circuit after adding the calibration module is shown in FIG. 4 .
  • the input end of the calibration algorithm module is connected with the successive approximation search logic module.
  • the calibration digital-to-analog conversion module may be a calibration differential capacitor array (labeled as CALDACP/CALDACN in FIG. 4 ), connected to the input of the pair comparator, and may be configured to, during conversion, based on the currently received calibration code pair the input of the comparator. The voltage is compensated.
  • the calibration digital-to-analog conversion module may also use other circuit structures, such as a capacitor-resistor array. This embodiment does not limit the specific circuit structure of the calibration digital-to-analog conversion module.
  • the calibration algorithm module is further configured to store mismatch codes.
  • the calibration control module is further configured to set the calibration code as a preset intermediate calibration code during the sampling period, and transmit the intermediate calibration code to the calibration digital-to-analog conversion module.
  • the ADC circuit further includes an input preprocessing module, and the output terminal of the input preprocessing module is connected to the input terminal of the analog-to-digital conversion module.
  • the ADC circuit can be controlled by the sequence shown in FIG. 6 , wherein DIFF_EN2 refers to the second control signal.
  • the input preprocessing module is used to receive the input signal, and is configured to output the first signal based on the input signal when the second control signal is a third level that matches the first level; when the second control signal is a third level that matches the second level level matched to the fourth electrical usually, outputting the second signal based on the input signal;
  • the second control signal performs level switching during conversion.
  • the input preprocessing module may include at least a first switch
  • the first switch is configured to switch the signal output by the input pre-processing module based on the second control signal.
  • the first switch may be set at the negative terminal of the input pre-processing module.
  • the positive terminal of the input preprocessing module can also be provided with the same switch as the first switch, so as to reduce the output voltage imbalance between the positive and negative terminals of the input preprocessing module and improve the accuracy of analog-to-digital conversion .
  • the positive end of the input preprocessing module may not be provided with a switch, and the input voltage of the positive end is connected to the analog-to-digital conversion module.
  • the positive end of the input preprocessing module is provided with a switch.
  • one end of the first switch is used to connect the negative end input voltage to the negative end of the input preprocessing module, and the other end is connected to the analog-to-digital conversion module;
  • one end of the first switch is used to connect the negative end of the input pre-processing module to the first preset voltage, and the other end is connected to the analog-to-digital conversion module.
  • the ADC circuit shown in FIG. 8 wherein the analog-to-digital conversion module may include a digital-to-analog conversion module, a comparison module and a logic module, and the digital-to-analog conversion module may be used for sampling and holding and quantization.
  • the quantization may adopt a successive approximation manner, or other manners, which are not limited in this embodiment.
  • the digital-to-analog conversion module is connected to the input preprocessing module, and is configured to execute the first working mode corresponding to the first signal when the first control signal is at the first level during conversion; when the first control signal is at the second level , executing the second working mode corresponding to the second signal;
  • the input end of the comparison module is connected with the digital-to-analog conversion module, and the output end is connected with the logic module;
  • the logic module is configured to output a digital signal corresponding to the input signal.
  • the above-mentioned digital-to-analog conversion module can be a digital-to-analog conversion differential capacitor array (marked as DAC in FIG. 9 ), the above comparison module may be a comparator (marked as COMP in FIG. 9 ), and the logic module may be a SAR logic module.
  • the digital-to-analog conversion module includes a positive-end digital-to-analog conversion module and a negative-end digital-to-analog conversion module, the positive-end digital-to-analog conversion module is adapted to the second switch, and the negative-end digital-to-analog conversion module is adapted to the third switch;
  • the second switch and the third switch are adapted to the first working mode
  • the second switch When the first control signal is at the second level, the second switch is adapted to the second working mode, and the third switch is used to connect the second preset voltage to the negative-end digital-to-analog conversion module.
  • the above-mentioned second switch is used to connect the positive terminal output voltage of the input preprocessing module to the positive terminal digital-to-analog conversion module
  • the above-mentioned third switch is used to connect the output voltage at the negative end of the input preprocessing module to the digital-to-analog conversion module at the negative end.
  • the above-mentioned ADC circuit can realize continuous conversion of differential signals and single-ended signals under the control of the first control signal and the second control signal.
  • the above-mentioned logic module is further configured to quantize the error voltage of the digital-to-analog conversion module to obtain the mismatch code during calibration. That is to say, during the calibration period, the existing logic modules in the analog-to-digital conversion module can be reused to calculate the mismatch code, and there is no need to add additional logic modules in the subsequent calibration modules, which optimizes the logic complexity of the calibration module and reduces The area of the ADC circuit is reduced.
  • the above-mentioned ADC circuit can also realize the continuous conversion of the differential signal and the single-ended signal.
  • the logic module since the logic module is multiplexed, there is no need to add another logic module, the logic complexity of the calibration module is optimized, and the area of the ADC circuit is reduced.
  • An embodiment of the present application provides a method for controlling an ADC circuit, and the method may be used to control the above-mentioned ADC circuit.
  • the control method will be introduced below with reference to the flowchart of the control method of the ADC circuit shown in FIG. 10 .
  • the clock control signal sar_clk, the sampling control signal sar_sample, the first control signal DIFF_EN1 and the second control signal DIFF_EN2 can be set in advance for the ADC circuit.
  • sar_sample can be initially low level, switched from low level to high level on the second rising edge of sar_clk, and switched from high level to low level on the fourth rising edge,
  • the sampling period is 2 clock periods; switch from high level to low level on the 4th rising edge of sar_clk, switch from low level to high level on the 16th rising edge, and the conversion period is 12 clock periods.
  • the initial level of the sampling control signal, the position of the specific switching level, the sampling period, and the conversion period are not limited.
  • the first control signal can be used to control the working mode of the ADC circuit during the conversion period, specifically, it can control the working mode of the digital-to-analog conversion module (DAC) in the analog-to-digital conversion module during the conversion period, and the ADC circuit
  • the circuit includes the calibration module, it controls the working mode of the calibration module.
  • the first control signal can be switched before the sampling control signal is switched to low level, that is, the first control signal can be switched during the sampling period, The switching of the first control signal does not affect the sampling function of the digital-to-analog conversion module.
  • the level of the first control signal can be switched earlier than the sampling control signal, so as to avoid affecting the conversion.
  • DIFF_EN1 can be switched earlier than sar_sample during the sampling period, for example, on the third rising edge of sar_clk, DIFF_EN1 switches from low level to high level, or it can be on the second or third A falling edge switches from low to high.
  • the second control signal can be used to control the output voltage mode of the input preprocessing module.
  • the second control signal can be switched to a high voltage when the sampling control signal Switching is performed before leveling, that is, the second control signal can be switched in level during conversion.
  • the level of the second control signal can be switched one or more clock cycles earlier than the sampling control signal, so as to avoid affecting the sampling.
  • DIFF_EN2 can be switched one or more clock cycles earlier than sar_sample during conversion, for example, on the first rising edge of sar_clk, DIFF_EN2 switches from low level to high level; in the ADC circuit During the conversion period of sar_clk, DIFF_EN2 can switch from high level to low level on the fifth rising edge of sar_clk, and can also switch from high level to low level on the fifteenth rising edge.
  • Step 1001 during conversion, when the first control signal is at the first level, output the corresponding first digital signal based on the sampling first signal, and output the corresponding first digital signal based on the sampling when the first control signal is at the second level corresponding to the second digital signal.
  • the first control signal can control the working mode of the ADC circuit, so that the ADC circuit can execute the first working mode corresponding to the differential signal or the second working mode corresponding to the single-ended signal, and output a digital signal corresponding to the differential signal or the single-ended signal.
  • the first level may be a high level or a low level, which is not limited in this embodiment.
  • the second level is opposite to the first level. When the first level is high, the second level is low; when the first level is low, the second level is high.
  • the ADC circuit may collect signals of multiple channels outside the circuit, where the collected signals may at least include differential signals and single-ended signals.
  • differential signals there can be two channels of input, such as channel X and channel X-1.
  • the signal of channel X can be used as the positive input signal VINP of the digital-to-analog conversion module, and the signal of channel X-1 is the input signal of the digital-to-analog conversion module.
  • Negative input signal VINN For single-ended signals, there may be an input of one channel, for example, channel X-2, and the signal of channel X-2 may be used as the positive input signal VINP of the digital-to-analog conversion module.
  • the acquired signal may be sampled based on a digital-to-analog conversion module.
  • the differential signal and the single-ended signal can be sampled alternately based on the digital-to-analog conversion module, that is, if the current sampling period samples the differential signal, then the next sampling period samples the single-ended signal ; If the single-ended signal is sampled in the current sampling period, the differential signal will be sampled in the next sampling period.
  • the differential signal i.e. the first signal
  • the sampled differential signal can be converted to output the corresponding first digital signal
  • the single-ended signal i.e. The second signal
  • Step 1002 during the conversion period, through the calibration module, determine the calibration code based on the mismatch code obtained during the calibration period, for The analog-to-digital conversion module performs calibration code compensation.
  • the error voltage of the digital-to-analog conversion module may be quantized to obtain a mismatch code. Furthermore, during the conversion period, the calibration code can be input into the analog-to-digital conversion module through the calibration module, and the error voltage of the digital-to-analog conversion module can be compensated to realize the calibration of the digital signal output by the analog-to-digital conversion module, so as to improve the accuracy of the ADC circuit .
  • the calibration module includes a calibration digital-to-analog conversion module, a calibration algorithm module, and a calibration control module.
  • the above step 1002 can be as the following steps 1101-1103.
  • Step 1101 when the first control signal is at the first level, through the calibration algorithm module, determine the first calibration code corresponding to the first signal based on the mismatch code; when the first control signal is at the second level, through the calibration algorithm module, A second calibration code corresponding to the second signal is determined based on the mismatch code.
  • the first control signal may control the working mode of the calibration algorithm module, so that the calibration algorithm module calculates and outputs the first calibration code corresponding to the differential signal or the second calibration code corresponding to the single-ended signal.
  • the working mode of the calibration algorithm module corresponds to the working mode of the ADC circuit during the above conversion.
  • the working mode is the first working mode corresponding to the differential signal.
  • the calibration algorithm module can calculate the differential signal based on the offset of the digital-to-analog conversion module and the error voltage of the capacitance mismatch.
  • a first calibration code and store the first calibration code in the calibration algorithm module.
  • the working mode is the second working mode corresponding to the single-ended signal.
  • the calibration algorithm module can calculate the single-ended signal based on the error voltage of the offset of the digital-to-analog conversion module and the capacitance mismatch
  • the second calibration code of the signal is stored in the calibration algorithm module.
  • Step 1102 transmit the calibration code currently output by the calibration algorithm module to the calibration digital-to-analog conversion module.
  • the SAR logic control signal can control the calibration differential capacitance array by controlling the calibration control module, and the output of the calibration control module is determined by the output of the calibration algorithm module.
  • the calibration code CALCODE_I ⁇ M:1> output by the calibration algorithm module is a differential calibration code (ie, the first calibration code)
  • the calibration control module can output the positive calibration code CALCODE_P ⁇ M:1> and the negative calibration code CALCODE_N ⁇ M:1> respectively, and transmit them to the calibration differential capacitor array.
  • the positive-terminal calibration code CALCODE_P ⁇ M:1> can be input into the positive-terminal capacitor array of the calibration differential capacitor array
  • the negative-terminal calibration code CALCODE_N ⁇ M:1> can be input into the negative-terminal capacitor array of the calibration differential capacitor array.
  • the calibration code CALCODE_I ⁇ M:1> output by the calibration algorithm module is a single-ended calibration code (that is, the second calibration code), and the processing of the subsequent calibration control module is the same as above, where No longer.
  • Step 1103 based on the calibration of the digital-to-analog conversion module, perform voltage compensation on the analog-to-digital conversion module according to the currently received calibration code.
  • the positive terminal capacitor array of the calibration differential capacitor array can receive the differential calibration code CALCODE_P ⁇ M:1>, fill the calibration code value CALCODE_P ⁇ M:1> to the voltage of the positive input terminal of the comparator; the negative terminal capacitor array of the calibration differential capacitor array can receive the differential calibration code CALCODE_N ⁇ M:1>, and will calibrate The code value CALCODE_N ⁇ M:1> is fed back to the voltage at the negative input terminal of the comparator.
  • the calibration differential capacitor array can receive the single-ended calibration code and compensate the voltage at the input terminal of the comparator.
  • the specific processing is the same as above, and will not be repeated here.
  • a back-up reset can also be performed to set the voltage of the calibration digital-to-analog conversion module to a preset intermediate calibration code.
  • CALCODE_P/N ⁇ M:1> as shown in Figure 3, during the sampling period, the calibration control module outputs the preset intermediate calibration code according to the sampling control signal, and transmits the intermediate calibration code to the calibration differential capacitor array, and the calibration differential capacitor The array is set to an intermediate calibration code value ready to compensate for positive and negative error voltages during normal conversions.
  • control method introduced above can realize continuous calibration of differential signals and single-ended signals.
  • continuous conversion of differential signals and single-ended signals can also be realized through the flow chart of the control method of the ADC circuit shown in FIG. 12 .
  • the ADC circuit also includes an input preprocessing module, and the control method is as follows in steps 1201-1203.
  • Step 1201 receiving an input signal
  • Step 1202 when the second control signal is a third level matching the first level, the first signal is obtained based on the input signal through the input preprocessing module;
  • Step 1203 when the second control signal is at a fourth level matching the second level, the second signal is obtained based on the input signal through an input preprocessing module.
  • the third level may be a high level or a low level, which is not limited in this embodiment.
  • the fourth level is opposite to the third level. When the third level is high, the fourth level is low; when the third level is low, the fourth level is high.
  • the differential signal there may be two channels of input, such as channel X and channel X-1, and the signal of channel X may be used as the positive terminal of the input preprocessing module
  • the input signal VINP the signal of the channel X-1 is the input signal VINN of the negative terminal of the input preprocessing module.
  • the second control signal can control the output voltage mode of the input pre-processing module, so that the input pre-processing module can output the first signal corresponding to the differential signal, or the second signal corresponding to the single-ended signal.
  • the output voltage mode of the input preprocessing module can be a differential mode.
  • the positive terminal output signal VIN+ of the input preprocessing module can be the signal VINP of channel X
  • the negative terminal output signal VIN - May be signal VINN of channel X-1.
  • the output voltage mode of the input preprocessing module can be single-ended mode.
  • the positive terminal output signal VIN+ of the input preprocessing module can be the signal VINP of channel X-2, and the negative terminal
  • the output signal VIN- can be a first preset voltage.
  • the first preset voltage can be the built-in positive reference voltage VREFN, the negative reference voltage VREFP or other fixed voltage values.
  • the second preset voltage below is the same, and the first preset voltage and the second preset voltage can be the same It may also be different, which is not limited in this embodiment.
  • the input preprocessing module includes at least a first switch, and the switching of the output first signal or the second signal can be realized through the first switch.
  • the first switch can be controlled based on the second control signal, and the input preprocessing can be switched. Process the signal output by the block.
  • the control method for the first switch can be as follows:
  • control the first switch When the second control signal is at the third level, control the first switch to connect the negative input voltage from the negative terminal of the input preprocessing module to the analog-to-digital conversion module; connect the positive terminal input voltage to the positive terminal of the input preprocessing module Analog-to-digital conversion module;
  • control the first switch When the second control signal is at the fourth level, control the first switch to connect the first preset voltage to the analog-to-digital conversion module from the negative terminal of the input preprocessing module; connect the positive terminal input voltage to the positive terminal of the input preprocessing module into the analog-to-digital conversion module.
  • the switch state during the sampling period as shown in Figures 13 and 14 take the positive and negative terminals of the input preprocessing module as an example, wherein the switch at the positive terminal is used to connect the input voltage of the positive terminal to the analog-to-digital conversion module;
  • the switch at the negative end is used to connect the input voltage at the negative end or the first preset voltage to the analog-to-digital conversion module.
  • the switch at the negative end corresponds to the above-mentioned first switch.
  • a specific implementation manner in which the first control signal controls the output voltage mode of the input preprocessing module is as follows:
  • one end of the switch at the positive end can be used to receive the input voltage at the positive end, and the other end can be connected to the analog-digital conversion module; one end of the switch at the negative end can be used to receive the input voltage at the negative end, and the other end can be used to receive the input voltage at the negative end.
  • One end is connected with the analog-to-digital conversion module.
  • the second control signal When the second control signal is at the fourth level, one end of the switch at the positive end can be used to receive the input voltage at the positive end, and the other end can be connected to the analog-to-digital conversion module; one end of the switch at the negative end can be used to receive the first preset voltage, The other end is connected with the analog-to-digital conversion module.
  • the analog-to-digital conversion module may include a digital-to-analog conversion module, a comparison module and a logic module, and the digital-to-analog conversion module is used for sampling and holding and quantization.
  • the analog-to-digital conversion module can sample and convert input analog signals so as to output corresponding digital signals.
  • the digital-to-analog conversion module can output to the input pre-processing module The output signal is sampled without modifying the circuit structure of the digital-to-analog conversion module.
  • the control method for the analog-to-digital conversion module can be as follows: control the digital-to-analog conversion module to execute the first working mode corresponding to the first signal; based on the logic module, Outputting a first digital signal corresponding to the first signal.
  • the control method for the analog-to-digital conversion module can be as follows: control the digital-to-analog conversion module to execute the second working mode corresponding to the second signal; based on the logic module, output the second working mode corresponding to the second signal Digital signal.
  • the digital-to-analog conversion module may include a positive-end digital-to-analog conversion module and a negative-end digital-to-analog conversion module, the positive-end digital-to-analog conversion module is adapted to the second switch, and the negative-end digital-to-analog conversion module is adapted to the third switch.
  • the second switch and the third switch the switching of the working mode of the digital-to-analog conversion module can be realized.
  • the control method is as follows: when the first control signal is at the first level, control the second switch and the third switch to adapt to the first working mode; when the first control signal is at the second level, control the second switch to adapt to the second working mode mode, controlling the third switch to connect the second preset voltage to the negative-end digital-to-analog conversion module.
  • the successive approximation search logic module can be used to control the digital-to-analog conversion differential capacitance array respectively. each switch. At this time, the positive and negative capacitor arrays of the digital-to-analog conversion differential capacitor array are controlled by the successive approximation search logic module at the same time.
  • the difference between the second preset voltage and the first preset voltage connected to the input pre-processing module may not be greater than a difference threshold.
  • the difference threshold may be equal to (VREFN+VREFP)/2.
  • the second preset voltage is equal to the first preset voltage.
  • the digital signal output by the ADC circuit may be processed based on the voltage difference.
  • the second preset voltage can be subtracted from the first preset voltage to obtain a voltage difference; based on the principle of analog-to-digital conversion in the ADC circuit, the voltage difference is converted into a difference code value; the output of the ADC circuit The digital signal code value is subtracted from the difference code value to obtain the final digital signal code value.
  • N is the number of bits of the ADC circuit, and the difference code value can be positive or negative.
  • the above-mentioned processing of converting difference code values may be processed in a circuit, or may be processed by software during use, which is not limited in this embodiment.
  • the mismatch code in the above step 1002 can be calculated by the logic module in the analog-to-digital conversion module, and the specific processing is as follows: during calibration, the multiplexing logic module performs a calculation on the error voltage of the digital-to-analog conversion module Quantize to get the mismatch code.
  • the SAR ADC circuit shown in Figure 9 in the calibration error stage, the existing successive approximation search logic module in the analog-to-digital conversion module can be reused, and the SAR logic control signal controls the calibration control module to control the calibration of the differential capacitor array. Quantify the offset of the digital-to-analog conversion differential capacitance array and the error voltage of capacitance mismatch, and transmit the obtained mismatch code to the calibration algorithm module, and the calibration algorithm module stores the mismatch code.
  • the ADC circuit may further include a reset switch, which may be used to connect the bias voltage to the digital-to-analog conversion module.
  • the reset switch SWCM1/2 can be closed, so that one plate of the capacitor in the digital-to-analog conversion differential capacitor array is reset to the bias voltage VCM.
  • the reset switch SWCM1/2 can be turned off.
  • the ADC circuit can realize continuous calibration of two different working modes, and it is not necessary to restart the ADC circuit to configure different working modes.
  • the quantization error voltage is realized by multiplexing the logic module, without adding another logic module, the logic complexity of the calibration module is optimized, and the area of the ADC circuit can be reduced.
  • the exemplary embodiment of the present application further provides a chip, including the ADC circuit provided in the embodiment of the present application.
  • An exemplary embodiment of the present application further provides an electronic device, including: the ADC circuit provided in the embodiment of the present application; at least one processor; and a memory communicatively connected to the at least one processor.
  • the memory stores a computer program executable by at least one processor, and the computer program is used to cause the electronic device to execute the method according to the embodiment of the present application when executed by the at least one processor.
  • Exemplary embodiments of the present application also provide a non-transitory computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor of a computer, is used to cause the computer to execute the method according to the embodiment of the present application.
  • Electronic Equipment is intended to mean various forms of digital electronic computer equipment, such as, data center servers, notebook computers, thin clients, laptop computers, desktop computers, workstations, personal digital assistants, blade servers, mainframe computers, and other suitable computer.
  • Electronic devices may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smart phones, wearable devices, and other similar computing devices.
  • the components shown herein, their connections and relationships, and their functions, are by way of example only, and are not intended to limit implementations of the applications described and/or claimed herein.
  • an electronic device 1700 includes a computing unit 1701, which can perform calculations according to a computer program stored in a read-only memory (ROM) 1702 or a computer program loaded from a storage unit 1708 into a random access memory (RAM) 1703. Various appropriate actions and processes are performed. In the RAM 1703, various programs and data necessary for the operation of the device 1700 can also be stored.
  • the computing unit 1701, ROM 1702, and RAM 1703 are connected to each other through a bus 1704.
  • An input/output (I/O) interface 1705 is also connected to the bus 1704 .
  • the input unit 1706 can be any type of device capable of inputting information to the electronic device 1700.
  • the input unit 1706 can receive input numeric or character information, and generate key signal input related to user settings and/or function control of the electronic device.
  • the output unit 1707 may be any type of device capable of presenting information, and may include, but is not limited to, a display, a speaker, a video/audio output terminal, a vibrator, and/or a printer.
  • the storage unit 1704 may include, but not limited to, magnetic disks and optical disks.
  • the communication unit 1709 allows the electronic device 1700 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks, and may include but not limited to a modem, a network card, an infrared communication device, a wireless communication transceiver and/or a chip Groups, such as Bluetooth devices, WiFi devices, WiMax devices, cellular communication devices, and/or the like.
  • the computing unit 1701 may be various general-purpose and/or special-purpose processing components with processing and computing capabilities. Some examples of computing units 1701 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any suitable processor, controller, microcontroller, etc.
  • the computing unit 1701 executes the various methods and processes described above.
  • the method of controlling the ADC circuit may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 1708 .
  • part or all of the computer program may be loaded and/or installed on the electronic device 1700 via the ROM 1702 and/or the communication unit 1709 .
  • the computing unit 1701 can be configured to execute the control method of the ADC circuit in any other suitable way (for example, by means of firmware).
  • Program codes for implementing the methods of the present application may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented.
  • the program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
  • a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device.
  • a machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • a machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing.
  • machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.
  • RAM random access memory
  • ROM read only memory
  • EPROM or flash memory erasable programmable read only memory
  • CD-ROM compact disk read only memory
  • magnetic storage or any suitable combination of the foregoing.
  • machine-readable medium and “computer-readable medium” refer to any computer program product, apparatus, and/or means for providing machine instructions and/or data to a programmable processor (eg, magnetic disk, optical disk, memory, programmable logic device (PLD)), including machine-readable media that receive machine instructions as machine-readable signals.
  • machine-readable signal refers to any signal used to provide machine instructions and/or data to a programmable processor.
  • the systems and techniques described herein can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user. ); and a keyboard and pointing device (eg, a mouse or a trackball) through which a user can provide input to the computer.
  • a display device e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor
  • a keyboard and pointing device eg, a mouse or a trackball
  • Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and can be in any form (including Acoustic input, speech input or, tactile input) to receive input from the user.
  • the systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., as a a user computer having a graphical user interface or web browser through which a user can interact with embodiments of the systems and techniques described herein), or including such backend components, middleware components, Or any combination of front-end components in a computing system.
  • the components of the system can be interconnected by any form or medium of digital data communication, eg, a communication network. Examples of communication networks include: Local Area Network (LAN), Wide Area Network (WAN) and the Internet.
  • a computer system may include clients and servers.
  • Clients and servers are generally remote from each other and usually network to interact.
  • the relationship of client and server arises by computer programs running on the respective computers and having a client-server relationship to each other.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

本申请提供一种ADC电路及其控制方法，属于电子技术领域。所述ADC电路至少包括：模数转换模块，校准模块；所述模数转换模块，被配置为在转换期间，当第一控制信号为第一电平时，基于采样的第一信号输出对应的第一数字信号，当所述第一控制信号为第二电平时，基于采样的第二信号输出对应的第二数字信号；所述校准模块与所述模数转换模块连接，被配置为基于校准期间得到的失配码确定校准码，对所述模数转换模块进行校准码回补；其中，所述第一控制信号在采样期间进行电平切换。采用本申请，可以实现对模数转换模块的差分模式和单端模式的连续校准。

Description

一种ADC电路及其控制方法
本申请要求于2022年2月10日提交中国专利局、申请号为202210124222.9、发明名称为“一种ADC电路及其控制方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，尤其涉及一种ADC电路及其控制方法。
背景技术
在电子技术领域中，模拟数字转换器(Analog-to-Digital Converter,ADC)电路可以用于信号测量，将模拟信号转换为数字信号。
在某些应用场景下，需要支持连续测量不同输入通道的差分信号和单端信号。目前常规做法是，通过切换ADC工作模式，利用差分模式和单端模式分别处理差分信号和单端信号。
但是，现有的ADC不能连续运行两种工作模式，例如，需要对差分信号处理完毕后，才会重新配置ADC，再对单端信号进行处理，中间会存在冗余的模式切换时间，不能连续运行。并且当对ADC精度要求比较高时，需要对ADC进行校准，传统方法也无法满足连续对ADC差分模式和单端模式进行校准。
发明内容
为了解决现有技术的问题，本申请实施例提供了一种ADC电路及其控制方法。技术方案如下：
根据本申请的一方面，提供了一种ADC电路，所述ADC电路至少包括：模数转换模块，校准模块；
所述模数转换模块，被配置为在转换期间，当第一控制信号为第一电平时，基于采样的第一信号输出对应的第一数字信号，当所述第一控制信号为第二电平时，基于采样的第二信号输出对应的第二数字信号；
所述校准模块与所述模数转换模块连接，被配置为基于校准期间得到的失配码确定校准码，对所述模数转换模块进行校准码回补；
其中，所述第一控制信号在采样期间进行电平切换。
可选的，所述校准模块包括校准数模转换模块，校准算法模块，校准控制模块；
所述校准算法模块的输入端与所述模数转换模块连接，输出端与所述校准控制模块连接，被配置为当所述第一控制信号为所述第一电平时，基于所述失配码确定所述第一信号对应的第一校准码；当所述第一控制信号为所述第二电平时，基于所述失配码确定所述第二信号对应的第二校准码；
所述校准控制模块，被配置为在所述转换期间，将所述校准算法模块当前输出的校准码传输至所述校准数模转换模块；
所述校准数模转换模块，被配置为在所述转换期间，基于当前接收的校准码对所述数模转换模块进行电压回补。
可选的，所述校准算法模块，还被配置为存储所述失配码。
可选的，所述校准控制模块，还被配置为在所述采样期间，将校准码设置为预设的中间校准码，将所述中间校准码传输至所述校准数模转换模块。
可选的，所述ADC电路还包括输入预处理模块，所述输入预处理模块的输出端与所述模数转换模块的输入端连接；
所述输入预处理模块用于接收输入信号，被配置为当第二控制信号为与所述第一电平相匹配的第三电平时，基于所述输入信号输出所述第一信号；当所述第二控制信号为与所述第二电平相匹配的第四电平时，基于所述输入信号输出所述第二信号；
其中，所述第二控制信号在所述转换期间进行电平切换。
可选的，所述输入预处理模块至少包括第一开关；
所述第一开关，被配置为基于所述第二控制信号，切换所述输入预处理模块输出的信号。
可选的，当所述第二控制信号为所述第三电平时，所述第一开关的一端用于在所述输入预处理模块的负端接入负端输入电压，另一端与所述模数转换模块连接；
当所述第二控制信号为所述第四电平时，所述第一开关的一端用于在所述输入预处理模块的负端接入第一预设电压，另一端与所述模数转换模块连接。
可选的，所述模数转换模块包括数模转换模块、比较模块和逻辑模块，所述数模转换模块用于采样保持和量化；
所述数模转换模块与所述输入预处理模块连接，被配置为在所述转换期间，当所述第一控制信号为所述第一电平时，执行所述第一信号对应的第一工作模式；当所述第一控制信号为所述第二电平时，执行所述第二信号对应的第二工作模式；
所述比较模块的输入端与所述数模转换模块连接，输出端与所述逻辑模块连接；
所述逻辑模块，被配置为输出所述输入信号对应的数字信号。
可选的，所述数模转换模块包括正端数模转换模块和负端数模转换模块，所述正端数模转换模块和第二开关相适配，所述负端数模转换模块和第三开关相适配；
在所述转换期间，
当所述第一控制信号为所述第一电平时，所述第二开关和所述第三开关适配所述第一工作模式；
当所述第一控制信号为所述第二电平时，所述第二开关适配所述第二工作模式，所述第三开关用于将第二预设电压接入所述负端数模转换模块。
可选的，所述第二预设电压与接入所述输入预处理模块的第一预设电压之间的差值不大于差值阈值。
可选的，所述逻辑模块，还被配置为在校准期间，对数模转换模块的误差电压进行量化，得到失配码。
根据本申请的另一方面，提供了一种ADC电路的控制方法，所述ADC电路至少包括：模数转换模块、校准模块，所述方法包括：
在转换期间，当第一控制信号为第一电平时，基于采样的第一信号输出对应的第一数字信号，当所述第一控制信号为第二电平时，基于采样的第二信号输出对应的第二数字信号；
在所述转换期间，通过所述校准模块，基于校准期间得到的失配码确定校准码，对所述模数转换模块进行校准码回补；
其中，所述第一控制信号在采样期间进行电平切换。
可选的，所述校准模块包括校准数模转换模块，校准算法模块，校准控制模块；
所述通过所述校准模块，基于校准期间得到的失配码确定校准码，对所述模数转换模块进行校准码回补，包括：
当所述第一控制信号为所述第一电平时，通过所述校准算法模块，基于所述失配码确定所述第一信号对应的第一校准码；当所述第一控制信号为所述第二电平时，通过所述校准算法模块，基于所述失配码确定所述第二信号对应的第二校准码；
将所述校准算法模块当前输出的校准码传输至所述校准数模转换模块；
基于所述校准数模转换模块，根据当前接收的校准码对所述模数转换模块进行电压回补。
可选的，所述方法还包括：
基于所述校准算法模块存储所述失配码。
可选的，所述方法还包括：
在所述采样期间，将所述校准数模转换模块的电压设置为预设的中间校准码。
可选的，所述ADC电路还包括输入预处理模块，所述方法还包括：
接收输入信号；
当第二控制信号为与所述第一电平相匹配的第三电平时，通过所述输入预处理模块，基于所述输入信号获取第一信号；
当所述第二控制信号为与所述第二电平相匹配的第四电平时，通过所述输入预处理模块，基于所述输入信号获取第二信号；
其中，所述第二控制信号在所述转换期间进行电平切换。
可选的，所述输入预处理模块至少包括第一开关；
所述方法还包括：基于所述第二控制信号控制所述第一开关，切换所述输入预处理模块输出的信号。
可选的，所述基于所述第二控制信号控制所述第一开关，切换所述输入预处理模块输出的信号，包括：
当所述第二控制信号为所述第三电平时，控制所述第一开关将负端输入电压从所述输入预处理模块的负端接入所述模数转换模块；将正端输入电压从所述输入预处理模块的正端接入所述模数转换模块；
当所述第二控制信号为所述第四电平时，控制所述第一开关将第一预设电压从所述输入预处理模块的负端接入所述模数转换模块；将正端输入电压从所述输入预处理模块的正端接入所述模数转换模块。
可选的，所述模数转换模块包括数模转换模块、比较模块和逻辑模块，所述数模转换模块用于采样保持和量化；
所述基于采样的第一信号输出对应的第一数字信号，包括：控制所述数模转换模块执行所述第一信号对应的第一工作模式；基于所述逻辑模块，输出所述第一信号对应的第一数字信号；
所述基于采样的第二信号输出对应的第二数字信号，包括：控制所述数模转换模块执行所述第二信号对应的第二工作模式；基于所述逻辑模块，输出所述第二信号对应的第二数字信号。
可选的，所述数模转换模块包括正端数模转换模块和负端数模转换模块，所述正端数模转换模块和第二开关相适配，所述负端数模转换模块和第三开关相适配；
所述方法还包括：
当所述第一控制信号为所述第一电平时，控制所述第二开关和所述第三开关适配所述第一工作模式；
当所述第一控制信号为所述第二电平时，控制所述第二开关适配所述第二工作模式，控制所述第三开关将第二预设电压接入所述负端数模转换模块。
可选的，所述第二预设电压与接入所述输入预处理模块的第一预设电压之间的差值不大于差值阈值。
可选的，所述方法还包括：
在校准期间，复用所述逻辑模块对数模转换模块的误差电压进行量化，得到失配码。
根据本申请的另一方面，提供了一种芯片，包括上述ADC电路。
根据本申请的另一方面，提供了一种电子设备，包括：
上述ADC电路；
处理器；以及
存储程序的存储器，
其中，所述程序包括指令，所述指令在由所述处理器执行时使所述处理器执行上述ADC电路的控制方法。
根据本申请的另一方面，提供了一种存储有计算机指令的非瞬时计算机可读存储介质，其中，所述计算机指令用于使计算机执行上述ADC电路的控制方法。
本申请实施例中，通过第一控制信号，ADC电路可以实现对两种不同的工作模式的连续校准，不需要重新启动ADC电路来对不同的工作模式进行配置。
附图说明
在下面结合附图对于示例性实施例的描述中，本申请的更多细节、特征和优点被公开，在附图中：
图1示出了根据本申请示例性实施例提供的ADC电路结构示意图；
图2示出了根据本申请示例性实施例提供的ADC电路结构示意图；
图3示出了根据本申请示例性实施例提供的时序控制示意图；
图4示出了根据本申请示例性实施例提供的SAR ADC电路结构示意图；
图5示出了根据本申请示例性实施例提供的ADC电路结构示意图；
图6示出了根据本申请示例性实施例提供的时序控制示意图；
图7示出了根据本申请示例性实施例提供的输入预处理模块示意图；
图8示出了根据本申请示例性实施例提供的ADC电路结构示意图；
图9示出了根据本申请示例性实施例提供的SAR ADC电路结构示意图；
图10示出了根据本申请示例性实施例提供的ADC电路的控制方法流程图；
图11示出了根据本申请示例性实施例提供的ADC电路的校准控制方法流程图；
图12示出了根据本申请示例性实施例提供的ADC电路的控制方法流程图；
图13示出了根据本申请示例性实施例提供的采样期间开关状态示意图；
图14示出了根据本申请示例性实施例提供的采样期间开关状态示意图；
图15示出了根据本申请示例性实施例提供的转换期间开关状态示意图；
图16示出了根据本申请示例性实施例提供的转换期间开关状态示意图；
图17示出了能够用于实现本申请的实施例的示例性电子设备的结构框图。
具体实施方式
下面将参照附图更详细地描述本申请的实施例。虽然附图中显示了本申请的某些实施例，然而应当理解的是，本申请可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本申请。应当理解的是，本申请的附图及实施例仅用于示例性作用，并非用于限制本申请的保护范围。
应当理解，本申请的方法实施方式中记载的各个步骤可以按照不同的顺序执行，和/或并行执行。此外，方法实施方式可以包括附加的步骤和/或省略执行示出的步骤。本申请的范围在此方面不受限制。
本文使用的术语“包括”及其变形是开放性包括，即“包括但不限于”。术语“基于”是“至少部分地基于”。术语“一个实施例”表示“至少一个实施例”；术语“另一实施例”表示“至少一个另外的实施例”；术语“一些实施例”表示“至少一些实施例”。其他术语的相关定义将在下文描述中给出。需要注意，本申请中提及的“第一”、“第二”等概念仅用于对不同的装置、模块或单元进行区分，并非用于限定这些装置、模块或单元所执行的功能的顺序或者相互依存关系。
需要注意，本申请中提及的“一个”、“多个”的修饰是示意性而非限制性的，本领域技术人员应当理解，除非在上下文另有明确指出，否则应该理解为“一个或多个”。
本申请实施方式中的多个装置之间所交互的消息或者信息的名称仅用于说明性的目的，而并不是用于对这些消息或信息的范围进行限制。
本申请实施例提供了一种ADC电路，如图1所示，该ADC电路至少包括：模数转换模块，校准模块。
模数转换模块，被配置为在转换期间，当第一控制信号为第一电平时，基于采样的第一信号输出对应的第一数字信号，当第一控制信号为第二电平时，基于采样的第二信号输出对应的第二数字信号；
校准模块与模数转换模块连接，被配置为基于校准期间得到的失配码确定校准码，对 模数转换模块进行校准码回补；
其中，第一控制信号在采样期间进行电平切换。
在一种可能的实施方式中，上述第一信号的输入信号可以是差分信号，第一信号可以是对应的差分信号；上述第二信号的输入信号可以是单端信号，第二信号可以是对应的伪差分信号。
可选的，如图2所示的ADC电路，其中，校准模块可以包括校准数模转换模块，校准算法模块，校准控制模块。该ADC电路可以由如图3所示的时序进行控制，其中，sar_clk是指时钟控制信号，sar_sample是指采样控制信号，DIFF_EN1是指第一控制信号，CALCODE_I<M:1>是指校准算法模块输出的校准码，CALCODE_P/N<M:1>是指校准控制模块输出的校准码，M位数由校准数模转换模块的位数决定。
校准算法模块的输入端与模数转换模块连接，输出端与校准控制模块连接，被配置为当第一控制信号为第一电平时，基于失配码确定第一信号对应的第一校准码；当第一控制信号为第二电平时，基于失配码确定第二信号对应的第二校准码；
校准控制模块，被配置为在转换期间，将校准算法模块当前输出的校准码传输至校准数模转换模块；
校准数模转换模块，被配置为在转换期间，基于当前接收的校准码对数模转换模块进行电压回补。
在一种可能的实施方式中，当ADC电路为SAR ADC电路时，相对应的增加校准模块后的电路如图4所示。校准算法模块的输入端与逐次逼近搜索逻辑模块连接。校准数模转换模块可以是校准差分电容阵列(图4中标记为CALDACP/CALDACN)，与对比较器的输入端连接，可以被配置为在转换期间，基于当前接收的校准码对比较器输入端的电压进行回补。
除了图4示出的校准差分电容阵列，校准数模转换模块还可以采用其他的电路结构，例如电容电阻阵列，本实施例对校准数模转换模块的具体电路结构不作限定。
可选的，校准算法模块，还被配置为存储失配码。
可选的，校准控制模块，还被配置为在采样期间，将校准码设置为预设的中间校准码，将中间校准码传输至校准数模转换模块。
可选的，如图5所示的ADC电路结构示意图，ADC电路还包括输入预处理模块，输入预处理模块的输出端与模数转换模块的输入端连接。该ADC电路可以由如图6所示的时序进行控制，其中，DIFF_EN2是指第二控制信号。
输入预处理模块用于接收输入信号，被配置为当第二控制信号为与第一电平相匹配的第三电平时，基于输入信号输出第一信号；当第二控制信号为与第二电平相匹配的第四电 平时，基于输入信号输出所述第二信号；
其中，第二控制信号在转换期间进行电平切换。
可选的，输入预处理模块至少可以包括第一开关；
第一开关，被配置为基于第二控制信号，切换输入预处理模块输出的信号。
如图7所示的输入预处理模块示意图，第一开关可以设置于输入预处理模块的负端。
在一种可能的实施方式中，输入预处理模块的正端也可以设置有与第一开关相同的开关，用以减少输入预处理模块正负两端输出电压失调，提高模数转换的准确性。
在另一种可能的实施方式中，输入预处理模块的正端也可以不设置开关，将正端输入电压接入模数转换模块。本实施例对输入预处理模块的正端是否设置开关不作限定。
可选的，当第二控制信号为第三电平时，第一开关的一端用于在输入预处理模块的负端接入负端输入电压，另一端与模拟数字转换模块连接；
当第二控制信号为第四电平时，第一开关的一端用于在输入预处理模块的负端接入第一预设电压，另一端与模数转换模块连接。
可选的，如图8所示的ADC电路，其中，模数转换模块可以包括数模转换模块、比较模块和逻辑模块，数模转换模块可以用于采样保持和量化。该量化可以采用逐次逼近的方式，也可以采用其他方式，本实施例对此不作限定。
数模转换模块与输入预处理模块连接，被配置为在转换期间，当第一控制信号为第一电平时，执行第一信号对应的第一工作模式；当第一控制信号为第二电平时，执行第二信号对应的第二工作模式；
比较模块的输入端与数模转换模块连接，输出端与逻辑模块连接；
逻辑模块，被配置为输出输入信号对应的数字信号。
在一种可能的实施方式中，如图9所示的SAR ADC(Successive Approximation Register Analog-to-Digital Converter，逐次逼近式模拟数字转换器)电路，上述数模转换模块可以是数字模拟转换差分电容阵列(图9中标记为DAC)，上述比较模块可以是比较器(图9中标记为COMP)，逻辑模块可以是SAR逻辑模块。
可选的，数模转换模块包括正端数模转换模块和负端数模转换模块，正端数模转换模块和第二开关相适配，负端数模转换模块和第三开关相适配；
在转换期间，
当第一控制信号为第一电平时，第二开关和第三开关适配第一工作模式；
当第一控制信号为第二电平时，第二开关适配第二工作模式，第三开关用于将第二预设电压接入负端数模转换模块。
在采样期间，上述第二开关用于将输入预处理模块的正端输出电压接入正端数模转换 模块，上述第三开关用于将输入预处理模块的负端输出电压接入负端数模转换模块。
上述ADC电路可以在第一控制信号和第二控制信号的控制之下实现差分信号和单端信号的连续转换。
可选的，上述逻辑模块，还被配置为在校准期间，对数模转换模块的误差电压进行量化，得到失配码。也即是说，在校准期间，可以复用模数转换模块中已有的逻辑模块来计算失配码，无需在后续的校准模块中额外增加逻辑模块，优化了校准模块逻辑复杂度，并减小了ADC电路的面积。
上述ADC电路在实现差分信号和单端信号的连续校准的基础上，还可以实现对差分信号和单端信号的连续转换。其中，由于复用了逻辑模块，无需额外增加另一逻辑模块，优化了校准模块逻辑复杂度，并减小了ADC电路的面积。
本申请实施例提供了一种ADC电路的控制方法，该方法可以用于控制上述ADC电路。下面将参照图10所示的ADC电路的控制方法流程图，对控制方法进行介绍。
首先对图3、6中示出的时序控制关系进行介绍。
在电子设备中可以预先对ADC电路设置时钟控制信号sar_clk、采样控制信号sar_sample、第一控制信号DIFF_EN1、第二控制信号DIFF_EN2。
当采样控制信号为高电平时，ADC电路处于采样期间，执行采样相关的处理；当采样控制信号为低电平时，ADC电路处于转换期间，执行转换相关的处理。如图3、6所示，sar_sample初始可以为低电平，在sar_clk的第2个上升沿从低电平切换为高电平，在第4个上升沿从高电平切换为低电平，采样周期为2个时钟周期；在sar_clk的第4个上升沿从高电平切换为低电平，在第16个上升沿从低电平切换为高电平，转换周期为12个时钟周期。本实施例对采样控制信号的初始电平、具体切换电平的位置以及采样周期、转换周期不作限定。
在本实施例中，第一控制信号可以用于控制ADC电路在转换期间的工作模式，具体可以是控制模数转换模块中的数模转换模块(DAC)在转换期间的工作模式，以及在ADC电路包括校准模块时，控制校准模块的工作模式。为了保证ADC电路在转换之前可以提前配置好相应的工作模式，第一控制信号可以在采样控制信号切换为低电平之前进行切换，也即是第一控制信号可以在采样期间进行电平切换，第一控制信号的切换不影响数模转换模块的采样功能。
在一种优选的实施方式中，第一控制信号可以比采样控制信号提前切换电平，避免对转换造成影响。如图3、6所示，DIFF_EN1可以在采样期间，比sar_sample提前切换，比如在sar_clk的第3个上升沿，DIFF_EN1从低电平切换到高电平，也可以在第2个或第3 个下降沿从低电平切换到高电平。本实施例对第一控制信号具体切换电平的位置不作限定。
在本实施例中，第二控制信号可以用于控制输入预处理模块的输出电压模式，为了保证ADC电路采样之前可以提前处理好外部输入信号，第二控制信号可以在采样控制信号切换为高电平之前进行切换，也即是第二控制信号可以在转换期间进行电平切换。
在一种优选的实施方式中，第二控制信号可以比采样控制信号提前1个时钟周期或者多个时钟周期切换电平，避免对采样造成影响。如图6所示，DIFF_EN2可以在转换期间，比sar_sample提前1个时钟周期或者多个时钟周期切换，比如在sar_clk的第1个上升沿，DIFF_EN2从低电平切换到高电平；在ADC电路的转换期间，DIFF_EN2可以在sar_clk的第5个上升沿从高电平切换到低电平，也可以在第15个上升沿从高电平切换到低电平。本实施例对第二控制信号具体切换电平的位置不作限定。
其次对图10中示出的ADC电路的控制方法进行介绍。
步骤1001，在转换期间，当第一控制信号为第一电平时，基于采样的第一信号输出对应的第一数字信号，当第一控制信号为第二电平时，基于采样的第二信号输出对应的第二数字信号。
其中，第一控制信号可以控制ADC电路的工作模式，使得ADC电路可以执行差分信号对应的第一工作模式或者单端信号对应的第二工作模式，输出差分信号或单端信号对应的数字信号。第一电平可以是高电平，也可以是低电平，本实施例对此不作限定。第二电平与第一电平相反，当第一电平为高电平时，第二电平为低电平；当第一电平为低电平时，第二电平为高电平。
在一种可能的实施方式中，ADC电路可以对电路外部多个通道的信号进行采集，其中采集的信号可以至少包括差分信号和单端信号。对于差分信号，可以具有两个通道的输入，例如通道X和通道X-1，通道X的信号可以作为数模转换模块的正端输入信号VINP，通道X-1的信号为数模转换模块的负端输入信号VINN。对于单端信号，可以具有一个通道的输入，例如通道X-2，通道X-2的信号可以作为数模转换模块的正端输入信号VINP。
在采样期间，可以基于数模转换模块对获取的信号进行采样。在不同的采样期间，可以基于数模转换模块交替对差分信号和单端信号进行采样，也即是说，如果当前的采样期间对差分信号进行采样，则在下一个采样期间对单端信号进行采样；如果当前的采样期间对单端信号进行采样，则在下一个采样期间对差分信号进行采样。
在转换期间，如果对应的采样期间对差分信号(即第一信号)进行采样，则可以对采样的差分信号进行转换，输出对应的第一数字信号；如果对应的采样期间对单端信号(即第二信号)进行采样，则可以对采样的单端信号进行转换，输出对应的第二数字信号。
步骤1002，在转换期间，通过校准模块，基于校准期间得到的失配码确定校准码，对 模数转换模块进行校准码回补。
在一种可能的实施方式中，在校准期间，可以对数模转换模块的误差电压进行量化，得到失配码。进而，在转换期间，可以通过校准模块将校准码输入模数转换模块，将数模转换模块的误差电压进行回补，实现对模数转换模块输出的数字信号的校准，以提高ADC电路的精度。
可选的，校准模块包括校准数模转换模块，校准算法模块，校准控制模块。在此基础上，如图11所示的ADC电路的校准控制方法流程图，上述步骤1002可以如下述步骤1101-1103。
步骤1101，当第一控制信号为第一电平时，通过校准算法模块，基于失配码确定第一信号对应的第一校准码；当第一控制信号为第二电平时，通过校准算法模块，基于失配码确定第二信号对应的第二校准码。
在一种可能的实施方式中，第一控制信号可以控制校准算法模块的工作模式，使得校准算法模块计算并输出差分信号对应的第一校准码或者单端信号对应的第二校准码。校准算法模块的工作模式与上述转换期间ADC电路的工作模式相对应。
当第一控制信号为第一电平时，工作模式为差分信号对应的第一工作模式，在转换期间，校准算法模块可以基于数模转换模块的失调和电容失配的误差电压，计算差分信号的第一校准码，并将该第一校准码存储在校准算法模块中。
当第一控制信号为第二电平时，工作模式为单端信号对应的第二工作模式，在转换期间，校准算法模块可以基于数模转换模块的失调和电容失配的误差电压，计算单端信号的第二校准码，并将该第二校准码存储在校准算法模块中。
步骤1102，将校准算法模块当前输出的校准码传输至校准数模转换模块。
在一种可能的实施方式，SAR逻辑控制信号可以通过控制校准控制模块，来控制校准差分电容阵列，校准控制模块的输出由校准算法模块的输出决定。如图9所示的SAR ADC电路，在转换期间，当第一控制信号为第一电平时，校准算法模块输出的校准码CALCODE_I<M:1>为差分校准码(即第一校准码)，此时，校准控制模块可以分别输出正端校准码CALCODE_P<M:1>和负端校准码CALCODE_N<M:1>，传输至校准差分电容阵列。其中，正端校准码CALCODE_P<M:1>可以输入校准差分电容阵列的正端电容阵列，负端校准码CALCODE_N<M:1>可以输入校准差分电容阵列的负端电容阵列。
当第一控制信号为第二电平时，校准算法模块输出的校准码CALCODE_I<M:1>为单端校准码(即第二校准码)，后续校准控制模块的处理与上述同理，此处不再赘述。
步骤1103，基于校准数模转换模块，根据当前接收的校准码对模数转换模块进行电压回补。
在一种可能的实施方式中，如图4所示的SAR ADC电路，在转换期间，当第一控制信号为第一电平时，校准差分电容阵列的正端电容阵列可以接收到差分校准码CALCODE_P<M:1>，将校准码值CALCODE_P<M:1>回补至比较器正输入端的电压；校准差分电容阵列的负端电容阵列可以接收到差分校准码CALCODE_N<M:1>，将校准码值CALCODE_N<M:1>回补至比较器负输入端的电压。
当第一控制信号为第二电平时，校准差分电容阵列可以接收到单端校准码，对比较器输入端的电压进行回补，具体处理与上述同理，此处不再赘述。
在上述步骤1103之前的采样期间，还可以进行回补复位，将校准数模转换模块的电压设置为预设的中间校准码。如图3所示的CALCODE_P/N<M:1>，在采样期间，校准控制模块根据采样控制信号输出预置的中间校准码，并将中间校准码传输至校准差分电容阵列，将校准差分电容阵列设置为中间校准码值，为正常转换期间补偿可正可负的误差电压做好准备。
上文介绍的控制方法可以实现对差分信号和单端信号的连续校准，此外，还可以通过如图12所示的ADC电路的控制方法流程图，实现对差分信号和单端信号的连续转换。此时，ADC电路还包括输入预处理模块，该控制方法如下述步骤1201-1203。
步骤1201，接收输入信号；
步骤1202，当第二控制信号为与第一电平相匹配的第三电平时，通过输入预处理模块，基于输入信号获取第一信号；
步骤1203，当第二控制信号为与第二电平相匹配的第四电平时，通过输入预处理模块，基于输入信号获取第二信号。
其中，第三电平可以是高电平，也可以是低电平，本实施例对此不作限定。第四电平与第三电平相反，当第三电平为高电平时，第四电平为低电平；当第三电平为低电平时，第四电平为高电平。
在一种可能的实施方式中，参照上述步骤1001的介绍，对于差分信号，可以具有两个通道的输入，例如通道X和通道X-1，通道X的信号可以作为输入预处理模块的正端输入信号VINP，通道X-1的信号为输入预处理模块的负端输入信号VINN。对于单端信号，可以具有一个通道的输入，例如通道X-2，通道X-2的信号可以作为输入预处理模块的正端输入信号VINP。
第二控制信号可以控制输入预处理模块的输出电压模式，使得输入预处理模块可以输出差分信号对应的第一信号，或者单端信号对应的第二信号。
当第二控制信号为第三电平时，输入预处理模块的输出电压模式可以为差分模式，此时，输入预处理模块的正端输出信号VIN+可以为通道X的信号VINP，负端输出信号VIN- 可以为通道X-1的信号VINN。
当第二控制信号为第四电平时，输入预处理模块的输出电压模式可以为单端模式，此时，输入预处理模块的正端输出信号VIN+可以为通道X-2的信号VINP，负端输出信号VIN-可以为第一预设电压。第一预设电压可以是内置的正端参考电压VREFN、负端参考电压VREFP或者其它固定电压值，后文的第二预设电压同理，第一预设电压和第二预设电压可以相同也可以不同，本实施例对此不作限定。
可选的，输入预处理模块至少包括第一开关，可以通过第一开关实现对输出第一信号或第二信号的切换，具体的，可以是基于第二控制信号控制第一开关，切换输入预处理模块输出的信号。
对第一开关的控制方法可以如下：
当第二控制信号为第三电平时，控制第一开关将负端输入电压从输入预处理模块的负端接入模数转换模块；将正端输入电压从输入预处理模块的正端接入模数转换模块；
当第二控制信号为第四电平时，控制第一开关将第一预设电压从输入预处理模块的负端接入模数转换模块；将正端输入电压从输入预处理模块的正端接入模数转换模块。
具体的，如图13、14所示的采样期间开关状态，以输入预处理模块的正负端均包括开关为例，其中，正端的开关用于将正端输入电压接入模数转换模块；负端的开关用于将负端输入电压或第一预设电压接入模数转换模块。负端的开关与上述第一开关相对应。
第一控制信号控制输入预处理模块的输出电压模式的一种具体实施方式如下：
当第二控制信号为第三电平时，可以将正端的开关的一端用于接收正端输入电压，另一端与模数转换模块连接；将负端的开关的一端用于接收负端输入电压，另一端与模数转换模块连接。此时，输出电压模式为差分模式，VIN+＝VINP，VIN-＝VINN，输入预处理模块输出差分信号对应的第一信号，并将VINP输入数模转换模块的正端，将VINN输入数模转换模块的负端。
当第二控制信号为第四电平时，可以将正端的开关的一端用于接收正端输入电压，另一端与模数转换模块连接；将负端的开关的一端用于接收第一预设电压，另一端与模数转换模块连接。此时，输出电压模式为单端模式，VIN+＝VINP，VIN-＝第一预设电压，输入预处理模块输出单端信号对应的第二信号，并将VINP输入数模转换模块的正端，将第一预设电压输入数模转换模块的负端。
可选的，模数转换模块可以包括数模转换模块、比较模块和逻辑模块，数模转换模块用于采样保持和量化。模数转换模块可以对输入的模拟信号进行采样和转换，以便输出对应的数字信号。
采样期间，不管是差分模式还是单端模式，数模转换模块都可以对输入预处理模块输 出的信号进行采样，不需要修改数模转换模块的电路结构。
转换期间，对于上述步骤1001，当第一控制信号为第一电平时，对模数转换模块的控制方法可以如下：控制数模转换模块执行第一信号对应的第一工作模式；基于逻辑模块，输出第一信号对应的第一数字信号。当第一控制信号为第二电平时，对模数转换模块的控制方法可以如下：控制数模转换模块执行第二信号对应的第二工作模式；基于逻辑模块，输出第二信号对应的第二数字信号。
可选的，数模转换模块可以包括正端数模转换模块和负端数模转换模块，正端数模转换模块和第二开关相适配，负端数模转换模块和第三开关相适配。通过第二开关和第三开关，可以实现对数模转换模块的工作模式的切换。
控制方法如下：当第一控制信号为第一电平时，控制第二开关和第三开关适配第一工作模式；当第一控制信号为第二电平时，控制第二开关适配第二工作模式，控制第三开关将第二预设电压接入负端数模转换模块。
在一种可能的实施方式中，如图15、16所示的转换期间开关状态，当第一控制信号为第一电平时，可以基于逐次逼近搜索逻辑模块，分别控制数字模拟转换差分电容阵列的每个开关。此时，数字模拟转换差分电容阵列的正负端电容阵列同时受逐次逼近搜索逻辑模块控制。
当第一控制信号为第二电平时，基于逐次逼近搜索逻辑模块，控制数字模拟转换差分电容阵列的正端电容阵列的每个开关；将数字模拟转换差分电容阵列的负端电容阵列的每个开关，一端接收第二预设电压，另一端与负端电容连接。此时，只有数字模拟转换差分电容阵列的正端电容阵列受逐次逼近搜索逻辑模块控制，负端电容阵列固定接入上述第二预设电压，也即是正端参考电压VREFN、负端参考电压VREFP或者其它固定电压值。
可选的，第二预设电压可以与接入输入预处理模块的第一预设电压之间的差值不大于差值阈值。其中，差值阈值可以等于(VREFN+VREFP)/2。在一种优选的实施方式中，第二预设电压与第一预设电压相等。
在另一种可能的实施方式中，当第二预设电压与第一预设电压不相等时，可以基于电压差值对ADC电路输出的数字信号进行处理。具体的，可以是将第二预设电压与第一预设电压相减，得到电压差值；基于ADC电路中模数转换的原理，将电压差值转换成差异码值；将ADC电路输出的数字信号码值与差异码值相减，得到最终的数字信号码值。
示例性的，当ADC电路处理单端信号时，若第一预设电压为0V，第二预设电压为1/2*VREFP，则电压差值可以采用如下公式得到：电压差值＝第二预设电压-第一预设电压＝1/2*VREFP。对电压差值采用如下公式转换为差异码值：差异码值＝电压差值/VREFP*2^N＝2^(N-1)。对数字信号码值采用如下公式，计算最终的数字信号码值：最终的数字信号 码值＝数字信号码值-差异码值。
当ADC电路处理差分信号时，若第一预设电压为0V，第二预设电压为1/2*VREFP，则电压差值可以采用如下公式得到：电压差值＝第二预设电压-第一预设电压＝1/2*VREFP。对电压差值采用如下公式转换为差异码值：差异码值＝电压差值/VREFP*2^(N-1)＝2^(N-2)。对数字信号码值采用如下公式，计算最终的数字信号码值：最终的数字信号码值＝数字信号码值-差异码值。
其中，N为ADC电路的位数，差异码值可正可负。此外，上述转换差异码值的处理可以在电路中处理，也可以在使用过程中通过软件处理，本实施例对此不作限定。
在一种优选的实施方式中，上述步骤1002的失配码可以由模数转换模块中的逻辑模块计算得到，具体处理如下：在校准期间，复用逻辑模块对数模转换模块的误差电压进行量化，得到失配码。如图9所示的SAR ADC电路，在校准误差阶段，可以复用模数转换模块中已有的逐次逼近搜索逻辑模块，SAR逻辑控制信号通过控制校准控制模块，来控制校准差分电容阵列，进行量化数字模拟转换差分电容阵列的失调和电容失配的误差电压大小，并将得到的失配码传输至校准算法模块，并由校准算法模块存储失配码。
可选的，ADC电路还可以包括复位开关，复位开关可以用于将偏置电压接入数模转换模块。
在一种可能的实施方式中，如图13、14所示，在采样期间，可以将复位开关SWCM1/2闭合，使得数字模拟转换差分电容阵列中电容的一个极板复位至偏置电压VCM。此外，如图15、16所示，在转换期间，可以将复位开关SWCM1/2断开。
本申请实施例可以获得如下有益效果：
(1)通过第一控制信号，ADC电路可以实现对两种不同的工作模式的连续校准，不需要重新启动ADC电路来对不同的工作模式进行配置。
(2)通过本申请提供的ADC电路以及相应的时序控制，在实现对差分模式和单端模式的连续校准的基础上，还可以实现连续切换。
(3)在校准误差阶段，通过复用逻辑模块实现量化误差电压，不需要额外添加另一逻辑模块，优化了校准模块的逻辑复杂度，并且可以减小ADC电路的面积。
本申请示例性实施例还提供一种芯片，包括本申请实施例提供的ADC电路。
本申请示例性实施例还提供一种电子设备，包括：本申请实施例提供的ADC电路；至少一个处理器；以及与至少一个处理器通信连接的存储器。存储器存储有能够被至少一个处理器执行的计算机程序，计算机程序在被至少一个处理器执行时用于使电子设备执行根据本申请实施例的方法。
本申请示例性实施例还提供一种存储有计算机程序的非瞬时计算机可读存储介质，其中，计算机程序在被计算机的处理器执行时用于使计算机执行根据本申请实施例的方法。
参考图17，现将描述可以作为本申请的电子设备1700的结构框图，其是可以应用于本申请的各方面的硬件设备的示例。电子设备旨在表示各种形式的数字电子的计算机设备，诸如，数据中心服务器、笔记本电脑、瘦客户机、膝上型计算机、台式计算机、工作站、个人数字助理、刀片式服务器、大型计算机、和其它适合的计算机。电子设备还可以表示各种形式的移动装置，诸如，个人数字处理、蜂窝电话、智能电话、可穿戴设备和其它类似的计算装置。本文所示的部件、它们的连接和关系、以及它们的功能仅仅作为示例，并且不意在限制本文中描述的和/或者要求的本申请的实现。
如图17所示，电子设备1700包括计算单元1701，其可以根据存储在只读存储器(ROM)1702中的计算机程序或者从存储单元1708加载到随机访问存储器(RAM)1703中的计算机程序，来执行各种适当的动作和处理。在RAM 1703中，还可存储设备1700操作所需的各种程序和数据。计算单元1701、ROM 1702以及RAM 1703通过总线1704彼此相连。输入/输出(I/O)接口1705也连接至总线1704。
电子设备1700中的多个部件连接至I/O接口1705，包括：输入单元1706、输出单元1707、存储单元1708以及通信单元1709。输入单元1706可以是能向电子设备1700输入信息的任何类型的设备，输入单元1706可以接收输入的数字或字符信息，以及产生与电子设备的用户设置和/或功能控制有关的键信号输入。输出单元1707可以是能呈现信息的任何类型的设备，并且可以包括但不限于显示器、扬声器、视频/音频输出终端、振动器和/或打印机。存储单元1704可以包括但不限于磁盘、光盘。通信单元1709允许电子设备1700通过诸如因特网的计算机网络和/或各种电信网络与其他设备交换信息/数据，并且可以包括但不限于调制解调器、网卡、红外通信设备、无线通信收发机和/或芯片组，例如蓝牙设备、WiFi设备、WiMax设备、蜂窝通信设备和/或类似物。
计算单元1701可以是各种具有处理和计算能力的通用和/或专用处理组件。计算单元1701的一些示例包括但不限于中央处理单元(CPU)、图形处理单元(GPU)、各种专用的人工智能(AI)计算芯片、各种运行机器学习模型算法的计算单元、数字信号处理器(DSP)、以及任何适当的处理器、控制器、微控制器等。计算单元1701执行上文所描述的各个方法和处理。例如，在一些实施例中，ADC电路的控制方法可被实现为计算机软件程序，其被有形地包含于机器可读介质，例如存储单元1708。在一些实施例中，计算机程序的部分或者全部可以经由ROM 1702和/或通信单元1709而被载入和/或安装到电子设备1700上。在一些实施例中，计算单元1701可以通过其他任何适当的方式(例如，借助于固件)而被配置为执行ADC电路的控制方法。
用于实施本申请的方法的程序代码可以采用一个或多个编程语言的任何组合来编写。这些程序代码可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理器或控制器，使得程序代码当由处理器或控制器执行时使流程图和/或框图中所规定的功能/操作被实施。程序代码可以完全在机器上执行、部分地在机器上执行，作为独立软件包部分地在机器上执行且部分地在远程机器上执行或完全在远程机器或服务器上执行。
在本申请的上下文中，机器可读介质可以是有形的介质，其可以包含或存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的程序。机器可读介质可以是机器可读信号介质或机器可读储存介质。机器可读介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。机器可读存储介质的更具体示例会包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或快闪存储器)、光纤、便捷式紧凑盘只读存储器(CD-ROM)、光学储存设备、磁储存设备、或上述内容的任何合适组合。
如本申请使用的，术语“机器可读介质”和“计算机可读介质”指的是用于将机器指令和/或数据提供给可编程处理器的任何计算机程序产品、设备、和/或装置(例如，磁盘、光盘、存储器、可编程逻辑装置(PLD))，包括，接收作为机器可读信号的机器指令的机器可读介质。术语“机器可读信号”指的是用于将机器指令和/或数据提供给可编程处理器的任何信号。
为了提供与用户的交互，可以在计算机上实施此处描述的系统和技术，该计算机具有：用于向用户显示信息的显示装置(例如，CRT(阴极射线管)或者LCD(液晶显示器)监视器)；以及键盘和指向装置(例如，鼠标或者轨迹球)，用户可以通过该键盘和该指向装置来将输入提供给计算机。其它种类的装置还可以用于提供与用户的交互；例如，提供给用户的反馈可以是任何形式的传感反馈(例如，视觉反馈、听觉反馈、或者触觉反馈)；并且可以用任何形式(包括声输入、语音输入或者、触觉输入)来接收来自用户的输入。
可以将此处描述的系统和技术实施在包括后台部件的计算系统(例如，作为数据服务器)、或者包括中间件部件的计算系统(例如，应用服务器)、或者包括前端部件的计算系统(例如，具有图形用户界面或者网络浏览器的用户计算机，用户可以通过该图形用户界面或者该网络浏览器来与此处描述的系统和技术的实施方式交互)、或者包括这种后台部件、中间件部件、或者前端部件的任何组合的计算系统中。可以通过任何形式或者介质的数字数据通信(例如，通信网络)来将系统的部件相互连接。通信网络的示例包括：局域网(LAN)、广域网(WAN)和互联网。
计算机系统可以包括客户端和服务器。客户端和服务器一般远离彼此并且通常通过通 信网络进行交互。通过在相应的计算机上运行并且彼此具有客户端-服务器关系的计算机程序来产生客户端和服务器的关系。

Claims (17)

  1. 一种模拟数字转换器ADC电路，所述ADC电路至少包括：模数转换模块，校准模块；
    所述模数转换模块，被配置为在转换期间，当第一控制信号为第一电平时，基于采样的第一信号输出对应的第一数字信号，当所述第一控制信号为第二电平时，基于采样的第二信号输出对应的第二数字信号；
    所述校准模块与所述模数转换模块连接，被配置为基于校准期间得到的失配码确定校准码，对所述模数转换模块进行校准码回补；
    其中，所述第一控制信号在采样期间进行电平切换。
  2. 根据权利要求1所述的ADC电路，其中，所述校准模块包括校准数模转换模块，校准算法模块，校准控制模块；
    所述校准算法模块的输入端与所述模数转换模块连接，输出端与所述校准控制模块连接，被配置为当所述第一控制信号为所述第一电平时，基于所述失配码确定所述第一信号对应的第一校准码；当所述第一控制信号为所述第二电平时，基于所述失配码确定所述第二信号对应的第二校准码；
    所述校准控制模块，被配置为在所述转换期间，将所述校准算法模块当前输出的校准码传输至所述校准数模转换模块；
    所述校准数模转换模块，被配置为在所述转换期间，基于当前接收的校准码对所述数模转换模块进行电压回补。
  3. 根据权利要求2所述的ADC电路，其中，所述校准算法模块，还被配置为存储所述失配码。
  4. 根据权利要求2所述的ADC电路，其中，所述校准控制模块，还被配置为在所述采样期间，将校准码设置为预设的中间校准码，将所述中间校准码传输至所述校准数模转换模块。
  5. 根据权利要求1所述的ADC电路，其中，所述ADC电路还包括输入预处理模块，所述输入预处理模块的输出端与所述模数转换模块的输入端连接；
    所述输入预处理模块用于接收输入信号，被配置为当第二控制信号为与所述第一电平相匹配的第三电平时，基于所述输入信号输出所述第一信号；当所述第二控制信号为与所述第二电平相匹配的第四电平时，基于所述输入信号输出所述第二信号；
    其中，所述第二控制信号在所述转换期间进行电平切换。
  6. 根据权利要求5所述的ADC电路，其中，所述模数转换模块包括数模转换模块、比 较模块和逻辑模块，所述数模转换模块用于采样保持和量化；
    所述数模转换模块与所述输入预处理模块连接，被配置为在所述转换期间，当所述第一控制信号为所述第一电平时，执行所述第一信号对应的第一工作模式；当所述第一控制信号为所述第二电平时，执行所述第二信号对应的第二工作模式；
    所述比较模块的输入端与所述数模转换模块连接，输出端与所述逻辑模块连接；
    所述逻辑模块，被配置为输出所述输入信号对应的数字信号。
  7. 根据权利要求6所述的ADC电路，其中，所述逻辑模块，还被配置为在校准期间，对数模转换模块的误差电压进行量化，得到失配码。
  8. 一种ADC电路的控制方法，所述ADC电路至少包括：模数转换模块、校准模块，所述方法包括：
    在转换期间，当第一控制信号为第一电平时，基于采样的第一信号输出对应的第一数字信号，当所述第一控制信号为第二电平时，基于采样的第二信号输出对应的第二数字信号；
    在所述转换期间，通过所述校准模块，基于校准期间得到的失配码确定校准码，对所述模数转换模块进行校准码回补；
    其中，所述第一控制信号在采样期间进行电平切换。
  9. 根据权利要求8所述的ADC电路的控制方法，其中，所述校准模块包括校准数模转换模块，校准算法模块，校准控制模块；
    所述通过所述校准模块，基于校准期间得到的失配码确定校准码，对所述模数转换模块进行校准码回补，包括：
    当所述第一控制信号为所述第一电平时，通过所述校准算法模块，基于所述失配码确定所述第一信号对应的第一校准码；当所述第一控制信号为所述第二电平时，通过所述校准算法模块，基于所述失配码确定所述第二信号对应的第二校准码；
    将所述校准算法模块当前输出的校准码传输至所述校准数模转换模块；
    基于所述校准数模转换模块，根据当前接收的校准码对所述模数转换模块进行电压回补。
  10. 根据权利要求8所述的ADC电路的控制方法，其中，所述方法还包括：
    基于所述校准算法模块存储所述失配码。
  11. 根据权利要求8所述的ADC电路的控制方法，其中，所述方法还包括：
    在所述采样期间，将所述校准数模转换模块的电压设置为预设的中间校准码。
  12. 根据权利要求8所述的ADC电路，其中，所述ADC电路还包括输入预处理模块，所述方法还包括：
    接收输入信号；
    当第二控制信号为与所述第一电平相匹配的第三电平时，通过所述输入预处理模块，基于所述输入信号获取第一信号；
    当所述第二控制信号为与所述第二电平相匹配的第四电平时，通过所述输入预处理模块，基于所述输入信号获取第二信号；
    其中，所述第二控制信号在所述转换期间进行电平切换。
  13. 根据权利要求12所述的ADC电路的控制方法，其中，所述模数转换模块包括数模转换模块、比较模块和逻辑模块，所述数模转换模块用于采样保持和量化；
    所述基于采样的第一信号输出对应的第一数字信号，包括：控制所述数模转换模块执行所述第一信号对应的第一工作模式；基于所述逻辑模块，输出所述第一信号对应的第一数字信号；
    所述基于采样的第二信号输出对应的第二数字信号，包括：控制所述数模转换模块执行所述第二信号对应的第二工作模式；基于所述逻辑模块，输出所述第二信号对应的第二数字信号。
  14. 根据权利要求13所述的ADC电路的控制方法，其中，所述方法还包括：
    在校准期间，复用所述逻辑模块对数模转换模块的误差电压进行量化，得到失配码。
  15. 一种芯片，包括如权利要求1-7中任一项所述的ADC电路。
  16. 一种电子设备，包括：
    权利要求1-7中任一所述的ADC电路；
    处理器；以及
    存储程序的存储器，
    其中，所述程序包括指令，所述指令在由所述处理器执行时使所述处理器执行根据权利要求8-14中任一项所述的方法。
  17. 一种存储有计算机指令的非瞬时计算机可读存储介质，其中，所述计算机指令用于使计算机执行根据权利要求8-14中任一项所述的方法。
PCT/CN2023/075318 2022-02-10 2023-02-10 一种adc电路及其控制方法 WO2023151632A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210124222.9A CN114499520A (zh) 2022-02-10 2022-02-10 一种adc电路及其控制方法
CN202210124222.9 2022-02-10

Publications (1)

Publication Number Publication Date
WO2023151632A1 true WO2023151632A1 (zh) 2023-08-17

Family

ID=81479393

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/075318 WO2023151632A1 (zh) 2022-02-10 2023-02-10 一种adc电路及其控制方法

Country Status (2)

Country Link
CN (1) CN114499520A (zh)
WO (1) WO2023151632A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114448436A (zh) * 2022-02-10 2022-05-06 芯海科技（深圳）股份有限公司 一种adc电路及其控制方法
CN114499520A (zh) * 2022-02-10 2022-05-13 芯海科技（深圳）股份有限公司 一种adc电路及其控制方法
CN114978172A (zh) * 2022-06-21 2022-08-30 西安芯海微电子科技有限公司 一种模数转换电路、控制方法、芯片及电子设备
CN116401199B (zh) * 2023-06-09 2024-03-05 珠海智融科技股份有限公司 信号转换电路、发送方法、装置、电子设备和存储介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130214946A1 (en) * 2012-02-16 2013-08-22 Renesas Electronics Corporation A/D Converter and Method for Calibrating the Same
CN106374930A (zh) * 2016-09-28 2017-02-01 东南大学 基于数字域自校正的逐次逼近模数转换器及模数转换方法
CN110995264A (zh) * 2019-12-26 2020-04-10 上海贝岭股份有限公司 Cdac的电容失配的校准系统和逐次逼近型adc
CN114401006A (zh) * 2022-01-07 2022-04-26 灿芯半导体(上海)股份有限公司 一种逐次逼近型adc的电容校准方法
CN114448436A (zh) * 2022-02-10 2022-05-06 芯海科技（深圳）股份有限公司 一种adc电路及其控制方法
CN114499520A (zh) * 2022-02-10 2022-05-13 芯海科技（深圳）股份有限公司 一种adc电路及其控制方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9369146B2 (en) * 2012-12-31 2016-06-14 Silicon Laboratories Inc. Successive approximation register analog-to-digital converter with single-ended measurement
CN112838866B (zh) * 2019-11-22 2023-08-04 北京钛方科技有限责任公司 校准逻辑控制电路及方法、逐次逼近型模数转换器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130214946A1 (en) * 2012-02-16 2013-08-22 Renesas Electronics Corporation A/D Converter and Method for Calibrating the Same
CN106374930A (zh) * 2016-09-28 2017-02-01 东南大学 基于数字域自校正的逐次逼近模数转换器及模数转换方法
CN110995264A (zh) * 2019-12-26 2020-04-10 上海贝岭股份有限公司 Cdac的电容失配的校准系统和逐次逼近型adc
CN114401006A (zh) * 2022-01-07 2022-04-26 灿芯半导体(上海)股份有限公司 一种逐次逼近型adc的电容校准方法
CN114448436A (zh) * 2022-02-10 2022-05-06 芯海科技（深圳）股份有限公司 一种adc电路及其控制方法
CN114499520A (zh) * 2022-02-10 2022-05-13 芯海科技（深圳）股份有限公司 一种adc电路及其控制方法

Also Published As

Publication number Publication date
CN114499520A (zh) 2022-05-13

Similar Documents

Publication Publication Date Title
WO2023151632A1 (zh) 一种adc电路及其控制方法
WO2023151633A1 (zh) 一种adc电路及其控制方法
US9647676B2 (en) Method and apparatus for reducing SAR input loading
US9621179B1 (en) Metastability error reduction in asynchronous successive approximation analog to digital converter
CN106374930A (zh) 基于数字域自校正的逐次逼近模数转换器及模数转换方法
KR20170010515A (ko) 적분기 및 sar adc를 포함하는 반도체 장치
KR20060052937A (ko) 공간 효율적 저전력 주기적 ａ／ｄ 변환기
TW201306493A (zh) 模數轉換器及模數轉換方法
WO2021061885A1 (en) Enhancing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters
CN101854174A (zh) 一种流水线型模数转换器及其子转换级电路
WO2023088280A1 (zh) 意图识别方法、装置、可读介质及电子设备
TW202306324A (zh) 訊號轉換裝置、動態元件匹配電路與動態元件匹配方法
CN111934689A (zh) 一种高精度模数转换器及转换方法
US7675450B1 (en) Digital-to-analog converter (DAC) for high frequency and high resolution environments
US20050270296A1 (en) Video card
CN111034052A (zh) 用于在不具有附加有源电路的sar adc中启用宽输入共模范围的方法和装置
CN113364460B (zh) 用于超高速时域交织adc的快速收敛时钟偏差校准方法
TW202023204A (zh) 連續逼近式類比數位轉換器及其操作方法
KR101878593B1 (ko) 아날로그 디지털 변환기 및 그 동작 방법
CN105406868A (zh) 用于模/数转换的自适应计时
US8547258B2 (en) Compressive sense based reconstruction in the presence of frequency offset
CN116996068A (zh) 用于高精度模数转换器的增益和失调误差校准电路
WO2019113772A1 (zh) 用于模数转换的方法和模数转换器
US10200052B2 (en) Analog-to-digital converter
US11711094B2 (en) Algorithm for high speed SAR ADC

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23752411

Country of ref document: EP

Kind code of ref document: A1