WO2023142575A1 - 一种电源开关电路和一次性可编程存储器 - Google Patents

一种电源开关电路和一次性可编程存储器 Download PDF

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Publication number
WO2023142575A1
WO2023142575A1 PCT/CN2022/129203 CN2022129203W WO2023142575A1 WO 2023142575 A1 WO2023142575 A1 WO 2023142575A1 CN 2022129203 W CN2022129203 W CN 2022129203W WO 2023142575 A1 WO2023142575 A1 WO 2023142575A1
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Prior art keywords
inverter
power switch
coupled
control signal
switch circuit
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PCT/CN2022/129203
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English (en)
French (fr)
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林典鹏
蔡江铮
布明恩
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华为技术有限公司
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Publication of WO2023142575A1 publication Critical patent/WO2023142575A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the embodiments of the present application relate to the circuit field, and in particular to a power switch circuit and a one-time programmable memory.
  • the conventional voltage transistors in EFUSE (for example, CORE transistors) will withstand high IO voltage. Since the operating voltage of CORE transistors is low, if the CORE transistors withstand high IO voltage for a long time, it may affect the device. stability, resulting in misprogramming. Therefore, in order to improve the stability of EFUSE programming, how to constrain the programming time of EFUSE has become an urgent problem to be solved.
  • Embodiments of the present application provide a power switch circuit and a one-time programmable memory, which can reduce the time during which a CORE transistor in a memory cell array is subjected to high voltage, and improve the stability of EFUSE programming.
  • a power switch circuit which is used to provide a programming voltage for the memory cell array in the one-time programmable memory when the one-time programmable memory is programmed, and the power switch circuit includes a first input interface , the first input interface is used to receive a programming control signal, and the programming control signal is used to control whether the one-time programmable memory is in the programming mode; wherein, when the one-time programmable memory is in the programming mode and writing, the output of the power switch circuit The level of the terminal is consistent with the level of the programming control signal.
  • the one-time programmable memory being in programming mode means that the one-time programmable memory is accessible.
  • the one-time programmable memory is in programming mode, data can be read or written in the one-time programmable memory.
  • the one-time programmable memory when the one-time programmable memory is in the programming mode and is being written, it may also be referred to as being programmed in the one-time programmable memory.
  • the level of the output end of the power switch circuit can be consistent with the level of the programming control signal. Therefore, when the one-time programmable memory starts programming (for example, starts writing), the output terminal of the power switch circuit also outputs a programming voltage following the programming control signal. That is to say, the power switch circuit in this solution outputs the programming voltage time can follow the EFUSE programming time, so EFUSE does not need to bear the meaningless PS power-on time, and can reduce the CORE tube in the memory cell array in EFUSE to withstand high voltage Time, improve the stability of EFUSE programming. Moreover, the present application does not restrict the power-on time of the switch control signal PS, and can also reduce the time for the CORE transistor in the memory cell array to withstand high voltage.
  • the power switch circuit includes a first logic circuit and a second logic circuit, the input terminal of the first logic circuit is coupled to the first input interface, and the output terminal of the first logic circuit is coupled to the second The input terminal of the logic circuit, the output terminal of the second logic circuit is the output terminal of the power switch circuit, and the output terminal of the power switch circuit is used for coupling with the memory cell array in the one-time programmable memory.
  • the operating voltage of the first logic circuit is lower than the operating voltage of the second logic circuit.
  • the operating voltage of the first logic circuit may be lower.
  • the operating voltage of the second logic circuit may be higher than that of the first logic circuit.
  • the power switch circuit further includes a second input interface, where the second input interface is used to receive a switch control signal, and the switch control signal is used to control whether the power switch circuit works.
  • the above-mentioned first logic circuit includes I first inverters, first NAND gates and second inverters connected in series, where I is an even number greater than or equal to 2, and the I The input end of the first inverter among the first inverters connected in series is coupled to the second input interface, and the output end of the last inverter among the first inverters connected in series is coupled to the first NAND
  • the first input terminal of the gate, the second input terminal of the first NAND gate is coupled to the first input interface, the output terminal of the first NAND gate is coupled to the input terminal of the second inverter, and the second inverter The output terminal of is the output terminal of the first logic circuit.
  • the power switch circuit can receive switch control signals and programming control signals, and when programming the one-time programmable memory, the time for the power switch circuit to output the programming voltage can follow the programming time of EFUSE, so EFUSE does not need to bear meaningless PS
  • the power-on time can reduce the time that the CORE tube in the memory cell array in the EFUSE is subjected to high voltage, and improve the stability of EFUSE programming.
  • the power switch circuit further includes a third input interface, where the third input interface is used to receive a power control signal, and the power control signal is used to control power on and off of the power switch circuit.
  • the above-mentioned first logic circuit includes a third inverter, a second NAND gate, M fourth inverters connected in series, a third NAND gate, and a fifth inverter M is an odd number greater than or equal to 3; the input terminal of the third inverter is coupled to the third input interface, the output terminal of the third inverter is coupled to the first input terminal of the second NAND gate, and the second NAND
  • the second input terminal of the gate is coupled to the second input interface, the output terminal of the second NAND gate is coupled to the input terminal of the first inverter among the M fourth inverters, and the last one of the M fourth inverters is
  • the output terminal of the inverter is coupled to the first input terminal of the third NAND gate, the second input terminal of the third NAND gate is coupled to the first input interface, and the output terminal of the third NAND gate is coupled to the fifth inverter
  • the input end of the inverter, the output end of the fifth inverter is the output end of the first logic circuit.
  • the power switch circuit can receive the switch control signal, power control signal and programming control signal, and when the one-time programmable memory is programmed, the time for the power switch circuit to output the programming voltage can follow the programming time of EFUSE, so EFUSE does not need to bear
  • the meaningless PS power-on time can reduce the time that the CORE tube in the memory cell array in EFUSE is subjected to high voltage, and improve the stability of EFUSE programming.
  • this solution can independently control the power on and off of the power switch circuit through the power control signal, so that the power switch circuit can be isolated from other external circuits. When the power switch circuit does not need to be powered on, there is no need to power off the external power supply. Affect the normal use of external circuits.
  • the above-mentioned power switch circuit further includes a fourth input interface and a sixth inverter, the fourth input interface is used to receive a read-write control signal, and the read-write control signal is used to Read or write data in the programmable memory, the input end of the sixth inverter is coupled to the fourth input interface, the output end of the sixth inverter is coupled to the third NAND gate the third input terminal.
  • the power switch circuit can receive switch control signals, power control signals, read and write control signals and programming control signals, and when programming the one-time programmable memory, the time for the power switch circuit to output the programming voltage can follow the programming time of EFUSE , so EFUSE does not need to bear meaningless PS power-on time, which can reduce the time for the CORE tube in the memory cell array in EFUSE to withstand high voltage, and improve the stability of EFUSE programming.
  • the second logic circuit includes N seventh inverters connected in series, where N is an even number greater than or equal to 2, and the first of the N seventh inverters connected in series
  • the input terminal of the inverter is the input terminal of the second logic circuit
  • the output terminal of the last inverter among the N seventh inverters connected in series is the output terminal of the second logic circuit.
  • the second logic circuit includes a first metal oxide semiconductor MOS transistor and K eighth inverters connected in series, K is an odd number greater than or equal to 3, and K eighth inverters connected in series
  • K is an odd number greater than or equal to 3
  • K eighth inverters connected in series The input terminal of the first inverter in the eighth inverter is the input terminal of the second logic circuit, and the output terminal of the last inverter in the eighth inverters connected in series is coupled to the gate of the first MOS transistor pole, the source of the first MOS transistor is coupled to the second voltage, and the drain of the first MOS transistor is coupled to the output terminal of the second logic circuit.
  • the second logic circuit further includes a first power control circuit
  • the first power control circuit includes a second MOS transistor and a third MOS transistor
  • the source of the second MOS transistor is coupled to the third voltage
  • the gate of the second MOS transistor is used to receive the first control signal
  • the level of the first control signal is opposite to the level of the switch control signal
  • the drain of the second MOS transistor is coupled to the source of the third MOS transistor
  • the first The gates of the three MOS transistors are used to receive the second control signal
  • the level of the second control signal is consistent with the output level of the output terminal of the first logic circuit
  • the drain of the third MOS transistor is coupled to the output of the second logic circuit end.
  • the voltage of the output terminal VQR of the power switch circuit is VDD
  • the voltage of the output terminal VQR of the power switch circuit is VQPS. That is, in this solution, the output voltage of the output terminal VQR of the power switch circuit in the non-programming state is maintained at VDD instead of zero voltage. Therefore, when the power switch circuit switches to the programming state, the voltage amplitude of the output terminal VQR of the power switch circuit changes from VDD to VQPS instead of changing from 0 to VQPS, so that the voltage range of the output terminal VQR of the power switch circuit varies greatly. Reduced, so that the instantaneous current pulse of the power switch circuit can be reduced, and the circuit risk and power consumption can be reduced.
  • the above-mentioned second logic circuit further includes a second power control circuit
  • the second power control circuit includes a fourth MOS transistor and a fifth MOS transistor
  • the gate of the fourth MOS transistor is coupled to the first The gate of the MOS transistor
  • the drain of the fourth MOS transistor is coupled to the output terminal of the second logic circuit
  • the source of the fourth MOS transistor is coupled to the drain of the fifth MOS transistor
  • the gate of the fifth MOS transistor is used to receive A switch control signal
  • the source of the fifth MOS transistor is coupled to the third voltage.
  • the voltage amplitude of the output terminal VQR of the power switch circuit changes from VDD to VQPS instead of changing from 0 to VQPS, so that the voltage range of the output terminal VQR of the power switch circuit varies greatly Reduced, so that the instantaneous current pulse of the power switch circuit can be reduced, and the circuit risk and power consumption can be reduced.
  • the operating voltage of the inverter in the first logic circuit is the first voltage
  • the operating voltage of the inverter in the second logic circuit is the second voltage
  • the first voltage is lower than at the second voltage
  • the second aspect of the embodiments of the present application provides a one-time programmable memory
  • the one-time programmable memory includes a memory cell array
  • the power switch circuit described in any implementation manner of the first aspect above the power supply
  • the output terminal of the switch circuit is coupled to the memory cell array.
  • the one-time programmable memory may be EFUSE.
  • FIG. 1 is a schematic structural diagram of a one-time programmable memory provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of a circuit structure of a power switch circuit provided in an embodiment of the present application
  • FIG. 3 is a schematic diagram of a signal timing sequence of a power switch circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the circuit structure of another power switch circuit provided by the embodiment of the present application.
  • FIG. 5 is a schematic diagram of signal timing of another power switch circuit provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of the circuit structure of another power switch circuit provided by the embodiment of the present application.
  • FIG. 7 is a schematic circuit structure diagram of another power switch circuit provided by the embodiment of the present application.
  • FIG. 8 is a schematic circuit structure diagram of another power switch circuit provided by the embodiment of the present application.
  • FIG. 9 is a schematic circuit structure diagram of another power switch circuit provided by the embodiment of the present application.
  • FIG. 10 is a schematic circuit structure diagram of another power switch circuit provided by the embodiment of the present application.
  • FIG. 11 is a schematic diagram of an instantaneous current pulse of a power switch circuit provided by an embodiment of the present application.
  • At least one item (piece) of a, b or c can represent: a, b, c, a and b, a and c, b and c, or, a and b and c, wherein a, b and c can be single or multiple.
  • words such as “first” and “second” are used to distinguish the same or similar items with basically the same function and effect, Those skilled in the art can understand that words such as “first” and “second” do not limit the quantity and execution order.
  • first in the first inverter and “second” in the third inverter in the embodiment of the present application are only used to distinguish different inverters.
  • the first, second, etc. descriptions that appear in the embodiments of this application are only for illustration and to distinguish the description objects, and there is no order, nor does it represent a special limitation on the number of devices in the embodiments of this application, and cannot constitute a limitation on the number of devices in this application. Any limitations of the examples.
  • CMOS complementary metal oxide semiconductor
  • the CMOS inverter consists of a PMOS transistor and an NMOS transistor, the gate of the PMOS transistor is coupled to the gate of the NMOS transistor, the source of the PMOS transistor is coupled to the power supply, and the drain of the PMOS transistor is coupled to the drain of the NMOS transistor.
  • the source level of the NMOS transistor is grounded (VSS in the drawings of the embodiment of the present application may be a ground terminal).
  • the gate of the PMOS transistor is the input end of the CMOS inverter, and the drain of the PMOS transistor is the output end of the CMOS inverter.
  • the PMOS transistor When the input terminal of the inverter inputs a high level, the PMOS transistor is turned off, the NMOS transistor is turned on, and the output terminal of the CMOS inverter outputs a low level.
  • the PMOS transistor When the input terminal of the inverter inputs a low level, the PMOS transistor is turned on, the NMOS transistor is turned off, and the output terminal of the CMOS inverter outputs a high level.
  • FIG. 1 is a schematic diagram of the architecture of a one-time programmable memory EFUSE provided by the embodiment of the present application.
  • the EFUSE includes a logic power supply voltage controller, a power switch (Powerswitch) circuit, a row decoding circuit, and a memory cell array , signal control circuit, column decoding circuit and sense amplifier.
  • Powerswitch Powerswitch
  • the input terminal of the logic supply voltage controller is used to receive the logic supply voltage
  • the input terminal of the power switch circuit is used to receive the programming voltage.
  • the programming voltage VQPS can be transmitted to the Bitcell in the memory cell array through the control terminal of the power switch circuit for programming.
  • Fig. 2 is a schematic circuit structure diagram of a power switch circuit, as shown in Fig. 2, the power switch circuit includes an inverter 20, a NAND gate 21, an inverter 22, an inverter 23, an inverter 24, and Inverter 25 to Inverter 28 .
  • the input terminal of the inverter 20 is used to receive the power control signal PD (PowerDown)
  • the output terminal of the inverter 20 is coupled to the first input terminal of the NAND gate 21, and the second input terminal of the NAND gate 21 is used for The switch control signal PS is received.
  • the output terminal of the NAND gate 21 is coupled to the input terminal of the inverter 22, and the inverter 22 to the inverter 28 are sequentially connected in series.
  • the output terminal of the inverter 28 is the output terminal VQR of the power switch circuit, and the output terminal of the power switch circuit can be coupled with the memory cell array in the EFUSE.
  • the power control signal PD is used to control power on and off of the power switch circuit. For example, when the power switch circuit is powered on, the power control signal PD is at low level, and when the power switch circuit is powered off, the power control signal PD is at high level.
  • the switch control signal PS is used to control whether the power switch circuit works. For example, when the power switch circuit is working, the switch control signal PS is at high level, and when the power switch circuit is not working, the switch control signal PS is at low level.
  • the inverter in FIG. 2 may be a CMOS inverter.
  • the operating voltage of the inverter 20 , the inverter 22 to the inverter 24 in FIG. 2 is VDD
  • the operating voltage of the inverter 25 to the inverter 28 is VQPS
  • VDD is smaller than VQPS.
  • the working voltage of the inverter 20 , the inverter 22 to the inverter 24 is 0.9V
  • the working voltage of the inverter 25 to the inverter 28 is 1.8V.
  • the power control signal PD when the power switch circuit starts to work, the power control signal PD is low level 0, the inverter 20 outputs high level, the switch control signal PS is high level, and the NAND gate 21 outputs low level , after inverting in sequence from the inverter 22 to the inverter 28, the output terminal VQR of the power switch circuit outputs a high level.
  • the programming voltage VQPS is transmitted to the memory cell array of EFUSE (not shown in FIG. 2 ), and the CORE transistor in the memory cell array will bear the programming voltage VQPS.
  • the operating voltage of the CORE transistor in the memory cell array is low (for example, the operating voltage of the CORE transistor is about 0.9V), and the programming voltage VQPS is relatively high (for example, the voltage of VQPS is about 1.8V), if the CORE transistor Sustaining high voltage for a long time will affect the stability of the device, and there may be problems of misprogramming or misprogramming.
  • the cumulative power-on time of the switch control signal PS can be constrained (for example, the cumulative power-on time of the switch control signal PS does not exceed 0.2s).
  • the actual programming time of EFUSE and the power-on time of the switch control signal PS may not match, causing the power-on time of the switch control signal PS to be much longer than the actual programming time, resulting in the accumulation of the switch control signal PS Power time exceeds constraint time.
  • the CORE transistor in the memory cell array will have a stability problem.
  • the switch control signal PS when the switch control signal PS changes from low level to high level, the power switch circuit starts to work.
  • the programming control signal STR STROBE
  • EFUSE starts programming. Since the switch control signal PS is powered on and EFUSE starts programming, there is a period of time interval, which includes the setup time of the switch control signal PS, the addressing time of the row and column decoding circuit, and the like. Therefore, when multiple EFUSEs are used, the non-programmed EFUSE needs to bear the meaningless PS power-on time, causing the PS power-on time to be much longer than the actual programming time, resulting in the cumulative power-on time of the switch control signal PS exceeding the constraint time. It will affect the stability of the device and misprogramming may occur.
  • the embodiment of the present application provides a power switch circuit, the time of output programming voltage of the power switch circuit can follow the programming time of EFUSE, thereby reducing the time for the CORE tube in the memory cell array to withstand high voltage , can improve the stability of EFUSE programming. Moreover, when the power switch circuit is switched to the programming state, by reducing the voltage range of the output terminal of the power switch circuit, the instantaneous current pulse of the power switch circuit can be reduced, and the circuit risk and power consumption can be reduced.
  • An embodiment of the present application provides a power switch circuit, which is used to provide a programming voltage for the memory cell array in the one-time programmable memory when the one-time programmable memory is programmed, and the power switch circuit includes a first input interface , the first input interface is used to receive a programming control signal STR, and the programming control signal STR is used to control whether the one-time programmable memory is in a programming mode.
  • the level of the output terminal VQR of the power switch circuit is consistent with the level of the programming control signal STR.
  • the one-time programmable memory being in programming mode means that the one-time programmable memory is accessible.
  • the one-time programmable memory is in programming mode, data can be read or written in the one-time programmable memory.
  • the one-time programmable memory when the one-time programmable memory is in the programming mode and is being written, it may also be called when the one-time programmable memory is programmed.
  • Fig. 4 is a schematic diagram of a power switch circuit provided by the embodiment of the present application.
  • the power switch circuit further includes a first logic circuit and a second logic circuit, and the input terminal of the first logic circuit is coupled to the first input interface, the output end of the first logic circuit is coupled to the input end of the second logic circuit, the output end of the second logic circuit is the output end VQR of the power switch circuit, and the output end VQR of the power switch circuit is used to communicate with the one-time programmable memory The memory cell array in the coupling.
  • the operating voltage of the first logic circuit is lower than the operating voltage of the second logic circuit.
  • the operating voltage of the first logic circuit may be lower.
  • the operating voltage of the second logic circuit may be higher than that of the first logic circuit.
  • EFUSE when the program control signal STR changes from low level to high level, EFUSE starts programming. When the programming control signal STR changes from high level to low level, EFUSE stops programming. That is, the programming control signal STR is used to control whether the EFUSE is programmed. When the EFUSE is programmed, the programming control signal STR is at a high level; when the EFUSE is not programmed, the programming control signal STR is at a low level. In some other examples, the programming control signal STR can be used to control whether the EFUSE is programmed or not, and can also be used to control whether the EFUSE reads data.
  • the power switch circuit in the embodiment of the present application introduces the programming control signal STR, and when the one-time programmable memory is programmed, the level of the output terminal VQR of the power switch circuit can be consistent with the level of the programming control signal. That is, when the programming control signal STR changes from low level to high level and EFUSE starts programming, the output terminal VQR of the power switch circuit also follows the programming control signal STR to output the programming voltage. Therefore, in the power switch circuit provided by the embodiment of the present application, the time for the power switch circuit to output the programming voltage can follow the programming time of EFUSE, so EFUSE does not need to bear the meaningless PS power-on time, and can reduce the number of CORE transistors in the memory cell array. Under high pressure time, improve the stability of EFUSE programming.
  • the above-mentioned power switch circuit further includes a second input interface, the second input interface is used for receiving the switch control signal PS, and the switch control signal PS is used for controlling whether the power switch circuit works.
  • the switch control signal PS is at high level
  • the switch control signal PS is at low level.
  • the time for the power switch circuit to output the programming voltage (VQR shown by the dotted line in FIG. 5 ) can follow the programming time of EFUSE.
  • the non-programmed EFUSE needs to endure the meaningless PS power-on time, so the time for the power switch circuit to output the programming voltage (VQR shown by the dotted line in Figure 5) is longer than the actual programming time Much more time.
  • the first logic circuit in the power switch circuit can include three kinds of circuit structures
  • the second logic circuit in the power switch circuit can also include three kinds of circuit structures
  • any circuit structure that the first logic circuit includes and the second logic circuit includes Any of the circuit structures can be combined into a power switch circuit. That is to say, the circuit switch circuit provided in the embodiment of the present application includes at least 9 different circuit structures.
  • the circuit structures of the first logic circuit and the second logic circuit are introduced respectively below. It should be noted that the following embodiments exemplarily introduce specific circuit structures of some power switch circuits.
  • the first circuit structure of the first logic circuit includes a first inverter, a first NAND gate and a second inverter connected in series, and I is an even number greater than or equal to 2, and I is connected in series
  • the input terminal of the first inverter in the connected first inverters is coupled to the second input interface, and the output terminal of the last inverter in the first inverters connected in series is coupled to the first NAND gate
  • the first input terminal of the first NAND gate, the second input terminal of the first NAND gate is coupled to the first input interface, the output terminal of the first NAND gate is coupled to the input terminal of the second inverter, and the output terminal of the second inverter is the output terminal of the first logic circuit.
  • the specific number of the first inverters included in the first logic circuit is related to parameters such as the storage capacity of the EFUSE. For example, if the storage capacity of EFUSE is large, the output terminal VQR of the power switch circuit has a large load, which requires the power switch circuit to have a relatively large driving capability, so more first inverters can be provided.
  • the first logic circuit includes 4 first inverters connected in series, and the 4 first inverters connected in series are inverter 1 to inverter 4 respectively.
  • the input terminal of the inverter 1 is coupled to the second input interface for receiving the switch control signal PS, and the inverters 1 to 4 are sequentially connected in series.
  • the output terminal of the inverter 4 is coupled to one input terminal of the NAND gate 1, the other input terminal of the NAND gate 1 is coupled to the first input interface for receiving the programming control signal STR, and the output terminal of the NAND gate 1 is coupled to To the input terminal of the inverter 5, the output terminal of the inverter 5 is the output terminal of the first logic circuit.
  • the above-mentioned first NAND gate and the second inverter can also be replaced by an AND gate, so the power switch circuit provided by this application can be equivalently replaced by a plurality of circuits with different structures, and these circuit structures are all in Within the scope of protection of the embodiments of the present application.
  • the first circuit structure of the second logic circuit includes N seventh inverters connected in series, where N is an even number greater than or equal to 2.
  • the input terminal of the first inverter in the seventh inverters connected in series is the input terminal of the second logic circuit, and the output terminal of the last inverter in the seventh inverters connected in series is the second logic circuit. the output of the logic circuit.
  • the specific number of the seventh inverters included in the second logic circuit is related to parameters such as the storage capacity of the EFUSE.
  • the second logic circuit includes 4 inverters connected in series, and the 4 inverters connected in series are respectively inverter 6 to inverter 9 as an example.
  • the input end of the inverter 6 is the input end of the second logic circuit
  • the inverter 6 to the inverter 9 are connected in series in turn
  • the output end of the inverter 9 is the output end of the second logic circuit VQR.
  • the operating voltage of the inverter in the first logic circuit is the first voltage VDD
  • the operating voltage of the inverter in the second logic circuit is the second voltage VQPS
  • the first voltage VDD is lower than the second voltage VQPS.
  • the inverter in the first logic circuit and the inverter in the second logic circuit may be CMOS inverters.
  • the drawings of the embodiments of the present application do not show the specific circuit structure of the inverter in the first logic circuit in detail.
  • the source voltage VDD of the PMOS transistor of the inverter in the first logic circuit can be a voltage of about 0.9V
  • the source voltage VQPS of the PMOS transistor of the inverter in the second logic circuit can be Voltage around 1.8V.
  • the embodiment of the present application does not limit the specific voltage values of the source voltage of the PMOS transistor of the inverter in the first logic circuit and the source voltage of the PMOS transistor of the inverter in the second logic circuit.
  • the switch control signal PS is at high level, and the programming control signal STR is at low level.
  • the switch control signal PS input to the inverter 1 is sequentially inverted by the inverter 1 to the inverter 4, and the inverter 4 outputs a high level. Since the programming control signal STR is at a low level, the NAND gate 1 outputs a high level, and after being inverted by the inverter 5, the first logic circuit outputs a low level. After the low-level signal input to the second logic circuit is sequentially inverted by the inverter 6 to the inverter 9, the output terminal of the power switch circuit outputs a low level.
  • the switch control signal PS is at high level
  • the programming control signal STR is at high level.
  • the switch control signal PS input to the inverter 1 is sequentially inverted by the inverter 1 to the inverter 4, and the inverter 4 outputs a high level.
  • the programming control signal STR is at a high level
  • the NAND gate 1 outputs a low level
  • the first logic circuit outputs a high level.
  • the output terminal of the power switch circuit outputs a high-level signal.
  • the level of the output terminal VQR of the power switch circuit is consistent with the level of the programming control signal STR, so the time for the power switch circuit to output the programming voltage follows the programming time of EFUSE, which can reduce the storage time.
  • the CORE tube in the cell array is under high pressure for a long time, which improves the stability of EFUSE programming.
  • the above-mentioned power switch circuit further includes a third input interface, the third input interface is used to receive a power control signal PD, and the power control signal PD is used to control power on and off of the power switch circuit.
  • the power control signal PD is at low level
  • the switch control signal PS is at high level. It can be understood that the power on and off of the power switch circuit can be independently controlled through the power control signal, so that the power switch circuit can be isolated from other external circuits.
  • the power switch circuit does not need to be powered on, there is no need to power off the external power supply. It will affect the normal use of external circuits.
  • the second circuit structure of the first logic circuit includes a third inverter, a second NAND gate, M fourth inverters connected in series, a third NAND gate, and a fifth inverter device, M is an odd number greater than or equal to 3.
  • the input end of the third inverter is coupled to the third input interface for receiving the power control signal PD, the output end of the third inverter is coupled to the first input end of the second NAND gate, and the second NAND gate
  • the second input terminal is coupled to the second input interface for receiving the switch control signal PS, the output terminal of the second NAND gate is coupled to the input terminal of the first inverter in the M fourth inverters, and the M fourth inverters
  • the output terminal of the last inverter among the inverters is coupled to the first input terminal of the third NAND gate, and the second input terminal of the third NAND gate is coupled to the first input interface for receiving the programming control signal STR,
  • the output terminal of the third NAND gate is coupled to the input terminal of the fifth inverter, and the output terminal of the fifth inverter is the output terminal of the first logic circuit.
  • the specific number of fourth inverters included in the first logic circuit is related to parameters such as the storage capacity of the EFUSE. For example, if the storage capacity of EFUSE is large, the output terminal VQR of the power switch circuit has a large load, which requires the power switch circuit to have a relatively large driving capability, so more fourth inverters can be provided.
  • the first logic circuit includes three fourth inverters connected in series, and the three fourth inverters connected in series are inverters 11 to 13 respectively.
  • the input terminal of the inverter 10 is coupled to the third input interface for receiving the power control signal PD, and the output terminal of the inverter 10 is coupled to an input terminal of the NAND gate 2 .
  • the other input terminal of the NAND gate 2 is coupled to the second input interface for receiving the switch control signal PS, the output terminal of the NAND gate 2 is coupled to the input terminal of the inverter 11, and the inverter 11 to the inverter 13 sequentially connected in series.
  • the output terminal of the inverter 13 is coupled to the first input terminal of the NAND gate 3, the second input terminal of the NAND gate 3 is coupled to the first input interface for receiving the programming control signal STR, and the output terminal of the NAND gate 3 Coupled to the input terminal of the inverter 14, the output terminal of the inverter 14 is the output terminal of the first logic circuit.
  • the power control signal PD is at low level
  • the switch control signal PS is at high level
  • the programming control signal STR is at low level. Since the programming control signal STR is at a low level, the NAND gate 3 outputs a high level, and after being inverted by the inverter 14 , the first logic circuit outputs a low level. After the low-level signal input to the second logic circuit is sequentially inverted by the inverter 6 to the inverter 9, the output terminal of the power switch circuit outputs a low-level signal.
  • the power control signal PD when EFUSE is in programming mode and starts programming, the power control signal PD is at low level, the switch control signal PS is at high level, and the programming control signal STR is at high level.
  • the power control signal PD input to the inverter 10 is outputted at a high level after passing through the inverter 10 . Since the switch control signal PS is at a high level, the NAND gate 2 outputs a low level. After successive inversions from the inverter 11 to the inverter 13, the inverter 13 outputs a high level. Since the programming control signal STR is at a high level, the NAND gate 3 outputs a low level, and after being inverted by the inverter 14 , the first logic circuit outputs a high level. After the high-level signal input to the second logic circuit is sequentially inverted by the inverter 6 to the inverter 9, the output terminal of the power switch circuit outputs a high-level signal.
  • the level of the output terminal VQR of the power switch circuit is consistent with the level of the programming control signal STR, so the time for the power switch circuit to output the programming voltage follows
  • the programming time of EFUSE can reduce the time that the CORE tube in the memory cell array is subjected to high voltage, and improve the stability of EFUSE programming.
  • the third circuit structure of the first logic circuit on the basis of the second circuit structure of the above-mentioned first logic circuit, the first logic circuit also includes a fourth input interface and a sixth inverter, and the fourth input interface is used for Receive the read-write control signal WR, the read-write control signal WR is used to read or write data in the one-time programmable memory, the input end of the sixth inverter is coupled to the fourth input interface, the sixth inverter The output terminal is coupled to the third input terminal of the third NAND gate.
  • the read/write control signal WR when writing data in EFUSE (for example, when EFUSE is programming), the read/write control signal WR is low level, and when reading data in EFUSE, the read/write control signal WR is high level.
  • the first logic circuit shown in FIG. 8 also includes a fourth input interface for receiving the read-write control signal WR and an inverter 15 , the input end of the inverter 15 is coupled to the fourth input interface for receiving the read/write control signal WR, and the output end of the inverter 15 is coupled to the third input end of the NAND gate 3 .
  • the power control signal PD is at low level
  • the switch control signal PS is at high level
  • the programming control signal STR is at low level. Since the programming control signal STR is at a low level, the NAND gate 3 outputs a high level, and after being inverted by the inverter 14 , the first logic circuit outputs a low level. After the low-level signal input to the second logic circuit is sequentially inverted by the inverter 6 to the inverter 9, the output terminal of the power switch circuit outputs a low-level signal.
  • the power control signal PD when EFUSE is in the programming mode and starts programming, the power control signal PD is at low level, the switch control signal PS is at high level, the programming control signal STR is at high level, and the read/write control signal WR is at low level level.
  • the power control signal PD input to the inverter 10 is outputted at a high level after passing through the inverter 10 . Since the switch control signal PS is at a high level, the NAND gate 2 outputs a low level. After successive inversions from the inverter 11 to the inverter 13, the inverter 13 outputs a high level. Since the read/write control signal WR is at low level, it becomes high level after being reversed by the inverter 15 .
  • the programming control signal STR is high level, the signals input to the three input terminals of the NAND gate 3 are all high level, so the NAND gate 3 outputs low level, and after the inversion by the inverter 14, the first logic circuit output high level.
  • the output terminal of the power switch circuit outputs a high-level signal. That is, when EFUSE is programmed, the level of the output terminal of the power switch circuit is consistent with the level of the programming control signal.
  • the level of the output terminal VQR of the power switch circuit is consistent with the level of the programming control signal STR, so the time for the power switch circuit to output the programming voltage follows
  • the programming time of EFUSE can reduce the time that the CORE tube in the memory cell array is subjected to high voltage, and improve the stability of EFUSE programming.
  • the second circuit structure of the second logic circuit includes K eighth inverters connected in series, the first MOS transistor and the first power supply control circuit, K is an odd number greater than or equal to 3, K
  • K is an odd number greater than or equal to 3
  • K The input terminal of the first inverter among the eighth inverters connected in series is the input terminal of the second logic circuit, and the output terminal of the last inverter among the eighth inverters connected in series is coupled to the first MOS
  • the gate of the transistor, the source of the first MOS transistor is coupled to the second voltage, and the drain of the first MOS transistor is coupled to the output terminal of the second logic circuit.
  • the first power supply control circuit includes a second MOS transistor and a third MOS transistor, the source of the second MOS transistor is coupled to the third voltage, and the gate of the second MOS transistor is used to receive the first control signal! PS, the level of the first control signal is opposite to the level of the switch control signal PS, the drain of the second MOS transistor is coupled to the source of the third MOS transistor, and the gate of the third MOS transistor is used to receive the second control Signal A, the level of the second control signal A is consistent with the output level of the output terminal of the first logic circuit, and the drain of the third MOS transistor is coupled to the output terminal of the second logic circuit.
  • the third voltage may be the same as the first voltage.
  • the specific number of the eighth inverters included in the second logic circuit is related to parameters such as the storage capacity of the EFUSE.
  • the second logic circuit includes three eighth inverters connected in series, and the three eighth inverters connected in series are inverters 16 to 18 respectively.
  • the input terminal of the inverter 16 is the input terminal of the second logic circuit
  • the inverter 16 to the inverter 18 are sequentially connected in series
  • the output terminal of the inverter 18 is coupled to the gate of the MOS transistor P1
  • the source of the MOS transistor P1 is coupled to VQPS
  • the drain of the MOS transistor P1 is coupled to the output terminal of the second logic circuit.
  • the source of the MOS transistor P2 is coupled to VDD, and the gate of the MOS transistor P2 is used to receive the first control signal!
  • the drain of the MOS transistor P2 is coupled to the source of the MOS transistor P3, the gate of the MOS transistor P3 is used to receive the second control signal A, and the drain of the MOS transistor P3 is coupled to the output terminal of the second logic circuit.
  • the power control signal PD is low level
  • the switch control signal PS is high level
  • the programming control signal STR is low level
  • the first control signal! PS is low level. Since the programming control signal STR is at a low level, the NAND gate 3 outputs a high level, and after being inverted by the inverter 14 , the output terminal A of the first logic circuit outputs a low level. After the low-level signal input to the second logic circuit is sequentially inverted by the inverter 16 to the inverter 18, the output terminal B of the inverter 18 outputs a high-level signal, and the MOS transistor P1 is in an off state. Thanks to the first control signal!
  • the function of the MOS transistor P1 is to cut off the connection between VQPS and VDD when VQPS is powered off, so as to avoid leakage problems caused by the connection of VQPS and VDD.
  • the power control signal PD when EFUSE is in the programming mode and starts programming, the power control signal PD is low level, the switch control signal PS is high level, the programming control signal STR is high level, the first control signal! PS is low level.
  • the power control signal PD input to the inverter 10 is outputted at a high level after passing through the inverter 10 . Since the switch control signal PS is at a high level, the NAND gate 2 outputs a low level. After successive inversions from the inverter 11 to the inverter 13, the inverter 13 outputs a high level.
  • the NAND gate 3 Since the programming control signal STR is at a high level, the NAND gate 3 outputs a low level, and after being inverted by the inverter 14 , the output terminal A of the first logic circuit outputs a high level. After the high-level signal input to the second logic circuit is sequentially inverted by the inverter 16 to the inverter 18, the output terminal B of the inverter 18 outputs a low level, the MOS transistor P1 is in the conduction state, and the power switch circuit The voltage at the output terminal VQR is VQPS. Thanks to the first control signal! PS is at low level, and the output terminal A of the first logic circuit is at high level, so the MOS transistor P2 is turned on and the MOS transistor P3 is turned off.
  • the voltage of the output terminal VQR of the power switch circuit when EFUSE is in the programming mode but does not start programming, the voltage of the output terminal VQR of the power switch circuit is VDD; when EFUSE is in the programming mode and starts programming, the power switch The voltage at the output terminal VQR of the circuit is VQPS. That is, by introducing the first power control circuit into the second logic circuit, the output voltage of the output terminal VQR of the power switch circuit in the non-programming state is maintained at VDD instead of zero voltage.
  • the voltage amplitude of the output terminal VQR of the power switch circuit changes from VDD to VQPS instead of changing from 0 to VQPS, so that the voltage range of the output terminal VQR of the power switch circuit varies greatly. Reduced, so that the instantaneous current pulse of the power switch circuit can be reduced, and the circuit risk and power consumption can be reduced.
  • the third circuit structure of the second logic circuit includes K eighth inverters connected in series, a first MOS transistor, and a second power control circuit, where K is an odd number greater than or equal to 3.
  • the input end of the first inverter among the K eighth inverters connected in series is the input end of the second logic circuit, and the output end of the last inverter among the K eighth inverters connected in series is coupled to the first inverter.
  • the gate of a MOS transistor, the source of the first MOS transistor is coupled to the second voltage, and the drain of the first MOS transistor is coupled to the output terminal of the second logic circuit.
  • the second power supply control circuit includes a fourth MOS transistor and a fifth MOS transistor, the gate of the fourth MOS transistor is coupled to the gate of the first MOS transistor, and the drain of the fourth MOS transistor is coupled to the output terminal of the second logic circuit, The source of the fourth MOS transistor is coupled to the drain of the fifth MOS transistor, the gate of the fifth MOS transistor is used to receive the switch control signal PS, and the source of the fifth MOS transistor is coupled to the third voltage.
  • the third voltage may be the same as the first voltage.
  • the specific number of the eighth inverters included in the second logic circuit is related to parameters such as the storage capacity of the EFUSE.
  • the second logic circuit including three eighth inverters connected in series, and the three eighth inverters connected in series are inverters 16 to 18 as an example.
  • the input terminal of the inverter 16 is the input terminal of the second logic circuit, and the inverter 16 to the inverter 18 are sequentially connected in series, and the output terminal of the inverter 18 is coupled to the gate of the MOS transistor P1 , the source of the MOS transistor P1 is coupled to VQPS, and the drain of the MOS transistor P1 is coupled to the output terminal of the second logic circuit.
  • the gate of the MOS transistor N1 is coupled to the gate of the MOS transistor P1, the drain of the MOS transistor N1 is coupled to the output terminal VQR of the second logic circuit, the source of the MOS transistor N1 is coupled to the drain of the MOS transistor N2, and the MOS transistor N2
  • the gate of the MOS transistor N2 is used to receive the switch control signal PS, and the source of the MOS transistor N2 is coupled to the third voltage VDD.
  • the power switch circuit when the power switch circuit includes the second circuit structure of the above-mentioned first logic circuit and the third circuit structure of the second logic circuit, the specific working principles of the power switch circuit in different scenarios will be introduced.
  • the power control signal PD is at low level
  • the switch control signal PS is at high level
  • the programming control signal STR is at low level. Since the programming control signal STR is at a low level, the NAND gate 3 outputs a high level, and after being inverted by the inverter 14 , the output terminal A of the first logic circuit outputs a low level.
  • the output terminal B of the inverter 18 outputs a high level
  • the MOS transistor P1 is turned off, and the MOS transistor N1 is turned on. Since the switch control signal PS is at a high level, the MOS transistor N2 is turned on, and the voltage of the output terminal VQR of the power switch circuit is VDD.
  • the power control signal PD when EFUSE is in programming mode and starts programming, the power control signal PD is at low level, the switch control signal PS is at high level, and the programming control signal STR is at high level.
  • the power control signal PD input to the inverter 10 is outputted at a high level after passing through the inverter 10 . Since the switch control signal PS is at a high level, the NAND gate 2 outputs a low level. After successive inversions from the inverter 11 to the inverter 13, the inverter 13 outputs a high level.
  • the NAND gate 3 Since the programming control signal STR is at a high level, the NAND gate 3 outputs a low level, and after being inverted by the inverter 14 , the output terminal A of the first logic circuit outputs a high level. After the high-level signal input to the second logic circuit is sequentially inverted by the inverter 16 to the inverter 18, the output terminal B of the inverter 18 outputs a low level, the MOS transistor P1 is in the conduction state, and the MOS transistor N1 is in the ON state. In the off state, the voltage of the output terminal VQR of the power switch circuit is VQPS.
  • the voltage of the output terminal VQR of the power switch circuit when EFUSE is in the programming mode but does not start programming, the voltage of the output terminal VQR of the power switch circuit is VDD; when EFUSE is in the programming mode and starts programming, the power switch circuit The voltage at the output terminal VQR of the circuit is VQPS. That is, by introducing the second power control circuit into the second logic circuit, the output voltage of the output terminal VQR of the power switch circuit in the non-programming state is maintained at VDD instead of zero voltage.
  • the voltage amplitude of the output terminal VQR of the power switch circuit changes from VDD to VQPS instead of changing from 0 to VQPS, so that the voltage range of the output terminal VQR of the power switch circuit varies greatly. Reduced, so that the instantaneous current pulse of the power switch circuit can be reduced, and the circuit risk and power consumption can be reduced.
  • FIG. 11 is a schematic diagram of an instantaneous current pulse of a power switch circuit.
  • the power switch circuit does not include the above-mentioned first power control circuit and the second power control circuit
  • the voltage of the output terminal VQR of the power switch circuit The amplitude changes from 0 to VQPS, and the maximum amplitude of the instantaneous current pulse is 413.5mA.
  • the power switch circuit includes the first power control circuit shown in FIG. 9 or the second power control circuit shown in FIG.
  • the second circuit structure and the third circuit structure of the above-mentioned second logic circuit can reduce the instantaneous current pulse of the power switch circuit, reduce circuit risk and power consumption.
  • any one of the three circuit structures included in the first logic circuit and any one of the three circuit structures included in the second logic circuit can be combined into a power switch circuit.
  • FIG. 6 to FIG. 10 in the embodiment of the present application show schematic circuit structure diagrams of some power switch circuits.
  • the embodiment of the present application does not limit the high and low levels of the above-mentioned switch control signal PS, power control signal PD, programming control signal STR, read-write control signal WR, etc. in different states. If the above-mentioned switch control signal PS, power control The high and low levels of the signal PD, the programming control signal STR, the read-write control signal WR, etc. in different states are inconsistent with the above-mentioned embodiments, and it is only necessary to add or subtract an inverter in the power switch circuit. For example, when the power switch circuit is working, the switch control signal PS can also be at a low level, and when the power switch circuit is not working, the switch control signal PS can also be at a high level.
  • the power switch circuit provided in the embodiment of the present application can be equivalently replaced with various circuit structures, and these circuit structures are all within the protection scope of the present application.
  • the embodiment of the present application does not limit the specific circuit structure of the power switch circuit. As long as the output terminal of the power switch circuit can follow the programming control signal to output the programming voltage, any power switching circuit is within the scope of protection of the embodiments of the present application.
  • the embodiment of the present application also provides a one-time programmable memory, the one-time programmable memory includes a memory cell array, and a power switch circuit as described in any one of the above embodiments, the output end of the power switch circuit is coupled to The memory cell array.
  • the one-time programmable memory may be EFUSE.
  • the steps of the methods or algorithms described in connection with the disclosure of this application can be implemented in the form of hardware, or can be implemented in the form of a processor executing software instructions.
  • the software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (random access memory, RAM), flash memory, erasable programmable read-only memory (erasable programmable ROM, EPROM), electrically erasable Programmable read-only memory (electrically EPROM, EEPROM), registers, hard disk, removable hard disk, CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
  • the storage medium may also be a component of the processor.
  • the processor and storage medium can be located in the ASIC.
  • the functions described in the present invention may be implemented by hardware, software, firmware or any combination thereof.
  • the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
  • Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage media may be any available media that can be accessed by a general purpose or special purpose computer.

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Abstract

本申请实施例公开了一种电源开关电路和一次性可编程存储器，涉及电路领域，能够缓解因一次性可编程存储器中的CORE管长时间承受较高的IO电压，影响器件的稳定性，导致误编程的问题。具体方案为：电源开关电路用于在一次性可编程存储器编程时为一次性可编程存储器中的存储单元阵列提供编程电压，电源开关电路包括第一输入接口，第一输入接口用于接收编程控制信号，编程控制信号用于控制一次性可编程存储器是否处于编程模式；其中，在一次性可编程存储器处于编程模式且写入时，电源开关电路的输出端的电平与编程控制信号的电平一致。

Description

一种电源开关电路和一次性可编程存储器
本申请要求于2022年01月29日提交国家知识产权局、申请号为202210112331.9、申请名称为“一种电源开关电路和一次性可编程存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及电路领域，尤其涉及一种电源开关电路和一次性可编程存储器。
背景技术
随着芯片集成度的提高，芯片的可靠性、生产良率和芯片功耗成为设计和制造中的重要课题。由于一次性可编程存储器(Electrically program fuse，EFUSE)具备较高的存储可靠性，因此在芯片中加入EFUSE可以较好的解决芯片良率低和可靠性问题。
EFUSE在编程时，EFUSE中的常规电压晶体管(例如，CORE管)会承受较高的IO电压，由于CORE管的工作电压较低，如果CORE管长时间承受较高的IO电压，可能会影响器件的稳定性，造成误编程。因此，为了提高EFUSE编程的稳定性，如何对EFUSE的编程时间进行约束成为了亟待解决的问题。
发明内容
本申请实施例提供一种电源开关电路和一次性可编程存储器，能够减小存储单元阵列中的CORE管承受高压的时间，提高EFUSE编程的稳定性。
为达到上述目的，本申请实施例采用如下技术方案：
本申请实施例的第一方面，提供一种电源开关电路，用于在一次性可编程存储器编程时，为一次性可编程存储器中的存储单元阵列提供编程电压，电源开关电路包括第一输入接口，第一输入接口用于接收编程控制信号，该编程控制信号用于控制一次性可编程存储器是否处于编程模式；其中，在一次性可编程存储器处于编程模式且写入时，电源开关电路的输出端的电平与编程控制信号的电平一致。
在一些实施例中，一次性可编程存储器处于编程模式是指该一次性可编程存储器可访问。例如，一次性可编程存储器处于编程模式时，可以在一次性可编程存储器中读出或写入数据。本申请中的在一次性可编程存储器处于编程模式且写入时，也可以称为在一次性可编程存储器编程时。
基于本方案，通过在电源开关电路中引入编程控制信号STR，而且在一次性可编程存储器处于编程模式且写入时，电源开关电路的输出端的电平可以与编程控制信号的电平保持一致。因此，当一次性可编程存储器开始编程(比如，开始写入)时，电源开关电路的输出端也跟随该编程控制信号输出编程电压。也就是说，本方案中的电源开关电路输出编程电压的时间可以跟随EFUSE的编程时间，因此EFUSE无需承受无意义的PS上电时间，能够减小EFUSE中存储单元阵列中的CORE管承受高压的时间，提高EFUSE编程的稳定性。而且本申请可以不对开关控制信号PS的上电时间进行约束，也能减小存储单元阵列中的CORE管承受高压的时间。
在一种可能的实现方式，上述电源开关电路包括第一逻辑电路和第二逻辑电路，该第一逻辑电路的输入端耦合至上述第一输入接口，第一逻辑电路的输出端耦合至第二逻辑电路的输入端，第二逻辑电路的输出端为电源开关电路的输出端，电源开关电路的输出端用于与一次性可编程存储器中的存储单元阵列耦合。
在一些示例中，上述第一逻辑电路的工作电压低于第二逻辑电路的工作电压。例如，为了确保第一逻辑电路与接收的编程控制信号的电压相同，第一逻辑电路的工作电压可以较低。为了确保一次性可编程存储器中的存储单元阵列有足够的编程电压，第二逻辑电路的工作电压可以较第一逻辑电路的工作电压高一些。
在一种可能的实现方式，上述电源开关电路还包括第二输入接口，该第二输入接口用于接收开关控制信号，该开关控制信号用于控制电源开关电路是否工作。
在另一种可能的实现方式中，上述第一逻辑电路包括I个串联连接的第一反相器、第一与非门和第二反相器，I为大于或等于2偶数，该I个串联连接的第一反相器中的首个反相器的输入端耦合至第二输入接口，I个串联连接的第一反相器中最后一个反相器的输出端耦合至第一与非门的第一输入端，第一与非门的第二输入端耦合至第一输入接口，第一与非门的输出端耦合至第二反相器的输入端，所述第二反相器的输出端为第一逻辑电路的输出端。
基于本方案，电源开关电路可以接收开关控制信号和编程控制信号，而且在一次性可编程存储器编程时，电源开关电路输出编程电压的时间可以跟随EFUSE的编程时间，因此EFUSE无需承受无意义的PS上电时间，能够减小EFUSE中存储单元阵列中的CORE管承受高压的时间，提高EFUSE编程的稳定性。
在又一种可能的实现方式中，上述电源开关电路还包括第三输入接口，该第三输入接口用于接收电源控制信号，该电源控制信号用于控制电源开关电路的上下电。
在又一种可能的实现方式中，上述第一逻辑电路包括第三反相器、第二与非门、M个串联连接的第四反相器、第三与非门，以及第五反相器，M为大于或等于3的奇数；第三反相器输入端耦合至第三输入接口，第三反相器的输出端耦合至第二与非门的第一输入端，第二与非门的第二输入端耦合至第二输入接口，第二与非门的输出端耦合至M个第四反相器中首个反相器的输入端，M个第四反相器中最后一个反相器的输出端耦合至第三与非门的第一输入端，第三与非门的第二输入端耦合至第一输入接口，第三与非门的输出端耦合至第五反相器的输入端，第五反相器的输出端为第一逻辑电路的输出端。
基于本方案，电源开关电路可以接收开关控制信号、电源控制信号和编程控制信号，而且在一次性可编程存储器编程时，电源开关电路输出编程电压的时间可以跟随EFUSE的编程时间，因此EFUSE无需承受无意义的PS上电时间，能够减小EFUSE中存储单元阵列中的CORE管承受高压的时间，提高EFUSE编程的稳定性。而且本方案通过电源控制信号能够独立控制电源开关电路的上下电，使得电源开关电路可以与外部其他电路隔离开，当电源开关电路不需要上电时，无需要将外部电源进行下电，不会影响外部电路的正常使用。
在又一种可能的实现方式中，上述电源开关电路还包括第四输入接口和第六反相器，该第四输入接口用于接收读写控制信号，所述读写控制信号用于在一次性可编程 存储器中读出或写入数据，该第六反相器的输入端耦合至所述第四输入接口，所述第六反相器的输出端耦合至所述第三与非门的第三输入端。
基于本方案，电源开关电路可以接收开关控制信号、电源控制信号、读写控制信号和编程控制信号，而且在一次性可编程存储器编程时，电源开关电路输出编程电压的时间可以跟随EFUSE的编程时间，因此EFUSE无需承受无意义的PS上电时间，能够减小EFUSE中存储单元阵列中的CORE管承受高压的时间，提高EFUSE编程的稳定性。
在又一种可能的实现方式中，上述第二逻辑电路包括N个串联连接的第七反相器，N为大于或等于2的偶数，该N个串联连接的第七反相器中首个反相器的输入端为第二逻辑电路的输入端，N个串联连接的第七反相器中最后一个反相器的输出端为第二逻辑电路的输出端。
在又一种可能的实现方式中，上述第二逻辑电路包括第一金属氧化物半导体MOS管和K个串联连接的第八反相器，K为大于或等于3的奇数，K个串联连接的第八反相器中首个反相器的输入端为第二逻辑电路的输入端，K个串联连接的第八反相器中最后一个反相器的输出端耦合至第一MOS管的栅极，第一MOS管的源级耦合至第二电压，第一MOS管的漏极耦合至第二逻辑电路的输出端。
在又一种可能的实现方式中，第二逻辑电路还包括第一电源控制电路，第一电源控制电路包括第二MOS管和第三MOS管，第二MOS管的源级耦合至第三电压，第二MOS管的栅极用于接收第一控制信号，第一控制信号的电平与开关控制信号的电平相反，第二MOS管的漏极耦合至第三MOS管的源级，第三MOS管的栅极用于接收第二控制信号，第二控制信号的电平与第一逻辑电路的输出端输出的电平一致，第三MOS管的漏极耦合至第二逻辑电路的输出端。
基于本方案，在EFUSE处于编程模式但未开始编程时，电源开关电路的输出端VQR的电压为VDD，在EFUSE处于编程模式且开始编程时，电源开关电路的输出端VQR的电压为VQPS。即，本方案中电源开关电路的输出端VQR在非编程状态下的输出电压维持为VDD，而不是零电压。从而在电源开关电路切换至编程状态时，电源开关电路的输出端VQR的电压幅度是从VDD变为VQPS，而不是从0变为VQPS，使得电源开关电路的输出端VQR的电压幅度变化范围大大减小，从而能够减小电源开关电路的瞬间电流脉冲，降低电路风险和功耗。
在又一种可能的实现方式中，上述第二逻辑电路还包括第二电源控制电路，第二电源控制电路包括第四MOS管和第五MOS管，第四MOS管的栅极耦合至第一MOS管的栅极，第四MOS管的漏极耦合至第二逻辑电路的输出端，第四MOS管的源级耦合至第五MOS管的漏极，第五MOS管的栅极用于接收开关控制信号，第五MOS管的源级耦合至第三电压。
基于本方案，在EFUSE处于编程模式但未开始编程时，电源开关电路的输出端VQR的电压为VDD，在EFUSE处于编程模式且开始编程时，电源开关电路的输出端VQR的电压为VQPS。即，本方案中电源开关电路的输出端VQR在非编程状态下的输出电压维持为VDD，而不是零电压。从而在电源开关电路切换至编程状态时，电源开关电路的输出端VQR的电压幅度是从VDD变为VQPS，而不是从0变为VQPS， 使得电源开关电路的输出端VQR的电压幅度变化范围大大减小，从而能够减小电源开关电路的瞬间电流脉冲，降低电路风险和功耗。
在又一种可能的实现方式中，上述第一逻辑电路中的反相器的工作电压为第一电压，上述第二逻辑电路中的反相器的工作电压为第二电压，第一电压低于第二电压。
本申请实施例的第二方面，提供一种一次性可编程存储器，所述一次性可编程存储器包括存储单元阵列，以及如上述第一方面任一实现方式所述的电源开关电路，所述电源开关电路的输出端耦合至所述存储单元阵列。在一些示例中，该一次性可编程存储器可以为EFUSE。
附图说明
图1为本申请实施例提供的一种一次性可编程存储器的架构示意图；
图2为本申请实施例提供的一种电源开关电路的电路结构示意图；
图3为本申请实施例提供的一种电源开关电路的信号时序示意图；
图4为本申请实施例提供的另一种电源开关电路的电路结构示意图；
图5为本申请实施例提供的另一种电源开关电路的信号时序示意图；
图6为本申请实施例提供的另一种电源开关电路的电路结构示意图；
图7为本申请实施例提供的另一种电源开关电路的电路结构示意图；
图8为本申请实施例提供的另一种电源开关电路的电路结构示意图；
图9为本申请实施例提供的另一种电源开关电路的电路结构示意图；
图10为本申请实施例提供的另一种电源开关电路的电路结构示意图；
图11为本申请实施例提供的一种电源开关电路的瞬间电流脉冲示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c，或，a和b和c，其中a、b和c可以是单个，也可以是多个。另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定。比如，本申请实施例中的第一反相器中的“第一”和第三反相器中的“第二”仅用于区分不同的反相器。本申请实施例中出现的第一、第二等描述，仅作示意与区分描述对象之用，没有次序之分，也不表示本申请实施例中对设备个数的特别限定，不能构成对本申请实施例的任何限制。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
首先对本申请实施例中的互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)反相器进行介绍。
CMOS反相器由一个PMOS管和一个NMOS管组成，PMOS管的栅极耦合至和NMOS管的栅极，PMOS管的源级耦合至电源，PMOS管的漏极耦合至NMOS管的漏极，NMOS管的源级接地(本申请实施例附图中的VSS可以为接地端)。PMOS管的栅极为CMOS反相器的输入端，PMOS管的漏极为CMOS反相器的输出端。当反相器的输入端输入高电平时，PMOS管关断，NMOS管导通，CMOS反相器的输出端输出低电平。当反相器的输入端输入低电平时，PMOS管导通，NMOS管关断，CMOS反相器的输出端输出高电平。
图1为本申请实施例提供的一种一次性可编程存储器EFUSE的架构示意图，如图1所示，EFUSE包括逻辑电源电压控制器、电源开关(Powerswitch)电路、行译码电路、存储单元阵列、信号控制电路、列译码电路和灵敏放大器。
如图1所示，逻辑电源电压控制器的输入端用于接收逻辑电源电压，电源开关电路的输入端用于接收编程电压。当EFUSE编程时，通过电源开关电路的控制端可以将编程电压VQPS传输至存储单元阵列中的Bitcell进行编程。
图2为一种电源开关电路的电路结构示意图，如图2所示，该电源开关电路包括反相器20、与非门21、反相器22、反相器23、反相器24，以及反相器25至反相器28。其中，反相器20的输入端用于接收电源控制信号PD(PowerDown)，反相器20的输出端耦合至与非门21的第一输入端，与非门21的第二输入端用于接收开关控制信号PS。与非门21的输出端耦合至反相器22的输入端，反相器22至反相器28依次串联连接。反相器28的输出端为电源开关电路的输出端VQR，该电源开关电路的输出端可以与EFUSE中的存储单元阵列耦合。
电源控制信号PD用于控制电源开关电路的上下电。例如，当电源开关电路上电时，电源控制信号PD为低电平，当电源开关电路下电时，电源控制信号PD为高电平。开关控制信号PS用于控制电源开关电路是否工作。例如，当电源开关电路工作时，开关控制信号PS为高电平，当电源开关电路不工作时，开关控制信号PS为低电平。
图2中的反相器可以为CMOS反相器。图2中的反相器20、反相器22至反相器24的工作电压为VDD，反相器25至反相器28的工作电压为VQPS，VDD小于VQPS。例如，反相器20、反相器22至反相器24的工作电压为0.9V，反相器25至反相器28的工作电压为1.8V。
如图2所示，当电源开关电路开始工作时，电源控制信号PD为低电平0，反相器20输出高电平，开关控制信号PS为高电平，与非门21输出低电平，经反相器22至反相器28依次反相后，电源开关电路的输出端VQR输出高电平。此时，编程电压VQPS传输到EFUSE的存储单元阵列(图2中未示出)，存储单元阵列中的CORE管会承受该编程电压VQPS。由于存储单元阵列中的CORE管的工作电压较低(例如，CORE管的工作电压为0.9V左右的电压)，而编程电压VQPS较高(例如，VQPS的电压为1.8V左右)，如果CORE管长时间承受较高的电压，将对器件的稳定性造成影响，可能会出现误编程或误烧写的问题。
为了提高EFUSE编程的稳定性，在实际使用EFUSE时，可以对开关控制信号PS 的累计上电时间进行约束(例如，开关控制信号PS的累计上电时间不超过0.2s)。但是，在实际使用EFUSE时，EFUSE实际编程的时间和开关控制信号PS的上电时间可能不匹配，导致开关控制信号PS的上电时间比实际编程时间多很多，造成开关控制信号PS的累计上电时间超过约束时间。当开关控制信号PS的累计上电时间超过约束时间时，存储单元阵列中的CORE管就会出现稳定性的问题。
例如，如图3所示，开关控制信号PS从低电平变为高电平时，电源开关电路开始工作。编程控制信号STR(STROBE)从低电平变为高电平时，EFUSE开始编程。由于开关控制信号PS上电到EFUSE开始编程有一段时间间隔，这个间隔包括开关控制信号PS的建立时间(setup time)、行列译码电路寻址时间等。因此，在多个EFUSE使用时，非编程的EFUSE需要承受无意义的PS上电时间，造成PS的上电时间比实际编程时间多很多，导致开关控制信号PS的累计上电时间超过约束时间，会对器件的稳定性造成影响，可能会出现误编程。
另外，由于EFUSE的存储单元阵列较大，使得VQR端的负载较大，因此VQR的前一级反相器需要较大的驱动能力。这就导致每当PS上电时电源开关电路输出VQR的初始时刻会产生很大的瞬间电流脉冲，也会对EFUSE的稳定性造成影响。
为了提高EFUSE编程的稳定性，本申请实施例提供一种电源开关电路，该电源开关电路的输出编程电压的时间可以跟随EFUSE的编程时间，从而减小存储单元阵列中的CORE管承受高压的时间，能够提高EFUSE编程的稳定性。而且在电源开关电路切换至编程状态时，通过将电源开关电路的输出端的电压幅度变化范围减小，能够降低电源开关电路的瞬间电流脉冲，降低电路风险和功耗。
本申请实施例提供一种电源开关电路，该电源开关电路用于在一次性可编程存储器编程时，为一次性可编程存储器中的存储单元阵列提供编程电压，该电源开关电路包括第一输入接口，第一输入接口用于接收编程控制信号STR，该编程控制信号STR用于控制一次性可编程存储器是否处于编程模式。其中，在一次性可编程存储器处于编程模式且写入时，电源开关电路的输出端VQR的电平与编程控制信号STR的电平一致。
在一些实施例中，一次性可编程存储器处于编程模式是指该一次性可编程存储器可访问。例如，一次性可编程存储器处于编程模式时，可以在一次性可编程存储器中读出或写入数据。本申请实施例中的在一次性可编程存储器处于编程模式且写入时，也可以称为在一次性可编程存储器编程时。
图4为本申请实施例提供的一种电源开关电路的示意图，如图4所示，电源开关电路还包括第一逻辑电路和第二逻辑电路，第一逻辑电路的输入端耦合至第一输入接口，第一逻辑电路的输出端耦合至第二逻辑电路的输入端，第二逻辑电路的输出端为电源开关电路的输出端VQR，电源开关电路的输出端VQR用于与一次性可编程存储器中的存储单元阵列耦合。
在一些示例中，第一逻辑电路的工作电压低于第二逻辑电路的工作电压。例如，为了确保第一逻辑电路与接收的编程控制信号的电压相同，第一逻辑电路的工作电压可以较低。为了确保一次性可编程存储器中的存储单元阵列有足够的编程电压，第二逻辑电路的工作电压可以较第一逻辑电路的工作电压高一些。
在一些示例中，当编程控制信号STR从低电平变为高电平，EFUSE开始编程时。当编程控制信号STR从高电平变为低电平时，EFUSE停止编程。即，编程控制信号STR用于控制EFUSE是否编程，EFUSE编程时，编程控制信号STR为高电平；EFUSE未编程时，编程控制信号STR为低电平。在另一些示例中，编程控制信号STR既可以用于控制EFUSE是否编程，还可以用于控制EFUSE是否读数据。
本申请实施例中的电源开关电路引入了编程控制信号STR，而且在一次性可编程存储器编程时，电源开关电路的输出端VQR的电平可以与编程控制信号的电平保持一致。即，当编程控制信号STR从低电平变为高电平，EFUSE开始编程时，电源开关电路的输出端VQR也跟随该编程控制信号STR输出编程电压。因此，本申请实施例提供的电源开关电路中，电源开关电路输出编程电压的时间可以跟随EFUSE的编程时间，因此EFUSE无需承受无意义的PS上电时间，能够减小存储单元阵列中的CORE管承受高压的时间，提高EFUSE编程的稳定性。
在一些实施例中，上述电源开关电路还包括第二输入接口，第二输入接口用于接收开关控制信号PS，该开关控制信号PS用于控制电源开关电路是否工作。当电源开关电路工作时，开关控制信号PS为高电平，当电源开关电路不工作时，开关控制信号PS为低电平。
例如，如图5所示，在本申请实施例中，当编程控制信号STR从低电平变为高电平时，电源开关电路输出编程电压的时间(图5中的点划线所示的VQR)可以跟随EFUSE的编程时间。在图2和图3所示的相关技术中，非编程的EFUSE需要承受无意义的PS上电时间，因此电源开关电路输出编程电压的时间(图5中的虚线所示的VQR)比实际编程时间多很多。很显然，与图2所示的方案相比，由于本申请中电源开关电路输出编程电压的时间可以跟随EFUSE的编程时间，因此能够减小存储单元阵列中的CORE管承受高压的时间，提高EFUSE编程的稳定性。另外，如图5所示，虽然本申请中开关控制信号PS上电到EFUSE开始编程有一段时间间隔，但是本申请中电源开关电路输出编程电压的时间可以跟随EFUSE的编程时间，因此EFUSE无需承受无意义的PS上电时间。也就是说，本申请可以不对开关控制信号PS的上电时间进行约束，也能减小存储单元阵列中的CORE管承受高压的时间。
电源开关电路中的第一逻辑电路可以包括三种电路结构，电源开关电路中的第二逻辑电路也可以包括三种电路结构，第一逻辑电路包括的任一种电路结构和第二逻辑电路包括的任一种电路结构可以组合为一种电源开关电路。也就是说，本申请实施例提供的电路开关电路至少包括9种不同的电路结构。下面分别对第一逻辑电路和第二逻辑电路的电路结构进行介绍。需要说明的是，下述实施例示例性的介绍部分电源开关电路的具体电路结构。
第一逻辑电路的第一种电路结构：第一逻辑电路包括I个串联连接的第一反相器、第一与非门和第二反相器，I为大于或等于2偶数，I个串联连接的第一反相器中的首个反相器的输入端耦合至第二输入接口，I个串联连接的第一反相器中最后一个反相器的输出端耦合至第一与非门的第一输入端，第一与非门的第二输入端耦合至第一输入接口，第一与非门的输出端耦合至第二反相器的输入端，第二反相器的输出端为第一逻辑电路的输出端。
在一些实施例中，第一逻辑电路包括的第一反相器的具体数量与EFUSE的存储容量等参数有关。例如，如果EFUSE的存储容量较大，那么电源开关电路的输出端VQR的负载较大，这就需要电源开关电路具备较大的驱动能力，因此可以设置较多个第一反相器。
例如，以第一逻辑电路包括4个串联连接的第一反相器，该4个串联连接的第一反相器分别为反相器1至反相器4为例。如图6所示，反相器1的输入端耦合至用于接收开关控制信号PS的第二输入接口，反相器1至反相器4依次串联连接。反相器4的输出端耦合至与非门1的一个输入端，与非门1的另一个输入端耦合至用于接收编程控制信号STR的第一输入接口，与非门1的输出端耦合至反相器5的输入端，反相器5的输出端为第一逻辑电路的输出端。
在一些实施例中，上述第一与非门和第二反相器也可以用一个与门代替，因此本申请提供的电源开关电路可以用多个不同结构的电路等同替换，这些电路结构均在本申请实施例的保护范围内。
第二逻辑电路的第一种电路结构：第二逻辑电路包括N个串联连接的第七反相器，N为大于或等于2的偶数。N个串联连接的第七反相器中首个反相器的输入端为第二逻辑电路的输入端，N个串联连接的第七反相器中最后一个反相器的输出端为第二逻辑电路的输出端。
在一些实施例中，第二逻辑电路包括的第七反相器的具体数量与EFUSE的存储容量的大小等参数有关。
例如，以第二逻辑电路包括4个串联连接的反相器，该4个串联连接的反相器分别为反相器6至反相器9为例。如图6所示，反相器6的输入端为第二逻辑电路的输入端，反相器6至反相器9依次串联连接，反相器9的输出端为第二逻辑电路的输出端VQR。
在一些实施例中，第一逻辑电路中的反相器的工作电压为第一电压VDD，第二逻辑电路中的反相器的工作电压为第二电压VQPS，第一电压VDD低于第二电压VQPS。第一逻辑电路中的反相器和第二逻辑电路中的反相器可以为CMOS反相器。本申请实施例的附图未详细示出第一逻辑电路中的反相器的具体电路结构。
例如，如图6所示，第一逻辑电路中反相器的PMOS管的源级电压VDD可以为0.9V左右的电压，第二逻辑电路中反相器的PMOS管的源级电压VQPS可以为1.8V左右的电压。本申请实施例对于第一逻辑电路中反相器的PMOS管的源级电压和第二逻辑电路中反相器的PMOS管的源级电压的具体电压值并不限定。
下面结合图6，对电源开关电路包括上述第一逻辑电路的第一种电路结构和第二逻辑电路的第一种电路结构时，该电源开关电路在不同场景下的具体工作原理进行介绍。
如图6所示，当EFUSE处于编程模式但未开始编程时，开关控制信号PS为高电平，编程控制信号STR为低电平。输入反相器1的开关控制信号PS，经反相器1至反相器4依次反相后，反相器4输出高电平。由于编程控制信号STR为低电平，因此与非门1输出高电平，经反相器5反相后，第一逻辑电路输出低电平。输入第二逻辑电路的低电平信号经反相器6至反相器9依次反相后，电源开关电路的输出端输出低 电平。
如图6所示，当EFUSE处于编程模式且开始编程时，开关控制信号PS为高电平，编程控制信号STR为高电平。输入反相器1的开关控制信号PS，经反相器1至反相器4依次反相后，反相器4输出高电平。由于编程控制信号STR为高电平，因此与非门1输出低电平，经反相器5反相后，第一逻辑电路输出高电平。输入第二逻辑电路的低电平信号经反相器6至反相器9依次反相后，电源开关电路的输出端输出高电平。
如图6所示，当EFUSE处于非编程模式时，开关控制信号PS为低电平，电源开关电路不工作，电源开关电路的输出端VQR为浮空状态，EFUSE的存储单元阵列内的电路会将VQR拉低至低电平。
可以理解的，当EFUSE处于编程模式时，电源开关电路的输出端VQR的电平与编程控制信号STR的电平一致，因此电源开关电路输出编程电压的时间跟随EFUSE的编程时间，能够减小存储单元阵列中的CORE管承受高压的时间，提高EFUSE编程的稳定性。
在一些实施例中，上述电源开关电路还包括第三输入接口，第三输入接口用于接收电源控制信号PD，电源控制信号PD用于控制电源开关电路的上下电。当电源开关电路上电时，电源控制信号PD为低电平，当电源开关电路下电时，开关控制信号PS为高电平。可以理解的，通过电源控制信号能够独立控制电源开关电路的上下电，使得电源开关电路可以与外部其他电路隔离开，当电源开关电路不需要上电时，无需要将外部电源进行下电，不会影响外部电路的正常使用。
第一逻辑电路的第二种电路结构：第一逻辑电路包括第三反相器、第二与非门、M个串联连接的第四反相器、第三与非门，以及第五反相器，M为大于或等于3的奇数。第三反相器的输入端耦合至用于接收电源控制信号PD的第三输入接口，第三反相器的输出端耦合至第二与非门的第一输入端，第二与非门的第二输入端耦合至用于接收开关控制信号PS的第二输入接口，第二与非门的输出端耦合至M个第四反相器中首个反相器的输入端，M个第四反相器中最后一个反相器的输出端耦合至第三与非门的第一输入端，第三与非门的第二输入端耦合至用于接收编程控制信号STR的第一输入接口，第三与非门的输出端耦合至第五反相器的输入端，第五反相器的输出端为第一逻辑电路的输出端。
在一些实施例中，第一逻辑电路包括的第四反相器的具体数量与EFUSE的存储容量的大小等参数有关。例如，如果EFUSE的存储容量较大，那么电源开关电路的输出端VQR的负载较大，这就需要电源开关电路具备较大的驱动能力，因此可以设置较多个第四反相器。
例如，以第一逻辑电路包括3个串联连接的第四反相器，该3个串联连接的第四反相器分别为反相器11至反相器13为例。如图7所示，反相器10的输入端耦合至用于接收电源控制信号PD的第三输入接口，反相器10的输出端耦合至与非门2的一个输入端。与非门2的另一个输入端耦合至用于接收开关控制信号PS的第二输入接口，与非门2的输出端耦合至反相器11的输入端，反相器11至反相器13依次串联连接。反相器13的输出端耦合至与非门3的第一输入端，与非门3的第二输入端耦合至用于接收编程控制信号STR的第一输入接口，与非门3的输出端耦合至反相器14的输入 端，反相器14的输出端为第一逻辑电路的输出端。
下面结合图7，对电源开关电路包括上述第一逻辑电路的第二种电路结构和第二逻辑电路的第一种电路结构时，该电源开关电路在不同场景下的具体工作原理进行介绍。
如图7所示，当EFUSE处于编程模式但未开始编程时，电源控制信号PD为低电平，开关控制信号PS为高电平，编程控制信号STR为低电平。由于编程控制信号STR为低电平，因此与非门3输出高电平，经反相器14反相后，第一逻辑电路输出低电平。输入第二逻辑电路的低电平信号经反相器6至反相器9依次反相后，电源开关电路的输出端输出低电平。
如图7所示，当EFUSE处于编程模式且开始编程时，电源控制信号PD为低电平，开关控制信号PS为高电平，编程控制信号STR为高电平。输入反相器10的电源控制信号PD，经反相器10后输出高电平。由于开关控制信号PS为高电平，因此与非门2输出低电平。经反相器11至反相器13依次反相后，反相器13输出高电平。由于编程控制信号STR为高电平，因此与非门3输出低电平，经反相器14反相后，第一逻辑电路输出高电平。输入第二逻辑电路的高电平信号经反相器6至反相器9依次反相后，电源开关电路的输出端输出高电平。
如图7所示，当EFUSE处于非编程模式时，开关控制信号PS为低电平，电源开关电路不工作，电源开关电路的输出端VQR为浮空状态，EFUSE的存储单元阵列内的电路会将VQR拉低至低电平。
可以理解的，图7所示的电源开关电路，当EFUSE处于编程模式时，电源开关电路的输出端VQR的电平与编程控制信号STR的电平一致，因此电源开关电路输出编程电压的时间跟随EFUSE的编程时间，能够减小存储单元阵列中的CORE管承受高压的时间，提高EFUSE编程的稳定性。
第一逻辑电路的第三种电路结构：在上述第一逻辑电路的第二种电路结构的基础上，第一逻辑电路还包括第四输入接口和第六反相器，第四输入接口用于接收读写控制信号WR，该读写控制信号WR用于在一次性可编程存储器中读出或写入数据，第六反相器的输入端耦合至第四输入接口，第六反相器的输出端耦合至第三与非门的第三输入端。
在一些示例中，当在EFUSE中写入数据时(例如，EFUSE编程时)，读写控制信号WR为低电平，当在EFUSE中读出数据时，读写控制信号WR为高电平。
例如，结合图7，如图8所示，在图7所示的第一逻辑电路的基础上，图8所示的第一逻辑电路还包括用于接收读写控制信号WR的第四输入接口和反相器15，反相器15的输入端耦合至用于接收读写控制信号WR的第四输入接口，反相器15的输出端耦合至与非门3的第三输入端。
下面结合图8，对电源开关电路包括上述第一逻辑电路的第三种电路结构和第二逻辑电路的第一种电路结构时，该电源开关电路在不同场景下的具体工作原理进行介绍。
如图8所示，当EFUSE处于编程模式但未开始编程时，电源控制信号PD为低电平，开关控制信号PS为高电平，编程控制信号STR为低电平。由于编程控制信号STR 为低电平，因此与非门3输出高电平，经反相器14反相后，第一逻辑电路输出低电平。输入第二逻辑电路的低电平信号经反相器6至反相器9依次反相后，电源开关电路的输出端输出低电平。
如图8所示，当EFUSE处于编程模式且开始编程时，电源控制信号PD为低电平，开关控制信号PS为高电平，编程控制信号STR为高电平，读写控制信号WR为低电平。输入反相器10的电源控制信号PD，经反相器10后输出高电平。由于开关控制信号PS为高电平，因此与非门2输出低电平。经反相器11至反相器13依次反相后，反相器13输出高电平。由于读写控制信号WR为低电平，经反相器15反向后为高电平。由于编程控制信号STR为高电平，输入与非门3的三个输入端的信号均为高电平，因此与非门3输出低电平，经反相器14反相后，第一逻辑电路输出高电平。输入第二逻辑电路的高电平信号经反相器6至反相器9依次反相后，电源开关电路的输出端输出高电平。即在EFUSE编程时，电源开关电路的输出端的电平与编程控制信号的电平一致。
可以理解的，图8所示的电源开关电路，当EFUSE处于编程模式时，电源开关电路的输出端VQR的电平与编程控制信号STR的电平一致，因此电源开关电路输出编程电压的时间跟随EFUSE的编程时间，能够减小存储单元阵列中的CORE管承受高压的时间，提高EFUSE编程的稳定性。
第二种逻辑电路的第二种电路结构：第二逻辑电路包括K个串联连接的第八反相器、第一MOS管和第一电源控制电路，K为大于或等于3的奇数，K个串联连接的第八反相器中首个反相器的输入端为第二逻辑电路的输入端，K个串联连接的第八反相器中最后一个反相器的输出端耦合至第一MOS管的栅极，第一MOS管的源级耦合至第二电压，第一MOS管的漏极耦合至第二逻辑电路的输出端。第一电源控制电路包括第二MOS管和第三MOS管，第二MOS管的源级耦合至第三电压，第二MOS管的栅极用于接收第一控制信号！PS，该第一控制信号的电平与开关控制信号PS的电平相反，第二MOS管的漏极耦合至第三MOS管的源级，第三MOS管的栅极用于接收第二控制信号A，该第二控制信号A的电平与第一逻辑电路的输出端输出的电平一致，第三MOS管的漏极耦合至第二逻辑电路的输出端。
在一些实施例中，第三电压可以与第一电压相同。第二逻辑电路包括的第八反相器的具体数量与EFUSE的存储容量等参数有关。
例如，以第二逻辑电路包括3个串联连接的第八反相器，该3个串联连接的第八反相器分别为反相器16至反相器18为例。如图9所示，反相器16的输入端为第二逻辑电路的输入端，反相器16至反相器18依次串联连接，反相器18的输出端耦合至MOS管P1的栅极，MOS管P1的源级耦合至VQPS，MOS管P1的漏极耦合至第二逻辑电路的输出端。MOS管P2的源级耦合至VDD，MOS管P2的栅极用于接收第一控制信号！PS，MOS管P2的漏极耦合至MOS管P3的源级，MOS管P3的栅极用于接收第二控制信号A，MOS管P3的漏极耦合至第二逻辑电路的输出端。
下面结合图9，对电源开关电路包括上述第一逻辑电路的第二种电路结构和第二逻辑电路的第二种电路结构时，该电源开关电路在不同场景下的具体工作原理进行介绍。
如图9所示，当EFUSE处于编程模式但未开始编程时，电源控制信号PD为低电平，开关控制信号PS为高电平，编程控制信号STR为低电平，第一控制信号！PS为低电平。由于编程控制信号STR为低电平，因此与非门3输出高电平，经反相器14反相后，第一逻辑电路的输出端A输出低电平。输入第二逻辑电路的低电平信号经反相器16至反相器18依次反相后，反相器18的输出端B输出高电平，MOS管P1处于关断状态。由于第一控制信号！PS为低电平，第一逻辑电路的输出端A为低电平，因此MOS管P2和MOS管P3导通，电源开关电路的输出端VQR的电压为VDD。可以理解的，MOS管P1的作用是可以在VQPS掉电时，将VQPS与VDD之间切断，避免VQPS与VDD相连引起漏电问题。
如图9所示，当EFUSE处于编程模式且开始编程时，电源控制信号PD为低电平，开关控制信号PS为高电平，编程控制信号STR为高电平，第一控制信号！PS为低电平。输入反相器10的电源控制信号PD，经反相器10后输出高电平。由于开关控制信号PS为高电平，因此与非门2输出低电平。经反相器11至反相器13依次反相后，反相器13输出高电平。由于编程控制信号STR为高电平，因此与非门3输出低电平，经反相器14反相后，第一逻辑电路的输出端A输出高电平。输入第二逻辑电路的高电平信号经反相器16至反相器18依次反相后，反相器18的输出端B输出低电平，MOS管P1处于导通状态，电源开关电路的输出端VQR的电压为VQPS。由于第一控制信号！PS为低电平，第一逻辑电路的输出端A为高电平，因此MOS管P2导通和MOS管P3关断。
可以理解的，上述第二逻辑电路的第二种电路结构在EFUSE处于编程模式但未开始编程时，电源开关电路的输出端VQR的电压为VDD，在EFUSE处于编程模式且开始编程时，电源开关电路的输出端VQR的电压为VQPS。即，通过在第二逻辑电路中引入第一电源控制电路，使得电源开关电路的输出端VQR在非编程状态下的输出电压维持为VDD，而不是零电压。从而在电源开关电路切换至编程状态时，电源开关电路的输出端VQR的电压幅度是从VDD变为VQPS，而不是从0变为VQPS，使得电源开关电路的输出端VQR的电压幅度变化范围大大减小，从而能够减小电源开关电路的瞬间电流脉冲，降低电路风险和功耗。
第二种逻辑电路的第三种电路结构：第二逻辑电路包括K个串联连接的第八反相器、第一MOS管和第二电源控制电路，K为大于或等于3的奇数。K个串联连接的第八反相器中首个反相器的输入端为第二逻辑电路的输入端，K个串联连接的第八反相器中最后一个反相器的输出端耦合至第一MOS管的栅极，第一MOS管的源级耦合至第二电压，第一MOS管的漏极耦合至第二逻辑电路的输出端。第二电源控制电路包括第四MOS管和第五MOS管，第四MOS管的栅极耦合至第一MOS管的栅极，第四MOS管的漏极耦合至第二逻辑电路的输出端，第四MOS管的源级耦合至第五MOS管的漏极，第五MOS管的栅极用于接收开关控制信号PS，第五MOS管的源级耦合至第三电压。
在一些实施例中，第三电压可以与第一电压相同。第二逻辑电路包括的第八反相器的具体数量与EFUSE的存储容量等参数有关。
例如，以第二逻辑电路包括3个串联连接的第八反相器，该3个串联连接的第八 反相器分别为反相器16至反相器18为例。如图10所示，反相器16的输入端为第二逻辑电路的输入端，反相器16至反相器18依次串联连接，反相器18的输出端耦合至MOS管P1的栅极，MOS管P1的源级耦合至VQPS，MOS管P1的漏极耦合至第二逻辑电路的输出端。MOS管N1的栅极耦合至MOS管P1的栅极，MOS管N1的漏极耦合至第二逻辑电路的输出端VQR，MOS管N1的源级耦合至MOS管N2的漏极，MOS管N2的栅极用于接收开关控制信号PS，MOS管N2的源级耦合至第三电压VDD。
下面结合图10，对电源开关电路包括上述第一逻辑电路的第二种电路结构和第二逻辑电路的第三种电路结构时，该电源开关电路在不同场景下的具体工作原理进行介绍。
如图10所示，当EFUSE处于编程模式但未开始编程时，电源控制信号PD为低电平，开关控制信号PS为高电平，编程控制信号STR为低电平。由于编程控制信号STR为低电平，因此与非门3输出高电平，经反相器14反相后，第一逻辑电路的输出端A输出低电平。输入第二逻辑电路的低电平信号经反相器16至反相器18依次反相后，反相器18的输出端B输出高电平，MOS管P1关断，MOS管N1导通。由于开关控制信号PS为高电平，因此MOS管N2导通，电源开关电路的输出端VQR的电压为VDD。
如图10所示，当EFUSE处于编程模式且开始编程时，电源控制信号PD为低电平，开关控制信号PS为高电平，编程控制信号STR为高电平。输入反相器10的电源控制信号PD，经反相器10后输出高电平。由于开关控制信号PS为高电平，因此与非门2输出低电平。经反相器11至反相器13依次反相后，反相器13输出高电平。由于编程控制信号STR为高电平，因此与非门3输出低电平，经反相器14反相后，第一逻辑电路的输出端A输出高电平。输入第二逻辑电路的高电平信号经反相器16至反相器18依次反相后，反相器18的输出端B输出低电平，MOS管P1处于导通状态，MOS管N1处于关断状态，电源开关电路的输出端VQR的电压为VQPS。
可以理解的，上述第二逻辑电路的第三种电路结构在EFUSE处于编程模式但未开始编程时，电源开关电路的输出端VQR的电压为VDD，在EFUSE处于编程模式且开始编程时，电源开关电路的输出端VQR的电压为VQPS。即，通过在第二逻辑电路中引入第二电源控制电路，使得电源开关电路的输出端VQR在非编程状态下的输出电压维持为VDD，而不是零电压。从而在电源开关电路切换至编程状态时，电源开关电路的输出端VQR的电压幅度是从VDD变为VQPS，而不是从0变为VQPS，使得电源开关电路的输出端VQR的电压幅度变化范围大大减小，从而能够减小电源开关电路的瞬间电流脉冲，降低电路风险和功耗。
图11为一种电源开关电路的瞬间电流脉冲示意图。如图11中的(a)所示，当电源开关电路未包括上述第一电源控制电路和第二电源控制电路时，在电源开关电路切换至编程状态时，电源开关电路的输出端VQR的电压幅度是从0变为VQPS，此时瞬间电流脉冲的最大幅值为413.5mA。如图11中的(b)所示，当电源开关电路包括上述图9所示的第一电源控制电路或图10所示的第二电源控制电路时，在电源开关电路切换至编程状态时，电源开关电路的输出端VQR的电压幅度是从VDD变为VQPS，此时瞬间电流脉冲的最大幅值为313.4mA。因此，上述第二逻辑电路的第二种电路结 构和第三种电路结构可以减小电源开关电路的瞬间电流脉冲，降低电路风险和功耗。
需要说明的是，上述第一逻辑电路包括的三种电路结构中任一种电路结构和第二逻辑电路包括的三种电路结构中的任一种电路结构可以组合为一种电源开关电路。本申请实施例中的图6至图10示出了部分电源开关电路的电路结构示意图。
另外，本申请实施例对于上述开关控制信号PS、电源控制信号PD、编程控制信号STR、读写控制信号WR等在不同状态下的高低电平并不限定，如果上述开关控制信号PS、电源控制信号PD、编程控制信号STR、读写控制信号WR等在不同状态下的高低电平与上述实施例不一致，只需要在电源开关电路中增加或减去一个反相器即可。例如，当电源开关电路工作时，开关控制信号PS也可以为低电平，当电源开关电路不工作时，开关控制信号PS也可以为高电平，此时，只需要在开关电源电路中开关控制信号PS的输出端增加或减去一个反相器即可实现上述电源开关电路的效果。也就是所，本申请实施例提供的电源开关电路可以用多种电路结构等同替换，这些电路结构均在本申请的保护范围内，本申请实施例对于电源开关电路的具体电路结构并不限定，只要是电源开关电路的输出端可以跟随编程控制信号输出编程电压的任一种电源开关电路均在本申请实施例的保护范围内。
本申请实施例还提供一种一次性可编程存储器，该一次性可编程存储器包括存储单元阵列，以及如上述任一实施例中所述的电源开关电路，所述电源开关电路的输出端耦合至所述存储单元阵列。在一些示例中，该一次性可编程存储器可以为EFUSE。
结合本申请公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(random access memory，RAM)、闪存、可擦除可编程只读存储器(erasable programmable ROM，EPROM)、电可擦可编程只读存储器(electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本发明所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。

Claims (13)

  1. 一种电源开关电路，其特征在于，用于在一次性可编程存储器编程时，为所述一次性可编程存储器中的存储单元阵列提供编程电压，所述电源开关电路包括第一输入接口，所述第一输入接口用于接收编程控制信号，所述编程控制信号用于控制所述一次性可编程存储器是否处于编程模式；其中，在所述一次性可编程存储器处于编程模式且写入时，所述电源开关电路的输出端的电平与所述编程控制信号的电平一致。
  2. 根据权利要求1所述的电源开关电路，其特征在于，所述电源开关电路还包括第一逻辑电路和第二逻辑电路，所述第一逻辑电路的输入端耦合至所述第一输入接口，所述第一逻辑电路的输出端耦合至所述第二逻辑电路的输入端，所述第二逻辑电路的输出端为所述电源开关电路的输出端，所述电源开关电路的输出端用于与所述一次性可编程存储器中的存储单元阵列耦合。
  3. 根据权利要求2所述的电源开关电路，其特征在于，所述电源开关电路还包括第二输入接口，所述第二输入接口用于接收开关控制信号，所述开关控制信号用于控制所述电源开关电路是否工作。
  4. 根据权利要求3所述的电源开关电路，其特征在于，所述第一逻辑电路包括I个串联连接的第一反相器、第一与非门和第二反相器，所述I为大于或等于2偶数，所述I个串联连接的第一反相器中的首个反相器的输入端耦合至所述第二输入接口，所述I个串联连接的第一反相器中最后一个反相器的输出端耦合至所述第一与非门的第一输入端，所述第一与非门的第二输入端耦合至所述第一输入接口，所述第一与非门的输出端耦合至所述第二反相器的输入端，所述第二反相器的输出端为所述第一逻辑电路的输出端。
  5. 根据权利要求3所述的电源开关电路，其特征在于，所述电源开关电路还包括第三输入接口，所述第三输入接口用于接收电源控制信号，所述电源控制信号用于控制所述电源开关电路的上下电。
  6. 根据权利要求5所述的电源开关电路，其特征在于，所述第一逻辑电路包括第三反相器、第二与非门、M个串联连接的第四反相器、第三与非门，以及第五反相器，所述M为大于或等于3的奇数；所述第三反相器输入端耦合至所述第三输入接口，所述第三反相器的输出端耦合至所述第二与非门的第一输入端，所述第二与非门的第二输入端耦合至所述第二输入接口，所述第二与非门的输出端耦合至所述M个第四反相器中首个反相器的输入端，所述M个第四反相器中最后一个反相器的输出端耦合至所述第三与非门的第一输入端，所述第三与非门的第二输入端耦合至所述第一输入接口，所述第三与非门的输出端耦合至所述第五反相器的输入端，所述第五反相器的输出端为所述第一逻辑电路的输出端。
  7. 根据权利要求6所述的电源开关电路，其特征在于，所述第一逻辑电路还包括第四输入接口和第六反相器，所述第四输入接口用于接收读写控制信号，所述读写控制信号用于在一次性可编程存储器中读出或写入数据，所述第六反相器的输入端耦合至所述第四输入接口，所述第六反相器的输出端耦合至所述第三与非门的第三输入端。
  8. 根据权利要求2-7中任一项所述的电源开关电路，其特征在于，所述第二逻辑电路包括N个串联连接的第七反相器，所述N为大于或等于2的偶数，所述N个串 联连接的第七反相器中首个反相器的输入端为所述第二逻辑电路的输入端，所述N个串联连接的第七反相器中最后一个反相器的输出端为所述第二逻辑电路的输出端。
  9. 根据权利要求2-7中任一项所述的电源开关电路，其特征在于，所述第二逻辑电路包括第一金属氧化物半导体MOS管和K个串联连接的第八反相器，所述K为大于或等于3的奇数，所述K个串联连接的第八反相器中首个反相器的输入端为所述第二逻辑电路的输入端，所述K个串联连接的第八反相器中最后一个反相器的输出端耦合至所述第一MOS管的栅极，所述第一MOS管的源级耦合至第二电压，所述第一MOS管的漏极耦合至所述第二逻辑电路的输出端。
  10. 根据权利要求9所述的电源开关电路，其特征在于，所述第二逻辑电路还包括第一电源控制电路，所述第一电源控制电路包括第二MOS管和第三MOS管，所述第二MOS管的源级耦合至第三电压，所述第二MOS管的栅极用于接收第一控制信号，所述第一控制信号的电平与所述开关控制信号的电平相反，所述第二MOS管的漏极耦合至所述第三MOS管的源级，所述第三MOS管的栅极用于接收第二控制信号，所述第二控制信号的电平与所述第一逻辑电路的输出端输出的电平一致，所述第三MOS管的漏极耦合至所述第二逻辑电路的输出端。
  11. 根据权利要求9所述的电源开关电路，其特征在于，所述第二逻辑电路还包括第二电源控制电路，所述第二电源控制电路包括第四MOS管和第五MOS管，所述第四MOS管的栅极耦合至所述第一MOS管的栅极，所述第四MOS管的漏极耦合至所述第二逻辑电路的输出端，所述第四MOS管的源级耦合至所述第五MOS管的漏极，所述第五MOS管的栅极用于接收所述开关控制信号，所述第五MOS管的源级耦合至第三电压。
  12. 根据权利要求2-11中任一项所述的电源开关电路，其特征在于，所述第一逻辑电路中的反相器的工作电压为第一电压，所述第二逻辑电路中的反相器的工作电压为第二电压，所述第一电压低于所述第二电压。
  13. 一种一次性可编程存储器，其特征在于，所述一次性可编程存储器包括存储单元阵列，以及如权利要求1-12中任一项所述的电源开关电路，所述电源开关电路的输出端耦合至所述存储单元阵列。
PCT/CN2022/129203 2022-01-29 2022-11-02 一种电源开关电路和一次性可编程存储器 WO2023142575A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101556825A (zh) * 2009-05-20 2009-10-14 炬力集成电路设计有限公司 一种集成电路
CN106057244A (zh) * 2016-05-30 2016-10-26 安凯(广州)微电子技术有限公司 一种efuse电路及可编程存储装置
CN107967929A (zh) * 2017-11-30 2018-04-27 上海华力微电子有限公司 一种存储单元及其存储阵列结构、操作方法
CN108766499A (zh) * 2018-04-26 2018-11-06 上海华力微电子有限公司 E-fuse存储阵列、e-fuse以及e-fuse操作方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101556825A (zh) * 2009-05-20 2009-10-14 炬力集成电路设计有限公司 一种集成电路
CN106057244A (zh) * 2016-05-30 2016-10-26 安凯(广州)微电子技术有限公司 一种efuse电路及可编程存储装置
CN107967929A (zh) * 2017-11-30 2018-04-27 上海华力微电子有限公司 一种存储单元及其存储阵列结构、操作方法
CN108766499A (zh) * 2018-04-26 2018-11-06 上海华力微电子有限公司 E-fuse存储阵列、e-fuse以及e-fuse操作方法

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