WO2023142420A1 - 半导体器件及其制造方法、电子设备 - Google Patents

半导体器件及其制造方法、电子设备 Download PDF

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WO2023142420A1
WO2023142420A1 PCT/CN2022/110320 CN2022110320W WO2023142420A1 WO 2023142420 A1 WO2023142420 A1 WO 2023142420A1 CN 2022110320 W CN2022110320 W CN 2022110320W WO 2023142420 A1 WO2023142420 A1 WO 2023142420A1
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manufacturing
layer
tunnel junction
magnetic tunnel
inert gas
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PCT/CN2022/110320
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English (en)
French (fr)
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张云森
李辉辉
罗杰
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北京超弦存储器研究院
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Publication of WO2023142420A1 publication Critical patent/WO2023142420A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details

Definitions

  • the present application relates to the field of semiconductor devices, in particular to a semiconductor device, a manufacturing method thereof, and electronic equipment.
  • Magnetic random access memory (Magnetic Random Access Memory, MRAM) is a random access memory that stores data in the nature of magnetoresistance. It has the characteristics of high-speed reading and writing, large capacity and low energy consumption.
  • the core storage device of MRAM is the magnetic tunnel junction (Magnetic Tunnel Junction, MTJ).
  • An embodiment of the present application provides a manufacturing method of a semiconductor device, the manufacturing method comprising:
  • the precursor gas of cyano radical and provide plasma, make the precursor gas of cyano radical form cyano radical in plasma, adopt described cyano radical to patterned magnetic tunnel junction layer and
  • the material of the hard mask layer is chemically treated, and the ion source gas of the inert gas ions is formed into inert gas ions, and the chemically treated product and the patterned magnetic tunnel junction layer without chemical treatment are formed by using the inert gas ions and hard mask layer materials are removed to obtain the semiconductor device;
  • the chemical treatment is chemical reaction, or chemical modification, or chemical reaction and chemical modification.
  • the material of the magnetic tunnel junction layer may include iron, cobalt, cobalt-iron-boron, nickel, tungsten, molybdenum, chromium, ruthenium, iridium, palladium, platinum, magnesium oxide, aluminum, zinc, titanium and any one or more of rhodium.
  • the material of the hard mask layer may be selected from any one or more of tantalum and tantalum nitride.
  • the precursor gas of the cyano radical can be selected from HCN, (CN) 2 , CH 3 CN, a mixed gas of CH 4 and NH 3 , a mixed gas of CH 3 OH and NH 3 , any one or more of the mixed gas of CH 3 CH 2 OH and NH 3 .
  • the pressure during the chemical treatment may be 0.3 mTorr to 10 mTorr.
  • the ion source gas of the inert gas ions may include any one or more of neon, argon, krypton, and xenon.
  • the ion source gas of the inert gas ion may also include a carrier gas, and the carrier gas may be selected from any one or more of CO, CO 2 , N 2 , O 2 and He .
  • the total flow rate of the precursor gas of the cyano radical and the ion source gas of the inert gas ions may be 100 sccm to 2000 sccm.
  • the power of the radio frequency source power supply for generating and maintaining the plasma may be 100 watts to 3000 watts.
  • the frequency of the radio frequency source may be 13.56MHz.
  • the use of the inert gas ions to remove the chemically treated product and the material of the patterned magnetic tunnel junction layer and hard mask layer without chemical treatment may include: using radio frequency
  • the bias power supply accelerates the inert gas ions, and uses the accelerated inert gas ions to bombard the chemically treated product and the non-chemically treated patterned magnetic tunnel junction layer and hard mask layer materials to Material removal.
  • the ion acceleration voltage provided by the radio frequency bias power supply may be 30V to 1000V.
  • the frequency of the radio frequency bias power supply may be 13.56MHz to 400kHz, for example, may be 13.56MHz, 2MHz or 400kHz.
  • the processes of forming cyano radicals, chemical treatment, and removal using the inert gas ions can be performed in an inductively coupled plasma etching chamber.
  • the manufacturing method may further include:
  • ion beam etching is used to trim the sidewall of the patterned magnetic tunnel junction layer to obtain the semiconductor devices;
  • ion beam etching is used to pattern the The sidewall of the magnetic tunnel junction layer is trimmed to obtain the semiconductor device.
  • the ion source gas for ion beam etching may be selected from any one or more of neon, argon, krypton, and xenon.
  • the embodiment of the present application also provides a semiconductor device, which is obtained by the above-mentioned manufacturing method.
  • the diameter of the magnetic tunnel junction of the semiconductor device may be sub-80 nm, sub-70 nm, sub-60 nm or sub-50 nm.
  • the embodiment of the present application also provides an electronic device, including the semiconductor device provided in the above embodiment of the present application.
  • Figure 1 is the curve of sputtering rate and deposition rate as a function of incident angle during the etching process of a specific etching front end using IBE;
  • Figure 2 is a schematic diagram of the formation principle of the shadow effect
  • Fig. 3 is a metal and a reaction product diagram that can undergo chemical reactions and/or chemical modifications with cyano radicals
  • FIG. 4 is a schematic diagram of the process of step S40;
  • Fig. 5 is a schematic diagram of the structure of the ICP etching chamber and the variation diagram of the ion energy distribution with the ion flux under different radio frequency bias power supply frequencies;
  • 6A is a schematic structural diagram of an intermediate product obtained in the method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;
  • 6B is a schematic structural diagram of an intermediate product obtained in the method for manufacturing a semiconductor device according to an exemplary embodiment of the present application.
  • 6C is a schematic structural diagram of an intermediate product obtained in the method for manufacturing a semiconductor device according to an exemplary embodiment of the present application.
  • FIG. 6D is a schematic structural diagram of a semiconductor device according to an exemplary embodiment of the present application.
  • 10-etching front end 20-gas inlet; 30-RF source power supply; 40-RF bias power supply; 50-throttle position sensor with throttle valve; 60-plasma; 70-wafer; 100-substrate; 110 -dielectric; 120-via; 210-bottom electrode layer; 210'-bottom electrode; 220-magnetic tunnel junction layer; 220'-magnetic tunnel junction; 230-hard mask layer; 230'-top electrode; 240-insulation layer.
  • setting and “connection” should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • connection should be interpreted in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • the current mainstream semiconductor etching process is reactive ion etching (Reactive Ion Etching, RIE).
  • RIE reactive Ion Etching
  • halogen gas such as Cl 2
  • the halogen gas forms halogen radicals in the plasma, and the halogen radicals chemically react with the material to be etched, and the reaction product Etching can be achieved by pumping away.
  • MTJs some materials that form MTJs, such as Fe, Co, Mg, Ru, Pt, Pd, Al, Rh, Mo, Ni, or Ir, etc., do not react at all or very poorly with the halogen radicals formed in the plasma Moreover, the subsequent dehalogenation process will introduce H 2 O, which is unacceptable in the MTJ manufacturing process. Therefore, conventional RIE is not suitable for etching of MTJ arrays.
  • FIG. 1 is a curve of sputtering rate and deposition rate varying with incident angle during the etching process of a specific etching front end 10 by using IBE.
  • IBE is a dynamic equilibrium process of sputtering and deposition.
  • the sputtering rate will vary with the incident angle ⁇ of Ar + or Ar, but the deposition rate will not vary with the incident angle of Ar + or Ar .
  • the deposition rate is not constant.
  • the deposition rate is strongly related to the surrounding environment of the specific etching front 10 and will change dynamically as time goes by.
  • the incident direction of Ar + or Ar will maintain an inclination angle ⁇ with the normal of the etching front 10 , especially when the deposition rate is higher.
  • the inclination angle ⁇ of the Ar + or Ar incident direction can be increased to increase the sputtering rate, thereby realizing the material removal of the specific etching front end 10.
  • the geometric size of the etched area shrinks, there is limited room for increasing the inclination angle ⁇ of the Ar + or Ar incident direction, resulting in an increase in the sputtering rate brought about by increasing the inclination angle ⁇ .
  • Fig. 2 is a schematic diagram of the formation principle of the shadow effect. IBE is not an optimal etching scheme for high-density MTJ arrays due to shadowing effects.
  • An embodiment of the present application provides a method for manufacturing a semiconductor device, including:
  • S20 sequentially forming a bottom electrode layer, a magnetic tunnel junction layer, and a hard mask layer on the substrate;
  • S40 providing the precursor gas of cyano radicals, and providing plasma, so that the precursor gas of cyano radicals forms cyano radicals in the plasma, and using the cyano radicals to pattern the magnetic tunnel junction
  • the materials of the layer and the hard mask layer are chemically treated, and the ion source gas of the inert gas ions is formed into inert gas ions, and the chemically treated products and the non-chemically treated patterned magnetic tunnels are formed by using the inert gas ions. Material removal of the junction layer and the hard mask layer to obtain the semiconductor device;
  • the chemical treatment is chemical reaction, or chemical modification, or chemical reaction and chemical modification.
  • the manufacturing method of the semiconductor device of the embodiment of the present application uses cyano radicals and inert gas ions to carry out cooperative etching (including using cyano radicals to chemically react the materials of the patterned magnetic tunnel junction layer and hard mask layer and/or or chemical modification, and the use of inert gas ions to physically bombard and remove materials to achieve synergistic etching), because chemical reactions and chemical modifications are isotropic, the sticking coefficient of chemical etching by-products (Sticking Coefficient) is smaller than physical The adhesion coefficient of etching, which will effectively reduce or even avoid the shadow effect problem of IBE etching; moreover, the inert gas ions remove chemically reacted and/or chemically modified and unchemically reacted and chemically modified materials by physical bombardment , can greatly increase the removal efficiency.
  • the manufacturing method of the semiconductor device of the embodiment of the present application is conducive to the miniaturization of MTJ, and is suitable for preparing high-density MRAM memory, for example, preparing an MTJ with a diameter of Sub-80nm, Sub-70nm, Sub-60nm or Sub-50nm array.
  • the substrate may be a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) substrate.
  • CMOS complementary Metal Oxide Semiconductor
  • the material of the magnetic tunnel junction layer may include iron (Fe), cobalt (Co), cobalt iron boron (CoFeB), nickel (Ni), tungsten (W), molybdenum (Mo), Chromium (Cr), Ruthenium (Ru), Iridium (Ir), Palladium (Pd), Platinum (Pt), Magnesium Oxide (MgO), Aluminum (Al), Zinc (Zn), Titanium (Ti), and Rhodium (Rh) Any one or more of these.
  • the materials that make up the magnetic tunnel junction are heavy metals or magnetic metals, such as: iron (Fe), cobalt (Co), nickel (Ni), tungsten (W), molybdenum (Mo), chromium (Cr), ruthenium (Ru), iridium (Ir), palladium (Pd), platinum (Pt), magnesium (Mg), aluminum (Al), zinc (Zn), titanium (Ti), rhodium (Rh) and tantalum (Ta), etc.
  • the inventors of the present application found that the conventional free radicals formed in the plasma were very difficult to chemically react with these materials or chemically modify them when carrying out the research on the magnetic tunnel junction, but the cyano radicals formed in the plasma ( -C ⁇ N, Cyano-Group Radical) can chemically react and/or be chemically modified with metals other than Ta.
  • FIG. 3 is a diagram of metals and reaction products that can undergo chemical reactions and/or chemical modifications with cyano radicals summarized by the inventors of the present application.
  • the cyano radicals formed in the plasma can form complexes with inert metals such as Fe, Co, Ni, Mg, Pt, Pd, Al, Zn, Ru, Ir, W, Ti, Rh, Mo, etc.
  • inert metals such as Fe, Co, Ni, Mg, Pt, Pd, Al, Zn, Ru, Ir, W, Ti, Rh, Mo, etc.
  • FIG. 4 is a schematic diagram of the process of step S40.
  • Ta has been abandoned as an interlayer coupling layer material (Ta as an interlayer coupling layer cannot withstand the 400°C CMOS back-end annealing process); and because Ta does not interact with cyano radicals A chemical reaction or chemical modification takes place, so it can be used as an MTJ hard mask (HM) layer material.
  • the material of the hard mask layer may be selected from any one or more of tantalum (Ta) and tantalum nitride (TaN).
  • the precursor gas of the cyano radical can be selected from HCN, (CN) 2 , CH 3 CN, a mixed gas of CH 4 and NH 3 , a mixed gas of CH 3 OH and NH 3 , any one or more of the mixed gas of CH 3 CH 2 OH and NH 3 .
  • These gases can generate cyano radicals in the plasma, for example, the plasma formed by the precursor gas of the cyano radicals and the inert gas.
  • the pressure during the chemical treatment may be 0.3 mTorr to 10 mTorr.
  • the ion source gas of the inert gas ions may include any one or more of neon, argon, krypton, and xenon, and CO, CO 2 , N 2 ,, Any one or more of O2 and He is used as a carrier gas.
  • a turbocharged molecular pump with a large suction force and a larger gas (comprising the precursor gas of the cyano radical and the inert gas) can be selected as much as possible.
  • Ion source gas flow of gas ions.
  • the total flow rate of the precursor gas of cyano radicals and the ion source gas of inert gas ions may be 100 sccm to 2000 sccm.
  • the power of the RF source power (RF Source Power) for generating and maintaining the plasma may be 100 watts to 3000 watts.
  • the frequency of the radio frequency source may be 13.56 MHz.
  • the use of the inert gas ions to remove the chemically treated product and the material of the patterned magnetic tunnel junction layer and hard mask layer without chemical treatment may include: using radio frequency The bias power supply (RF Bias Power) accelerates the inert gas ions, and uses the accelerated inert gas ions to the product of the chemical treatment and the patterned magnetic tunnel junction layer and hard mask layer without chemical treatment. The material is bombarded to remove the material.
  • RF Bias Power The bias power supply
  • the ion acceleration voltage provided by the RF bias power supply may be 30V to 1000V.
  • the ion accelerating voltage can adopt pulse bias voltage, that is, repeat cycles between applying bias voltage and no bias voltage, based on repeated cycles of chemical reaction and/or chemical modification and purely physical etching
  • pulse bias voltage that is, repeat cycles between applying bias voltage and no bias voltage, based on repeated cycles of chemical reaction and/or chemical modification and purely physical etching
  • ALE Atomic Layer Etching
  • the frequency of the radio frequency bias power supply may be 13.56MHz to 400kHz, for example, it may be 13.56MHz, 2MHz or 400kHz, and for example, it may be 400kHz.
  • P working pressure
  • V the volume of the reaction chamber
  • flow the gas flow rate
  • C sccm/mTorr the key indicator of the pumping force of the reaction etching chamber.
  • step S40 may be performed in an inductively coupled plasma (Inductively Coupled Plasma, ICP) etching chamber.
  • ICP Inductively Coupled Plasma
  • FIG. 5 is a schematic diagram of the structure of the ICP etching chamber and a diagram of ion energy distribution versus ion flux under different RF bias power frequencies.
  • the ICP etching chamber includes a gas inlet 20, a radio frequency source power supply 30, a radio frequency bias power supply 40, a throttle position sensor 50 with a throttle valve;
  • the ion source gas (comprising gas-carrying gas) of gas ion all enters the inside of ICP etching chamber through gas inlet 20, and inert gas is ionized to form plasma 60 (comprising inert gas ion), and the precursor gas of cyano radical is in plasma
  • the cyano radicals are formed in the ICP etching chamber, and the wafer 70 (wafer, whose diameter may be 300 mm) is etched cooperatively by using the cyano radicals and inert gas ions.
  • the material of the bottom electrode may be selected from any one or a combination of titanium (Ti) and titanium nitride (TiN).
  • step S20 may include: after forming the bottom electrode layer and before forming the magnetic tunnel junction layer, planarizing the bottom electrode layer by using a chemical mechanical planarization (Chemical Mechanical Planarization, CMP) process to Obtain planarization requirements for fabricating MTJ cells.
  • CMP Chemical Mechanical Planarization
  • the magnetic tunnel junction layer may include multiple film layers
  • the magnetic tunnel junction layer may include a reference layer, a barrier layer and a free layer
  • the above step S20 may include: sequentially forming a bottom electrode layer, a reference layer, a barrier layer, a free layer and a hard mask on the substrate layer;
  • the magnetic tunnel junction layer may include a synthetic antiferromagnetic layer, a reference layer, a barrier layer and a free layer
  • the above step S20 may include: sequentially forming a bottom electrode layer, an antiferromagnetic layer, a reference layer on the substrate layer, barrier layer, free layer and hard mask layer;
  • the magnetic tunnel junction layer may include a synthetic antiferromagnetic layer, a ferromagnetic coupling layer, a reference layer, a barrier layer, and a free layer
  • the above step S20 may include: sequentially forming a bottom electrode layer on the substrate, synthesizing Antiferromagnetic layer, ferromagnetic coupling layer, reference layer, barrier layer, free layer and hard mask layer.
  • the total thickness of the magnetic tunnel junction layer may be 10 nm to 20 nm, and has a bottom pinned (Bottom Pinned) structure.
  • the reference layer has magnetic polarization invariance
  • the reference layer of vertical MRAM generally includes [Co/Ni] n Co/(Ru or Ir)/Co[Ni/Co ] m , [Co/Pd] n Co/(Ru or Ir)/Co[Pd/Co] m , or [Co/Pt] n Co/(Ru or Ir)/Co[Pt/Co] m supercrystal Lattice multilayer film structure, 0 ⁇ m ⁇ 3, 2 ⁇ n ⁇ 7, and can be realized through the lattice barrier layer and cobalt iron boron (CoFeB), cobalt iron (CoFe)/cobalt iron boron (CoFeB), iron oxide Cobalt (CoFe)/nickel-iron alloy (NiFe), cobalt boride (CoB) or iron boride (FeB) ferromagnetic coupling; the total thickness of the reference layer may be
  • the material of the barrier layer can be a non-magnetic metal oxide, for example, it can be magnesium oxide (MgO), magnesium zinc oxide (MgZnO), magnesium boron oxide (MgBO), magnesium aluminum oxide (MgAlO), preferably magnesium oxide (MgO); the thickness of the barrier layer may be 0.5nm to 2.5nm.
  • MgO magnesium oxide
  • MgZnO magnesium zinc oxide
  • MgBO magnesium boron oxide
  • MgAlO magnesium aluminum oxide
  • MgO magnesium oxide
  • the thickness of the barrier layer may be 0.5nm to 2.5nm.
  • the free layer has a variable magnetic polarization
  • the material of the vertical pSTT-MRAM free layer can be cobalt-iron-boron (CoFeB), CoFe/cobalt-iron-boron (CoFeB), iron (Fe)/ Cobalt-iron-boron (CoFeB), cobalt-iron-boron (CoFeB)/tungsten (W)/cobalt-iron-boron (CoFeB), cobalt-iron-boron (CoFeB)/molybdenum (Mo)/cobalt-iron-boron (CoFeB); the free layer
  • the thickness may be 0.8nm to 2.3nm.
  • the hard mask layer may serve as a top electrode layer forming a top electrode.
  • the material of the hard mask layer can be tantalum (Ta), tantalum nitride (TaN) or tantalum (Ta)/tantalum nitride (TaN), in order to obtain better engraved contours in halogen plasma and in MTJ and its A higher etching selectivity ratio is obtained during BE etching; the thickness of the hard mask layer may be 20nm to 100nm.
  • a sacrificial mask layer may be deposited on the hard mask layer, and its forming material may be selected from silicon oxide (SiO 2 ), silicon carbide (SiC), silicon oxynitride (SiON), silicon nitride (SiN), and nitrocarburized Any one or more of silicon (SiCN).
  • step S30 may include: using a tri-layer mask (Tri-layer) mode, completing pattern definition on the magnetic tunnel junction layer and completing reactive ion etching (RIE) on the hard mask layer, And the residual polymer is removed by RIE process and/or wet process, so that the pattern is transferred to the top of the magnetic tunnel junction layer.
  • Tri-layer tri-layer mask
  • RIE reactive ion etching
  • the manufacturing method may further include: during step S40 and/or after step S40 is completed, using ion beam etching to trim the sidewall of the magnetic tunnel junction to obtain the semiconductor device, In order to eliminate the re-deposition and etching damage caused by the etching in the previous step.
  • the ion source gas for ion beam etching may be selected from any one or more of neon, argon, krypton, and xenon.
  • the manufacturing method may further include: after trimming the sidewalls of the magnetic tunnel junction, depositing an insulating layer around the magnetic tunnel junction and on the surface of the top electrode and the bottom electrode to protect the magnetic tunnel junction , top and bottom electrodes.
  • the material of the insulating layer may be selected from silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO x ), silicon oxynitride (SiON) and silicon carbide nitride (SiCN) any one or more of them.
  • the embodiment of the present application also provides a semiconductor device, which can be obtained by the above-mentioned manufacturing method.
  • the diameter of the magnetic tunnel junction (ie, a single pattern of the patterned magnetic tunnel junction layer) of the semiconductor device may be Sub-80nm, Sub-70nm, Sub-60nm or Sub-50nm.
  • the semiconductor device may be a magnetic tunnel junction array.
  • the semiconductor device may be a magnetic random access memory (MRAM) including a magnetic tunnel junction array.
  • MRAM magnetic random access memory
  • the embodiment of the present application also provides an electronic device, including the semiconductor device provided in the above embodiment of the present application.
  • the electronic device may include electronic devices such as a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
  • electronic devices such as a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
  • the manufacturing method of the semiconductor device of this embodiment includes:
  • S10 Provide a surface-polished CMOS substrate 100 with a non-copper (Cu) through hole 120, and the substrate 100 is a dielectric 110 except the through hole 120, as shown in FIG. 6A;
  • Cu non-copper
  • the bottom electrode layer 210 forming the bottom electrode (Bottom Electrode, BE), the magnetic tunnel junction layer 220 forming the magnetic tunnel junction (MTJ), and the hard mask layer 230 (which can form the top electrode) are sequentially deposited.
  • Bottom Electrode, TE also known as the top electrode layer
  • the material for forming the bottom electrode layer 210 is generally Ti or TiN, etc.; moreover, generally after the bottom electrode layer 210 is deposited and formed, the bottom electrode layer 210 is planarized by a chemical mechanical planarization process to obtain a fabricated The planarization requirements of the MTJ unit;
  • the magnetic tunnel junction layer 220 includes a plurality of film layers with a total thickness of 10nm to 20nm, which is formed by sequentially stacking up a reference layer, a barrier layer and a free layer and has a bottom pinned structure;
  • the reference layer has magnetic polarization invariance
  • the reference layer of vertical MRAM generally includes [Co/Ni] n Co/(Ru or Ir)/Co[Ni/Co] m , [Co/Pd] n Co/(Ru or Ir)/Co[Pd/Co] m , or [Co/Pt] n Co/(Ru or Ir)/Co[Pt/Co] m superlattice multilayer film structure, and can Cobalt iron boron (CoFeB), cobalt iron (CoFe)/cobalt iron boron (CoFeB), cobalt iron (CoFe)/nickel iron alloy (NiFe), cobalt boride (CoB) or boride Ferromagnetic coupling of iron (FeB), the total thickness of which can be from 4nm to 15nm;
  • the material of the barrier layer can be a non-magnetic metal oxide, preferably magnesium oxide (MgO), and its thickness can be 0.5nm to 2.5nm;
  • the free layer has variable magnetic polarization
  • the material of the vertical pSTT-MRAM free layer can be cobalt iron boron (CoFeB), CoFe/cobalt iron boron (CoFeB), iron (Fe)/cobalt iron boron (CoFeB), cobalt Iron boron (CoFeB)/tungsten (W)/cobalt iron boron (CoFeB), cobalt iron boron (CoFeB)/molybdenum (Mo)/cobalt iron boron (CoFeB), the thickness can be 0.8nm to 2.3nm;
  • the thickness of the hard mask layer 230 can be 20nm to 100nm, and the material can be tantalum (Ta), tantalum nitride (TaN) or tantalum (Ta)/tantalum nitride (TaN), in order to obtain more Easy to profile and obtain higher etching selectivity when MTJ and its BE are etched;
  • a sacrificial mask layer can be deposited on the hard mask layer 230, and the material of the sacrificial mask layer can be silicon oxide (SiO x ), silicon carbide (SiC), silicon oxynitride (SiON), silicon nitride ( SiN) or silicon carbide nitride (SiCN), etc.;
  • S30 Graphically define the pattern of the magnetic tunnel junction layer 220, and transfer the pattern to the top of the magnetic tunnel junction layer 220;
  • the three-layer mask (Tri-layer) mode is used to complete the pattern definition of the magnetic tunnel junction layer 220 and complete the reactive ion etching (RIE) on the hard mask layer 230, and use the RIE process and/or or a wet process to remove the residual polymer so that the pattern is transferred to the top of the magnetic tunnel junction layer 220;
  • RIE reactive ion etching
  • a precursor gas of a cyano radical may comprise: providing a precursor gas of a cyano radical, and providing a plasma such that the precursor gas of a cyano radical is formed in the plasma, for example, a plasma formed by a precursor gas of a cyano radical and an inert gas cyano radicals, chemically react the cyano radicals with the patterned magnetic tunnel junction layer 220 and the hard mask layer 230 and/or use the cyano radicals to react the patterned magnetic tunnel junction layer 220 and the hard mask
  • the material of the membrane layer 230 is chemically modified, and the ion source gas of the inert gas ions is formed into inert gas ions, and the chemical reaction product and/or the chemically modified material and/or the chemically-reacted and/or unreacted Chemically modified patterned magnetic tunnel junction layer 220 and hard mask layer 230 material removal;
  • the precursor gas of the cyano radical can be selected from HCN, (CN) 2 , CH 3 CN, a mixed gas of CH 4 and NH 3 , a mixed gas of CH 3 OH and NH 3 , CH 3 CH 2 OH Any one or more of the mixed gases with NH 3 ;
  • the pressure when the chemical reaction and/or the chemical modification is carried out can be 0.3mTorr to 10mTorr;
  • the ion source gas of the inert gas ions can include any one or more of neon, argon, krypton, and xenon, and any one of CO, CO 2 , N 2 , O 2 and He can be added or more as gas-carrying;
  • the total flow of the precursor gas of the cyano radical and the ion source gas of the inert gas ion can be 100sccm to 2000sccm;
  • the power of the RF source power (RF Source Power) that generates and maintains the plasma can be 100 watt to 3000 watt;
  • the frequency of the radio frequency source power supply can be 13.56MHz;
  • the ion acceleration voltage provided by RF Bias Power can be 30V to 1000V; and the ion acceleration voltage can adopt pulse bias;
  • the frequency of the RF bias power supply can be 13.56MHz, 2MHz or 400kHz;
  • step S50 During step S40 and/or after step S40 is completed, ion beam etching is used to trim the sidewall of the magnetic tunnel junction to obtain the semiconductor device;
  • the ion source gas for ion beam etching can be selected from any one or more of neon, argon, krypton, and xenon;
  • S60 Deposit an insulating layer 240 around the magnetic tunnel junction 220' of the semiconductor device, and make the insulating layer 240 cover the top electrode 230' and the bottom electrode 210', as shown in FIG. 6D;
  • the material of the insulating layer 240 may be silicon nitride (SiN), silicon oxide (SiO x ), silicon carbide (SiC), silicon oxynitride (SiON) or silicon carbide nitride (SiCN) and the like.

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Abstract

一种半导体器件及其制造方法、电子设备，所述制造方法包括：提供基底（100）；在基底（100）上形成底电极层（210）、磁性隧道结层（220）和硬掩膜层（230）；对磁性隧道结层（220）和硬掩膜层（230）进行图案化；提供氰基自由基的前驱体气体，并提供等离子体，使氰基自由基的前驱体气体在等离子体中形成氰基自由基，采用氰基自由基对图案化的磁性隧道结层（220）和硬掩膜层（230）的材料进行化学处理，并采用惰性气体离子将所述化学处理的产物和未经过化学处理的图案化的磁性隧道结层（220）和硬掩膜层（230）的材料移除，得到半导体器件。

Description

半导体器件及其制造方法、电子设备
本申请要求于2022年01月28日提交中国专利局、申请号为2022101063939、发明名称为“一种磁性隧道结阵列及其制造方法”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本申请涉及半导体器件领域，尤指一种半导体器件及其制造方法、电子设备。
背景技术
磁性随机存取存储器(Magnetic Random Access Memory,MRAM)是以磁电阻性质来存储数据的随机存储器，它具有高速读写、大容量以及低能耗的特点。MRAM的核心存储器件是磁性隧道结(Magnetic Tunnel Junction,MTJ)。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制本申请的保护范围。
本申请实施例提供了一种半导体器件的制造方法，所述制造方法包括：
提供基底；
在所述基底上依次形成底电极层、磁性隧道结层和硬掩膜层；
对所述磁性隧道结层和所述硬掩膜层进行图案化；
提供氰基自由基的前驱体气体，并提供等离子体，使氰基自由基的前驱体气体在等离子体中形成氰基自由基，采用所述氰基自由基对图案化的磁性隧道结层和硬掩膜层的材料进行化学处理，并使惰性气体离子的离子源气体形成惰性气体离子，采用所述惰性气体离子将所述化学处理的产物和未经过化学处理的图案化的磁性隧道结层和硬掩膜层的材料移除，得到所述半导体 器件；
其中，所述化学处理为化学反应、或化学修饰、或化学反应和化学修饰。
在本申请的实施例中，所述磁性隧道结层的材料可以包括铁、钴、钴铁硼、镍、钨、钼、铬、钌、铱、钯、铂、氧化镁、铝、锌、钛和铑中的任意一种或多种。
在本申请的实施例中，所述硬掩膜层的材料可以选自钽和氮化钽中的任意一种或多种。
在本申请的实施例中，所述氰基自由基的前驱体气体可以选自HCN、(CN) 2、CH 3CN、CH 4与NH 3的混合气体、CH 3OH与NH 3的混合气体、CH 3CH 2OH与NH 3的混合气体中的任意一种或多种。
在本申请的实施例中，所述化学处理进行时的压强可以为0.3mTorr至10mTorr。
在本申请的实施例中，所述惰性气体离子的离子源气体可以包括氖气、氩气、氪气、氙气中的任意一种或多种。
在本申请的实施例中，所述惰性气体离子的离子源气体还可以包括携气，所述携气可以选自CO、CO 2、N 2、O 2和He中的任意一种或多种。
在本申请的实施例中，所述氰基自由基的前驱体气体和所述惰性气体离子的离子源气体的总流量可以为100sccm至2000sccm。
在本申请的实施例中，产生并维持所述等离子体的射频源电源的功率可以为100watt至3000watt。
在本申请的实施例中，所述射频源电源的频率可以为13.56MHz。
在本申请的实施例中，所述采用所述惰性气体离子将所述化学处理的产物和未经过化学处理的图案化的磁性隧道结层和硬掩膜层的材料移除可以包括：采用射频偏压电源将所述惰性气体离子加速，并采用加速后的惰性气体离子对所述化学处理的产物和未经过化学处理的图案化的磁性隧道结层和硬掩膜层的材料进行轰击以将材料移除。
在本申请的实施例中，射频偏压电源提供的离子加速电压可以为30V至1000V。
在本申请的实施例中，所述射频偏压电源的频率可以为13.56MHz至400kHz，例如，可以为13.56MHz、2MHz或400kHz。
在本申请的实施例中，所述形成氰基自由基、所述化学处理、以及采用所述惰性气体离子进行移除的过程可以在电感耦合等离子体刻蚀腔体中进行。
在本申请的实施例中，所述制造方法还可以包括：
在所述形成氰基自由基、所述化学处理、以及采用所述惰性气体离子进行移除的过程中，采用离子束刻蚀对图案化的磁性隧道结层的侧壁进行修剪，得到所述半导体器件；或者，
在采用所述惰性气体离子进行移除之后，采用离子束刻蚀对图案化的磁性隧道结层的侧壁进行修剪，得到所述半导体器件；
在所述形成氰基自由基、所述化学处理、以及采用所述惰性气体离子进行移除的过程中，以及在采用所述惰性气体离子进行移除之后，采用离子束刻蚀对图案化的磁性隧道结层的侧壁进行修剪，得到所述半导体器件。
在本申请的实施例中，所述离子束刻蚀的离子源气体可以选自氖气、氩气、氪气、氙气中的任意一种或多种。
本申请实施例还提供了一种半导体器件，其通过如上所述的制造方法得到。
在本申请的实施例中，所述半导体器件的磁性隧道结的直径可以为亚80nm、亚70nm、亚60nm或亚50nm。
本申请实施例还提供了一种电子设备，包括如上本申请实施例提供的所述半导体器件。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为采用IBE对特定刻蚀前端进行刻蚀过程中的溅射速率和沉积速率随入射角的变化曲线；
图2为阴影效应的形成原理示意图；
图3为能够与氰基自由基发生化学反应和/或化学修饰的金属以及反应产物图；
图4为步骤S40的进行过程示意图；
图5为ICP刻蚀腔体的结构示意图以及在不同的射频偏压电源频率下离子能量分布随离子通量的变化图；
图6A为本申请示例性实施例的半导体器件的制造方法的得到的中间品的结构示意图；
图6B为本申请示例性实施例的半导体器件的制造方法的得到的中间品的结构示意图；
图6C为本申请示例性实施例的半导体器件的制造方法的得到的中间品的结构示意图；
图6D为本申请示例性实施例的半导体器件的结构示意图。
附图中的标记符号的含义为：
10-刻蚀前端；20-气体入口；30-射频源电源；40-射频偏压电源；50-带节流阀的节气门位置传感器；60-等离子体；70-晶片；100-基底；110-电介质；120-通孔；210-底电极层；210’-底电极；220-磁性隧道结层；220’-磁性隧道结；230-硬掩膜层；230’-顶电极；240-绝缘层。
详述
本文中的实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是实现方式和内容可以在不脱离本申请的宗旨及其范围的条件下被变换为各种各样的形式。因此，本申请不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
本申请中的附图比例可以作为实际工艺中的参考，但不限于此。例如：各个膜层的厚度和间距等，可以根据实际需要进行调整。本申请的一个方式不局限于附图所示的形状或数值等。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“垂直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“设置”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
目前主流的半导体刻蚀工艺为反应离子刻蚀(Reactive Ion Etching,RIE)。在刻蚀多晶硅或金属的时候，一般采用卤素气体(例如Cl 2)作为主刻蚀气体，卤素气体在等离子体中形成卤素自由基，卤素自由基与待刻蚀材料进行化学反应，将反应产物抽走即可实现刻蚀。然而，形成MTJ的某些材料，例如Fe、Co、Mg、Ru、Pt、Pd、Al、Rh、Mo、Ni或Ir等，根本不或者非常难与在等离子体中形成的卤素自由基发生反应而被抽走；而且，后续去卤工艺会引入H 2O，这是MTJ制造工艺不能接受的。故而，传统的RIE不适用于MTJ阵列的刻蚀。
目前，低密度的MTJ阵列一般采用离子束刻蚀(Ion Beam Etching,IBE)方案。IBE利用辉光放电原理将氩气离化为Ar +，Ar +经过阳极电场的加速对样品表面进行物理轰击，以达到刻蚀的作用。图1为采用IBE对特定的刻蚀前端10进行刻蚀过程中的溅射速率和沉积速率随入射角的变化曲线。如图1所示，由于IBE的副产物并不是气体，副产物会进行再次沉积，所以IBE是一个溅射和沉积的动态平衡过程。对于特定的刻蚀前端(Etch Front)10来说， 溅射速率会随着Ar +或Ar的入射角θ变化而变化，而沉积速率并不会随着Ar +或Ar的入射角变化而变化。不过，沉积速率并不是不变的，沉积速率与该特定刻蚀前端10所处的周围环境强相关，并随着时间的推延会动态变化。为了获得较大的溅射速率，一般Ar +或Ar的入射方向都会与刻蚀前端10的法线维持一个倾角θ，特别是沉积速率较大的时候。对特定的刻蚀前端10，当沉积速率大于溅射速率时，可以增大Ar +或Ar入射方向的倾角θ，使溅射速率增大，从而实现特定刻蚀前端10的材料移除。然而，如图2所示，随着被刻蚀区域几何尺寸的缩小，Ar +或Ar入射方向的倾角θ的增大空间有限，导致增大倾角θ所带来的溅射速率增大也不能使溅射速率大于沉积速率，进而无法满足特定刻蚀前端10的材料移除条件，此时“材料移除”(即，刻蚀)会停止，该特定的刻蚀前端10处于材料能被移除的倾角θ的Ar +或Ar束阴影处，这种效应叫阴影效应(Shadowing Effect)。图2为阴影效应的形成原理示意图。由于阴影效应的存在，IBE并不是高密度MTJ阵列的最佳刻蚀方案。
本申请实施例提供一种半导体器件的制造方法，包括：
S10：提供基底；
S20：在所述基底上依次形成底电极层、磁性隧道结层和硬掩膜层；
S30：对所述磁性隧道结层和硬掩膜层进行图案化；
S40：提供氰基自由基的前驱体气体，并提供等离子体，使氰基自由基的前驱体气体在等离子体中形成氰基自由基，采用所述氰基自由基对图案化的磁性隧道结层和硬掩膜层的材料进行化学处理，并使惰性气体离子的离子源气体形成惰性气体离子，采用所述惰性气体离子将所述化学处理的产物和未经过化学处理的图案化的磁性隧道结层和硬掩膜层的材料移除，得到所述半导体器件；
其中，所述化学处理为化学反应、或化学修饰、或化学反应和化学修饰。
本申请实施例的半导体器件的制造方法采用氰基自由基和惰性气体离子进行协同刻蚀(包括采用氰基自由基对图案化的磁性隧道结层和硬掩膜层的材料进行化学反应和/或化学修饰，以及采用惰性气体离子对材料进行物理轰击移除，实现协同刻蚀)，由于化学反应和化学修饰是各向同性的，化学刻 蚀副产物的黏附系数(Sticking Coefficient)要小于物理刻蚀的黏附系数，这将有效降低甚至避免IBE刻蚀的阴影效应问题；而且，惰性气体离子对经过化学反应和/或化学修饰以及未经过化学反应和化学修饰的材料通过物理轰击进行移除，可以大大增大移除效率。因此，本申请实施例的半导体器件的制造方法有利于MTJ的缩微化，适于制备高密度的MRAM存储器，例如，制备直径为Sub-80nm、Sub-70nm、Sub-60nm或Sub-50nm的MTJ阵列。
在本申请的实施例中，所述基底可以为互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)基底。
在本申请的实施例中，所述磁性隧道结层的材料可以包含铁(Fe)、钴(Co)、钴铁硼(CoFeB)、镍(Ni)、钨(W)、钼(Mo)、铬(Cr)、钌(Ru)、铱(Ir)、钯(Pd)、铂(Pt)、氧化镁(MgO)、铝(Al)、锌(Zn)、钛(Ti)和铑(Rh)等中的任意一种或多种。
目前，组成磁性隧道结(MTJ)的材料为重金属或磁性金属，比如：铁(Fe)、钴(Co)、镍(Ni)、钨(W)、钼(Mo)、铬(Cr)、钌(Ru)、铱(Ir)、钯(Pd)、铂(Pt)、镁(Mg)、铝(Al)、锌(Zn)、钛(Ti)、铑(Rh)和钽(Ta)等。本申请的发明人在进行磁性隧道结研究时发现，在等离子中形成的常规自由基非常难与这些材料发生化学反应或者是对其进行化学修饰，但在等离子体中形成的氰基自由基(-C≡N，Cyano-Group Radical)能与除了Ta之外的其它金属发生化学反应和/或化学修饰。
图3为本申请的发明人总结出的能够与氰基自由基发生化学反应和/或化学修饰的金属以及反应产物图。如图3所示，在等离子体中形成的氰基自由基可以与Fe、Co、Ni、Mg、Pt、Pd、Al、Zn、Ru、Ir、W、Ti、Rh、Mo等惰性金属发生络合化学反应和/或化学修饰，生成Fe(CN) 3、Co(CN) 2、Co(CN) 3、Ni(CN) 2、Mg(CN) 2、Pd(CN) 2、Al(CN) 3、Zn(CN) 2、Pt(CN) 2、Ru(CN) 3、Ir(CN) 3、W(CN) 4、Ti(CN) 4、Rh(CN) 3、Mo(CN) 4等。图4为步骤S40的进行过程示意图。
在目前的主流的MTJ主堆叠层中，已经抛弃了Ta做层间耦合层材料(作为层间耦合层的Ta不能经受400℃CMOS后端退火工艺)；而且由于Ta并不与氰基自由基发生化学反应或化学修饰，因此可以作为MTJ硬掩模(HM) 层材料。
在本申请的实施例中，所述硬掩膜层的材料可以选自钽(Ta)和氮化钽(TaN)中的任意一种或多种。
在本申请的实施例中，所述氰基自由基的前驱体气体可以选自HCN、(CN) 2、CH 3CN、CH 4与NH 3的混合气体、CH 3OH与NH 3的混合气体、CH 3CH 2OH与NH 3的混合气体中的任意一种或多种。这些气体在等离子体，例如，由氰基自由基的前驱体气体和惰性气体形成的等离子体中均可以产生氰基自由基。
在本申请的实施例中，所述化学处理进行时的压强可以为0.3mTorr至10mTorr。
在本申请的实施例中，所述惰性气体离子的离子源气体可以包括氖气、氩气、氪气、氙气中的任意一种或多种，并可以添加CO、CO 2、N 2,、O 2和He中的任意一种或多种作为携气。
步骤S40中，为了获得较好的移除效果，可以尽可能选用大抽力的涡轮增压分子泵(TMP)和较大的气体(包括所述氰基自由基的前驱体气体和所述惰性气体离子的离子源气体)流量。在本申请的实施例中，所述氰基自由基的前驱体气体和惰性气体离子的离子源气体的总流量可以为100sccm至2000sccm。
在本申请的实施例中，产生并维持所述等离子体的射频源电源(RF Source Power)的功率可以为100watt至3000watt。在本申请的实施例中，所述射频源电源的频率可以为13.56MHz。
在本申请的实施例中，所述采用所述惰性气体离子将所述化学处理的产物和未经过化学处理的图案化的磁性隧道结层和硬掩膜层的材料移除可以包括：采用射频偏压电源(RF Bias Power)将所述惰性气体离子加速，并采用加速后的惰性气体离子对所述化学处理的产物和未经过化学处理的图案化的磁性隧道结层和硬掩膜层的材料进行轰击以将材料移除。
在本申请的实施例中，所述射频偏压电源提供的离子加速电压可以为30V至1000V。
在本申请的实施例中，离子加速电压可以采用脉冲偏压，即在加偏压与不加偏压之间进行反复循环，基于化学反应和/或化学修饰与单纯只有物理刻蚀的反复循环等一系列类似原子层刻蚀(Atomic Layer Etching,ALE)的理念，以获得较佳的刻蚀效果。
在本申请的实施例中，所述射频偏压电源的频率可以为13.56MHz至400kHz，例如，可以为13.56MHz、2MHz或400kHz，还例如，可以为400kHz。
在本申请的实施例中，为了减少反应副产物的再次沉积，必须减少其停留时间(Residence Time，Г res)，其中：Г res＝PV/flow＝V/C sccm/mTorr，P为工作压强，V为反应腔体的体积，flow为气体流量，C sccm/mTorr为反应刻蚀腔体的抽力的关键指标。
在本申请的实施例中，步骤S40可以在电感耦合等离子体(Inductively Coupled Plasma，ICP)刻蚀腔体中进行。图5为ICP刻蚀腔体的结构示意图以及在不同的射频偏压电源频率下离子能量分布随离子通量的变化图。如图5左图所示，ICP刻蚀腔体包括气体入口20、射频源电源30、射频偏压电源40、带节流阀的节气门位置传感器50；氰基自由基的前驱体气体、惰性气体离子的离子源气体(包括携气)都通过气体入口20进入ICP刻蚀腔体内部，惰性气体被电离形成等离子体60(包括惰性气体离子)，氰基自由基的前驱体气体在等离子体中形成氰基自由基，在ICP刻蚀腔体内采用氰基自由基和惰性气体离子对晶片70(wafer，直径可以为300mm)进行协同刻蚀。
在本申请的实施例中，所述底电极的材料可以选自钛(Ti)和氮化钛(TiN)中的任意一种或多种的组合。
在本申请的实施例中，步骤S20可以包括：在形成底电极层之后，形成磁性隧道结层之前，采用化学机械平坦化(Chemical Mechanical Planarization，CMP)工艺对底电极层进行平坦化处理，以获得制作MTJ单元的平坦化要求。
在本申请的实施例中，所述磁性隧道结层可以包括多个膜层；
例如，所述磁性隧道结层可以包括参考层、势垒层和自由层，上述步骤S20可以包括：在所述基底上依次形成底电极层、参考层、势垒层、自由层和硬掩膜层；
又例如，所述磁性隧道结层可以包括合成反铁磁层、参考层、势垒层和自由层，上述步骤S20可以包括：在所述基底上依次形成底电极层、反铁磁层、参考层、势垒层、自由层和硬掩膜层；
再例如，所述磁性隧道结层可以包括合成反铁磁层、铁磁耦合层、参考层、势垒层和自由层，上述步骤S20可以包括：在所述基底上依次形成底电极层、合成反铁磁层、铁磁耦合层、参考层、势垒层、自由层和硬掩膜层。
在本申请的实施例中，所述磁性隧道结层的总厚度可以为10nm至20nm，并且具有底部钉扎(Bottom Pinned)结构。
在本申请的实施例中，所述参考层具有磁极化不变性，垂直型MRAM(pSTT-MRAM)的参考层一般包括[Co/Ni] nCo/(Ru或Ir)/Co[Ni/Co] m、[Co/Pd] nCo/(Ru或Ir)/Co[Pd/Co] m、或[Co/Pt] nCo/(Ru或Ir)/Co[Pt/Co] m的超晶格多层膜结构，0≤m≤3，2≤n≤7，并可以通过晶格隔断层实现与钴铁硼(CoFeB)、铁化钴(CoFe)/钴铁硼(CoFeB)、铁化钴(CoFe)/镍铁合金(NiFe)、硼化钴(CoB)或硼化铁(FeB)的铁磁耦合；所述参考层的总厚度可以为4nm至15nm。
在本申请的实施例中，所述势垒层的材料可以为非磁性金属氧化物，例如，可以为氧化镁(MgO)、氧化镁锌(MgZnO)、氧化镁硼(MgBO)、氧化镁铝(MgAlO)，优选为氧化镁(MgO)；所述势垒层的厚度可以为0.5nm至2.5nm。
在本申请的实施例中，所述自由层具有可变磁极化，垂直型pSTT-MRAM自由层的材料可以为钴铁硼(CoFeB)、CoFe/钴铁硼(CoFeB)、铁(Fe)/钴铁硼(CoFeB)、钴铁硼(CoFeB)/钨(W)/钴铁硼(CoFeB)、钴铁硼(CoFeB)/钼(Mo)/钴铁硼(CoFeB)；所述自由层的厚度可以为0.8nm至2.3nm。
所述硬掩膜层可以作为形成顶电极的顶电极层。所述硬掩膜层的材料可以为钽(Ta)、氮化钽(TaN)或钽(Ta)/氮化钽(TaN)，以期在卤素电浆中获得更好刻轮廓和在MTJ及其BE刻蚀的时候获得更高刻蚀选择比；所述硬掩膜层的厚度可以为20nm至100nm。
另外，可以在硬掩模层上沉积牺牲掩模层，其形成材料可以选自氧化硅 (SiO 2)、碳化硅(SiC)、氮氧化硅(SiON)、氮化硅(SiN)和氮碳化硅(SiCN)中的任意一种或多种。
在本申请的实施例中，步骤S30可以包括：采用三层掩模(Tri-layer)的模式，对磁性隧道结层完成图形化定义和对硬掩模层完成反应离子刻蚀(RIE)，并采用RIE工艺和/或湿法工艺除去残留的聚合物，以使图案转移到磁性隧道结层的顶部。
在本申请的实施例中，所述制造方法还可以包括：在步骤S40进行过程中和/或步骤S40完成之后，采用离子束刻蚀对磁性隧道结侧壁进行修剪，得到所述半导体器件，以消除上一步骤的刻蚀带来的再次沉积和刻蚀损伤。
在本申请的实施例中，所述离子束刻蚀的离子源气体可以选自氖气、氩气、氪气、氙气中的任意一种或多种。
在本申请的实施例中，所述制造方法还可以包括：在对磁性隧道结侧壁进行修剪之后，在磁性隧道结周围和顶电极、底电极表面沉积绝缘层，以对所述磁性隧道结、顶电极和底电极进行覆盖。
在本申请的实施例中，所述绝缘层的材料可以选自氮化硅(SiN)、碳化硅(SiC)、氧化硅(SiO x)、氮氧化硅(SiON)和氮碳化硅(SiCN)中的任意一种或多种。
本申请实施例还提供了一种半导体器件，所述半导体器件可以通过如上所述的制造方法得到。在本申请的实施例中，所述半导体器件的磁性隧道结(即图案化的磁性隧道结层的单个图案)的直径可以为Sub-80nm、Sub-70nm、Sub-60nm或Sub-50nm。
在本申请的实施例中，所述半导体器件可以为磁性隧道结阵列。
在本申请的实施例中，所述半导体器件可以为含有磁性隧道结阵列的磁性随机存取存储器(MRAM)。
本申请实施例还提供了一种电子设备，包括如上本申请实施例提供的所述半导体器件。
在本申请实施例中，所述电子设备可以包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源等电子设备。
下面将结合本申请的一些示例性实施例来详细阐述本申请的技术方案。
本实施例的半导体器件的制造方法，如图6A至图6D所示，包括：
S10：提供表面抛光的带非铜(Cu)通孔120的CMOS基底100，基底100上除通孔120之外的为电介质110，如图6A所示；
S20：在CMOS基底100一侧表面依次沉积形成底电极(Bottom Electrode,BE)的底电极层210、形成磁性隧道结(MTJ)的磁性隧道结层220和硬掩膜层230(可以形成顶电极(Top Electrode,TE)，又叫顶电极层)，如图6B所示；
其中，形成所述底电极层210的材料一般为Ti或TiN等；而且，一般在沉积形成底电极层210之后，采用化学机械平坦化的工艺对底电极层210进行平坦化处理，以获得制作MTJ单元的平坦化要求；
所述磁性隧道结层220包括多个膜层，总厚度为10nm至20nm，为由参考层、势垒层和自由层依次向上叠加形成且具有底部钉扎的结构；
所述参考层具有磁极化不变性，垂直型MRAM(pSTT-MRAM)的参考层一般包括[Co/Ni] nCo/(Ru或Ir)/Co[Ni/Co] m、[Co/Pd] nCo/(Ru或Ir)/Co[Pd/Co] m、或[Co/Pt] nCo/(Ru或Ir)/Co[Pt/Co] m的超晶格多层膜结构，并可以通过晶格隔断层实现与钴铁硼(CoFeB)、铁化钴(CoFe)/钴铁硼(CoFeB)、铁化钴(CoFe)/镍铁合金(NiFe)、硼化钴(CoB)或硼化铁(FeB)的铁磁耦合，其总厚度可以为4nm至15nm；
所述势垒层的材料可以为非磁性金属氧化物，优选为氧化镁(MgO)，其厚度可以为0.5nm至2.5nm；
所述自由层具有可变磁极化，垂直型pSTT-MRAM自由层的材料可以为钴铁硼(CoFeB)、CoFe/钴铁硼(CoFeB)、铁(Fe)/钴铁硼(CoFeB)、钴铁硼(CoFeB)/钨(W)/钴铁硼(CoFeB)、钴铁硼(CoFeB)/钼(Mo)/钴铁硼(CoFeB)，其厚度可以为0.8nm至2.3nm；
所述硬掩膜层230的厚度可以为20nm至100nm，材料可以为钽(Ta)、氮化钽(TaN)或钽(Ta)/氮化钽(TaN)，以期在卤素电浆中获得更好刻轮廓和在MTJ及其BE刻蚀的时候获得更高刻蚀选择比；
可以在硬掩模层230上沉积一层牺牲掩模层，所述牺牲掩模层的材料可以为氧化硅(SiO x)、碳化硅(SiC)、氮氧化硅(SiON)、氮化硅(SiN)或氮碳化硅(SiCN)等；
S30：图形化定义磁性隧道结层220的图案，并且转移图案到磁性隧道结层220的顶部；
在此过程中，采用三层掩模(Tri-layer)的模式，对磁性隧道结层220完成图形化定义和对硬掩模层230完成反应离子刻蚀(RIE)，并采用RIE工艺和/或湿法工艺除去残留的聚合物，以使图案转移到磁性隧道结层220的顶部；
S40：采用氰基自由基与惰性气体离子协同刻蚀的方案对磁性隧道结层220以及底电极层210进行刻蚀，如图6C所示；
可以包括：提供氰基自由基的前驱体气体，并提供等离子体，使氰基自由基的前驱体气体在等离子体，例如由氰基自由基的前驱体气体和惰性气体形成的等离子体中形成氰基自由基，将氰基自由基与图案化的磁性隧道结层220和硬掩膜层230的材料进行化学反应和/或采用氰基自由基对图案化的磁性隧道结层220和硬掩膜层230的材料进行化学修饰，并使惰性气体离子的离子源气体形成惰性气体离子，采用所述惰性气体离子将化学反应产物和/或被化学修饰的材料和/或未发生化学反应并且未被化学修饰的图案化的磁性隧道结层220和硬掩膜层230的材料移除；
其中，所述氰基自由基的前驱体气体可以选自HCN、(CN) 2、CH 3CN、CH 4与NH 3的混合气体、CH 3OH与NH 3的混合气体、CH 3CH 2OH与NH 3的混合气体中的任意一种或多种；
所述化学反应和/或所述化学修饰进行时的压强可以为0.3mTorr至10mTorr；
所述惰性气体离子的离子源气体可以包括氖气、氩气、氪气、氙气中的任意一种或多种，并可以添加CO、CO 2、N 2、O 2和He中的任意一种或多种作为携气；
所述氰基自由基的前驱体气体和所述惰性气体离子的离子源气体的总流 量可以为100sccm至2000sccm；
产生并维持所述等离子体的射频源电源(RF Source Power)的功率可以为100watt至3000watt；
所述射频源电源的频率可以为13.56MHz；
射频偏压电源(RF Bias Power)提供的离子加速电压可以为30V至1000V；并且离子加速电压可以采用脉冲偏压；
所述射频偏压电源的频率可以为13.56MHz、2MHz或400kHz；
S50：在步骤S40进行过程中和/或步骤S40完成之后，采用离子束刻蚀对磁性隧道结侧壁进行修剪，得到所述半导体器件；
其中，所述离子束刻蚀的离子源气体可以选自氖气、氩气、氪气、氙气中的任意一种或多种；
S60：在半导体器件的磁性隧道结220’周围沉积一层绝缘层240，并使绝缘层240覆盖顶电极230’和底电极210’，图6D所示；
其中，绝缘层240的材料可以为氮化硅(SiN)、氧化硅(SiO x)、碳化硅(SiC)、氮氧化硅(SiON)或氮碳化硅(SiCN)等。
虽然本申请所揭露的实施方式如上，但所述的内容仅为便于理解本申请而采用的实施方式，并非用以限定本申请。任何本申请所属领域内的技术人员，在不脱离本申请所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (19)

  1. 一种半导体器件的制造方法，包括：
    提供基底；
    在所述基底上依次形成底电极层、磁性隧道结层和硬掩膜层；
    对所述磁性隧道结层和所述硬掩膜层进行图案化；
    提供氰基自由基的前驱体气体，并提供等离子体，使氰基自由基的前驱体气体在等离子体中形成氰基自由基，采用所述氰基自由基对图案化的磁性隧道结层和硬掩膜层的材料进行化学处理，并使惰性气体离子的离子源气体形成惰性气体离子，采用所述惰性气体离子将所述化学处理的产物和未经过化学处理的图案化的磁性隧道结层和硬掩膜层的材料移除，得到所述半导体器件；
    其中，所述化学处理为化学反应、或化学修饰、或化学反应和化学修饰。
  2. 根据权利要求1所述的制造方法，其中，所述磁性隧道结层的材料包括铁、钴、钴铁硼、镍、钨、钼、铬、钌、铱、钯、铂、氧化镁、铝、锌、钛和铑中的任意一种或多种。
  3. 根据权利要求1所述的制造方法，其中，所述硬掩膜层的材料选自钽和氮化钽中的任意一种或多种。
  4. 根据权利要求1所述的制造方法，其中，所述氰基自由基的前驱体气体选自HCN、(CN) 2、CH 3CN、CH 4与NH 3的混合气体、CH 3OH与NH 3的混合气体、CH 3CH 2OH与NH 3的混合气体中的任意一种或多种。
  5. 根据权利要求1至4中任一项所述的制造方法，其中，所述化学处理进行时的压强为0.3mTorr至10mTorr。
  6. 根据权利要求1至4中任一项所述的制造方法，其中，所述惰性气体离子的离子源气体包括氖气、氩气、氪气、氙气中的任意一种或多种。
  7. 根据权利要求6所述的制造方法，其中，所述惰性气体离子的离子源气体还包括携气，所述携气选自CO、CO 2、N 2、O 2和He中的任意一种或多种。
  8. 根据权利要求1至4中任一项所述的制造方法，其中，所述氰基自由基的前驱体气体和所述惰性气体离子的离子源气体的总流量为100sccm至2000sccm。
  9. 根据权利要求1至4中任一项所述的制造方法，其中，产生并维持所述等离子体的射频源电源的功率为100watt至3000watt。
  10. 根据权利要求9所述的制造方法，其中，产生并维持所述等离子体的所述射频源电源的频率为13.56MHz。
  11. 根据权利要求1至4中任一项所述的制造方法，其中，所述采用所述惰性气体离子将所述化学处理的产物和未经过化学处理的图案化的磁性隧道结层和硬掩膜层的材料移除包括：采用射频偏压电源将所述惰性气体离子加速，并采用加速后的惰性气体离子对所述化学处理的产物和未经过化学处理的图案化的磁性隧道结层和硬掩膜层的材料进行轰击以将材料移除。
  12. 根据权利要求11所述的制造方法，其中，所述射频偏压电源提供的离子加速电压为30V至1000V。
  13. 根据权利要求12所述的制造方法，其中，所述射频偏压电源的频率为13.56MHz至400kHz。
  14. 根据权利要求1至4中任一项所述的制造方法，其中，所述形成氰基自由基、所述化学处理、以及采用所述惰性气体离子进行移除的过程在电感耦合等离子体刻蚀腔体中进行。
  15. 根据权利要求至1至14中任一项所述的制造方法，还包括：
    在所述形成氰基自由基、所述化学处理、以及采用所述惰性气体离子进行移除的过程中，采用离子束刻蚀对图案化的磁性隧道结层的侧壁进行修剪，得到所述半导体器件；或者，
    在采用所述惰性气体离子进行移除之后，采用离子束刻蚀对图案化的磁性隧道结层的侧壁进行修剪，得到所述半导体器件；
    在所述形成氰基自由基、所述化学处理、以及采用所述惰性气体离子进行移除的过程中，以及在采用所述惰性气体离子进行移除之后，采用离子束刻蚀对图案化的磁性隧道结层的侧壁进行修剪，得到所述半导体器件。
  16. 根据权利要求至15所述的制造方法，其中，所述离子束刻蚀的离子源气体选自氖气、氩气、氪气、氙气中的任意一种或多种。
  17. 一种半导体器件，通过权利要求至1至16中任一项所述的制造方法得到。
  18. 根据权利要求17所述的半导体器件，其磁性隧道结的直径为亚80nm、亚70nm、亚60nm或亚50nm。
  19. 一种电子设备，包括根据权利要求17或18所述的半导体器件。
PCT/CN2022/110320 2022-01-28 2022-08-04 半导体器件及其制造方法、电子设备 WO2023142420A1 (zh)

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