WO2023142157A1 - 阵列基板和显示面板 - Google Patents

阵列基板和显示面板 Download PDF

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Publication number
WO2023142157A1
WO2023142157A1 PCT/CN2022/075465 CN2022075465W WO2023142157A1 WO 2023142157 A1 WO2023142157 A1 WO 2023142157A1 CN 2022075465 W CN2022075465 W CN 2022075465W WO 2023142157 A1 WO2023142157 A1 WO 2023142157A1
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Prior art keywords
hole
substrate
array substrate
layer
display panel
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PCT/CN2022/075465
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English (en)
French (fr)
Inventor
龙时宇
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武汉华星光电技术有限公司
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Priority to US17/635,804 priority Critical patent/US20240038767A1/en
Publication of WO2023142157A1 publication Critical patent/WO2023142157A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present application relates to the field of display technology, and in particular to an array substrate and a display panel.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • AMOLED Active Matrix/Organic Light Emitting Diode
  • the industry usually uses PLN material as a flat layer, and through holes are made corresponding to the flat layer.
  • the prior art is prepared by exposure and development; however, due to the Limited by the material of the flat layer itself, the taper angle of the through hole is small, and the two sides of the through hole are arc-shaped, resulting in the area occupied by the through hole on the flat layer Larger, so that the area of the pixel is smaller, which in turn leads to a decrease in the aperture ratio of the display product.
  • Embodiments of the present application provide an array substrate and a display panel to alleviate the deficiencies in the related art.
  • an array substrate including:
  • a planar layer located on one side of the first substrate, the planar layer is provided with a first through hole;
  • the cross-sectional area of the first through hole gradually decreases in the direction in which the flat layer points to the first substrate, and the sandwich between the side wall of the first through hole and the bottom surface of the first through hole
  • the angle range is 50° ⁇ 90°.
  • the angle between the sidewall of the first through hole and the side of the planar layer away from the first base is in the range of 90°-130°.
  • the sidewall of the first through hole includes a first portion, and the cross section of the first portion is linear in a direction perpendicular to the first substrate.
  • the cross-section of the sidewall of the first through hole is linear.
  • the first through hole includes a first opening on a side away from the first substrate, and a second opening on a side close to the first substrate;
  • the ratio of the maximum width of the first opening to the maximum width of the second opening is M:N, the range of M is 2-3, and the range of N is 3-4.5.
  • the maximum width of the first opening ranges from 2 microns to 8 microns
  • the maximum width of the second opening ranges from 1.5 microns to 6 microns.
  • the array substrate includes a supporting area, and the orthographic projection of the first through hole on the first substrate is located outside the supporting area.
  • the array substrate further includes a passivation layer located on the side of the planar layer away from the first substrate;
  • the holes are connected to the second through hole, and the angle between the side wall of the second through hole and the first base is in the range of 50°-90°.
  • the angle between the side wall of the second through hole and the first base is the same as the angle between the side wall of the first through hole and the first base
  • the included angles are equal in size.
  • the sum of the depth of the first through hole and the depth of the second through hole ranges from 1 micron to 2.5 microns.
  • the array substrate further includes an electrode layer, and the electrode layer covers the sidewall of the second through hole, the sidewall of the first through hole and the first through hole. bottom of a through hole.
  • An embodiment of the present application provides a display panel, the display panel includes an array substrate, and the array substrate includes:
  • a planar layer located on one side of the first substrate, the planar layer is provided with a first through hole;
  • the cross-sectional area of the first through hole gradually decreases in the direction in which the flat layer points to the first substrate, and the sandwich between the side wall of the first through hole and the bottom surface of the first through hole Angle range is 50° ⁇ 90°.
  • the angle between the sidewall of the first through hole and the side of the flat layer away from the first substrate is in the range of 90°-130°.
  • the sidewall of the first through hole includes a first portion, and a cross section of the first portion is linear in a direction perpendicular to the first substrate.
  • the cross-section of the sidewall of the first through hole is linear.
  • the first through hole includes a first opening on a side away from the first substrate, and a second opening on a side close to the first substrate;
  • the ratio of the maximum width of the first opening to the maximum width of the second opening is M:N, the range of M is 2-3, and the range of N is 3-4.5.
  • the maximum width of the first opening ranges from 2 microns to 8 microns
  • the maximum width of the second opening ranges from 1.5 microns to 6 microns.
  • the array substrate includes a supporting area, and the orthographic projection of the first through hole on the first substrate is located outside the supporting area.
  • the array substrate further includes a passivation layer located on the side of the planar layer away from the first substrate;
  • the holes are connected to the second through hole, and the angle between the side wall of the second through hole and the first base is in the range of 50°-90°.
  • the angle between the side wall of the second through hole and the first base is the same as the angle between the side wall of the first through hole and the first base
  • the included angles are equal in size.
  • the embodiments of the present application provide an array substrate and a display panel, the array substrate includes a first base; a flat layer is located on one side of the first base, and the flat layer is provided with a second A through hole; wherein, in the embodiment of the present application, the cross-sectional area of the first through hole is gradually reduced in the direction of the flat layer pointing to the first substrate, and the side wall of the first through hole is connected to the
  • the included angle between the first substrates ranges from 50° to 90°, so as to reduce the area occupied by the first through holes on the flat layer, thereby increasing the aperture ratio of the display panel.
  • 1 is a schematic cross-sectional view of a flat layer of an existing array substrate
  • FIG. 2 is a schematic cross-sectional view of an array substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional view of the flat layer of the array substrate provided by the embodiment of the present application.
  • FIG. 4 is a top view of a through hole in a flat layer in an existing array substrate
  • Fig. 5 is a top view of the through hole in the flat layer in the array substrate provided by the embodiment of the present application
  • FIG. 6 is a flow chart of the steps of the method for preparing the array substrate provided by the embodiment of the present application.
  • FIG. 7A to 7E are structural schematic diagrams during the preparation process of the array substrate provided by the embodiment of the present application.
  • FIG. 1 is a schematic cross-sectional view of a flat layer of an existing array substrate.
  • the industry generally adopts PLN material as the planar layer, and adopts exposure and development to form the first through hole 81 in the planar layer 80; however, due to the influence of the planar layer in the process of manufacturing Due to the limitation of its own material, the taper angle (taper) of the first through hole 81 is small, and the two sides of the first through hole 81 are arc-shaped, so that the first through hole 81 is in the flat layer.
  • the larger area occupied by the 80 makes the pixel area smaller, which in turn leads to a decrease in the aperture ratio of the display product.
  • the present application provides an array substrate and a display panel for increasing the aperture ratio of the display panel.
  • the present application provides an array substrate and a display panel.
  • the array substrate 1 includes a first base 10 and a planar layer 80 located on one side of the first base 10 .
  • the planar layer 80 A first through hole 81 is provided on the top; wherein, the cross-sectional area of the first through hole 81 in the direction of the flat layer 80 pointing to the first substrate 10 gradually decreases, and the first through hole 81
  • the angle ⁇ between the side wall and the first base 10 is in the range of 50°-90°.
  • FIG. 2 is a schematic cross-sectional view of the array substrate provided by the embodiment of the present application
  • FIG. 3 is a schematic cross-sectional view of the flat layer of the array substrate provided by the embodiment of the present application.
  • This embodiment provides an array substrate 1, which includes a first base 10, a buffer layer 20, an active layer 30, a gate insulating layer 40, a second A metal layer 50 , an interlayer insulation layer 60 , a second metal layer 70 , a flat layer 80 , a first electrode layer 90 , a passivation layer 100 and a second electrode layer 110 .
  • the first base 10 includes a first substrate 11, a spacer layer 12, and a second substrate 13 that are stacked in sequence, wherein both the first substrate 11 and the second substrate 13 may include a rigid substrate Or a flexible substrate, when the first substrate 11 and the second substrate 13 are both rigid substrates, the material can be metal or glass, when the first substrate 11 and the second substrate 13 are all flexible substrates, the material can include acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane-based resin, cellulose resin, silicone resin, polyimide At least one of amino resins and polyamide-based resins; the material of the spacer layer 12 includes but is not limited to silicon nitride (SiNx), silicon oxide (SiOx) and other materials with water absorption properties.
  • the materials of the first substrate 11 , the second substrate 13 and the spacer layer 12 are not limited.
  • the active layer 30 includes but not limited to a polysilicon active layer or an oxide active layer, and the materials of the first metal layer 50 and the second metal layer 70 include molybdenum (Mo), aluminum (Al), Platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), At least one metal of titanium (Ti), tantalum (Ta) and tungsten (W), the second metal layer 70 is electrically connected to the active layer 30; wherein, in this embodiment, the active layer 30, the materials of the first metal layer 50 and the second metal layer 70 are not specifically limited.
  • the first metal layer 50 includes but not limited to a gate 51
  • the second metal layer 70 includes a source 71 and a drain 72
  • the array substrate 1 is provided with There are a first via hole 102 and a second via hole 103 passing through the gate insulating layer 40 and the interlayer insulating layer 60, and the second metal layer 70 passes through the first via hole 102 and the The second via hole 103 is connected to the active layer 30 to form the source 71 and the drain 72 .
  • the materials of the first electrode layer 90 and the second electrode layer 110 include but not limited to indium tin oxide, the first electrode layer 90 includes but not limited to the common electrode 91, the second The electrode layer 110 includes but not limited to the pixel electrode 111 .
  • the array substrate 1 includes a first substrate 10 and a buffer layer 20, an active layer 30, a gate insulating layer 40,
  • the first metal layer 50, the interlayer insulating layer 60, the second metal layer 70, the planar layer 80, the first electrode layer 90, the passivation layer 100, and the second electrode layer 110 are only used for illustration, and this embodiment does not describe the The film layer structure of the array substrate 1 is not specifically limited.
  • the flat layer 80 is provided with a first through hole 81, and the pixel electrode 111 is electrically connected to the drain electrode 72 through the first through hole 81; wherein, the first through hole 81 in the direction in which the flat layer 80 points to the first substrate 10 gradually decreases in cross-sectional area, and the angle between the side wall of the first through hole 81 and the bottom surface of the first through hole 81 The range of ⁇ is 50°-90°, wherein the bottom surface of the first through hole 81 is the side of the first through hole 81 close to the first substrate 10 .
  • the angle ⁇ between the side wall of the first through hole 81 and the side of the flat layer 80 away from the first substrate 10 is 90°-130°, understandably Yes, in this embodiment, by setting the angle ⁇ between the side wall of the first through hole 81 and the first substrate 10 to be in the range of 50°-90°, the side wall of the first through hole 81 and the first substrate 10
  • the included angle range ⁇ of the side of the flat layer 80 away from the first base 10 is 90°-130°, so as to reduce the opening size of the first through hole 81 , thereby reducing the size of the first through hole 81 The occupied area on the planar layer 80 .
  • the sidewall of the first through hole 81 includes a first part (not shown in the figure), and in the direction perpendicular to the first substrate 10, the The cross section is linear, specifically, the first part is connected to the side of the flat layer 80 away from the first substrate 10, and the flat layer 80 is linear at the junction with the first part; further Specifically, in one embodiment, in a direction perpendicular to the first substrate 10 , the cross-section of the sidewall of the first through hole 81 is linear.
  • the side wall of the first through hole 81 also includes other parts.
  • the cross-section of the other parts can be linear or arc-shaped.
  • this is not specifically limited; it can be understood that the above-mentioned first part is connected to the side of the flat layer 80 away from the first substrate 10, and the flat layer 80 is connected to the first part.
  • the linear shape is only used for illustration.
  • the joint between the first part and the side of the flat layer 80 away from the first base 10 may also be arc-shaped. In this embodiment There is no specific limitation on this.
  • the first through hole 81 includes a first opening 811 on a side away from the first substrate 10, and a second opening 812 on a side close to the first substrate 10; wherein, the first The ratio of the maximum width of an opening 811 to the maximum width of the second opening 812 is M:N, the range of M is 2-3, and the range of N is 3-4.5; specifically, the maximum width of the first opening 811 The range is from 2 microns to 8 microns, and the maximum width of the second opening 812 is from 1.5 microns to 6 microns.
  • the opening shape of the first through hole 81 is one of circular, elliptical and rectangular. Further, in this embodiment, the opening shape of the first through hole 81 is circular. Examples illustrate the technical solutions of the present application.
  • the diameter R3 of the opening on the side of the first through hole 81 away from the first substrate 10 is 2.9 microns
  • the diameter R3 of the opening on the side of the first through hole 81 close to the first substrate 10 is
  • the diameter R4 is 1.5 microns
  • the angle ⁇ between the sidewall of the first through hole 81 and the first substrate 10 is 74°.
  • Figure 4 is a top view of a flat layer through hole in an existing array substrate
  • Figure 5 is a top view of a flat layer through hole in an array substrate provided by an embodiment of the present application .
  • the planar layer 80 is usually made of organic materials.
  • the prior art In order to connect the pixel electrode 111 to the drain electrode 72, the prior art generally adopts exposure and development methods on the The flat layer 80 forms a first through hole 81.
  • the taper angle (taper) of the first through hole 81 is small.
  • the flat layer 80 is provided with a plurality of first through holes 81 , the opening shape of the first through holes 81 is circular, and the first through holes 81 are far away from the first substrate 10
  • the diameter R1 of the opening on one side is 6.8 microns
  • the diameter R2 of the opening on the side of the first through hole 81 close to the first substrate 10 is 3.1 microns
  • the side wall of the first through hole 81 is in contact with the first through hole 81.
  • the included angle ⁇ between the substrates 10 is 43°.
  • the opening shape of the first through hole 81 is set to be circular, and the diameter R3 of the opening of the first through hole 81 away from the first substrate 10 is 2.9 microns, so The diameter R4 of the opening of the first through hole 81 near the first substrate 10 is 1.5 microns, and the angle ⁇ between the side wall of the first through hole 81 and the first substrate 10 is 74° , thereby reducing the area occupied by the first through hole 81 on the planar layer 80 , thereby saving panel space, thereby increasing the pixel aperture ratio of the display panel using the array substrate 1 .
  • a second through hole 101 communicating with the first through hole 81 is opened on the passivation layer 100 , and the sidewall of the second through hole 101 is connected to the first substrate 10
  • the included angle ranges between 50°-90°, and the electrode layer is connected to the drain 72 through the first through hole 81 and the second through hole 101 .
  • the angle between the side wall of the second through hole 101 and the first substrate 10 is equal to the angle between the side wall of the first through hole 81 and the first substrate 10 , in the direction perpendicular to the first substrate 10, the cross section of the side wall of the second through hole 101 is linear, wherein the depth of the first through hole 81 and the depth of the second through hole 101
  • the sum of depths ranges from 1 micron to 2.5 microns
  • the pixel electrode 111 covers the sidewall of the second through hole 101 , the sidewall of the first through hole 81 and the bottom of the first through hole 81
  • the thickness of the pixel electrode 111 ranges from 450 angstroms to 520 angstroms; it should be noted that the depth of the first through hole 81, the depth of the second through hole 101 and the The thickness of 111 is not specifically limited.
  • a second through hole 101 communicating with the first through hole 81 is opened on the passivation layer 100 , and the sidewall of the second through hole 101 is connected to the first through hole 81 .
  • the included angle between a substrate 10 is equal to the included angle between the sidewall of the first through hole 81 and the first substrate 10, so that the second through hole 101 and the first through hole 81 can be formed by patterning with the same photomask, which reduces the process steps and does not increase the production cost, and is suitable for large-scale production.
  • the opening shape of the first through hole 81 is circular, and the diameter R1 of the opening of the first through hole 81 away from the first substrate 10 is 6.8 microns,
  • the diameter R2 of the opening of the first through hole 81 close to the first substrate 10 is 3.1 microns, and the angle ⁇ between the side wall of the first through hole 81 and the first substrate 10 is 43 °;
  • the opening shape of the first through hole 81 is circular, and the diameter R3 of the opening of the first through hole 81 away from the first substrate 10 is 2.9 microns, and the first through hole 81 is 2.9 microns.
  • the diameter R4 of the opening of a through hole 81 close to the first substrate 10 is 1.5 microns, and the angle ⁇ between the side wall of the first through hole 81 and the first substrate 10 is 74°.
  • the size of the first through hole 81 is not specifically limited in this embodiment.
  • the array substrate 1 provided in this embodiment can be applied in a liquid crystal display panel, and the liquid crystal display panel includes a plurality of spacer columns located on the side of the pixel electrode 111 away from the passivation layer 100 , wherein, the array substrate 1 includes a supporting area, the orthographic projection of the first through hole 81 on the first substrate 10 is located outside the supporting area, and the spacer post on the first substrate 10 The orthographic projection is located in the support area; it can be understood that in this embodiment, the orthographic projection of the first through hole 81 on the first substrate 10 is located outside the support area, and the spacer column is located in the support area.
  • the orthographic projection on the first substrate 10 is located in the support area, thereby preventing the spacer column from being located above the first through hole 81 and reducing the flatness at the position of the spacer column, reducing the liquid crystal Risk of extruded light leakage of the display panel due to instability of the spacer column.
  • FIG. 6 is a flow chart of the steps of the method for preparing the array substrate provided by the embodiment of the present application.
  • the preparation method of the array substrate 1 includes the following steps:
  • Step S10 preparing a flat layer 80 on the first substrate 10 .
  • the step S10 includes the following steps:
  • Step S11 sequentially prepare the buffer layer 20, the active layer 30, the gate insulating layer 40, the first metal layer 50, the interlayer insulating layer 60 and the second metal layer 70 on the first substrate 10; wherein, the first The base 10 includes a first substrate 11, a spacer layer 12, and a second substrate 13 stacked in sequence, the first metal layer 50 includes but not limited to a gate 51, the second metal layer 70 includes a source 71 and Drain 72 .
  • Step S12 preparing the planar layer 80 on the second metal layer 70, the material of the planar layer 80 includes but not limited to organic materials.
  • Step S20 using a photomask to etch the planar layer 80 to form a first through hole 81 on the planar layer 80, wherein the first through hole 81 points to the first through hole 81 on the planar layer 80 A cross-sectional area in the direction of the substrate 10 gradually decreases. In a direction perpendicular to the first substrate 10, the cross-section of the side wall of the first through hole 81 is linear, and the first through hole 81 The included angle between the sidewall of the first substrate 10 and the first substrate 10 ranges from 50° to 90°.
  • the preparation method of the array substrate 1 further includes the following steps:
  • Step S13 sequentially preparing a first electrode layer 90 and a passivation layer 100 on the planar layer 80, wherein the first electrode layer 90 includes but not limited to a common electrode 91, as shown in FIG. 7A.
  • step S20 includes the following steps:
  • Step S21 preparing a photoresist layer 120 on the passivation layer 100 , as shown in FIG. 7B .
  • Step S22 Expose the photoresist layer 120 by using the first half-tone mask 130, the first half-tone mask 130 includes a first light-transmitting region 131; wherein, the first light-transmitting region 131 is Circular, the diameter of the first light-transmitting region 131 ranges from 2 microns to 8 microns, as shown in FIG. 7C.
  • Step S23 develop the photoresist layer 120, remove the photoresist layer 120 corresponding to the first light-transmitting region 131, and form a through groove 121 on the photoresist layer 120, as shown in FIG. 7D .
  • Step S24 Etching the passivation layer 100 and the planar layer 80 corresponding to the through groove 121 to form a second through hole 101 and the first through hole 81, wherein the second through hole 101 In communication with the first through hole 81 , and in a direction perpendicular to the first substrate 10 , the cross section of the sidewall of the second through hole 101 is linear, as shown in FIG. 7E .
  • Step S25 peeling off the remaining photoresist layer 120 .
  • the present application prepares a photoresist layer 120 on the passivation layer 100, uses a first half-tone mask 130 to expose the photoresist layer 120, and then develops the photoresist layer 120 to remove the corresponding In the photoresist layer 120 of the first light-transmitting region 131, a through groove 121 is formed on the photoresist layer 120, and then, the passivation layer 100 and the passivation layer 100 corresponding to the through groove 121 are etched.
  • the flat layer 80 is used to form the second through hole 101 and the first through hole 81.
  • the size of the first light-transmitting region 131 on the first half-tone mask 130 so as to control the size of the through-groove 121 opened on the photoresist layer 120, and then meet the requirements of preparing a high PPI (pixel density unit) display device; it can be understood that, exposing the photoresist material can make The through hole with a diameter smaller than 2 microns belongs to the prior art, and this embodiment will not elaborate on it.
  • the method for preparing the array substrate 1 further includes the following steps:
  • Step S30 preparing a second electrode layer 110 on the passivation layer 100, the second electrode layer 110 includes but not limited to a pixel electrode 111, and the pixel electrode 111 passes through the second through hole 101 and the first A through hole 81 is electrically connected to the drain 72 .
  • the second through hole 101 communicating with the first through hole 81 is opened on the passivation layer 100, and in the direction perpendicular to the first substrate 10, the The cross-section of the side wall of the second through hole 101 is linear, so that the second through hole 101 and the first through hole 81 are patterned and formed with the same mask, which reduces the process steps and does not increase the production cost. , suitable for large-scale production.
  • This embodiment provides a display panel, which includes but is not limited to one of a light-emitting diode (Light-Emitting Diode, referred to as LED) and an organic light-emitting diode display panel (Organic Light Emitting Diode, referred to as OLED), This embodiment does not specifically limit this; it should be noted that this embodiment describes the technical solution of the present application by taking the display panel as an example of a light emitting diode display panel.
  • LED Light-Emitting Diode
  • OLED Organic Light Emitting Diode
  • the display panel includes the array substrate described in any of the above embodiments, a color filter substrate disposed opposite to the array substrate, and a color filter substrate located between the array substrate and the color filter substrate. liquid crystal layer.
  • the display panel further includes a color filter substrate disposed opposite to the array substrate, a liquid crystal layer and a spacer layer located between the array substrate and the color filter substrate.
  • the spacer layer includes a plurality of spacer columns, and the spacer columns are circular frustums, and further, the spacer columns are arranged upside down between the array substrate and the color filter substrate, that is, the spacer columns The end of the spacer column with a larger radius is in contact with the color filter substrate, and the end of the spacer column with a smaller radius is in contact with the array substrate, thereby playing a good supporting role.
  • the cross-sectional area of the first through hole in the direction in which the flat layer points to the first substrate to gradually decrease, in a direction perpendicular to the first substrate, the The cross-section of the side wall of the first through hole is linear, and the angle between the side wall of the first through hole and the first base is in the range of 50°-90°, so that In the direction of a substrate, the cross-section of the flat layer between the adjacent through holes is linear to increase the flatness at the position of the spacer column, thereby reducing the display panel due to the spacer Risk of extrusion light leakage caused by column instability.
  • the present application provides an array substrate and a display panel.
  • the array substrate includes a first base and a planar layer on one side of the first base, and the planar layer is provided with a first through hole;
  • the cross-sectional area of the first through hole in the direction from the flat layer to the first substrate gradually decreases, and the angle between the side wall of the first through hole and the first substrate is ⁇ ranges from 50° to 90°;
  • the present application gradually reduces the cross-sectional area of the first through hole in the direction in which the flat layer points to the first substrate, and the side wall of the first through hole
  • the angle ⁇ between the first substrate and the first substrate ranges from 50° to 90°, so as to reduce the area occupied by the first through hole on the flat layer, thereby increasing the aperture ratio of the display panel .

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Abstract

本申请提供一种阵列基板和显示面板，该阵列基板包括第一基底、及位于第一基底一侧的平坦层，平坦层上设置有第一通孔；本申请通过设置第一通孔在平坦层指向第一基底方向上的横截面积逐渐减小，且第一通孔的侧壁与第一基底之间的夹角范围为50°～90°，从而减小第一通孔的在平坦层上所占据的面积，进而提升显示面板的开口率。

Description

阵列基板和显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板和显示面板。
背景技术
随着显示技术的发展，显示器件已被广泛的应用于人们生活中的各个领域中，显示器件的种类也随之变得越来越多，目前，常用的显示设备包括液晶显示器(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示面板以及主动矩阵有机发光二极体面板(Active Ma trix/Organic Light Emitting Diode，AMOLED)。
在现有的显示屏的制作过程中，业内通常采用PLN材料作为平坦层，对应所述平坦层进行通孔，现有技术是采用曝光、显影的方式来制备；然而，由于在工艺制备过程中受所述平坦层自身材料的限制，所述通孔的锥度角(taper)较小，所述通孔两侧呈圆弧形，从而导致所述通孔在所述平坦层上所占据的面积较大，使得所述像素的面积较小，进而导致显示产品的开口率下降。
技术问题
本申请实施例提供一种阵列基板和显示面板，用以缓解相关技术中的不足。
技术解决方案
为实现上述效果，本申请实施例提供了一种阵列基板，包括：
第一基底；
平坦层，位于所述第一基底的一侧，所述平坦层设置有第一通孔；其中，
所述第一通孔在所述平坦层指向所述第一基底方向上的横截面积逐渐减小，且所述第一通孔的侧壁与所述第一通孔的底面之间的夹角范围为50°～90°。
在本申请实施例所提供的阵列基板中，所述第一通孔的侧壁与所述平坦层远离所述第一基底的一侧的夹角范围为90°～130°。
在本申请实施例所提供的阵列基板中，所述第一通孔的侧壁包括第一部 分，在垂直于所述第一基底的方向上，所述第一部分的截面呈直线型。
在本申请实施例所提供的阵列基板中，在垂直于所述第一基底的方向上，所述第一通孔的侧壁的截面呈直线型。
在本申请实施例所提供的阵列基板中，所述第一通孔包括远离所述第一基底一侧的第一开口、及靠近所述第一基底一侧的第二开口；
其中，所述第一开口的最大宽度与所述第二开口的最大宽度比值为M：N，M的范围为2～3，N的范围为3～4.5。
在本申请实施例所提供的阵列基板中，在垂直于所述第一基底的方向上，所述第一开口的最大宽度范围为2微米至8微米，所述第二开口的最大宽度范围为1.5微米至6微米。
在本申请实施例所提供的阵列基板中，所述阵列基板包括支撑区，所述第一通孔在所述第一基底上的正投影位于所述支撑区外。
在本申请实施例所提供的阵列基板中，所述阵列基板还包括位于所述平坦层远离第一基底的一侧的钝化层；其中，所述钝化层设有与所述第一通孔连通的第二通孔，且所述第二通孔的侧壁与所述第一基底之间的夹角范围为50°～90°。
在本申请实施例所提供的阵列基板中，所述第二通孔的侧壁与所述第一基底之间的夹角与所述第一通孔的侧壁与所述第一基底之间的夹角大小相等。
在本申请实施例所提供的阵列基板中，所述第一通孔的深度和所述第二通孔的深度之和的范围为1微米～2.5微米。
在本申请实施例所提供的阵列基板中，所述阵列基板还包括一电极层，所述电极层覆盖所述第二通孔的侧壁、所述第一通孔的侧壁以及所述第一通孔的底部。
本申请实施例提供一种显示面板，所述显示面板包括一阵列基板，所述阵列基板包括：
第一基底；
平坦层，位于所述第一基底的一侧，所述平坦层设置有第一通孔；其中，
所述第一通孔在所述平坦层指向所述第一基底方向上的横截面积逐渐减小，且所述第一通孔的侧壁与所述第一通孔的底面之间的夹角范围为50° ～90°。
在本申请实施例所提供的显示面板中，所述第一通孔的侧壁与所述平坦层远离所述第一基底的一侧的夹角范围为90°～130°。
在本申请实施例所提供的显示面板中，所述第一通孔的侧壁包括第一部分，在垂直于所述第一基底的方向上，所述第一部分的截面呈直线型。
在本申请实施例所提供的显示面板中，在垂直于所述第一基底的方向上，所述第一通孔的侧壁的截面呈直线型。
在本申请实施例所提供的显示面板中，所述第一通孔包括远离所述第一基底一侧的第一开口、及靠近所述第一基底一侧的第二开口；
其中，所述第一开口的最大宽度与所述第二开口的最大宽度比值为M：N，M的范围为2～3，N的范围为3～4.5。
在本申请实施例所提供的显示面板中，在垂直于所述第一基底的方向上，所述第一开口的最大宽度范围为2微米至8微米，所述第二开口的最大宽度范围为1.5微米至6微米。
在本申请实施例所提供的显示面板中，所述阵列基板包括支撑区，所述第一通孔在所述第一基底上的正投影位于所述支撑区外。
在本申请实施例所提供的显示面板中，所述阵列基板还包括位于所述平坦层远离第一基底的一侧的钝化层；其中，所述钝化层设有与所述第一通孔连通的第二通孔，且所述第二通孔的侧壁与所述第一基底之间的夹角范围为50°～90°。
在本申请实施例所提供的显示面板中，所述第二通孔的侧壁与所述第一基底之间的夹角与所述第一通孔的侧壁与所述第一基底之间的夹角大小相等。
有益效果
本申请实施例的有益效果：本申请实施例提供一种阵列基板和显示面板，所述阵列基板包括第一基底；平坦层，位于所述第一基底的一侧，所述平坦层设置有第一通孔；其中，本申请实施例通过设置所述第一通孔在所述平坦层指向所述第一基底方向上的横截面积逐渐减小，且所述第一通孔的侧壁与所述第 一基底之间的夹角范围为50°～90°，从而减小所述第一通孔的在所述平坦层上所占据的面积，进而提升所述显示面板的开口率。
附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有阵列基板的平坦层的截面示意图；
图2为本申请实施例所提供的阵列基板的截面示意图；
图3为本申请实施例所提供的阵列基板的平坦层的截面示意图；
图4为现有阵列基板中平坦层通孔的俯视图；
图5为本申请实施例所提供的阵列基板中平坦层通孔的俯视图
图6为本申请实施例所提供的阵列基板的制备方法的步骤流程图；
图7A～图7E为本申请实施例所提供的阵列基板制备过程中的结构示意图。
本发明的实施方式
本申请提供一种彩膜层的光学调节方法、显示面板以及移动终端，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
请参阅图1，为现有阵列基板的平坦层的截面示意图。
在现有技术中，业内通常采用PLN材料作为平坦层，并采用曝光、显影的方式在所述平坦层80形成第一通孔81，形成；然而，由于在工艺制备过程中受所述平坦层自身材料的限制，所述第一通孔81的锥度角(taper)较小，且所述第一通孔81两侧呈圆弧形，从而导致所述第一通孔81在所述平坦层80上所占据的面积较大，使得像素的面积较小，进而导致显示产品的开口率下降。基于此，本申请提供一种阵列基板和显示面板，用以提高所述显示面板的开口率。
请参阅图2～图7E，本申请提供一种阵列基板和显示面板，所述阵列基板 1包括第一基底10、及位于所述第一基底10一侧的平坦层80，所述平坦层80上设置有第一通孔81；其中，所述第一通孔81在所述平坦层80指向所述第一基底10方向上的横截面积逐渐减小，且所述第一通孔81的侧壁与所述第一基底10之间的夹角β范围为50°～90°。
可以理解的是，本申请通过设置所述第一通孔81在所述平坦层80指向所述第一基底10方向上的横截面积逐渐减小，且所述第一通孔81的侧壁与所述第一基底10之间的夹角β范围为50°～90°，从而减小所述第一通孔81的在所述平坦层80上所占据的面积，进而提升所述显示面板的开口率。
现结合具体实施例对本申请的技术方案进行描述。
请结合图2和图3；其中，图2为本申请实施例所提供的阵列基板的截面示意图；图3为本申请实施例所提供的阵列基板的平坦层的截面示意图。
本实施例提供一种阵列基板1，所述阵列基板1包括第一基底10和依次层叠设置于所述第一基底10一侧的缓冲层20、有源层30、栅极绝缘层40、第一金属层50、层间绝缘层60、第二金属层70、平坦层80、第一电极层90、钝化层100以及第二电极层110。
所述第一基底10包括依次层叠设置的第一衬底11、间隔层12以及第二衬底13，其中，所述第一衬底11和所述第二衬底13均可以包括刚性衬底或柔性衬底，当所述第一衬底11和所述第二衬底13均为刚性衬底时，材料可以是金属或玻璃，当所述第一衬底11和所述第二衬底13均为柔性衬底时，材料可以包括丙烯酸树脂、甲基丙烯酸树脂、聚异戊二烯、乙烯基树脂、环氧基树脂、聚氨酯基树脂、纤维素树脂、硅氧烷树脂、聚酰亚胺基树脂、聚酰胺基树脂中的至少一种；所述间隔层12的材质包括但不限于氮化硅(SiNx)、硅氧化物(SiOx)等具有吸水性能的材质，本实施例对所述第一衬底11、所述第二衬底13以及所述间隔层12的材料均不做限制。
所述有源层30包括但不限于多晶硅有源层或氧化物有源层，所述第一金属层50和所述第二金属层70的材料均包括钼(Mo)、铝(Al)、铂(Pt)、钯(Pd)、银(Ag)、镁(Mg)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、钙(Ca)、钛(Ti)、钽(Ta)和钨(W)中的至少一种金属，所述第二金属层70与所述有源层30电性连接；其中，本实施例对所述有源层30的种类，所述第一金属层50 和所述第二金属层70材料均不做具体限制。
具体地，在本实施例中，所述第一金属层50包括但不限于栅极51，所述第二金属层70包括源极71和漏极72，进一步的，所述阵列基板1内设置有穿过所述栅极绝缘层40和所述层间绝缘层60的第一过孔102和第二过孔103，所述第二金属层70穿过所述第一过孔102和所述第二过孔103与所述有源层30连接形成所述源极71和所述漏极72。
在本实施例中，所述第一电极层90和所述第二电极层110的材料包括但不限于氧化铟锡，所述第一电极层90包括但不限于公共电极91，所述第二电极层110包括但不限于像素电极111。
需要说明的是，在本实施例中，所述阵列基板1包括第一基底10和依次层叠设置于所述第一基底10一侧的缓冲层20、有源层30、栅极绝缘层40、第一金属层50、层间绝缘层60、第二金属层70、平坦层80、第一电极层90、钝化层100以及第二电极层110仅用于举例说明，本实施例对所述阵列基板1的膜层结构不做具体限制。
在本实施例中，所述平坦层80设置有第一通孔81，所述像素电极111通过所述第一通孔81与所述漏极72电性连接；其中，所述第一通孔81在所述平坦层80指向所述第一基底10方向上的横截面积逐渐减小，且所述第一通孔81的侧壁与所述第一通孔81的底面之间的夹角β范围为50°～90°，其中所述第一通孔81的底面为所述第一通孔81靠近所述第一基底10的一侧。
具体地，在本实施例中，所述第一通孔81的侧壁与所述平坦层80远离所述第一基底10的一侧的夹角范围γ为90°～130°，可以理解的是，本实施例通过设置所述第一通孔81的侧壁与所述第一基底10之间的夹角β范围为50°～90°，所述第一通孔81的侧壁与所述平坦层80远离所述第一基底10的一侧的夹角范围γ为90°～130°，从而减小所述第一通孔81的开口大小，进而减小所述第一通孔81的在所述平坦层80上所占据的面积。
需要说明的是，在一实施例中，所述第一通孔81的侧壁包括第一部分(图中未画出)，在垂直于所述第一基底10的方向上，所述第一部分的截面呈直线型，具体地，所述第一部分与所述平坦层80远离所述第一基底10的一侧衔接，且所述平坦层80在与所述第一部分的衔接处为直线型；进一步地，在一实施 例中，在垂直于所述第一基底10的方向上，所述第一通孔81的侧壁的截面呈直线型。
承上，所述第一通孔81的侧壁还包括其他部分，在垂直于所述第一基底10的方向上，所述其他部分的截面可以呈直线型，也可以圆弧形，本实施例对此不做具体限制；可以理解的是，上述所述第一部分与所述平坦层80远离所述第一基底10的一侧衔接，且所述平坦层80在与所述第一部分的衔接处为直线型仅用于举例说明，在另一实施例中，所述第一部分与所述平坦层80远离所述第一基底10的一侧的衔接处还可以为圆弧形，本实施例对此不做具体限制。
在本实施例中，所述第一通孔81包括远离所述第一基底10一侧的第一开口811、及靠近所述第一基底10一侧的第二开口812；其中，所述第一开口811的最大宽度与所述第二开口812的最大宽度比值为M：N，M的范围为2～3，N的范围为3～4.5；具体地，所述第一开口811的最大宽度范围为2微米至8微米，所述第二开口812的最大宽度范围为1.5微米至6微米。
在本实施例中，所述第一通孔81的开口形状为圆形、椭圆形以及矩形中的一种，进一步地，本实施例以所述第一通孔81的开口形状为圆形为例对本申请的技术方案进行举例说明。
在本实施例中，所述第一通孔81远离所述第一基底10一侧的开口的直径R3为2.9微米，所述第一通孔81靠近所述第一基底10一侧的开口的直径R4为1.5微米，所述第一通孔81的侧壁与所述第一基底10之间的夹角β为74°。
请结合图2、图3、图4和图5；其中，图4为现有阵列基板中平坦层通孔的俯视图；图5为本申请实施例所提供的阵列基板中平坦层通孔的俯视图。
需要说明的是，在现有技术中，所述平坦层80通常采用有机材料制备，为了使所述像素电极111与所述漏极72连接，现有技术通常采用曝光、显影的方式在所述平坦层80形成第一通孔81，然而，由于在工艺制备过程中受所述平坦层80自身材料的限制，所述第一通孔81的锥度角(taper)较小，具体地，在现有技术中，所述平坦层80上设有多个所述第一通孔81，所述第一通孔81的开口形状为圆形，所述第一通孔81远离所述第一基底10一侧的开口的直径R1为6.8微米，所述第一通孔81靠近所述第一基底10一侧的开口的 直径R2为3.1微米，所述第一通孔81的侧壁与所述第一基底10之间的夹角α为43°，根据圆形的面积公式S＝π·R 2可知，任一所述第一通孔81在所述平坦层80上所占据的面积S1为36.30平方微米。
在本实施例中，所述平坦层80上设有多个所述第一通孔81，所述第一通孔81的开口形状为圆形，所述第一开口811的直径R3为2.9微米，所述第二开口812的直径R4为1.5微米，所述第一通孔81的侧壁与所述第一基底10之间的夹角β为74°，根据圆形的面积公式S＝π·R 2可知，任一所述第一通孔81在所述平坦层80上所占据的面积S2为6.60平方微米，本实施例相对于现有技术来说，所述第一通孔81在所述平坦层80上所占据的面积减小了82％。
可以理解的是，本实施例通过设置所述第一通孔81的开口形状为圆形，所述第一通孔81远离所述第一基底10一侧的开口的直径R3为2.9微米，所述第一通孔81靠近所述第一基底10一侧的开口的直径R4为1.5微米，所述第一通孔81的侧壁与所述第一基底10之间的夹角β为74°，从而减小了所述第一通孔81在所述平坦层80上所占据的面积，进而可以节省面板空间，从而提高了采用所述阵列基板1的显示面板的像素开口率。
在本实施例中，所述钝化层100上开设有与所述第一通孔81连通的第二通孔101，且所述第二通孔101的侧壁与所述第一基底10之间的夹角范围为50°～90°，所述电极层通过所述第一通孔81和所述第二通孔101与所述漏极72连接。
进一步地，所述第二通孔101的侧壁与所述第一基底10之间的夹角与所述第一通孔81的侧壁与所述第一基底10之间的夹角大小相等，在垂直于所述第一基底10的方向上，所述第二通孔101的侧壁的截面呈直线型，其中，所述第一通孔81的深度和所述第二通孔101的深度之和的范围为1微米～2.5微米，所述像素电极111覆盖所述第二通孔101的侧壁、所述第一通孔81的侧壁以及所述第一通孔81的底部，所述像素电极111的厚度范围为450埃米～520埃米；需要说明的是，本实施例对所述第一通孔81的深度、所述第二通孔101的深度以及所述像素电极111的厚度均不做具体限制。
可以理解的是，本实施例通过在所述钝化层100上开设有与所述第一通孔 81连通的第二通孔101，且所述第二通孔101的侧壁与所述第一基底10之间的夹角与所述第一通孔81的侧壁与所述第一基底10之间的夹角大小相等，从而使得所述第二通孔101和所述第一通孔81可以采用同一道光罩图案化形成，减少了工艺制程步骤，不增加生产成本，适于规模化制作。
可以理解的是，在现有技术中，所述第一通孔81的开口形状为圆形，所述第一通孔81远离所述第一基底10一侧的开口的直径R1为6.8微米，所述第一通孔81靠近所述第一基底10一侧的开口的直径R2为3.1微米，所述第一通孔81的侧壁与所述第一基底10之间的夹角α为43°；在本实施例中，所述第一通孔81的开口形状为圆形，所述第一通孔81远离所述第一基底10一侧的开口的直径R3为2.9微米，所述第一通孔81靠近所述第一基底10一侧的开口的直径R4为1.5微米，所述第一通孔81的侧壁与所述第一基底10之间的夹角β为74°均仅用于举例说明，本实施例对所述第一通孔81的尺寸不做具体限定。
需要说明的是，本实施例所提供的阵列基板1可应用于液晶显示面板中，所述液晶显示面板包括位于所述像素电极111远离所述钝化层100一侧的多个隔垫柱，其中，所述阵列基板1包括支撑区，所述第一通孔81在所述第一基底10上的正投影位于所述支撑区外，所述隔垫柱在所述第一基底10上的正投影位于所述支撑区；可以理解的是，本实施例通过设置所述第一通孔81在所述第一基底10上的正投影位于所述支撑区外，所述隔垫柱在所述第一基底10上的正投影位于所述支撑区，从而避免所述隔垫柱位于所述第一通孔81上方而降低所述隔垫柱站位处的平坦性，降低了所述液晶显示面板因为所述隔垫柱不稳而导致的挤压漏光风险。
请参阅图6，本申请实施例所提供的阵列基板的制备方法的步骤流程图。
在本实施例中，所述阵列基板1的制备方法包括以下步骤：
步骤S10：在第一基底10上制备一平坦层80。
具体地，在本实施例中，所述步骤S10包括以下步骤：
步骤S11：在第一基底10上依次制备缓冲层20、有源层30、栅极绝缘层40、第一金属层50、层间绝缘层60以及第二金属层70；其中，所述第一基底10包括依次层叠设置的第一衬底11、间隔层12以及第二衬底13，所述第一 金属层50包括但不限于栅极51，所述第二金属层70包括源极71和漏极72。
步骤S12：在所述第二金属层70上制备所述平坦层80，所述平坦层80的材料包括但不限于有机材料。
步骤S20：采用一光罩对所述平坦层80进行刻蚀，在所述平坦层80上形成第一通孔81，其中，所述第一通孔81在所述平坦层80指向所述第一基底10方向上的横截面积逐渐减小，在垂直于所述第一基底10的方向上，所述第一通孔81的侧壁的截面呈直线型，且所述第一通孔81的侧壁与所述第一基底10之间的夹角范围为50°～90°。
其中，在所述步骤S20之前，所述阵列基板1地制备方法还包括以下步骤：
步骤S13:在所述平坦层80上依次制备第一电极层90和钝化层100，其中，所述第一电极层90包括但不限于公共电极91，如图7A所示。
在本实施例中,步骤S20包括以下步骤：
步骤S21：在所述钝化层100上制备一光阻层120，如图7B所示。
步骤S22：采用第一半色调掩模板130对所述光阻层120进行曝光、所述第一半色调掩模板130上包括第一透光区131；其中，所述第一透光区131为圆形，所述第一透光区131的直径范围为2微米至8微米,如图7C所示。
步骤S23：对所述光阻层120进行显影，去除对应于所述第一透光区131的所述光阻层120，在所述光阻层120上形成一通槽121,如图7D所示。
步骤S24：刻蚀对应所述通槽121处的所述钝化层100和所述平坦层80，形成第二通孔101和所述第一通孔81，其中，所述第二通孔101与所述第一通孔81连通，且在垂直于所述第一基底10的方向上，所述第二通孔101的侧壁的截面呈直线型,如图7E所示。
步骤S25：剥离剩余所述光阻层120。
需要说明的是，在现有技术中，由于在所述阵列基板的工艺制备过程中受所述平坦层80自身材料的限制，在对所述平坦层80进行开孔时，其解析度无法做到小于3微米，即，所述第一通孔81靠近所述第一基底10一侧的开口的直径大于3微米，从而无法满足高PPI(像素密度单位)显示设备的需求。
而本申请通过在所述钝化层100上制备一光阻层120，采用第一半色调掩模板130对所述光阻层120进行曝光、随后对所述光阻层120进行显影，去除 对应于所述第一透光区131的所述光阻层120，在所述光阻层120上形成一通槽121，然后，刻蚀对应所述通槽121处的所述钝化层100和所述平坦层80，形成第二通孔101和所述第一通孔81，因此在本实施例中，可以通过控制所述第一半色调掩模板130上所述第一透光区131的大小，从而控制所述光阻层120上开设的所述通槽121的大小，进而满足制备高PPI(像素密度单位)显示设备的需求；可以理解的是，对光阻材料进行曝光，可以制得直径大小小于2微米的通孔，属于现有技术，本实施例对此不做过多赘叙。
在本实施例中，所述阵列基板1的制备方法还包括以下步骤：
步骤S30：在所述钝化层100上制备第二电极层110，所述第二电极层110包括但不限于像素电极111，所述像素电极111通过所述第二通孔101和所述第一通孔81与所述漏极72电性连接。
可以理解的是，本实施例通过在所述钝化层100上开设有与所述第一通孔81连通的第二通孔101，且在垂直于所述第一基底10的方向上，所述第二通孔101的侧壁的截面呈直线型，从而使得所述第二通孔101和所述第一通孔81采用同一道光罩图案化形成，减少了工艺制程步骤，不增加生产成本，适于规模化制作。
本实施例提供一种显示面板，所述显示面板包括但不限于发光二极管(Li ght-Emitting Diode，简称LED)和有机发光二极管显示面板(Organic Light E mitting Diode，简称OLED)中的一种，本实施例对此不做具体限制；需要说明的是，本实施例以所述显示面板为发光二极管显示面板为例对本申请的技术方案进行描述。
在本实施例中，所述显示面板包括上述任一实施例中所述的阵列基板、与所述阵列基板相对设置的彩膜基板、及位于所述阵列基板和所述彩膜基板之间的液晶层。
可以理解的是，所述阵列基板已经在上述实施例中进行了详细的说明，在此不在重复说明。
在本实施例中，所述显示面板还包括与所述阵列基板相对设置的彩膜基板、位于所述阵列基板和彩膜基板之间的液晶层和隔垫层。
其中，所述隔垫层包括多个隔垫柱，所述隔垫柱为圆台体，进一步地，所 述隔垫柱倒置设于所述阵列基板和所述彩膜基板之间，即所述隔垫柱半径大的一端与所述彩膜基板接触，所述隔垫柱半径小的一端与所述阵列基板接触，从而起到良好地支撑作用。
可以理解的是，本实施例通过设置所述第一通孔在所述平坦层指向所述第一基底方向上的横截面积逐渐减小，在垂直于所述第一基底的方向上，所述第一通孔的侧壁的截面呈直线型，且所述第一通孔的侧壁与所述第一基底之间的夹角范围为50°～90°，从而在垂直于所述第一基底的方向上，使相邻所述通孔之间的所述平坦层的截面呈直线型，增加所述隔垫柱站位处的平坦性，从而降低了显示面板的因所述隔垫柱不稳导致的挤压漏光风险。
综上所述，本申请提供一种阵列基板和显示面板，所述阵列基板包括第一基底、及位于所述第一基底一侧的平坦层，所述平坦层上设置有第一通孔；其中，所述第一通孔在所述平坦层指向所述第一基底方向上的横截面积逐渐减小，且所述第一通孔的侧壁与所述第一基底之间的夹角β范围为50°～90°；本申请通过设置所述第一通孔在所述平坦层指向所述第一基底方向上的横截面积逐渐减小，且所述第一通孔的侧壁与所述第一基底之间的夹角β范围为50°～90°，从而减小所述第一通孔的在所述平坦层上所占据的面积，进而提升所述显示面板的开口率。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种阵列基板，其中，包括：
    第一基底；
    平坦层，位于所述第一基底的一侧，所述平坦层设置有第一通孔；其中，
    所述第一通孔在所述平坦层指向所述第一基底方向上的横截面积逐渐减小，且所述第一通孔的侧壁与所述第一通孔的底面之间的夹角范围为50°～90°。
  2. 如权利要求1所述的阵列基板，其中，所述第一通孔的侧壁与所述平坦层远离所述第一基底的一侧的夹角范围为90°～130°。
  3. 如权利要求2所述的阵列基板，其中，所述第一通孔的侧壁包括第一部分，在垂直于所述第一基底的方向上，所述第一部分的截面呈直线型。
  4. 如权利要求2所述的阵列基板，其中，在垂直于所述第一基底的方向上，所述第一通孔的侧壁的截面呈直线型。
  5. 如权利要求1所述的阵列基板，其中，所述第一通孔包括远离所述第一基底一侧的第一开口、及靠近所述第一基底一侧的第二开口；
    其中，所述第一开口的最大宽度与所述第二开口的最大宽度比值为M：N，M的范围为2～3，N的范围为3～4.5。
  6. 如权利要求5所述的阵列基板，其中，在垂直于所述第一基底的方向上，所述第一开口的最大宽度范围为2微米至8微米，所述第二开口的最大宽度范围为1.5微米至6微米。
  7. 如权利要求1所述的阵列基板，其中，所述阵列基板包括支撑区，所述第一通孔在所述第一基底上的正投影位于所述支撑区外。
  8. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括位于所述平坦层远离第一基底的一侧的钝化层；其中，所述钝化层设有与所述第一通孔连通的第二通孔，且所述第二通孔的侧壁与所述第一基底之间的夹角范围为50°～90°。
  9. 如权利要求8所述的阵列基板，其中，所述第二通孔的侧壁与所述第一基底之间的夹角与所述第一通孔的侧壁与所述第一基底之间的夹角大小相等。
  10. 如权利要求9所述的阵列基板，其中，所述第一通孔的深度和所述第二通孔的深度之和的范围为1微米～2.5微米。
  11. 如权利要求8所述的阵列基板，其中，所述阵列基板还包括一电极层，所述电极层覆盖所述第二通孔的侧壁、所述第一通孔的侧壁以及所述第一通孔的底部。
  12. 一种显示面板，其中，所述显示面板包括一阵列基板，所述阵列基板包括：
    第一基底；
    平坦层，位于所述第一基底的一侧，所述平坦层设置有第一通孔；其中，
    所述第一通孔在所述平坦层指向所述第一基底方向上的横截面积逐渐减小，且所述第一通孔的侧壁与所述第一通孔的底面之间的夹角范围为50°～90°。
  13. 如权利要求12所述的显示面板，其中，所述第一通孔的侧壁与所述平坦层远离所述第一基底的一侧的夹角范围为90°～130°。
  14. 如权利要求13所述的显示面板，其中，所述第一通孔的侧壁包括第一部分，在垂直于所述第一基底的方向上，所述第一部分的截面呈直线型。
  15. 如权利要求13所述的显示面板，其中，在垂直于所述第一基底的方向上，所述第一通孔的侧壁的截面呈直线型。
  16. 如权利要求12所述的显示面板，其中，所述第一通孔包括远离所述第一基底一侧的第一开口、及靠近所述第一基底一侧的第二开口；
    其中，所述第一开口的最大宽度与所述第二开口的最大宽度比值为M：N，M的范围为2～3，N的范围为3～4.5。
  17. 如权利要求16所述的显示面板，其中，在垂直于所述第一基底的方向上，所述第一开口的最大宽度范围为2微米至8微米，所述第二开口的最大宽度范围为1.5微米至6微米。
  18. 如权利要求12所述的显示面板，其中，所述阵列基板包括支撑区，所述第一通孔在所述第一基底上的正投影位于所述支撑区外。
  19. 如权利要求12所述的显示面板，其中，所述阵列基板还包括位于所述平坦层远离第一基底的一侧的钝化层；其中，所述钝化层设有与所述第一通 孔连通的第二通孔，且所述第二通孔的侧壁与所述第一基底之间的夹角范围为50°～90°。
  20. 如权利要求19所述的显示面板，其中，所述第二通孔的侧壁与所述第一基底之间的夹角与所述第一通孔的侧壁与所述第一基底之间的夹角大小相等。
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