CN110600482A - 一种阵列基板及其制作方法、显示面板 - Google Patents
一种阵列基板及其制作方法、显示面板 Download PDFInfo
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- CN110600482A CN110600482A CN201910733593.5A CN201910733593A CN110600482A CN 110600482 A CN110600482 A CN 110600482A CN 201910733593 A CN201910733593 A CN 201910733593A CN 110600482 A CN110600482 A CN 110600482A
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- 239000000758 substrate Substances 0.000 title claims abstract description 106
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 367
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 72
- 239000011229 interlayer Substances 0.000 claims abstract description 51
- 239000012528 membrane Substances 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000012044 organic layer Substances 0.000 claims description 30
- 239000010409 thin film Substances 0.000 claims description 17
- 239000010408 film Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 description 33
- 239000002184 metal Substances 0.000 description 33
- 238000010586 diagram Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 238000005452 bending Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 229920001621 AMOLED Polymers 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 3
- -1 polyethylene terephthalate Polymers 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 239000004695 Polyether sulfone Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229920000515 polycarbonate Polymers 0.000 description 2
- 239000004417 polycarbonate Substances 0.000 description 2
- 229920006393 polyether sulfone Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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Abstract
本申请涉及一种阵列基板及其制作方法、显示面板,该阵列基板包括:基底,基底包括显示区域;位于基底上的低温多晶硅层,低温多晶硅层位于显示区域;位于基底上且覆盖低温多晶硅层的无机膜组层,无机膜组层上设有通孔,通孔位于低温多晶硅层上方,且通孔的侧壁与底壁之间的夹角不小于100度;位于无机膜组层上的源漏极层,源漏极层覆盖通孔的侧壁和底壁,以与低温多晶硅层连接。通过这种方式,减小位于源漏极层与低温多晶硅层之间的层间通孔的锥角,进而避免源漏极层由于层间通孔的锥角过大而出现厚度较薄甚至断线的问题,从而提高产品良率。
Description
【技术领域】
本申请涉及显示技术领域,具体涉及一种阵列基板及其制作方法、显示面板。
【背景技术】
有源矩阵有机发光二极体(Active-matrix organic light emitting diode,简称AMOLED)面板因其高对比度、广色域、低功耗、可折叠等特性,逐渐成为新一代显示技术。
目前,在AMOLED面板的阵列基板制程工艺中,源漏极层通过层间通孔与薄膜晶体管的有源层实现连接。但是,由于层间通孔的锥角过大,会导致源漏极层出现厚度较薄甚至断线的问题。
【发明内容】
本申请的目的在于提供一种阵列基板及其制作方法、阵列基板,以避免源漏极层由于层间通孔的锥角过大而出现厚度较薄甚至断线的问题。
为了解决上述问题,本申请实施例提供了一种阵列基板,该阵列基板包括:基底,基底包括显示区域;位于基底上的低温多晶硅层,低温多晶硅层位于显示区域;位于基底上且覆盖低温多晶硅层的无机膜组层,无机膜组层上设有通孔,通孔位于低温多晶硅层上方,且通孔的侧壁与底壁之间的夹角不小于100度;位于无机膜组层上的源漏极层,源漏极层覆盖通孔的侧壁和底壁,以与低温多晶硅层连接。
其中,通孔的侧壁与底壁之间的夹角的范围为105~110度。
其中,无机膜组层包括依次远离低温多晶硅层的第一栅绝缘层、第二栅绝缘层、以及层间介质层,第一栅绝缘层、第二栅绝缘层和层间介质层的总厚度小于740纳米。
其中,第一栅绝缘层的厚度小于130纳米。
其中,第二栅绝缘层的厚度小于110纳米。
其中,层间介质层的厚度小于500纳米。
其中,阵列基板还包括有机层,有机层位于无机膜组层上且不填充通孔,源漏极层位于有机层上,有机层的厚度小于1500纳米。
为了解决上述问题,本申请实施例还提供了一种阵列基板的制作方法,该阵列基板的制作方法包括:提供基底,基底包括显示区域;在基底上形成低温多晶硅层,低温多晶硅层位于显示区域;在形成有低温多晶硅层的基底上形成无机膜组层;在无机膜组层上制作通孔,通孔位于低温多晶硅层上方,且通孔的侧壁与底壁之间的夹角不小于100度;在无机膜组层上形成源漏极层,源漏极层覆盖通孔的侧壁和底壁,以与低温多晶硅层连接。
其中,无机膜组层包括依次远离低温多晶硅层的第一栅绝缘层、第二栅绝缘层、以及层间介质层,在形成有低温多晶硅层的基底上形成无机膜组层的步骤具体包括:在形成有低温多晶硅层的基底上沉积第一栅绝缘层,第一栅绝缘层覆盖低温多晶硅层;在第一栅绝缘层上沉积第二栅绝缘层;在第二栅绝缘层上沉积层间介质层,第一栅绝缘层、第二栅绝缘层和层间介质层的总厚度小于1500纳米。
为了解决上述问题,本申请实施例还提供了一种显示面板,该显示面板包括上述任一项的阵列基板。
本申请的有益效果是:区别于现有技术,本申请提供的阵列基板包括基底、以及在基底上依次设置的低温多晶硅层、无机膜组层和源漏极层,其中,基底包括显示区域,低温多晶硅层位于显示区域,无机膜组层上设有通孔,通孔位于低温多晶硅层上方,且通孔的侧壁与底壁之间的夹角不小于100度,源漏极层覆盖通孔的侧壁和底壁以与低温多晶硅层连接,如此,通过减小位于源漏极层与低温多晶硅层之间的通孔的锥角,以避免源漏极层在通孔的锥角处出现厚度较薄甚至断线的问题,进而提高产品良率。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的阵列基板的结构示意图;
图2是图1中通孔131的结构示意图;
图3是本申请实施例提供的阵列基板的另一结构示意图;
图4是本申请实施例提供的阵列基板的另一结构示意图;
图5是本申请实施例提供的阵列基板的制作方法的流程示意图;
图6是图5中S43的结构示意图;
图7是本申请实施例提供的显示面板的结构示意图。
【具体实施方式】
下面结合附图和实施例,对本申请作进一步的详细描述。特别指出的是,以下实施例仅用于说明本申请,但不对本申请的范围进行限定。同样的,以下实施例仅为本申请的部分实施例而非全部实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例,都属于本申请保护的范围。
目前,在AMOLED面板的阵列基板制程工艺中,源漏极层通过层间通孔与薄膜晶体管的有源层实现连接,但由于层间通孔的锥角过大,会导致源漏极层出现厚度较薄甚至断线的问题。为了解决上述技术问题,本申请采用的技术方案是提供一种阵列基板,以避免源漏极层由于层间通孔的锥角过大而出现厚度较薄甚至断线的问题。
请参阅图1和图2,图1是本申请实施例提供的阵列基板的结构示意图,图2是图1中通孔131的结构示意图。如图1和图2所示,该阵列基板10包括基底11、以及在基底11上依次设置的的低温多晶硅层12、无机膜组层13和源漏极层14。其中,基底11包括显示区域C1,低温多晶硅层12位于显示区域C1,无机膜组层13覆盖低温多晶硅层12,其上设有通孔131,通孔131位于低温多晶硅层12上方,且通孔131的侧壁131A与底壁131B之间的夹角θ不小于100度,源漏极层14覆盖通孔131的侧壁131A和底壁131B以与低温多晶硅层12连接。
在本实施例中,通过设置通孔131的侧壁131A与底壁131B之间的夹角θ不小于100度,也即,通孔131的锥角不大于80度,能够避免在通孔131的侧壁131A和底壁131B上形成的源漏极层14由于锥角过大而在通孔131的锥角处出现厚度较薄甚至断线的问题。
具体实施时,可以通过设计一系列不同的曝光时间、曝光能量、刻蚀液等刻蚀条件,以确保通孔131的侧壁131A与底壁131B之间的夹角θ不小于100度。例如,在一些实施例中,通孔131的侧壁131A与底壁131B之间的夹角的范围可以为105~110度,也即,通孔131的锥角可以为70~75度,以避免源漏极层14在通孔131的锥角处出现厚度较薄甚至断线的问题。
其中,基底11可以为柔性基底,且其材质可以为聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚醚砜基板等有机聚合物中的一种。源漏极层14的材质可以为铝、铜、银等金属材料。
具体地,如图3所示,无机膜组层13可以包括依次远离低温多晶硅层12的第一栅绝缘层132、第二栅绝缘层133、以及层间介质层134,上述通孔131位于低温多晶硅层12上方,且贯穿第一栅绝缘层132、第二栅绝缘层133和层间介质层134。
其中,第一栅绝缘层132的材质可以为SiOx,第二栅绝缘层133的材质可以为SiNx,层间介电层134的材质可以为SiNx和SiOx中的一种或两种。
在一些实施例中,可以通过减小上述第一栅绝缘层132、第二栅绝缘层133和层间介质层134的总厚度,以减小贯穿第一栅绝缘层132、第二栅绝缘层133和层间介质层134的通孔131的深度,进而减小源漏极层14在通孔131内壁上的弯折应力,以避免源漏极层14出现断线的问题。例如,在现有的阵列基板中,若上述第一栅绝缘层132、第二栅绝缘层133和层间介质层134的总厚度为740纳米,则在本实施例中,可以设置上述第一栅绝缘层132、第二栅绝缘层133和层间介质层134的总厚度小于740纳米,以避免由于通孔131的深度过大而导致源漏极层14由于弯折应力过大而出现断线的问题。
在一个具体实施例中,可以通过减小第一栅绝缘层132的厚度,以达到减小上述第一栅绝缘层132、第二栅绝缘层133和层间介质层134的总厚度的目的。例如,在现有的阵列基板中,若上述第一栅绝缘层132的厚度为130纳米,则在本实施例中,可以设置上述第一栅绝缘层132的厚度小于130纳米,并且,在具体实施时,可以通过设计120纳米、110纳米、100纳米、90纳米等一系列不同厚度的第一栅绝缘层132进行试验,以在不影响阵列基板光电性能的情况下确定第一栅绝缘层132的最优厚度。
在另一个具体实施例中,还可以通过减小第二栅绝缘层133的厚度,以达到减小上述第一栅绝缘层132、第二栅绝缘层133和层间介质层134的总厚度的目的。例如,在现有的阵列基板中,若上述第二栅绝缘层133的厚度为110纳米,则在本实施例中,可以设置上述第二栅绝缘层133的厚度小于110纳米,并且,在具体实施时,可以通过设计100纳米、90纳米、80纳米、70纳米等一系列不同厚度的第二栅绝缘层133进行试验,以在不影响阵列基板光电性能的情况下确定第二栅绝缘层133的最优厚度。
在又一个具体实施例中,还可以通过减小层间介质层134的厚度,以达到减小上述第一栅绝缘层132、第二栅绝缘层133和层间介质层134的总厚度的目的。例如,在现有的阵列基板中,若上述层间介质层134的厚度为500纳米,则在本实施例中,可以设置上述层间介质层134的厚度小于500纳米,并且,在具体实施时,可以通过设计490纳米、480纳米470纳米、460纳米等一系列不同厚度的层间介质层134进行试验,以在不影响阵列基板光电性能的情况下确定层间介质层134的最优厚度。
需要说明的是,为达到减小第一栅绝缘层132、第二栅绝缘层133和层间介质层134的总厚度的目的,可以同时减小第一栅绝缘层132、第二栅绝缘层133和层间介质层134三者的厚度,例如,第一栅绝缘层132的厚度小于130纳米,第二栅绝缘层133的厚度小于110纳米,且层间介质层134的厚度小于500纳米,也可以仅减小第一栅绝缘层132、第二栅绝缘层133和层间介质层134中的其中一层或两层的厚度。
请继续参阅图3,阵列基板10还可以包括依次远离低温多晶硅层12的第一金属层15和第二金属层16。其中,第一金属层15和第二金属层16均位于显示区域C1,且第一金属层15位于第一栅绝缘层132和第二栅绝缘层133之间,第二金属层16位于第二栅绝缘层133和层间介质层134之间。
具体地,上述低温多晶硅层12可以为阵列基板10中薄膜晶体管的有源层,且源漏极层14经上述通孔131与低温多晶硅层12连接,第一金属层15可以为图案化的栅极层,且其包括阵列基板10中薄膜晶体管的栅极、以及存储电容的下电极,第二金属层16可以包括阵列基板10中存储电容的上电极,且该上电极与上述第一金属层15中的下电极共同构成阵列基板10中的存储电容。
在本实施例中,上述通孔131在基底11上的投影区域与上述第一金属层15和第二金属层16在基底11上的投影区域不重叠,也即,在无机膜组层13上制作通孔131时并不会损坏上述第一金属层15和第二金属层16。
在一些实施例中,如图4所示,无机膜组层13还可以包括开口135,该开口135位于显示区域C1,且其在上述基底11上的投影区域与上述低温多晶硅层12、第一金属层15和第二金属层16在基底11上的投影区域不重叠,也即,在无机膜组层13上制作开口135时并不会损坏阵列基板10中薄膜晶体管的结构。
进一步地,阵列基板10还可以包括有机层17,该有机层17位于无机膜组层13上,源漏极层14位于有机层17上,该有机层17填充上述开口135,但不填充通孔131。如此,通过在无机膜组层13上制作开口135,并在无机膜组层13上形成有机层17,且有机层17填充上述开口135,能够减小显示区域C1上的弯折应力,进而提高显示区域C1的弯折性能。
具体地,上述位于无机膜组层13与源漏极层14之间的有机层17会增大上述通孔131附近的膜层段差,进而会加重覆盖于通孔131内壁上的源漏极层14的局部厚度较薄甚至断线的问题。为了解决这一技术问题,可以减小上述有机层17的厚度,例如,可以设置有机层17的厚度小于1500纳米。
其中,有机层17的材质可以为聚酰亚胺系树脂、环氧系树脂或亚克力系树脂等有机绝缘材料。
需要说明的是,上述有机层17在整体上为厚度均一的层结构,但由于无机膜组层13在开口135处存在高度差,导致有机层17在填充开口135后会在开口135处出现一定程度的厚度不均一问题,因此,在本申请中,有机层17的厚度以远离开口135的有机层17的厚度为准。
区别于现有技术,本实施例中的阵列基板,通过减小位于源漏极层与低温多晶硅层之间的通孔的锥角,以避免源漏极层在通孔的锥角处出现厚度较薄甚至断线的问题,进而提高产品良率。
请参阅图5,图5是本申请实施例提供的阵列基板的制作方法的流程示意图,该阵列基板的制作方法具体流程可以如下:
S41:提供基底,基底包括显示区域。
其中,基底可以为柔性基底,且其材质可以为聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚醚砜基板等有机聚合物中的一种。
S42:在基底上形成低温多晶硅层,低温多晶硅层位于显示区域。
例如,在显示区域,利用化学气相沉积工艺在基底上形成非晶硅层,然后采用准分子镭射退火工艺对该非晶硅层进行处理,以形成对应的低温多晶硅层。
S43:在形成有低温多晶硅层的基底上形成无机膜组层。
其中,无机膜组层可以包括依次远离低温多晶硅层的第一栅绝缘层、第二栅绝缘层、以及层间介质层。具体地,如图6所示,S43可以包括:
S431:在形成有低温多晶硅层的基底上沉积第一栅绝缘层,第一栅绝缘层覆盖低温多晶硅层。
例如,利用化学气相沉积工艺,在形成有低温多晶硅层的基底上形成第一栅绝缘层。其中,第一栅绝缘层的材质可以为SiOx。
S432:在第一栅绝缘层上沉积第二栅绝缘层。
例如,利用化学气相沉积工艺,在第一栅绝缘层上形成第二栅绝缘层。其中,第二栅绝缘层的材质可以为SiNx。
S433:在第二栅绝缘层上沉积层间介质层,第一栅绝缘层、第二栅绝缘层和层间介质层的总厚度小于740纳米。
例如,利用化学气相沉积工艺,在第二栅绝缘层上形成层间介电层。其中,层间介电层的材质可以为SiNx和SiOx中的一种或两种。
在一个具体实施例中,在S431之后以及S432之前,还可以包括:
子步骤A:在第一栅绝缘层上形成第一金属层,第一金属层位于显示区域,且第二栅绝缘层覆盖第一金属层。
其中,第一金属层可以为图案化的栅极层,包括阵列基板中薄膜晶体管的栅极、以及存储电容的下电极。具体地,子步骤A可以具体包括:在显示区域,利用物理气相沉积工艺在第一栅绝缘层上铺设第一金属材料层,然后通过曝光、蚀刻工艺将该第一金属材料层图形化,以得到图案化的栅极层。其中,第一金属层的材质可以为钼。
在S432之后以及S433之前,还可以包括:
子步骤B:在第二栅绝缘层上形成第二金属层,第二金属层位于显示区域,且层间介质层覆盖第二金属层。
其中,第二金属层包括阵列基板中存储电容的上电极,该上电极与上述第一金属层中的下电极共同构成阵列基板中的存储电容。具体地,子步骤B可以具体包括:在显示区域,利用物理气相沉积工艺在第二栅绝缘层上铺设第二金属材料层,然后通过曝光、蚀刻工艺将该第二金属材料层图形化,以得到第二金属层。其中,第二金属层的材质可以为钼。
S44:在无机膜组层上制作通孔,通孔位于低温多晶硅层上方,且通孔的侧壁与底壁之间的夹角不小于100度。
例如,对位于显示区域上的无机膜组层的预设位置进行刻蚀,以形成通孔。其中,该通孔贯穿上述第一栅绝缘层、第二栅绝缘层和层间介质层,且其在基底上的投影区域与上述第一金属层和第二金属层在基底上的投影区域不重叠,也即,在无机膜组层上制作第一开口时并不会损坏上述第一金属层和第二金属层。
具体地,可以通过设计一系列不同的曝光时间、曝光能量、刻蚀液等刻蚀条件,以确保上述通过刻蚀工艺形成的通孔的侧壁与底壁之间的夹角不小于100度。例如,在一些实施例中,通孔的侧壁与底壁之间的夹角的范围可以为105~110度。
S45:在无机膜组层上形成源漏极层,源漏极层覆盖通孔的侧壁和底壁,以与低温多晶硅层连接。
例如,利用物理气相沉积工艺在无机膜组层、以及通孔的侧壁和底壁上铺设源漏极材料层,然后通过曝光、蚀刻工艺将该源漏极材料层图形化,以得到图案化的源漏极层。其中,源漏极层的材质可以为铝、铜、银等金属材料,且源漏极层经通孔与上述低温多晶硅层连接。
在本实施例中,通过设置通孔的侧壁与底壁之间的夹角不小于100度,也即,通孔的锥角不大于80度,能够避免在通孔的侧壁和底壁上形成的源漏极层由于锥角过大而在通孔的锥角处出现厚度较薄甚至断线的问题。
在上述S431、S433和S433中,通过控制形成的第一栅绝缘层、第二栅绝缘层和层间介质层的总厚度小于740纳米,能够减小贯穿第一栅绝缘层、第二栅绝缘层和层间介质层的通孔的深度,进而减小源漏极层在通孔内壁上的弯折应力,以避免源漏极层出现断线的问题。
具体地,可以通过控制形成的第一栅绝缘层的厚度小于130纳米,或者,也可以通过控制形成的第二栅绝缘层的厚度小于110纳米,或者,也可以通过控制形成的层间介质层的厚度小于500纳米,以达到第一栅绝缘层、第二栅绝缘层和层间介质层的总厚度小于740纳米的目的。
在一个实施例中,上述无机膜组层还可以包括开口,该开口位于显示区域,且其在上述基底上的投影区域与上述低温多晶硅层、第一金属层和第二金属层在基底上的投影区域不重叠,也即,在无机膜组层上制作开口时并不会损坏阵列基板中薄膜晶体管的结构。具体地,上述S44可以具体包括:在无机膜组层上制作通孔和开口,通孔位于低温多晶硅层上方,开口位于显示区域,且通孔的侧壁与底壁之间的夹角不小于100度。
进一步地,在上述S44之后以及S45之前,还可以包括:
在无机膜组层上形成有机层,有机层填充开口,但不填充通孔,源漏极层位于有机层上,有机层的厚度小于1500纳米。
如此,通过在无机膜组层上制作开口,并在无机膜组层上形成有机层,且有机层填充上述开口,能够减小显示区域上的弯折应力,进而提高显示区域的弯折性能。
另外,通过控制形成的有机层的厚度小于1500纳米,能够减小上述通孔附近的膜层段差,进而避免覆盖于通孔内壁上的源漏极层出现局部厚度较薄甚至断线的问题。
区别于现有技术,本实施例中的阵列基板的制作方法,通过减小位于源漏极层与低温多晶硅层之间的通孔的锥角,以避免源漏极层在通孔的锥角处出现厚度较薄甚至断线的问题,进而提高产品良率。
请参阅图7,图7是本申请实施例提供的显示面板的结构示意图。如图7所示,该显示面板80包括上述任一实施例的阵列基板81。
阵列基板81包括基底、以及在基底上依次设置的的低温多晶硅层、无机膜组层和源漏极层,其中,基底包括显示区域,低温多晶硅层位于显示区域,无机膜组层覆盖低温多晶硅层,其上设有通孔,通孔位于低温多晶硅层上方,且通孔的侧壁与底壁之间的夹角不小于100度,源漏极层覆盖通孔的侧壁和底壁以与低温多晶硅层连接。
区别于现有技术,本实施例中的显示面板,通过减小位于源漏极层与低温多晶硅层之间的通孔的锥角,以避免源漏极层在通孔的锥角处出现厚度较薄甚至断线的问题,进而提高产品良率。
以上所述仅为本申请的较佳实施例而已,并不用以限制本申请,凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本申请的保护范围之内。
Claims (10)
1.一种阵列基板,其特征在于,包括:
基底,所述基底包括显示区域;
位于所述基底上的低温多晶硅层,所述低温多晶硅层位于所述显示区域;
位于所述基底上且覆盖所述低温多晶硅层的无机膜组层,所述无机膜组层上设有通孔,所述通孔位于所述低温多晶硅层上方,且所述通孔的侧壁与底壁之间的夹角不小于100度;
位于所述无机膜组层上的源漏极层,所述源漏极层覆盖所述通孔的侧壁和底壁,以与所述低温多晶硅层连接。
2.根据权利要求1所述的阵列基板,其特征在于,所述通孔的侧壁与底壁之间的夹角的范围为105~110度。
3.根据权利要求1所述的阵列基板,其特征在于,所述无机膜组层包括依次远离所述低温多晶硅层的第一栅绝缘层、第二栅绝缘层、以及层间介质层,所述第一栅绝缘层、所述第二栅绝缘层和所述层间介质层的总厚度小于740纳米。
4.根据权利要求3所述的阵列基板,其特征在于,所述第一栅绝缘层的厚度小于130纳米。
5.根据权利要求3所述的阵列基板,其特征在于,所述第二栅绝缘层的厚度小于110纳米。
6.根据权利要求3所述的阵列基板,其特征在于,所述层间介质层的厚度小于500纳米。
7.根据权利要求1所述的阵列基板,其特征在于,所述阵列基板还包括有机层,所述有机层位于所述无机膜组层上且不填充所述通孔,所述源漏极层位于所述有机层上,所述有机层的厚度小于1500纳米。
8.一种阵列基板的制作方法,其特征在于,包括:
提供基底,所述基底包括显示区域;
在所述基底上形成低温多晶硅层,所述低温多晶硅层位于所述显示区域;
在形成有所述低温多晶硅层的所述基底上形成无机膜组层;
在所述无机膜组层上制作通孔,所述通孔位于所述低温多晶硅层上方,且所述通孔的侧壁与底壁之间的夹角不小于100度;
在所述无机膜组层上形成源漏极层,所述源漏极层覆盖所述通孔的侧壁和底壁,以与所述低温多晶硅层连接。
9.根据权利要求8所述的制作方法,其特征在于,所述无机膜组层包括依次远离所述低温多晶硅层的第一栅绝缘层、第二栅绝缘层、以及层间介质层,所述在形成有所述低温多晶硅层的所述基底上形成无机膜组层的步骤具体包括:
在形成有所述低温多晶硅层的所述基底上沉积第一栅绝缘层,所述第一栅绝缘层覆盖所述低温多晶硅层;
在所述第一栅绝缘层上沉积第二栅绝缘层;
在所述第二栅绝缘层上沉积层间介质层,所述第一栅绝缘层、第二栅绝缘层和层间介质层的总厚度小于740纳米。
10.一种显示面板,其特征在于,包括如权利要求1-7任一项所述的阵列基板。
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