CN103456624A - 过孔刻蚀方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 80
- 238000005530 etching Methods 0.000 title claims abstract description 57
- 239000010410 layer Substances 0.000 claims abstract description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 5
- 239000012212 insulator Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 9
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- 239000003595 mist Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
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- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
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- 239000000203 mixture Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
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- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
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- 238000005096 rolling process Methods 0.000 description 1
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Abstract
本发明公开了一种过孔刻蚀方法,涉及半导体制造领域,克服了现有技术过孔刻蚀方法过孔终点无法控制且坡度角不利的缺陷。本发明实施例的过孔刻蚀方法,包括:形成过孔刻蚀结构,过孔刻蚀结构包括依次形成在基板上的低温多晶硅层、栅极绝缘层、栅极金属层、层间绝缘层;在过孔刻蚀结构上形成包括过孔掩膜图形的掩膜层;采用第一刻蚀方法刻蚀过孔刻蚀结构,刻蚀至栅极绝缘层的第一厚度处;采用第二刻蚀方法刻蚀过孔刻蚀结构,刻蚀掉剩余厚度的栅极绝缘层,露出低温多晶硅层;移除掩膜层,形成过孔结构。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种过孔刻蚀方法。
背景技术
近年来,随着显示产品的应用领域越来越广泛,对显示技术的研究也变得越来越深入。作为一种新型制造工艺,LTPS(英文:Low TemperaturePoly-Silicon,中文:低温多晶硅)技术利用准分子激光退火工艺将非晶硅(a-Si)薄膜层转变为多晶硅(Poly-Si)薄膜层。相比非晶硅材料,多晶硅材料的电子迁移率有100倍以上的增加,因此使用LTPS技术可使显示产品具有更快的响应时间,具有更高的分辨率,更佳的画面显示品质。另外使用LTPS技术,能够减少集成电路IC,简化显示装置的外围,实现窄边框技术。
如图1所示,图1提供了一种应用LTPS的阵列基板中间结构,该中间结构包括:基板1、低温多晶硅层2、栅极绝缘层3、栅极金属层4、层间绝缘层5以及源漏极过孔6等等。为制备上述阵列基板中间结构,形成如图1所示的过孔,现有刻蚀工艺通常利用干法刻蚀或湿法刻蚀来完成过孔的刻蚀工作。
然而,发明人发现现有技术中至少存在如下问题:若要形成如图1所示的过孔,现有技术过孔刻蚀方法至少需要刻蚀栅极绝缘层以及层间绝缘层。通常来说,栅极绝缘层以及层间绝缘层的厚度之和大于0.6um,而低温多晶硅的厚度小于0.05um,因此,利用现有技术过孔刻蚀方法极容易发生过刻现象,从而出现低温多晶硅过刻蚀甚至将低温多晶硅全部刻蚀掉的情况,对阵列基板的性能产生不利影响。另一方面,现有技术过孔刻蚀方法通过多层连续刻蚀完成过孔的制备工作,因此可能存在过孔坡度角问题。举例来说,在相邻膜层过渡位置处,由于现有技术过孔刻蚀方法对不同膜层材质刻蚀速率的差异,因此会在过孔上形成了梯台,从而影响了过孔坡度角。若要消除该坡度角问题,还需进一步利用氢氟酸和氨的混合液进行湿法刻蚀,不仅增加了刻蚀工艺的复杂程度,而且对坡度角的修复效果有限。
发明内容
本发明的实施例提供一种过孔刻蚀方法,克服了现有技术过孔刻蚀方法过孔终点无法控制且坡度角不利的缺陷。
为解决上述技术问题,本发明的实施例采用如下技术方案:
一种过孔刻蚀方法,包括:
形成过孔刻蚀结构,所述过孔刻蚀结构包括依次形成在基板上的低温多晶硅层、栅极绝缘层、栅极金属层、层间绝缘层;
在所述过孔刻蚀结构上形成包括过孔掩膜图形的掩膜层;
采用第一刻蚀方法刻蚀所述过孔刻蚀结构,刻蚀至所述栅极绝缘层的第一厚度处;
采用第二刻蚀方法刻蚀所述过孔刻蚀结构,刻蚀掉剩余厚度的所述栅极绝缘层,露出所述低温多晶硅层;
移除所述掩膜层,形成过孔结构。
优选的,所述第一刻蚀方式为干法刻蚀;所述第二刻蚀方法为利用有机刻蚀气体的干法刻蚀,所述有机刻蚀气体为包括CF4、H2、C4F8、Ar、O2的混合气体。
优选的,所述第一刻蚀方法以及所述第二刻蚀方法的刻蚀腔体压力为0~20mtorr,刻蚀功率不小于5000W。
进一步的,所述栅极绝缘层的材料为氮化硅、氧化硅、碳化硅材料中的任意一种或任意几种。
进一步的,形成的所述过孔结构的坡度角为55°~75°。
本发明实施例提供的一种过孔刻蚀方法,该过孔刻蚀方法形成过孔的过程中采用了两次刻蚀工艺,从而能够在形成过孔结构的同时保留低温多晶硅层,而且可以形成较好的过孔坡度角。该过孔刻蚀方法工艺流程简单,形成的过孔结构较佳。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例过孔刻蚀结构的最终结构示意图;
图2为本发明实施例过孔刻蚀方法的流程示意图;
图3为本发明实施例过孔刻蚀结构的结构示意图之一;
图4为本发明实施例过孔刻蚀结构的结构示意图之二;
图5为本发明实施例过孔刻蚀结构的结构示意图之三;
图6为本发明实施例过孔刻蚀结构的结构示意图之四。
具体实施方式
本发明的实施例提供一种过孔刻蚀方法,克服了现有技术过孔刻蚀方法过孔终点无法控制且坡度角不利的缺陷。
以下描述中,为了说明而不是为了限定,提出了诸如特定系统结构、接口、技术之类的具体细节,以便透切理解本发明。然而,本领域的技术人员应当清楚,在没有这些具体细节的其它实施例中也可以实现本发明。在其它情况中,省略对众所周知的装置、电路以及方法的详细说明,以免不必要的细节妨碍本发明的描述。
下面结合下述附图对本发明实施例做详细描述。
本发明实施例提供了一种过孔刻蚀方法,如图2所示,该过孔刻蚀方法包括:
步骤S101:形成过孔刻蚀结构。
具体的,如图3所示,过孔刻蚀结构包括基板1、低温多晶硅层2、栅极绝缘层3、栅极金属层4、层间绝缘层5。需要说明的是,由于阵列基板制备工艺的不同,生成的过孔刻蚀结构并不仅限于如图3所示的膜层结构,例如:在层间绝缘层上方还可能设置有其他的绝缘膜层结构,此时本发明实施例的过孔刻蚀方法还需刻蚀掉除栅极绝缘层以及层间绝缘层外的其他绝缘膜层。在本实施例中仅以过孔刻蚀结构中包括有栅极绝缘层以及层间绝缘层为例进行介绍。本领域技术人员应该可以理解的是,本发明中所提及的过孔刻蚀结构以及过孔刻蚀结构的制备工艺并不构成对本发明实施例过孔刻蚀方法的进一步限定,在此不做赘述。
步骤S102:在所述过孔刻蚀结构上形成包括过孔掩膜图形的掩膜层。
具体的,如图4所示,在完成上述步骤S101的过孔刻蚀结构上形成掩膜层7,该掩膜层7中包括有用于形成过孔的过孔掩膜图形。例如,在如图3所示的孔刻蚀结构上旋转涂覆一层掩膜材料,利用构图工艺,生成包括过孔掩膜图形的掩膜层。其中,在本发明实施例中,构图工艺包括涂胶、曝光、显影、刻蚀、光刻胶剥离等步骤。
步骤S103:采用第一刻蚀方法刻蚀所述过孔刻蚀结构,刻蚀至所述栅极绝缘层的第一厚度处。
具体的,对完成上述步骤S102的过孔刻蚀结构进行第一刻蚀方法刻蚀。进一步的,第一刻蚀方法可包括干法刻蚀。如图5所示,采用第一刻蚀方法刻蚀过孔刻蚀结构,刻蚀的终点为栅极绝缘层3的第一厚度处。将所述栅极绝缘层的所述第一厚度定义为D1。具体的,第一厚度D1可为700~1400。通过第一刻蚀方法刻蚀,过孔刻蚀结构形成如图5所示的结构。
优选的,所述第一刻蚀方法的刻蚀腔体压力为0~20mtorr,刻蚀功率不小于5000W。
需要说明的是,由于第一刻蚀方法刻蚀终点为栅极绝缘层的第一厚度处,因此第一刻蚀方法至少需要刻蚀层间绝缘层以及部分栅极绝缘层;若过孔刻蚀结构中还包括设置在层间绝缘层上方的其他绝缘层时,第一刻蚀方法还需要刻蚀掉其他绝缘层。
步骤S104:采用第二刻蚀方法刻蚀所述过孔刻蚀结构,刻蚀掉剩余厚度的所述栅极绝缘层,露出所述低温多晶硅层。
具体的,对完成上述步骤S103的过孔刻蚀结构进行第二刻蚀方法刻蚀。采用第二刻蚀方法刻蚀过孔刻蚀结构,第二刻蚀方法刻蚀掉上述步骤剩余的栅极绝缘层露出低温多晶硅层。也就是说,第二刻蚀方法将上述步骤剩余的第一厚度栅极绝缘层刻蚀掉,且第二刻蚀方法的刻蚀终点为低温多晶硅层的对应位置处。通过第二刻蚀方法刻蚀,过孔刻蚀结构形成如图6所示的结构。
进一步的,第二刻蚀方法可包括为利用有机刻蚀气体的干法刻蚀,所述有机刻蚀气体为包括CF4、H2、C4F8、Ar、O2的混合气体。需要说明的是,利用上述有机刻蚀气体的干法刻蚀可令第二刻蚀方法具有较高的刻蚀选择性,使得第二刻蚀方法在刻蚀掉栅极绝缘层的同时最大程度的使低温多晶硅层得到保留。
优选的,所述第二刻蚀方法的刻蚀腔体压力为0~20mtorr,刻蚀功率不小于5000W。
步骤S105:移除所述掩膜层,形成过孔结构。
具体的,对完成上述步骤S104的过孔刻蚀结构采用剥离工艺,移除掩膜层的掩膜材料,在过孔刻蚀结构上形成过孔结构。此时过孔刻蚀结构形成如图1所示的结构。
进一步的,本发明实施例中过孔刻蚀方法提及的栅极绝缘层,其材料可为氮化硅、氧化硅、碳化硅材料中的任意一种或任意几种,或者也可以为本领域技术人员在本领域中常用的其他绝缘材料。
优选的,本发明实施例中过孔刻蚀方法形成的所述过孔结构的坡度角为55°~75°。
本发明实施例提供的一种过孔刻蚀方法,该过孔刻蚀方法工艺流程较为简单,形成过孔的过程中采用了两次刻蚀工艺。通过第一刻蚀方法以及第二刻蚀方法在形成过孔结构的同时保留低温多晶硅层,克服了现有技术易于过刻蚀低温多晶硅的缺陷;同时,由于采用了干法刻蚀工艺,保证了形成的过孔具有较好的坡度角。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。
Claims (6)
1.一种过孔刻蚀方法,其特征在于,包括:
形成过孔刻蚀结构,所述过孔刻蚀结构包括依次形成在基板上的低温多晶硅层、栅极绝缘层、栅极金属层、层间绝缘层;
在所述过孔刻蚀结构上形成包括过孔掩膜图形的掩膜层;
采用第一刻蚀方法刻蚀所述过孔刻蚀结构,刻蚀至所述栅极绝缘层的第一厚度处;
采用第二刻蚀方法刻蚀所述过孔刻蚀结构,刻蚀掉剩余厚度的所述栅极绝缘层,露出所述低温多晶硅层;
移除所述掩膜层,形成过孔结构。
2.根据权利要求1所述的过孔刻蚀方法,其特征在于,所述第一刻蚀方式为干法刻蚀;所述第二刻蚀方法为利用有机刻蚀气体的干法刻蚀,所述有机刻蚀气体为包括CF4、H2、C4F8、Ar、O2的混合气体。
3.根据权利要求1或2所述的过孔刻蚀方法,其特征在于,所述第一刻蚀方法以及所述第二刻蚀方法的刻蚀腔体压力为0~20mtorr,刻蚀功率不小于5000W。
5.根据权利要求1所述的过孔刻蚀方法,其特征在于,所述栅极绝缘层的材料为氮化硅、氧化硅、碳化硅材料中的任意一种或任意几种。
6.根据权利要求1所述的过孔刻蚀方法,其特征在于,形成的所述过孔结构的坡度角为55°~75°。
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WO2018171199A1 (zh) * | 2017-03-24 | 2018-09-27 | 京东方科技集团股份有限公司 | 制备阵列基板的方法、阵列基板和显示装置 |
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