WO2023134022A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2023134022A1
WO2023134022A1 PCT/CN2022/084072 CN2022084072W WO2023134022A1 WO 2023134022 A1 WO2023134022 A1 WO 2023134022A1 CN 2022084072 W CN2022084072 W CN 2022084072W WO 2023134022 A1 WO2023134022 A1 WO 2023134022A1
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WO
WIPO (PCT)
Prior art keywords
electrode
via hole
substrate
insulating layer
support structure
Prior art date
Application number
PCT/CN2022/084072
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English (en)
French (fr)
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WO2023134022A9 (zh
Inventor
童彬彬
王利忠
先建波
雷利平
龙春平
邸云萍
宁策
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000661.7A priority Critical patent/CN114730776A/zh
Publication of WO2023134022A1 publication Critical patent/WO2023134022A1/zh
Publication of WO2023134022A9 publication Critical patent/WO2023134022A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • Embodiments of the present disclosure relate to a display panel.
  • virtual reality technology is a new technology that "seamlessly" integrates real world information and virtual world information. Compared with conventional display products, the most obvious feature of virtual reality display products is their ultra-high resolution.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • At least one embodiment of the present disclosure provides a display panel.
  • the orthographic projections of the lines on the base substrate are at least partially overlapped to improve the resolution and aperture ratio of the display panel.
  • the display panel includes: a first substrate and a second substrate that are opposed to each other, wherein the first substrate includes a base substrate, and is sequentially arranged on the base substrate.
  • the first via hole is electrically connected to the first electrode, and a first support structure is provided in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; At least part of the first support structure is located in the first via hole; and the orthographic projection of the first via hole on the base substrate and the orthographic projection of the grid line on the base substrate overlap at least partially.
  • the first substrate is an array substrate, and the array substrate includes the gate lines and data lines arranged on the base substrate in a crosswise arrangement, and a plurality of pixel units;
  • the pixel unit includes: the first electrode, the second electrode and the first interlayer insulating layer; the distance between the second electrode and the first interlayer insulating layer is contact with the surface of the base substrate, and the second electrode extends from the upper surface of the first interlayer insulating layer to the sidewall and the lower opening area of the first via hole and is in contact with the lower opening area
  • the first electrode is connected.
  • the first interlayer insulating layer includes at least a planarization layer, and the first via hole penetrates through the planarization layer.
  • the surface of the first supporting structure close to the second substrate is a plane or a concave surface that is depressed toward one side of the base substrate.
  • the first supporting structure extends downwards in the first via hole to a lower opening area of the first via hole.
  • the first support structure extends upwards in the first via hole to the upper opening area of the first via hole, and the first support structure The top is higher than the upper surface of the first interlayer insulating layer.
  • the pixel unit further includes a third electrode located above the upper surface of the first interlayer insulating layer, and the third electrode is separated from the first interlayer insulating layer.
  • a second interlayer insulating layer is provided between the second electrodes on the upper surface of the insulating layer; the second interlayer insulating layer includes an opening penetrating with the first interlayer insulating layer, and the first support The structure extends toward the second substrate and has a protruding structure higher than the second interlayer insulating layer.
  • the third electrode includes metal oxide strip-shaped portions arranged at intervals on the upper surface of the second interlayer insulating layer, and Metal parts distributed between strip parts.
  • the third electrode includes a metal part and a metal oxide strip part covering the side surface and the upper surface of the metal part, and is parallel to the In the direction of the main surface of the base substrate, the third electrode includes a plurality of parts spaced apart from each other.
  • the part of the first support structure that exceeds the upper surface of the first interlayer insulating layer and the upper surface of the second interlayer insulating layer is vertically
  • the cross-sectional shape of the main surface of the base substrate and the direction perpendicular to the extension of the gate lines is a rectangle or a trapezoid or a trapezoid whose upper surface is recessed toward one side of the base substrate.
  • the first supporting structure extends beyond the upper surface of the second interlayer insulating layer toward the second substrate, and extends along the second interlayer The upper surface of the insulating layer extends away from the first via hole.
  • the pixel unit further includes a thin film transistor, and the thin film transistor includes a semiconductor layer, a source electrode and a drain electrode arranged at intervals, and the source electrode and the drain electrode connected to the semiconductor layer; the second electrode is a pixel electrode of the pixel unit; the first electrode is the drain or a transfer electrode used to connect the drain and the pixel electrode.
  • the first interlayer insulating layer includes at least an organic planarization layer
  • the second interlayer insulating layer includes at least an inorganic insulating layer
  • the third electrode is the The common electrode of the pixel unit.
  • the material of the drain electrode includes a transparent metal oxide conductive material.
  • the opening width d of the first via hole close to the upper surface of the first interlayer insulating layer satisfies: d ⁇ (K1*M/PPI)*(1 -AR).
  • the display panel further includes a thin film transistor
  • the thin film transistor includes a source electrode and a drain electrode arranged at intervals, and in a direction perpendicular to the main surface of the base substrate, the The angle formed between the edge of the first via hole close to the source and the plane where the main surface of the base substrate is located is ⁇ , and the edge of the first via hole close to the drain and the substrate The angle formed by the planes where the main surface of the base substrate is located is ⁇ , and ⁇ .
  • ⁇ > ⁇ and the difference between ⁇ - ⁇ ranges from 0.5° to 3°.
  • the design of the first via hole satisfies that the absolute value range of (d1-d2)-tan ⁇ 1*d3 is between 0 and 1.5, and d1 is the first The opening width of the side of the via hole away from the base substrate, d2 is the opening width of the side of the first via hole close to the base substrate, and d3 is the thickness of the first interlayer insulation, ⁇ 1 is an angle between the sidewall of the first via hole and the horizontal plane of the base substrate.
  • the first substrate further includes a switching transistor disposed on the base substrate; the switching transistor is disposed in the display area; the switching transistor includes sequentially stacked The first insulating layer, the light shielding layer, the second insulating layer, the metal oxide semiconductor layer, the gate insulating layer, the first gate, the third insulating layer, the first source, and the fourth insulating layer arranged on the base substrate layer and the first drain, and the first electrode is electrically connected to the metal oxide semiconductor layer through a third via hole sequentially passing through the fourth insulating layer, the third insulating layer and the gate insulating layer
  • the first source is electrically connected to the metal oxide semiconductor layer through a fourth via hole sequentially passing through the third insulating layer and the gate insulating layer.
  • the first substrate further includes a switching transistor disposed on the base substrate; the switching transistor is disposed in the display area; the switching transistor includes sequentially stacked The light shielding layer, buffer layer, first polysilicon layer, gate insulating layer, first gate, third insulating layer, base electrode layer, fourth insulating layer, first drain, The fifth insulating layer and the first source electrode, the basic electrode layer includes a first basic electrode and a second basic electrode oppositely arranged, and the first electrode communicates with the first electrode through the fifth via hole penetrating through the fourth insulating layer.
  • the first base electrode is electrically connected to serve as the first drain, and the first base electrode is connected to the first polysilicon through the sixth via hole penetrating through the third insulating layer and the gate insulating layer.
  • layers; the first source is electrically connected to the second base electrode through the seventh via hole that runs through the fifth insulating layer and the fourth insulating layer in sequence, and the second base electrode passes through the The third insulating layer and the eighth via hole of the gate insulating layer are electrically connected to the first polysilicon layer.
  • the contact portion of the first electrode and the second electrode is located at the fifth pass. hole and the seventh via hole, and the orthographic projection of the contact portion of the first electrode and the second electrode on the substrate is the same as that of the first grid on the substrate The orthographic projections on the substrate at least partially overlap.
  • the contact portion of the first electrode and the second electrode close to the fifth
  • the distance between one side of the via hole and the sixth via hole is equal to the length of the first electrode not covering the first gate.
  • the ends of the two ends of the light-shielding layer are located between the seventh via hole and the fifth via hole.
  • the contact portion of the first electrode and the second electrode is located between the seventh via hole and an end point of the light shielding layer close to the fifth via hole.
  • a second support structure is provided on the second substrate, and the surface of the first support structure close to the second substrate and the second support structure Surfaces of the structures close to the first substrate contact or maintain a set distance.
  • the orthographic projection of the second support structure on the base substrate and the orthographic projection of the first support structure on the base substrate are at least partially overlap.
  • the area of the contact surface between the second support structure and the first support structure is smaller than that of the second support structure or the contact surface of the first support structure.
  • the first interlayer insulating layer has a second via hole penetrating through the first interlayer insulating layer, and the second via hole is provided with a second via hole.
  • the orthographic projection of the third support structure on the base substrate and the orthographic projection of the second support structure on the base substrate do not have overlapping portions.
  • the third support structure extends away from the base substrate to the outside of the second via hole, and the third support structure fills the second via hole.
  • the via hole adapts the shape within the second via hole to the shape of the second via hole.
  • a longitudinal section of a portion of the third support structure extending beyond the second via hole has a trapezoidal shape.
  • the yield strength of the second support structure is greater than the joint pressure of the first substrate and the second substrate when the first substrate is combined with the second support structure alone.
  • the product of the area of the structure and the number of the second supporting structures is greater than the bond pressure of the first substrate and the second substrate when the first substrate is combined with the second support structure alone.
  • materials of the planarization layer and the first support structure are both light-transmitting materials.
  • the material of the first supporting structure is a light-shielding material
  • the extending direction of the first supporting structure is parallel to the extending direction of the gate lines.
  • FIG. 1 is a schematic cross-sectional structure diagram of a display panel provided by at least one embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of a first substrate provided by at least one embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure.
  • FIG. 5 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure.
  • FIG. 6 is a perspective view of a second electrode and a third electrode in the cross-sectional structure shown in FIG. 5;
  • FIG. 7 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure.
  • Fig. 9 is a perspective view of another second electrode and a third electrode provided by at least one embodiment of the present disclosure.
  • Fig. 10 is a schematic cross-sectional structure diagram of the structure shown in Fig. 9;
  • Fig. 11 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure.
  • Fig. 12 is a scanning electron micrograph of a first support structure provided by at least one embodiment of the present disclosure.
  • Fig. 13 is a schematic perspective view of a first substrate provided by at least one embodiment of the present disclosure.
  • Fig. 14 is a schematic perspective view of another first substrate provided by at least one embodiment of the present disclosure.
  • FIG. 15 is a process diagram of a method for manufacturing a display panel provided by at least one embodiment of the present disclosure.
  • FIG. 16 is a process diagram of another method for manufacturing a display panel provided by at least one embodiment of the present disclosure.
  • FIG. 17 is a process diagram of another method for manufacturing a display panel provided by at least one embodiment of the present disclosure.
  • FIG. 18 is a process diagram of another method for manufacturing a display panel provided by at least one embodiment of the present disclosure.
  • the inventors of the present disclosure have noticed that usually the first substrate included in the display panel has an interlayer insulating layer, a via structure is provided in the interlayer insulating layer, electrodes are provided in the via hole structure, and a supporting structure is provided in the interlayer insulating layer.
  • the area where the via hole structure is not set, and the orthographic projection of the gate line on the substrate and the orthographic projection of the via structure on the substrate do not overlap, so that the resolution and aperture ratio of the display panel are relatively high. Low, therefore, it can be considered to change the design of the display panel structure to improve the resolution and aperture ratio of the display panel.
  • the support structure is only arranged on the first substrate or the second substrate, so that it is easy to align the first substrate and the second substrate during the process of affixing the first substrate and the second substrate.
  • the corresponding display area or the corresponding display area of the second substrate is scratched, so it can be considered to set the first support structure and the second support structure on the first substrate and the second substrate respectively, so that the first substrate and the second During the mating process of the substrates, the surface of the first support structure close to the second substrate is in contact with the surface of the second support structure close to the first substrate, so as to support the second substrate and make a gap between the first substrate and the second substrate.
  • a gap is formed between the first substrate and the second substrate, so as to avoid scratching the display area corresponding to the first substrate or the display area corresponding to the second substrate during the process of joining the first substrate and the second substrate, thereby reducing the risk of edge light leakage.
  • At least one embodiment of the present disclosure provides a display panel, which can be applied to a high-resolution liquid crystal display panel.
  • the display panel includes: a first substrate (such as an array substrate) and a second substrate, and a first substrate and a second substrate A liquid crystal layer between the substrates, wherein the first substrate includes a base substrate, and a grid line, a first electrode, a first interlayer insulating layer and a second electrode arranged on the base substrate in sequence; the first interlayer The insulating layer has a first via hole penetrating through the first interlayer insulating layer, and the second electrode is electrically connected to the first electrode through the first via hole, in the area corresponding to the first via hole and away from the base substrate of the second electrode
  • One side of the first support structure is provided; at least part of the first support structure is located in the first via hole; and the orthographic projection of the first via hole on the base substrate and the orthographic projection of the grid line on the base substrate are at least partially overlapped.
  • At least part of the first support structure is located in the first via hole, and the orthographic projection of the first via hole on the base substrate and the orthographic projection of the grid line on the base substrate are at least partially overlapped. , to improve the resolution and aperture ratio of the display panel.
  • FIG. 1 is a schematic cross-sectional structure diagram of a display panel provided by at least one embodiment of the present disclosure.
  • the display panel 10 includes: a first substrate 101 and a second substrate 102 that are aligned with each other, wherein,
  • the first substrate 101 includes a base substrate 1011, and a gate line 1022, a first electrode 1012, a first interlayer insulating layer 1013, and a second electrode 1014 sequentially arranged on the base substrate 1011.
  • the first interlayer insulating layer 1013 has a first via hole 1015 penetrating through the first interlayer insulating layer 1013, the second electrode 1014 is electrically connected to the first electrode 1012 through the first via hole 1015, in the area corresponding to the first via hole 1015 and in the second
  • the side of the electrode 1014 away from the base substrate 1011 is provided with a first support structure 1016; at least part of the first support structure 1016 is located in the first via hole 1015; and the first via hole 1015 is on the base substrate 1011
  • the orthographic projection and the orthographic projection of the grid lines 1022 on the base substrate 1011 at least partially overlap. For example, in the display panel 10 shown in FIG.
  • At least part of the first supporting structure 1016 is located in the first via hole 1015, and the orthographic projection of the first via hole 1015 on the base substrate 1011 and the gate line 1022 are on the substrate.
  • the orthographic projections on the base substrate 1011 are at least partially overlapped, thereby improving the resolution and aperture ratio of the display panel 10 .
  • the first support structure 1016 has a bottom near the base substrate 1011 and an oppositely positioned top, and sides.
  • the area where the first support structure 1016 is located corresponding to the first via hole 1015 may be an area where the first support structure 1016 and the first via hole 1015 have at least a partial overlap.
  • the projection of the first support structure 1016 is located in the overlapping area of the first support structure 1016 and the first via hole 1015 .
  • a part of the projection of the first support structure 1016 is located in the overlapping area between the first support structure 1016 and the first via hole 1015, for example, the first support structure 1016 is located in the opening area of the first via hole 1015 and an area extending from the opening area of the first via hole 1015 to the outside.
  • FIG. 2 is a schematic plan view of a first substrate provided by at least one embodiment of the present disclosure.
  • the first substrate 101 is an array substrate, and the array substrate includes a lateral The gate line 1022 and the data line 1024 arranged vertically and crosswise, and a plurality of pixel units 1025, as shown in FIG. 1 and FIG.
  • the first interlayer insulating layer 1013 between the second electrodes 1014, the second electrode 1014 is in contact with the surface of the first interlayer insulating layer 1013 away from the base substrate 1011, and the second electrode 1014 is formed by the first interlayer insulating layer
  • the upper surface of 1013 extends to the sidewall and the lower opening area of the first via hole 1015 and is in contact with and connected to the first electrode 1012 located in the lower opening area.
  • the first interlayer insulating layer 1013 is a single-layer film, for example, a single-layer flat layer, and the material may be an organic transparent film layer.
  • the first interlayer insulating layer 1013 is a stacked insulating layer, and the stacked insulating layer may be multiple layers (including two layers).
  • the material can be a stack of organic and inorganic insulating layers, or a stack of multiple inorganic insulating layers.
  • the stack of multi-layer inorganic insulating layers can be a film layer containing not exactly the same element type, such as a stack of silicon oxide and silicon nitride, or a film layer stack of the same type of elements but different molar ratios, for example, each The film layers are all SixOy, but the values of x or y are different.
  • the first interlayer insulating layer 1013 is a flat layer with two main surfaces, an upper surface and a lower surface, the upper surface is far away from the base substrate 1011, and the lower surface is The surface is closer to the base substrate 1011.
  • the first interlayer insulating layer 1013 has a first via hole 1015, and the first via hole 1015 has a sidewall, an opening close to the upper surface of the first interlayer insulating layer 1013 (may be referred to as an upper opening or an upper hole), And an opening near the lower surface of the first interlayer insulating layer 1013 (may be referred to as a lower opening or a lower hole).
  • no other insulating layers are arranged on the first interlayer insulating layer 1013, and the first support structure 1016 is filled in the first via hole 1015 of the first interlayer insulating layer 1013, and is used to support the first interlayer insulating layer 1013.
  • the first substrate 101 and the second substrate 102 ensure a cell thickness within a certain range.
  • one or more insulating layers may be disposed on the first interlayer insulating layer 1013, and the multi-layer insulating layer may not have openings or part of the film layer may expose the opening of the first supporting structure 1016, at least part of the film layer Covering on the first support structure 1016, a film layer is formed on the first interlayer insulating layer 1013 according to the shape of the first support structure 1016, so that the first support structure 1016 is as high as It can still play the role of supporting the first substrate 101 and the second substrate 102 , and the cumulative thickness of other covered film layers needs to be considered when designing the support height.
  • the first supporting structure 1016 extends toward the second substrate 102 and has a protruding structure higher than the second interlayer insulating layer 1019 .
  • the second interlayer insulating layer 1019 is formed on the first interlayer insulating layer 1013.
  • the second interlayer insulating layer 1019 is formed on the first interlayer insulating layer 1013 by a deposition method
  • an implementation The method is that the second interlayer insulating layer 1019 is also located in the first via hole 1015.
  • Another implementation mode is that the area of the second interlayer insulating layer 1019 corresponding to the first via hole 1015 is removed and only the part of the upper surface of the first interlayer insulating layer 1013 .
  • the second interlayer insulating layer 1019 is formed on the first interlayer insulating layer 1013 having the first via hole 1015 by deposition, will be A similar via hole is formed, which still has a wall shape almost similar to that of the first via hole 1015 and two upper and lower openings at about the same position, that is, similar via holes can be formed according to the shape of the first via hole 1015 .
  • the second interlayer insulating layer 1019 also has an upper surface, a lower surface, via holes, an opening near the upper surface, and an opening near the lower surface.
  • the pixel unit 1025 is defined by the gate line 1022 and the data line 1024 arranged horizontally and vertically, and a pixel structure is arranged in the pixel unit 1025 .
  • the first interlayer insulating layer 1013 includes at least a planarization layer
  • the first via hole 1015 is a through hole penetrating the planarization layer
  • the planarization layer can function as a planarizer while reducing The parasitic capacitance between electrodes or signal lines makes the electrical signal in the display panel more stable.
  • the planarization layer included in the first interlayer insulating layer 1013 and the first support structure 1016 are made of light-transmitting materials, such as organic resin, so as to improve the light transmittance of the display panel.
  • the first supporting structure 1016 of the light-transmitting material has a large degree of freedom in design size, and is not limited by the grid lines below.
  • the material of the first support structure 1016 is a light-shielding material, which can effectively reduce light leakage in the area, but in order to increase the aperture ratio, the projection of the first support structure is located at the projection of the grid lines below it. Inside.
  • the first support structure 1016 is located above the gate line, and at least fills in the first via hole 1015 toward the gate when the upper surface of the first interlayer insulating layer 1013 or the second interlayer insulating layer 1019 extends.
  • the wire 1022 extends in the width direction as well as in the length direction.
  • the first supporting structure 1016 may exceed the edge of the gate line 1022 in the width direction, or may be located within the outline of the gate line 1022 .
  • the first supporting structure 1016 may extend toward the length direction of the gate line 1022 , for example, parallel to the extending direction of the gate line 1022 .
  • first support structures 1016 may be disposed above one gate line 1022 , for example, one pixel unit corresponds to one first support structure 1016 . Then, the adjacent first support structures 1016 may be separated from each other and set independently. They may also be connected to each other, for example, through an extension of the first support structure 1016 .
  • the surface of the first support structure 1016 close to the second substrate 102 is a plane or a concave surface that is recessed toward one side of the base substrate 1011.
  • the first support structure The surface of 1016 close to the second substrate 102 is a concave surface that is recessed toward one side of the base substrate 1011 .
  • the surface of the first support structure 1016 close to the second substrate 102 may also be a convex surface protruding toward the second substrate 102 .
  • a second support structure 1021 that cooperates with the first support structure 1016 to support the first substrate 101 and the second substrate 102 is also provided,
  • One of the first support structure 1016 and the second support structure 1021 is located on the first substrate 101, the other is located on the second substrate 102, and the first support structure 1016 and the second support structure 1021 are on the first substrate 101 and the second
  • the substrates 102 can contact each other or keep a certain distance, and define a space for containing the liquid crystal layer 104 between the first substrate 101 and the second substrate 102, and the contact position of the first support structure 1016 and the second support structure 1021
  • the shapes can be adapted to each other.
  • the surface of the first support structure 1016 close to the second substrate 102 is concave or flat
  • the surface of the second support structure 1021 close to the first substrate 101 may be convex or flat
  • the surface of the first support structure 1016 close to the second substrate The surface of 102 is convex or flat
  • the surface of the second support structure 1021 close to the first substrate 101 may be concave or flat.
  • the contact between the surface of the first support structure 1016 close to the second substrate 102 and the surface of the second support structure 1021 close to the first substrate 101 refers to the top of the first support structure 1016 surface and the top surface of the second support structure 1021 at least in part, so that there is a maximum gap between the first substrate 101 and the second substrate 102 in the direction perpendicular to the main surface of the base substrate 1011, or, the first support structure
  • the contact between the surface of the structure 1016 close to the second substrate 102 and the surface of the second support structure 1021 close to the first substrate 101 may also refer to the part of the first support structure 1016 at other positions on the surface close to the second substrate 102 and the second support structure 1021.
  • Parts of the support structure 1021 near other positions on the surface of the first substrate 101 are in contact, as long as there is a gap between the first substrate 101 and the second substrate 102, when the first substrate 101 and the second substrate 102 are aligned, no In this way, the display area corresponding to the first substrate 101 or the display area corresponding to the second substrate 102 is scratched, and the problem of light leakage in the edge area does not occur. And by arranging the first support structure 1016 in the area corresponding to the first via hole 1015, the problem of light leakage caused by the first via hole 1015 can be avoided.
  • the first support structure 1016 completely fills the first via hole 1015 of the first interlayer insulating layer 1013 and protrudes beyond the first via hole 1015 , and the first support structure 1016 close to the second substrate 102
  • the surface of the surface is a concave surface, which increases the surface area of the surface, so that the contact area between the first support structure 1016 and the second support structure 1021 will be larger, so that the effective support area of the first support structure 1016 to the second substrate 102 becomes larger. large, and can reduce the risk of the second supporting structure 1021 slipping off the first substrate 101 .
  • most of the first support structure 1016 is located in the first via hole 1015 .
  • the height of the first supporting structure 1016 is about 0.6 ⁇ m, which can meet the requirement of the display panel on the size of the gap.
  • the area of the contact surface between the second support structure 1021 and the first support structure 1016 is smaller than the cross-sectional area of the second support structure 1021 or the first support structure 1016 near the base substrate 1011 .
  • the second substrate 102 may include a substrate and a film layer structure disposed on the substrate.
  • the surface of the first support structure 1016 close to the second substrate 102 is recessed toward the side of the base substrate 1011, and the surface of the second support structure 1021 close to the first substrate 101 is recessed toward the side close to the first substrate 101.
  • One side of the support structure 1021 is raised, and this structural design can make the second support structure 1021 contact with the concave part of the first support structure 1016, so that the second support structure 1021 must first move upward when it wants to slide off the first substrate 101, Such a design can make the second support structure 1021 less likely to slip off the first support structure 1016, so that the size of the gap 103 between the first substrate 101 and the second substrate 102 is perpendicular to the main surface of the base substrate 1011 can be kept constant. As shown in FIG.
  • the dimension of the gap 103 between the first substrate 101 and the second substrate 102 on the main surface perpendicular to the base substrate 1011 is a+b, so that it is smaller than the dimension a+c, where a is the second
  • the maximum dimension of the support structure 1021 perpendicular to the main surface of the base substrate 1011 b is the minimum distance from the surface of the first support structure 1016 away from the base substrate 1011 to the surface of the first via hole 1015 away from the base substrate 1011
  • c is the maximum distance from the surface of the first support structure 1016 away from the base substrate 1011 to the surface of the first via hole 1015 away from the base substrate 1011 .
  • the thickness of the liquid crystal cell is a+b, and c>b, and the thickness of the liquid crystal cell affects the response speed of the liquid crystal.
  • the b value ranges from 0.30 microns to 0.45 microns.
  • the surface of the first support structure 1016 close to the second substrate 102 is in contact with the surface of the second support structure 1021 close to the first substrate 101, so as to support the second substrate 102 and provide support on the first substrate.
  • a gap is formed between 101 and the second substrate 102 .
  • the orthographic projection of the second support structure 1021 on the base substrate 1011 and the orthographic projection of the first support structure 1016 on the base substrate 1011 at least partially overlap.
  • the cross-sectional shape of the second supporting structure 1021 on a plane perpendicular to the main surface of the base substrate 1011 is a semicircle.
  • the yield strength of the second support structure 1021 is greater than the joint pressure when the first substrate 101 and the second substrate 102 are combined, the area of a single second support structure 1021 and the number of second support structures 1021 product of .
  • the yield strength of the second support structure 1021 refers to the maximum pressure at which the material of the second support structure 1021 undergoes elastic deformation, so as to prevent the second support structure 1021 from Plastic deformation occurs to affect the effect of the first substrate 101 and the second substrate 102 being joined together.
  • FIG. 3 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure.
  • the surface close to the first substrate 101 is concave, and the convex surface of the first support structure 1016 abuts against the concave surface of the second support structure 1021.
  • This structural design can make the concave part of the second support structure 1021 and the first support structure The protruding parts of 1016 are in contact with each other, so that the second support structure 1021 must first move upward when it wants to slide off the first substrate 101.
  • Such a design can make the second support structure 1021 less likely to slide off the first support structure 1016, So that the size of the gap 103 between the first substrate 101 and the second substrate 102 on the main surface perpendicular to the base substrate 1011 can be kept constant.
  • the surface of the first support structure 1016 close to the second substrate 102 may also be substantially parallel to the plane of the base substrate 1011 .
  • the second support structure 1021 corresponds to the first support structure 1016 one by one, that is, each first support structure 1016 is in contact with the second support structure 1021, and each second support structure 1021 All are in contact with one first support structure 1016, so the number of the second support structure 1021 is equal to that of the first support structure 1016.
  • the orthographic projection of the second support structure 1021 on the base substrate 1011 and the orthographic projection of the first support structure 1016 on the base substrate 1011 at least partially overlap.
  • the orthographic projection of the second support structure 1021 on the base substrate 1011 is located within the orthographic projection of the first support structure 1016 on the base substrate 1011 .
  • the cross-sectional shape of the second support structure 1021 on a plane perpendicular to the main surface of the base substrate 1011 is axisymmetric along the line AA' connecting the two endpoints A and A' of the x-axis with respect to an axis parallel to the z-axis
  • the cross-sectional shape of the first support structure 1016 on a plane perpendicular to the main surface of the base substrate 1011 is aligned along the line BB' between the two endpoints B and B' of the x-axis with respect to an axis parallel to the z-axis Symmetrically, line AA' is parallel to line BB' and the length of line AA' is less than the length of line BB'.
  • the cross-sectional shape of the second supporting structure 1021 in the direction perpendicular to the main surface of the base substrate 1011 and perpendicular to the gate line is semicircular, so that the second supporting structure 1021 and the first
  • the contact to a support structure 1016 may be a line contact.
  • Embodiments of the present disclosure are not limited thereto.
  • the cross-sectional shape of the second support structure 1021 on a plane perpendicular to the main surface of the base substrate 1011 may also be rectangular, triangular, etc., and the second support structure 1021 and the first support structure
  • the contact at 1016 may also be a surface contact, which is not limited in this embodiment of the present disclosure.
  • the first substrate 101 is an array substrate
  • the second substrate 102 is a color filter substrate
  • the first substrate is an array substrate and the color filter function is located on the array substrate, Also known as a COA substrate (color film on array, COA)
  • the second substrate 102 is a counter substrate.
  • the first substrate 101 is an array substrate
  • the second substrate 102 is a color filter substrate
  • a liquid crystal layer 104 is disposed in the gap 103 between the first substrate 101 and the second substrate 102 as an example for illustration.
  • the embodiments of the present disclosure are not limited thereto, as long as the finally formed structure can satisfy the display function.
  • the first interlayer insulating layer 1013 has an upper surface and a lower surface, and a first via hole 1015 has a sidewall close to the first interlayer insulating layer.
  • the first support structure 1016 extends downward in the first via hole 1015 to the lower opening area of the first via hole 1015 .
  • the first support structure 1016 extends upward from the bottom of the first via hole 1015 of the first interlayer insulating layer 1013 , that is, extends in a direction away from the main surface of the base substrate 1011 to fill
  • the first via hole 1015 continues to extend beyond the opening of the first via hole 1015 close to the upper surface of the first interlayer insulating layer, and the first supporting structure 1016 extends on the upper surface of the first interlayer insulating layer 1013 to Outside the first via hole 1015 , a portion extending out of the first via hole 1015 overlaps the upper surface of the first interlayer insulating layer 1013 .
  • first support structure 1016 is in contact with the upper surface of the second interlayer insulating layer.
  • the first support structure 1016 extends upward from the bottom of the first via hole 1015 of the first interlayer insulating layer 1013, that is, extends along a direction away from the main surface of the base substrate 1011 to fill the first via hole 1015 and continues to extend to the first via hole 1015.
  • the upper opening area of a via hole 1015 close to the upper surface of the first interlayer insulating layer 1013 continues to extend upward beyond the upper surface of the second interlayer insulating layer, so that at least part of the first support structure 1016 is located on the first interlayer insulating layer 1013.
  • the area of the surface is larger, so that the second support structure 1021 and the first support structure 1016 can contact more stably, so that the gap 103 between the first substrate 101 and the second substrate 102 is more constant.
  • the recessed part of the first support structure 1016 is located in the middle region of the cross-sectional shape of the first support structure 1016 on a plane perpendicular to the main surface of the base substrate 1011, the first support structure
  • the surface of 1016 away from the base substrate 1011 is axisymmetric with respect to the z-axis, and the coordinate axis is translated.
  • the position of the surface of the first support structure 1016 away from the base substrate 1011 closest to the base substrate 1011 can be the x-axis and At the point of intersection of the z-axis, the recessed portion of the first support structure 1016 is axisymmetric about the z-axis.
  • the above-mentioned first via hole 1015 is set in the gate line area corresponding to a plurality of pixel units 1025, and one pixel unit 1025 may correspond to one of the above-mentioned first via hole 1015 and one first support corresponding to the first via hole 1015.
  • the first via hole 1015 is a connection hole between the drain of the thin film transistor in the pixel unit 1025 and the pixel electrode.
  • the first electrode 1012 in the first via hole 1015 is connected to the drain of the thin film transistor in the pixel unit 1025, or the first electrode 1012 is directly used as the drain of the thin film transistor and connected to the semiconductor layer of the thin film transistor.
  • FIG. 4 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure. As shown in FIG. The second interlayer insulating layer 1019 , the first supporting structure 1016 is in contact with the upper surface of the second interlayer insulating layer 1019 .
  • the first support structure 1016 extends upward from the bottom of the first via hole 1015 of the first interlayer insulating layer 1013, that is, extends to fill the first via hole 1015 in a direction away from the main surface of the base substrate 1011 and continues to extend to The upper opening area of the first via hole 1015 close to the upper surface of the first interlayer insulating layer 1013 continues to extend upward beyond the second interlayer insulating layer 1019 , and the pixel unit 1025 also includes a
  • the third electrode 1110 that is, the second interlayer insulating layer 1019 is disposed between the third electrode 1110 and the second electrode 1014 on the upper surface of the first interlayer insulating layer 1013, and the second interlayer insulating layer 1019 Including an opening through the first via hole 1015 in the first interlayer insulating layer 1013 , the first support structure 1016 extends toward the second substrate 102 and has a protruding structure higher than the second interlayer insulating layer 1019 .
  • the third electrode 1110 includes metal oxide strips 1110a spaced apart from each other on the upper surface of the second interlayer insulating layer 1019, and metal oxide strips 1110a distributed between the metal oxide strips 1110a.
  • Section 1110b the material of the metal part 1110b includes a conductive metal, such as copper metal, molybdenum metal, and other materials with light-shielding and conductive properties, and the material of the metal oxide strip portion 1110a includes a transparent conductive material, such as indium tin oxide.
  • the metal part 1110b can reduce the crosstalk of light in different pixel areas, so as to improve light efficiency.
  • the first electrode 1012 may be a drain of a thin film transistor.
  • the drain is in direct contact with the metal oxide semiconductor layer, such as lapped.
  • the drain is a partially conductorized region of the metal oxide conductor layer.
  • the second electrode 1014 may be a pixel electrode
  • the third electrode 1110 may be a common electrode of a pixel unit.
  • the material of the first electrode 1012 and the second electrode 1014 may be a transparent metal oxide conductor material.
  • the metal oxide strip portion 1110a included in the third electrode 1110 is a conductor rather than a semiconductor.
  • the metal part 1110b included in the third electrode 1110 can block the light, thereby reducing cross-color of light of different colors along the z-axis direction, and the metal part 1110b can also function as a black matrix along the x-axis direction, so that When forming the second substrate 102, it is not necessary to make a black matrix along the x-axis direction, but only need to make a black matrix along the y-axis direction that crosses the x-axis direction in a direction parallel to the main surface of the base substrate 1011. In conventional black matrix manufacturing process, the black matrix in the x-axis direction and the y-axis direction are manufactured in different processes, so that the process steps of forming the black matrix in the x-axis direction on the second substrate 102 can be
  • FIG. 5 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure.
  • the third electrode 1110 includes a metal part 1110b and a side surface and an upper The metal oxide strip portion 1110a on the surface, and in a direction parallel to the main surface of the base substrate 1011, the third electrode 1110 includes a plurality of portions spaced apart from each other. That is, the combination of the metal part 1110b and the side surface of the cladding metal part 1110a and the metal oxide strip part 1110a on the surface away from the base substrate 1011 is spaced apart from each other.
  • FIG. 6 is a perspective view of the second electrode and the third electrode in the cross-sectional structure shown in FIG. 5.
  • the metal part 1110b as the common electrode and the metal oxide strip part 1110a are stacked in contact with each other.
  • the orthographic projection of the metal portion 1110b on the base substrate 1011 is located within the orthographic projection of the metal oxide strip portion 1110a on the base substrate 1011, and the orthographic projection of the second electrode 1014 on the base substrate 1011 and the metal oxide
  • the orthographic projections of the strip portion 1110a on the base substrate 1011 are at least partially overlapped.
  • the orthographic projection of the second electrode 1014 on the base substrate 1011 spans between the orthographic projections of adjacent metal oxide strip portions 1110 a on the base substrate 1011 .
  • the portion of the first supporting structure 1016 that exceeds the upper surface of the first interlayer insulating layer 1013 and the upper surface of the second interlayer insulating layer 1019 is perpendicular to the base substrate 1011.
  • the cross-sectional shape of the main surface and the direction perpendicular to the extension of the gate line 1022 is a trapezoidal structure in which the upper surface is recessed toward the side close to the base substrate 1011 . As shown in FIG.
  • the portion of the first supporting structure 1016 beyond the upper surface of the first interlayer insulating layer 1013 and the upper surface of the second interlayer insulating layer 1019 is perpendicular to the main surface of the base substrate 1011 and perpendicular to the gate
  • the cross-sectional shape in the direction along which the line 1022 extends is a trapezoidal structure in which the upper surface protrudes toward the side away from the base substrate 1011 .
  • the part of the first supporting structure 1016 that exceeds the upper surface of the first interlayer insulating layer 1013 and the upper surface of the second interlayer insulating layer 1019 is perpendicular to the main surface of the base substrate 1011 and perpendicular to the
  • the cross-sectional shape along the direction in which the grid lines 1022 extend may also be a rectangle, or a trapezoid, etc., which is not limited in this embodiment of the present disclosure.
  • the first support structure 1016 extends beyond the upper surface of the second interlayer insulating layer 1019 towards the second substrate 102, and along the second interlayer insulating layer
  • the upper surface of 1019 extends away from the first via hole 1015, that is, the first support structure 1016 extends beyond the upper surface of the second interlayer insulating layer 1019 to a direction perpendicular to the main surface of the base substrate 1011 and simultaneously to a direction parallel to the base substrate.
  • the base substrate 1011 extends in the direction of the main surface of the base substrate 1011, and the part extending in the direction parallel to the main surface of the base substrate 1011 is in contact with the upper surface of the second interlayer insulating layer 1019, so that the first supporting structure 1016 on the base substrate 1011
  • the orthographic projection covers and exceeds the orthographic projection area of the first via hole 1015 on the base substrate 1011 .
  • FIG. 4 and FIG. 5 there is a second via hole 1017 penetrating through the first interlayer insulating layer 1013 in the first interlayer insulating layer 1013 , and a third supporting structure 1018 is disposed in the second via hole 1017 , and the second via hole 1017 corresponds to the third support structure 1018 .
  • the second via hole 1017 is similar to the first via hole 1015, and is arranged in a plurality of pixel units 1025 corresponding to the area where the gate line 1022 is disposed, and one pixel unit 1025 may correspond to one second via hole 1017 and the corresponding The third support structure 1018.
  • the second via hole 1017 is a connection hole between the drain of the thin film transistor in the pixel unit 1025 and the pixel electrode.
  • the first via hole 1015 and the second via hole 1017 are holes in different regions, corresponding to thin film transistors in different regions.
  • the shapes and sizes of the first via hole 1015 and the second via hole 1017 can be the same or different, but the first The support structure 1016 is different from the third support structure 1018.
  • the first support structure 1016 cooperates with the second support structure 1021 to support the first substrate 101 and the second substrate 102, but the third support structure 1018 is solely used to support the first substrate 101 and the second substrate 102.
  • the second substrate 102 .
  • the shapes of the first support structure 1016 and the third support structure 1018 are different.
  • the first via hole 1015 is a hole corresponding to the first support structure 1016
  • the second via hole 1017 is a hole corresponding to the third support structure 1018, but it does not mean that the first via hole 1015 and the second via hole 1017 have structural differences. difference.
  • both the first via hole 1015 and the second via hole 1017 are located in the area corresponding to the gate line 1022 , and the size and shape of the first via hole 1015 and the second via hole 1017 are similar.
  • the display panel 10 includes two pixel units, and each pixel unit is correspondingly provided with a first via hole 1016 or a second via hole 1017 .
  • a third support structure 1018 is provided in the area corresponding to the second via hole 1017 and on the side of the second electrode 1014 away from the base substrate 1011, and the third support structure 1018 is located at
  • the orthographic projection on the base substrate 1011 and the orthographic projection of the second support structure 1021 on the substrate substrate 1011 do not have an overlapping portion because the third support structure 1018 is only cooperating with the first support structure 1016 to form one larger support structure Supporting the first substrate 101 and the second substrate 102 ensures the cell thickness of the liquid crystal cell.
  • the second support structure 1021 does not cooperate with the third support structure 1018 and does not extend to the area where the third support structure 1018 is located.
  • the third supporting structure 1018 can at least fill up the second via hole 1017 to reduce the risk of light leakage from the second via hole 1017 .
  • the third support structure 1018 extends away from the base substrate 1011 to the outside of the second via hole 1017, and the third support structure 1018 fills the second via hole 1017 so that it is located in the second via hole
  • the shape inside 1017 is adapted to the shape of the second via hole 1017 .
  • the third support structure 1018 extends to the outside of the second via hole 1017 along a direction perpendicular to the main surface of the base substrate 1011 , that is, extends to the second via hole 1017 in a direction parallel to the z-axis.
  • the maximum dimension of the third support structure 1018 in the direction parallel to the main surface of the base substrate 1011 is equal to the maximum dimension of the second via hole 1017 in the direction parallel to the main surface of the base substrate 1011 .
  • the line connecting the two farthest ends of the third support structure 1018 is the third support structure 1018 and the second
  • the connection line between the two points contacted by the electrode 1014 is the connection line of the largest opening along the x-axis direction on the surface of the first interlayer insulating layer 1013 away from the base substrate 1011 .
  • the third support structure 1018 extends upward from the second via hole 1017 and continues to extend upward beyond the second via hole 1017 and to the film layer where the second via hole 1017 is located (for example, The first interlayer insulating layer 1013) extends on the upper surface.
  • the first via hole 1015 and the second via hole 1017 are formed in the same process step, and the first via hole 1015 and the second via hole 1017 can be formed using the same mask. patterning process, and the first via hole 1015 and the second via hole 1017 have the same shape and size.
  • the longitudinal section of the part of the third support structure 1018 extending beyond the second via hole 1017 has a trapezoidal shape.
  • the third supporting structure 1018 extends to the part outside the second via hole 1017 along the direction perpendicular to the main surface of the base substrate 1011 .
  • the cross-sectional shape on the plane of is a positive trapezoid, so that the cross-sectional shape of the third support structure 1018 on the plane perpendicular to the main surface of the base substrate 1011 is along the z-axis direction, and from a position close to the base substrate 1011 to At positions away from the base substrate 1011 , the size in the x-axis direction first increases and then decreases.
  • the second electrode 1014 is in surface contact with the first electrode 1012 on the surface of the first via hole 1015 close to the base substrate 1011 to be electrically connected to each other, and the second electrode 1014 is at the The surfaces of the two via holes 1017 close to the base substrate 1011 are in surface contact with the first electrode 1012 to be electrically connected to each other, thereby ensuring the stability of the connection between the first electrode 1012 and the second electrode 1014, and the second electrode 1014 can also be connected to the first electrode 1014. Surfaces close to the base substrate 1011 of the first via hole 1015 and the second via hole 1017 are completely covered.
  • the second interlayer insulating layer 1019 is also disposed between the third support structure 1018 and the second electrode 1014, and the second interlayer insulating layer 1019 is provided with a The holes 1017 communicate with each other, and a third electrode 1110 is provided on the side of the second interlayer insulating layer 1019 away from the base substrate 1011 around the third supporting structure 1018 .
  • the second interlayer insulating layer 1019 can be formed on the side of the first support structure 1016 and the third support structure 1018 close to the substrate 101, or can be formed on the side of the first support structure 1016 and the third support structure 1018 away from the substrate.
  • One side of the base substrate 101 is not limited in the embodiments of the present disclosure.
  • the third support structure 1018 extends to the outside of the second via hole 1017 along a direction perpendicular to the main surface of the base substrate 1011, and the third support structure 1018 is parallel to the substrate.
  • the maximum dimension in the direction of the main surface of the base substrate 1011 and the maximum dimension of the second via hole 1017 in the direction parallel to the main surface of the base substrate 1011 are equal.
  • the third support structure 1018 extends to the part outside the second via hole 1017 along the direction perpendicular to the main surface of the base substrate 1011 , and in the direction perpendicular to the base substrate 1011
  • the cross-sectional shape on the plane of the main surface is a regular trapezoid.
  • the first interlayer insulating layer 1013 includes at least an organic planar layer
  • the second interlayer insulating layer 1019 includes at least an inorganic insulating layer
  • the third electrode 1110 is the common electrode of each pixel unit 1025.
  • An electric field is formed between the pixel electrode and the common electrode to drive the liquid crystal molecules in the liquid crystal layer 160 between the first substrate 101 and the second substrate 102 to deflect.
  • FIG. 7 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure.
  • the display area of the display panel 100 is a metal oxide thin film transistor.
  • the TFTs in the GOA region can be LTPS or metal oxide thin film transistors.
  • the semiconductor layer of the thin film transistor on the first substrate 101 includes low temperature polysilicon, metal oxide semiconductor.
  • the first substrate 101 further includes a driving transistor 120 and a switching transistor 130 disposed on the base substrate 1011 , the switching transistor 130 is disposed in the display area AA, and the driving transistor 120 is disposed in the peripheral area NA surrounding the display area AA.
  • the switch transistor 130 in the pixel unit area includes a first insulating layer 1301 , a light shielding layer 1302 , a second insulating layer 1303 , and a metal oxide semiconductor layer 1304 stacked on the base substrate 1011 in sequence.
  • the fourth insulating layer 1309, the third insulating layer 1307 and the fifth via hole 1311 of the gate insulating layer 1305 are electrically connected to the metal oxide semiconductor layer 1304 to serve as the first drain 1310, and the first source 1308 passes through the third
  • the insulating layer 1307 and the seventh via hole 1312 of the gate insulating layer 1305 are electrically connected to the metal oxide semiconductor layer 1304 .
  • the switching transistor 130 is configured to provide a turn-on voltage for the photoelectric driving of the display panel (for example, the deflection of liquid crystal molecules), and the metal oxide semiconductor layer 1304 in the switching transistor 130 has transparency to bring high transmittance The display effect of virtual reality technology has been further improved.
  • the drive transistor 120 includes a second polysilicon layer 1201, a first insulating layer 1301, a second gate (gate line) 1202, a second insulating layer 1303, a gate insulating layer 1305, and a source-drain electrode layer 1203.
  • the source-drain electrode layer 1203 includes a second source electrode 1203a and a second drain electrode 1203b, and the second source electrode 1203a and the second drain electrode 1203b are respectively connected to the second polycrystalline
  • the silicon layer 1204 is electrically connected, and the driving transistor 120 is configured to provide a driving voltage when the array substrate is used for displaying.
  • the driving transistor 120 uses the second polysilicon layer 1204 as a semiconductor layer to improve mobility and bring about narrow borders.
  • the second gate 1202 and the light-shielding layer 1302 are disposed on the same layer, that is, the second gate 1202 and the light-shielding layer 1302 can be formed using the same material, in the same process step, and formed on the same layer.
  • the materials of the second grid 1202 and the light-shielding layer 1302 can be copper metal, molybdenum metal and other materials with light-shielding properties and conductive properties, which are not limited in this embodiment of the present disclosure.
  • the source-drain electrode layer 1203 and the first gate 1306 are arranged in the same layer.
  • the source-drain electrode layer 1203 and the first gate 1306 may be formed of the same material, formed in the same process step, and formed in the same layer.
  • the second source electrode 1203a and the second drain electrode 1203b included in the source-drain electrode layer 1203 are respectively electrically connected to the second polysilicon layer 1204 through connection holes, and the connection holes pass through the gate insulating layer 1305 and the second insulating layer 1303 at the same time. and the first insulating layer 1301 .
  • the display panel 100 combines the technical effects of high mobility and narrow frame of the driving transistor 120 having polysilicon material as the semiconductor layer, and the technical effects of the switching transistor 130 having the metal oxide semiconductor material as the semiconductor layer.
  • the high transmittance display effect can further improve the virtual reality display effect of the display panel.
  • the third electrode 1110 includes metal oxide strip portions 1110a spaced from each other in a direction parallel to the main surface of the base substrate 1011, and metal oxide strip portions 1110a between the metal oxide strip portions 1110a.
  • the metal oxide strip part 1110a and the metal part 1110b refer to the relevant description of FIG. 4 above.
  • the region where the metal oxide semiconductor layer 1304 and the first gate 1306 are stacked is a channel region, that is, the M region marked by an elliptical dotted line, and the remaining regions are conductive regions, that is, the region marked by an elliptical dotted line
  • the ratio of the length of the channel region (M region) to the length of the conductorized region (N region) is 1/5 to 1/4, for example, the channel region (M region ) is 1/5 or 1/4 of the length of the conductorized region (N region), and the embodiments of the present disclosure are not limited to this.
  • the material of the channel region (M region) is oxide Indium gallium zinc, which has semiconductor properties.
  • the material of the conductive region (N region) is reduced InGaZnO, which has a conductive property.
  • the orthographic projection of the first grid 1306 on the base substrate 1011 and the orthographic projection of the light shielding layer 1302 on the base substrate 1011 at least partially overlap.
  • the orthographic projection of the first grid 1306 on the base substrate 1011 is located within the orthographic projection of the light shielding layer 1302 on the base substrate 1011 .
  • the distance from the first gate 1306 to the light shielding layer 1302 is 0 micrometers to 5 micrometers.
  • the orthographic projection of the channel region (M region) on the base substrate 1011 overlaps with the orthographic projection of the middle region of the light shielding layer 1302 on the base substrate 1011, and the channel region (M region) on the base substrate 1011
  • the orthographic projection is located within the orthographic projection of the light shielding layer 1302 on the base substrate 1011 .
  • the channel region (M region) has a double-layer structure or a triple-layer structure, and the layer structure of the channel region (M region) far away from the base substrate 1011 is denser than the channel region ( M region) close to the density of the layer structure of the base substrate 1011.
  • the materials of the conductive region (N region) and the channel region (M region) are different, and the material of the channel region (M region) includes oxygen element, indium element, gallium element and zinc element, and the conductive region N
  • the material includes oxygen element, indium element, gallium element, zinc element, boron element or phosphorus element and the like.
  • the material of the metal oxide semiconductor layer 1304 is indium gallium zinc oxide (IGZO), and the part of the metal oxide semiconductor layer 1304 connected to the first source 1308 and the first drain 1310 is conductorized In this way, the part of the metal oxide semiconductor layer 1304 other than the channel region (M region) can be better connected to the first source 1308 and the first drain 1310 .
  • IGZO indium gallium zinc oxide
  • FIG. 8 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure.
  • the difference between FIG. 8 and FIG. 7 is that, in FIG. into the first via hole 1015 so that the third electrode 1110 and the second electrode 1014 have more overlapping areas.
  • FIG. 8 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure. The difference between FIG. 8 and FIG. 7 is that, in FIG. into the first via hole 1015 so that the third electrode 1110 and the second electrode 1014 have more overlapping areas.
  • the second source 1203a includes a source base part and a source transfer part
  • the second drain 1203b includes a drain base part and a drain transfer part
  • both the source base part and the source base part pass through
  • the gate insulating layer 1305, the second insulating layer 1303 and the first insulating layer 1301 are arranged on the same layer as the first gate 1306, and the source transition part and the drain transition part both penetrate the third insulating layer 1307, and are connected with the first gate electrode 1306.
  • the first source electrode 1308 is set on the same layer, and the second source electrode 1063a and the second drain electrode 1063b are formed in two steps, which does not increase the process steps, and reduces the difficulty of forming connection holes, which can ensure that the second source electrode 1063a and the second drain electrode 1063b The stability of the electrical connection between the second drain electrode 1063b and the polysilicon layer 1061.
  • FIG. 8 For other structures of the display panel 100 shown in FIG. 8 , reference may be made to the relevant descriptions in FIG. 1 , FIG. 3 , FIG. 4 , FIG. 5 and FIG. 7 , which will not be repeated here.
  • FIG. 9 is a perspective view of yet another second electrode and a third electrode provided by at least one embodiment of the present disclosure
  • FIG. 10 is a schematic cross-sectional structure diagram of the structure shown in FIG. 9 .
  • the first The three electrodes 1110 include a metal oxide strip portion 1110a, and a metal portion 1110b disposed on the side of the metal oxide strip portion 1110a away from the substrate 1011, that is, the metal oxide portion 1110a and the metal strip portion 1110b form a stacked structure
  • the orthographic projection of the metal portion 1110b on the base substrate 1011 is located within the orthographic projection of the metal oxide strip portion 1110a on the base substrate 1011 .
  • the second electrode 1014 is connected between adjacent metal oxide strip parts 1110a, and the orthographic projection of the second electrode 1014 on the base substrate 1011 is the same as the orthographic projection of the metal oxide strip part 1110a on the base substrate 1011. Projections have overlapping parts.
  • the third electrode 1110 may be formed solely of metal oxides or metals or alloys.
  • the third electrode can be used as a common electrode
  • the second electrode 1014 can be used as a pixel electrode
  • the common electrode and the pixel electrode form an electric field to drive liquid crystal molecules.
  • the third electrode 1110 may be located in the same layer as the second electrode 1014 , or located in a different layer from the second electrode 1014 .
  • the metal part of the third electrode 1110 is separated from the second electrode 1014 by a layer of first insulating film
  • the metal oxide strip part of the third electrode 1110 is separated from the second electrode 1014 by a layer of second insulating film
  • the third electrode 1110 The metal part and the metal oxide strip part are electrically connected through the via holes penetrating the first insulating film and the second insulating film.
  • the structure of the third electrode 1110 is not limited, for example, the display area of the third electrode 1110 is a mesh structure, or a slit-like or plate-like structure.
  • FIG. 11 is a schematic cross-sectional structure diagram of another display panel provided by at least one embodiment of the present disclosure.
  • the channel layer on the first substrate 101 included in the display panel 100 is low temperature polysilicon (LTPS)
  • the first substrate 101 further includes a driving transistor 120 and a switching transistor 130 disposed on the base substrate 1011
  • the switching transistor 130 is disposed in the display area AA
  • the driving transistor 120 is disposed in the peripheral area NA surrounding the display area AA
  • the switching transistor 130 includes a light shielding layer 1302, a buffer layer 1313, a first polysilicon layer 1314, a gate insulating layer 1305, a first gate 1306, a third insulating layer 1307, a base electrode layer 1315
  • the basic electrode layer 1315 includes a first basic electrode 1315a and a second basic electrode 1315b oppositely arranged, and the first electrode 1012 is electrically
  • the six via holes 1317 are electrically connected to the first polysilicon layer 1314, and the first source electrode 1308 is electrically connected to the second base electrode 1315b through the seventh via hole 1312 passing through the fifth insulating layer 1316 and the fourth insulating layer 1309 in sequence,
  • the second base electrode 1315b is electrically connected to the first polysilicon layer 1314 through the eighth via hole 1318 penetrating through the third insulating layer 1307 and the gate insulating layer 1305.
  • the buffer layer 1313, the second polysilicon layer 1204, the gate insulating layer 1305, the second gate 1202, the third insulating layer 1307 and the source-drain electrode layer 1203, the source-drain electrode layer 1203 includes the second source 1203a and the second The drain 1203b, and the second source 1203a and the second drain 1203b are electrically connected to the second polysilicon layer 1204; the first gate 1306 and the second gate 1202 are set in the same layer; the source-drain electrode layer 1203 Set on the same layer as the base electrode layer 1315 , the low temperature polysilicon (LTPS) display panel uses the first polysilicon layer 1314 and the second polysilicon layer 1204 as semiconductor layers to improve mobility and bring about narrow frame technical effects.
  • LTPS low temperature polysilicon
  • the contact portion of the first electrode 1012 and the second electrode 1014 is located between the fifth via hole 1311 and the seventh via hole 1312, and
  • the orthographic projection of the contact portion of the first electrode 1012 and the second electrode 1014 on the substrate 1011 at least partially overlaps the orthographic projection of the first grid 1306 on the substrate 1011 .
  • the side of the contact portion of the first electrode 1012 and the second electrode 1014 close to the fifth via hole 1311 is in contact with the sixth via hole 1317.
  • the distance between them is equal to the length of the first electrode 1012 that does not cover the first grid 1306 .
  • the end points of the two ends of the light shielding layer 1302 are located between the seventh via hole 1312 and the fifth via hole 1311, and the first electrode 1012 and the fifth via hole 1311
  • the contact portion of the second electrode 1014 is located between the seventh via hole 1312 and an end of the light shielding layer 1302 close to the fifth via hole 1311 .
  • the first gate 1306 includes two parts spaced apart from each other in a direction parallel to the main surface of the base substrate 1011 , that is, a double gate structure is formed.
  • other structures of the display panel 100 shown in FIG. 11 may refer to related structures of conventional low temperature polysilicon (LTPS) display panels, which are not limited in the embodiments of the present disclosure.
  • LTPS low temperature polysilicon
  • the pixel unit 1025 further includes a thin film transistor, and the thin film transistor includes a switching transistor 130, and the thin film transistor 130 includes a semiconductor layer 1314, first source electrodes 1308 and second A drain 1310; the first source 1308 and the first drain 1310 are connected to the semiconductor layer 1314, the second electrode 1014 is the pixel electrode of the pixel unit 1025; the first electrode 1012 is the first drain 1310 or for As a transfer electrode connecting the first drain electrode 1310 and the pixel electrode.
  • the material of the first drain 1310 is transparent conductive oxide.
  • the material of the first drain 1310 includes a transparent metal oxide conductive material, such as indium tin oxide
  • the second electrode 1014 extends to the side of the first via hole 1015 close to the substrate 1011
  • the first drain 1310 is in surface contact with the second electrode 1014 , so that the connection between the first drain electrode 1310 and the second electrode 1014 is more stable without affecting the size of the aperture ratio of the display panel 100 .
  • the opening width d of the upper surface of the first via hole 1015 close to the first interlayer insulating layer 1013 satisfies: d ⁇ (K1*M/PPI)*(1-AR), and PPI is Pixel density, K1 is the aspect ratio of a single pixel, and AR is the aperture ratio.
  • W data is the width of the data line
  • W gate is the width of the gate line
  • the width of a single pixel P M/PPI
  • D min is the process exposure limit value, which is approximately equal to the width of the metal line, for example , which is equal to the width of the grid line.
  • D min may be the minimum value among the actual measured values of the grid lines or data lines.
  • the opening width d of the first via hole 1015 on the side away from the base substrate 1011 is proportional to K1, inversely proportional to the pixel density PPI, and transparent Overrate is inversely proportional.
  • the opening width of the first via hole 1015 on the side away from the base substrate 1011 or the opening width on the side close to the base substrate 1011 may be the opening width of the first support structure 1016, or the opening width of the first interlayer insulation The width of the opening on layer 1013.
  • the width of the opening on the side close to the base substrate 1011 may be the width of the opening on the first interlayer insulating layer 1013, or the width of the contact position between the first support structure 1016 and the first interlayer insulating layer 1013 or the width of the contact position between the first support structure 1016 and the second layer.
  • the width may be a width measured at one location or an average width measured at multiple locations.
  • d1-d2 is about 2.0 ⁇ m, and the d1-d2 is less than or equal to the thickness of the part of the first support structure 1016 protruding from the first via hole 1015 .
  • FIG. 12 is a scanning electron microscope image of a first support structure provided by at least one embodiment of the present disclosure. As shown in FIG. The angle formed between the surface close to the first source 1308 and the horizontal plane is ⁇ , the angle formed between the surface of the first via hole 1015 close to the first drain 1310 and the horizontal plane is ⁇ , in one example ⁇ , in In another example ⁇ .
  • ⁇ > ⁇ , and the difference of ⁇ - ⁇ is in the range of 0.5-3°.
  • the thickness of the part other than 1015, d1 is the opening width of the first via hole 1015 on the side away from the base substrate 1011
  • d2 is the opening width of the first via hole 1015 on the side close to the base substrate 1011
  • d3 is The thickness of the first interlayer insulation 1013 , ⁇ 1 is the angle between the sidewall of the first via hole 1015 and the horizontal plane.
  • the first electrode 1012 extends to the first Directly above the gate 1306 , that is, the orthographic projection of the first electrode 1012 on the substrate 1011 and the orthographic projection of the first gate 1306 on the substrate 1011 at least partially overlap.
  • the width extending from the right side of the first support structure 1016 beyond the first gate 1306 is w1
  • the thickness of the first interlayer insulating layer 1013 is H1
  • tan ⁇ H1/w1.
  • the minimum width w1 min extending from the right side of the first support structure 1016 to the outside of the first gate 1306 is 0.15 ⁇ m
  • the size of H1 is 2.41 ⁇ m
  • the size of ⁇ is 84°
  • w1 max is the maximum width extending from the right side of the first support structure 1016 to the outside of the first gate 1306
  • the w1 max is 2.0 ⁇ m
  • the size of H1 is 2.41 ⁇ m
  • the size of ⁇ is 50°.
  • FIG. 13 is a schematic perspective view of a first substrate provided by at least one embodiment of the present disclosure.
  • the oxide semiconductor layer 1304 is electrically connected to the first source electrode 1308 through the seventh via hole 1312, and the extending direction of the light shielding layer 1302 is parallel to the extending direction perpendicular to the extending direction of the portion of the metal oxide semiconductor layer 1304 electrically connected to the first electrode 1012.
  • the orthographic projection of the light-shielding layer 1302 on the base substrate 1011 overlaps with the orthographic projection of the first grid 1306 on the base substrate 1011
  • the part indicated by the dotted circle in FIG. 13 is the first support structure 1016 .
  • the orthographic projection of the contact portion of the first electrode 1012 and the second electrode 1014 on the base substrate 1011 is located within the orthographic projection of the first grid 1306 on the base substrate 1011 .
  • the side of the contact portion of the first electrode 1012 and the second electrode 1014 close to the fifth via hole 1311 and the fifth via hole 1311
  • the distance between is equal to the length of the first electrode 1012 that does not cover the first grid 1306 .
  • the first contact portion E of the first electrode 1012 and the second electrode 1014 is located between the fifth via hole 1311 and the seventh via hole 1312 , and the orthographic projection of the first contact portion E on the base substrate 1011 at least partially overlaps the orthographic projection of the first grid 1306 on the base substrate 1011 .
  • the end points of the two ends of the light shielding layer 1302 are located between the fifth via hole 1311 and the seventh via hole 1312, and the first contact portion E is located between the fifth via hole 1311 and the light shielding layer 1302. Between ends of the layer 1302 near the fourth via hole 1312 .
  • the distance from the orthographic projection of the contact portion on the first grid 1306 to the leftmost end of the first grid 1306 is 1/5 ⁇ 1/3 of the total length of the first grid 1306 .
  • the distance between the orthographic projection of the contact portion on the first grid 1306 and the seventh via hole 1312 is equal to the length of the first electrode 1012 not covering the first grid 1306 .
  • the endpoint on the left side of the light shielding layer 1302 is located to the left of the corresponding left endpoint of the first grid 1306, and the endpoint on the right side of the light shielding layer 1302 is located on the right side of the corresponding right endpoint of the first grid 1306. side, that is, the orthographic projection of the first grid 1306 on the base substrate 1011 is located within the orthographic projection of the light shielding layer 1302 on the base substrate 1011 .
  • the orthographic projection of the first contact portion on the base substrate 1011 is located between the orthographic projection of the end point of the left end of the light shielding layer 1302 on the base substrate 1011 and the orthographic projection of the fifth via hole 1311 on the base substrate 1011 .
  • the distance from the orthographic projection of the left end of the light shielding layer 1302 on the base substrate 1011 to the leftmost end of the first grid 1306 is 1/5 ⁇ 1/3 of the total length of the light shielding layer 1302 .
  • the distance between the fifth via hole 1311 and the seventh via hole 1312 is equal to the distance between the right end of the light shielding layer 1302 and the right end of the first gate 1306 .
  • the ratio of the area S to the area of the fifth via hole 1311 satisfies: S/S1 ⁇ 1/20 ⁇ 1/10.
  • the first electrode 1012 and the metal oxide semiconductor layer 1304 are completely overlapped, and the contact resistance is small, which is beneficial to the conduction characteristic of the switching transistor 130 .
  • Half-hole overlapping is the cause of process deviation, and the coverage value of the fifth via hole 1311 and the metal oxide semiconductor layer 1304 in this direction should not be exceeded.
  • the example of a half-hole lap may also apply if the resistance requirements are met.
  • the first electrode 1012 overlaps the side of the metal oxide semiconductor layer 1304, and the length of the first electrode 1012 not covering the metal oxide semiconductor layer 1304 accounts for 1/1 of the length of the metal oxide semiconductor layer 1304. 4-1/30.
  • the length of the first electrode 1012 that does not cover the metal oxide semiconductor layer 1304 is 0.1 ⁇ m-0.3 ⁇ m, which accounts for 1/20-1/9 of the length of the metal oxide semiconductor layer 1304 .
  • the contact portion of the first electrode 1012 and the second electrode 1014 is located between the fifth via hole 1311 and the seventh via hole 1312, and
  • the orthographic projection of the contact portion on the base substrate 1011 at least partially overlaps the orthographic projection of the first gate 1306 on the base substrate 1101 .
  • the materials of the first interlayer insulating layer 1013 and the first support structure 1016 are the same, and both are light-transmitting materials. Since a part of the first support structure 1016 needs to occupy the opening area, the first support structure 1016 is usually made of a transparent material, so that the part of the first support structure 1016 occupying the opening area does not affect the aperture ratio.
  • FIG. 14 is a schematic perspective view of another first substrate provided by at least one embodiment of the present disclosure.
  • the extending direction of the gate line and the gate 1306 are the same, that is, the extending direction of the first support structure 1016 is parallel to the extending direction of the gate 1306 .
  • the first support structure 1016 can block light so as to reduce cross-color between adjacent pixels, and can also play the role of a horizontal black matrix. In this way, it is not necessary to make a horizontal black matrix on the second substrate 102, but only a vertical black matrix. matrix, because the horizontal and vertical black matrixes are manufactured separately, thereby reducing the process steps on the second substrate 102 .
  • the gate line is a straight line with a constant line width and extends laterally, the gate line is located between two adjacent rows of pixel units, and there are two adjacent pixel units in the same column. pixel area. It is assumed that the pixel unit in the upper row is the first pixel unit, and the pixel unit in the lower row is the second pixel unit.
  • the metal oxide semiconductor layer 1304 is a wiring, which extends from the area where the first pixel unit is located across the gate line to the second pixel unit.
  • the overlapping area between the gate line and the metal oxide semiconductor layer is the gate of the thin film transistor.
  • the wiring extends from the data line area of the first pixel unit to the gate line and extends to the area corresponding to the fifth via hole in the second pixel unit.
  • the data line is in direct contact with the metal oxide semiconductor layer through the via hole below it, and a part of the data line is the source of the TFT.
  • a part of the gate line is the gate of the TFT, and this embodiment can maximize the aperture ratio of the pixel.
  • FIG. 15 is a process diagram of a method for manufacturing a display panel provided by at least one embodiment of the present disclosure. As shown in FIG. 15 , the preparation method includes follows the steps below:
  • Step S11 providing a base substrate.
  • the base substrate may be a glass substrate, a flexible substrate, a silicon substrate, etc., which is not limited in the embodiments of the present disclosure.
  • Step S12 forming a first electrode on the base substrate.
  • the first electrode may be a source-drain electrode of a thin film transistor, and the material of the first electrode may be a transparent metal oxide, such as indium tin oxide or the like.
  • Step S13 forming a first interlayer insulating layer on the first electrode.
  • the material of the first interlayer insulating layer may be a light-transmitting inorganic material.
  • Step S14 performing a patterning process on the first interlayer insulating layer to form a first via hole.
  • a conventional patterning process may be adopted: coating photoresist, using a mask plate to block, irradiating the photoresist with ultraviolet light to form a photoresist pattern, and using the photoresist pattern as a mask to irradiate the first interlayer insulating layer etch to form the first via hole.
  • Step S15 forming a second electrode on the first via hole, and electrically connecting the second electrode to the first electrode.
  • the second electrode may be a pixel electrode.
  • Step S16 forming a first supporting structure in the area corresponding to the first via hole and on the side of the second electrode away from the base substrate.
  • the first support structure completely fills the first via hole and protrudes beyond the first via hole, so as to avoid the problem of light leakage caused by the first via hole.
  • Step S17 providing a second substrate, forming a second support structure on the second substrate, the surface of the first support structure close to the second substrate is in contact with the surface of the second support structure close to the first substrate, so that the second substrate is supporting and forming a gap between the first substrate and the second substrate.
  • the surface of the first support structure close to the second substrate is in contact with the surface of the second support structure close to the first substrate to support the second substrate and form a gap between the first substrate and the second substrate. This avoids scratching the display area corresponding to the first substrate or the second substrate during the process of joining the first substrate and the second substrate, thereby reducing the risk of edge light leakage.
  • FIG. 16 is a process diagram of another method of manufacturing a display panel provided by at least one embodiment of the present disclosure. As shown in FIG. 16 , the manufacturing method includes:
  • Step S21 providing a base substrate.
  • Step S22 forming a first electrode on the base substrate.
  • Step S23 forming a first interlayer insulating layer on the first electrode.
  • Step S24 performing a patterning process on the first interlayer insulating layer to form a first via hole, and forming a second via hole penetrating through the first interlayer insulating layer in the first interlayer insulating layer.
  • Step S25 forming a second electrode on the first via hole, and electrically connecting the second electrode to the first electrode.
  • Step S26 forming a first insulating layer on a side of the second electrode away from the base substrate.
  • Step S27 forming a third electrode on a side of the first insulating layer away from the base substrate.
  • the third electrode includes metal oxide strip portions spaced apart from each other in a direction parallel to the main surface of the base substrate, and metal portions between the metal oxide strip portions, or the third electrode includes The metal layer and metal oxide clad side surfaces of the metal layer and a surface away from the base substrate, and the third electrode includes a plurality of portions spaced apart from each other in a direction parallel to the main surface of the base substrate.
  • Step S28 forming a first support structure in the area corresponding to the first via hole and on the side of the second electrode away from the base substrate, and forming a first support structure in the area corresponding to the second via hole and on the side of the second electrode away from the base substrate
  • One side forms a third support structure.
  • the orthographic projection of the third support structure on the substrate substrate and the orthographic projection of the second support structure on the substrate substrate do not have overlapping portions.
  • Step S29 providing a second substrate, forming a second support structure on the second substrate, the surface of the first support structure close to the second substrate is in contact with the surface of the second support structure close to the first substrate, so that the second substrate is supporting and forming a gap between the first substrate and the second substrate.
  • the surface of the first support structure close to the second substrate is in contact with the surface of the second support structure close to the first substrate to support the second substrate and form a gap between the first substrate and the second substrate, It can avoid scratching the display area corresponding to the first substrate or the second substrate during the process of joining the first substrate and the second substrate, thereby reducing the risk of edge light leakage.
  • FIG. 17 is a process diagram of another method of manufacturing a display panel provided by at least one embodiment of the present disclosure. As shown in FIG. 17 , the manufacturing method includes:
  • Step S31 providing a base substrate.
  • Step S32 forming a first electrode on the base substrate.
  • Step S33 forming a first interlayer insulating layer on the first electrode.
  • Step S34 performing a patterning process on the first interlayer insulating layer to form a first via hole, and forming a second via hole penetrating through the first interlayer insulating layer in the first interlayer insulating layer.
  • Step S35 forming a second electrode on the first via hole, and electrically connecting the second electrode to the first electrode.
  • Step S36 forming a first support structure in the area corresponding to the first via hole and on the side of the second electrode away from the base substrate, and forming a first support structure in the area corresponding to the second via hole and on the side of the second electrode away from the base substrate
  • One side forms a third support structure.
  • the orthographic projection of the third support structure on the substrate substrate and the orthographic projection of the second support structure on the substrate substrate do not have overlapping portions. That is, the number of the second support structures is less than the sum of the numbers of the first support structures and the third support structures.
  • the third support structure extends out of the second via hole along a direction perpendicular to the main surface of the base substrate, that is, extends out of the second via hole in a direction parallel to the z-axis, and the third support structure
  • a maximum dimension of the support structure in a direction parallel to the main surface of the base substrate is equal to a maximum dimension of the second via hole in a direction parallel to the main surface of the base substrate.
  • the third supporting structure can at least fill up the second via hole, so as to reduce the risk of light leakage in the second via hole.
  • Step S37 forming a first insulating layer on the sides of the first support structure and the third support structure away from the base substrate.
  • Step S38 forming a third electrode on a side of the first insulating layer away from the base substrate.
  • the third electrode includes metal oxide strip portions spaced apart from each other in a direction parallel to the main surface of the base substrate, and metal portions between the metal oxide strip portions, or the third electrode includes metal oxide strip portions. layer and cladding the side surface of the metal layer and the metal oxide strip-shaped portion of the surface away from the base substrate, and the third electrode includes a plurality of portions spaced apart from each other in a direction parallel to the main surface of the base substrate.
  • Step S39 providing a second substrate, forming a second support structure on the second substrate, the surface of the first support structure close to the second substrate is in contact with the surface of the second support structure close to the first substrate, so that the second substrate supporting and forming a gap between the first substrate and the second substrate.
  • Figure 17 the difference between Figure 17 and Figure 16 is that: in Figure 17, the first support structure and the third support structure are formed first, then the first insulating layer is formed, and then the third electrode is formed; in Figure 16, the first insulating layer is formed first layer, and then form the third electrode, and then form the first support structure and the third support structure.
  • the structure of the third electrode and the like can refer to the related description above, and will not be repeated here.
  • FIG. 18 is a process diagram of another method of manufacturing a display panel provided by at least one embodiment of the present disclosure. As shown in FIG. 18 , the manufacturing method includes:
  • Step S41 providing a base substrate.
  • Step S42 forming a first electrode on the base substrate.
  • Step S43 forming a first interlayer insulating layer on the first electrode.
  • Step S44 performing a patterning process on the first interlayer insulating layer to form a first via hole, and forming a second via hole penetrating through the first interlayer insulating layer in the first interlayer insulating layer.
  • Step S45 forming a second electrode on the first via hole, and electrically connecting the second electrode to the first electrode.
  • Step S46 forming a first supporting structure in the area corresponding to the first via hole and on the side of the second electrode away from the base substrate;
  • the third support structure is formed on the side, and the first insulating layer is formed during the process of forming the first support structure and the third support structure.
  • the orthographic projection of the third support structure on the substrate substrate and the orthographic projection of the second support structure on the substrate substrate do not have overlapping portions.
  • the first support structure, the third support structure and the first insulating layer are arranged in the same layer and formed of the same material.
  • Step S47 forming a third electrode on a side of the first insulating layer away from the base substrate.
  • the third electrode includes metal oxide strip portions spaced apart from each other in a direction parallel to the main surface of the base substrate, and metal portions between the metal oxide strip portions, or the third electrode includes metal oxide strip portions. layer and metal oxide covering side surfaces of the metal layer and a surface away from the base substrate, and the third electrode includes a plurality of portions spaced apart from each other in a direction parallel to the main surface of the base substrate.
  • the first insulating layer is interposed between the second electrode and the third electrode, so that the second electrode and the third electrode can correspond at the surface of the first via hole or the second via hole close to the base substrate. , so that the overlapping area of the orthographic projection of the second electrode on the base substrate and the orthographic projection of the third electrode on the base substrate.
  • Step S48 providing a second substrate, forming a second support structure on the second substrate, the surface of the first support structure close to the second substrate is in contact with the surface of the second support structure close to the first substrate, so that the second substrate supporting and forming a gap between the first substrate and the second substrate.
  • At least part of the first supporting structure is located in the first via hole, and the orthographic projection of the first via hole on the substrate and the grid line on the substrate The orthographic projections on the substrate are at least partially overlapped to improve the resolution and aperture ratio of the display panel.
  • the first support structure is provided in the area corresponding to the first via hole included in the flat layer on the first substrate, and the second support structure is provided on the second substrate.
  • the surface of a support structure close to the second substrate is in contact with the surface of the second support structure close to the first substrate, so as to support the second substrate and form a gap between the first substrate and the second substrate, so that the second substrate can be reduced.
  • the display area corresponding to the first substrate or the second substrate is scratched during the joining process of the first substrate and the second substrate, thereby reducing the risk of edge light leakage.
  • the first support structure is disposed in the area corresponding to the first via hole included in the planar layer, the problem of light leakage caused by the first via hole is avoided.
  • the display panel provided by at least one embodiment of the present disclosure combines the technical effects of high mobility and narrow frame of the drive transistor with polysilicon material as the semiconductor layer, and the technical effect of the switch transistor with metal oxide semiconductor material as the semiconductor layer.
  • the high transmittance display effect further improves the virtual reality display effect of the display panel.
  • using the first polysilicon layer and the second polysilicon layer as semiconductor layers can improve the mobility and bring about the technical effect of narrow borders.

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Abstract

本公开至少一实施例提供一种显示面板，该显示面板包括：相互对合的第一基板(101)和第二基板(102)，其中，所述第一基板(101)包括衬底基板(1011)，以及依次设置在所述衬底基板(1011)上的栅线(1022)、第一电极(1012)、第一层间绝缘层(1013)和第二电极(1014)；所述第一层间绝缘层(1013)中具有贯穿所述第一层间绝缘层(1013)的第一过孔(1015)，所述第二电极(1014)通过所述第一过孔(1015)与所述第一电极(1012)电连接，在所述第一过孔(1015)对应的区域且在所述第二电极(1014)的远离所述衬底基板(1011)的一侧设置有第一支撑结构(1016)；所述第一支撑结构(1016)的至少部分位于所述第一过孔(1015)内；且所述第一过孔(1015)在所述衬底基板(1011)上的正投影和所述栅线(1022)在所述衬底基板(1011)上的正投影至少部分交叠，该显示面板通过使得第一支撑结构(1016)的至少部分位于第一过孔(1015)内，且使得第一过孔(1015)在衬底基板(1011)上的正投影和栅线(1022)在衬底基板(1011)上的正投影至少部分交叠，以提高显示面板的分辨率和开口率。

Description

显示面板
本申请要求于2022年01月14日递交的中国专利申请第202210041921.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示面板。
背景技术
超高PPI的产品(如PPI从几百至几千)用于虚拟现实显示、瞄准镜等市场正在被各厂商开发并将逐渐走入用户视野。
以虚拟现实技术为例，虚拟现实技术是一种将真实世界信息和虚拟世界信息“无缝”集成的新技术。虚拟现实显示产品相对于常规的显示产品，其最明显的特征就是具有超高的分辨率。随着光电技术与半导体制造技术的发展，在显示装置中，例如，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)凭借其高品质画质、高空间利用率、低消耗功率、无辐射等优越特性在当前的显示器市场中占据着主导地位。
发明内容
本公开至少一实施例提供一种显示面板，该显示面板通过使得第一支撑结构的至少部分位于第一过孔内，且使得第一过孔在衬底基板上的正投影和栅极或栅线在衬底基板上的正投影至少部分交叠，以提高显示面板的分辨率和开口率。
本公开至少一实施例提供一种显示面板，该显示面板包括：相互对合的第一基板和第二基板，其中，所述第一基板包括衬底基板，以及依次设置在所述衬底基板上的栅线、第一电极、第一层间绝缘层和第二电极；所述第一层间绝缘层中具有贯穿所述第一层间绝缘层的第一过孔，所述第二电极通过所述第一过孔与所述第一电极电连接，在所述第一过孔对应的区域且在所述第二电极的远离所述衬底基板的一侧设置有第一支撑结构；所述第一支撑结 构的至少部分位于所述第一过孔内；且所述第一过孔在所述衬底基板上的正投影和所述栅线在所述衬底基板上的正投影至少部分交叠。
例如，在本公开至少一实施例提供的显示面板中，所述第一基板为阵列基板，所述阵列基板包括位于所述衬底基板上的横纵交叉设置的所述栅线和数据线，以及多个像素单元；所述像素单元包括：所述第一电极、所述第二电极和所述第一层间绝缘层；所述第二电极与所述第一层间绝缘层的远离所述衬底基板的表面接触，且所述第二电极由所述第一层间绝缘层的上表面延伸到所述第一过孔的侧壁和下部开口区域并与位于所述下部开口区域的所述第一电极连接。
例如，在本公开至少一实施例提供的显示面板中，所述第一层间绝缘层至少包含平坦化层，所述第一过孔贯穿所述平坦化层。
例如，在本公开至少一实施例提供的显示面板中，所述第一支撑结构的靠近所述第二基板的表面为平面或者向所述衬底基板的一侧凹陷的凹面。
例如，在本公开至少一实施例提供的显示面板中，所述第一支撑结构在所述第一过孔内向下延伸至所述第一过孔的下部开口区域。
例如，在本公开至少一实施例提供的显示面板中，所述第一支撑结构在所述第一过孔内向上延伸到所述第一过孔的上部开口区域且所述第一支撑结构的顶部高于所述第一层间绝缘层的上表面。
例如，在本公开至少一实施例提供的显示面板中，所述像素单元还包括位于所述第一层间绝缘层上表面上方的第三电极，所述第三电极与所述第一层间绝缘层的上表面上的第二电极之间设置有第二层间绝缘层；所述第二层间绝缘层上包含与所述第一层间绝缘层相贯通的开口，所述第一支撑结构朝向所述第二基板延伸并具有高出所述第二层间绝缘层的突出结构。
例如，在本公开至少一实施例提供的显示面板中，所述第三电极包括位于所述第二层间绝缘层上表面相互间隔分布的金属氧化物条状部分，以及在所述金属氧化物条状部分之间分布的金属部分。
例如，在本公开至少一实施例提供的显示面板中，所述第三电极包括金属部分和包覆所述金属部分的侧表面和上表面的金属氧化物条状部分，且在平行于所述衬底基板的主表面的方向上，所述第三电极包括相互间隔的多个部分。
例如，在本公开至少一实施例提供的显示面板中，所述第一支撑结构的 超过所述第一层间绝缘层的上表面和所述第二层间绝缘层的上表面的部分在垂直于所述衬底基板的主表面和垂直于所述栅线延伸的方向上的截面形状为矩形或者梯形或者上表面向所述衬底基板的一侧凹陷的类梯形。
例如，在本公开至少一实施例提供的显示面板中，所述第一支撑结构超过所述第二层间绝缘层的上表面朝向所述第二基板延伸，且沿着所述第二层间绝缘层的上表面远离所述第一过孔延伸。
例如，在本公开至少一实施例提供的显示面板中，所述像素单元还包括薄膜晶体管，所述薄膜晶体管包括半导体层、间隔设置的源极和漏极，所述源极和所述漏极与所述半导体层连接；所述第二电极为所述像素单元的像素电极；所述第一电极为所述漏极或者为用作连接所述漏极与所述像素电极的转接电极。
例如，在本公开至少一实施例提供的显示面板中，所述第一层间绝缘层至少包含有机平坦层，所述第二层间绝缘层至少包含无机绝缘层，所述第三电极为所述像素单元的公共电极。
例如，在本公开至少一实施例提供的显示面板中，所述漏极的材料包括透明金属氧化物导电材料。
例如，在本公开至少一实施例提供的显示面板中，所述第一过孔的靠近所述第一层间绝缘层的上表面的开口宽度d满足：d≤(K1*M/PPI)*(1-AR*1/(1-D min*PPI/M))，且M为固定值25400μm；PPI为像素密度，所述像素密度是每英寸所具有的所述像素单元的数量，1英寸＝25400μm；单个所述像素单元的宽度P＝M/PPI＝25400μm/PPI，K1为单个像素的长宽比值，AR为开口率，PPI为像素密度，D min为工艺曝光极限值。
例如，在本公开至少一实施例提供的显示面板中，所述第一过孔的靠近第一层间绝缘层的上表面的开口宽度d满足：d≈(K1*M/PPI)*(1-AR)。
例如，在本公开至少一实施例提供的显示面板中，还包括薄膜晶体管，所述薄膜晶体管包括间隔设置的源极和漏极，在垂直于所述衬底基板的主表面的方向上，所述第一过孔的靠近所述源极的边缘与所述衬底基板的主表面所在的平面形成的夹角为α，所述第一过孔的靠近所述漏极的边缘与所述衬底基板的主表面所在的平面形成的夹角为β，且α≥β。
例如，在本公开至少一实施例提供的显示面板中，α>β，且α-β的差值的范围为0.5-3°。
例如，在本公开至少一实施例提供的显示面板中，D min≤W gate≤d，d＝2.0μm～10μm，D min＝1.5μm～2μm。
例如，在本公开至少一实施例提供的显示面板中，所述第一过孔的设计满足(d1-d2)-tanβ1*d3的绝对值范围在0到1.5之间，d1为所述第一过孔的远离所述衬底基板的一侧的开口宽度，d2为所述第一过孔的靠近所述衬底基板的一侧的开口宽度，d3为所述第一层间绝缘的厚度，β1为所述第一过孔的侧壁与衬底基板的水平面之间的夹角。
例如，在本公开至少一实施例提供的显示面板中，所述第一基板还包括设置在所述衬底基板上的开关晶体管；所述开关晶体管设置在显示区域；所述开关晶体管包括依次层叠设置在所述衬底基板上的第一绝缘层、遮光层、第二绝缘层、金属氧化物半导体层、栅绝缘层、第一栅极、第三绝缘层、第一源极、第四绝缘层和第一漏极，且所述第一电极通过依次贯穿所述第四绝缘层、所述第三绝缘层和所述栅绝缘层的第三过孔与所述金属氧化物半导体层电连接以用作所述第一漏极，所述第一源极通过依次贯穿所述第三绝缘层和所述栅绝缘层的第四过孔与所述金属氧化物半导体层电连接。
例如，在本公开至少一实施例提供的显示面板中，所述第一基板还包括设置在所述衬底基板上的开关晶体管；所述开关晶体管设置在显示区域；所述开关晶体管包括依次层叠设置在所述衬底基板上的遮光层、缓冲层、第一多晶硅层、栅绝缘层、第一栅极、第三绝缘层、基础电极层、第四绝缘层、第一漏极、第五绝缘层和第一源极，所述基础电极层包括相对设置的第一基础电极和第二基础电极，且所述第一电极通过贯穿所述第四绝缘层的第五过孔与所述第一基础电极电连接以用作所述第一漏极，所述第一基础电极通过贯穿所述第三绝缘层和所述栅绝缘层的第六过孔与所述第一多晶硅层电连接；所述第一源极通过依次贯穿所述第五绝缘层和所述第四绝缘层的第七过孔与所述第二基础电极电连接，所述第二基础电极通过贯穿所述第三绝缘层和所述栅绝缘层的第八过孔与所述第一多晶硅层电连接。
例如，在本公开至少一实施例提供的显示面板中，在平行于所述衬底基板的主表面的方向上，所述第一电极和所述第二电极的接触部分位于所述第五过孔与所述第七过孔之间，且所述第一电极和所述第二电极的所述接触部分在所述衬底基板上的正投影与所述第一栅极在所述衬底基板上的正投影至少部分交叠。
例如，在本公开至少一实施例提供的显示面板中，在平行于所述衬底基板的主表面的方向上，所述第一电极和所述第二电极的接触部分的靠近所述第五过孔的一侧与所述第六过孔之间的距离等于所述第一电极的未覆盖所述第一栅极的长度。
例如，在本公开至少一实施例提供的显示面板中，在平行于所述衬底基板的主表面的方向上，所述遮光层的两端的端点位于所述第七过孔与所述第五过孔之间，所述第一电极和所述第二电极的接触部分位于所述第七过孔与所述遮光层的靠近所述第五过孔的端点之间。
例如，在本公开至少一实施例提供的显示面板中，在所述第二基板上设置有第二支撑结构，所述第一支撑结构的靠近所述第二基板的表面和所述第二支撑结构的靠近所述第一基板的表面接触或保持设定间距。
例如，在本公开至少一实施例提供的显示面板中，所述第二支撑结构在所述衬底基板上的正投影和所述第一支撑结构在所述衬底基板上的正投影至少部分交叠。
例如，在本公开至少一实施例提供的显示面板中，所述第二支撑结构与所述第一支撑结构的接触面的面积小于所述第二支撑结构或所述第一支撑结构的靠近所述衬底基板的区域的横截面的面积。
例如，在本公开至少一实施例提供的显示面板中，所述第一层间绝缘层中具有贯穿所述第一层间绝缘层的第二过孔，所述第二过孔中设置有第三支撑结构，所述第三支撑结构在所述衬底基板上的正投影和所述第二支撑结构在所述衬底基板上的正投影不具有交叠部分。
例如，在本公开至少一实施例提供的显示面板中，所述第三支撑结构背离所述衬底基板延伸至所述第二过孔之外，且所述第三支撑结构填充所述第二过孔使得位于所述第二过孔内的形状与所述第二过孔的形状相适应。
例如，在本公开至少一实施例提供的显示面板中，所述第三支撑结构延伸到所述第二过孔之外的部分的纵截面的形状为梯形。
例如，在本公开至少一实施例提供的显示面板中，所述第二支撑结构的屈服强度大于所述第一基板和所述第二基板对合时的对合压力与单个所述第二支撑结构的面积和所述第二支撑结构的个数的乘积。
例如，在本公开至少一实施例提供的显示面板中，所述平坦化层和所述第一支撑结构的材料均为透光材料。
例如，在本公开至少一实施例提供的显示面板中，所述第一支撑结构的材料为遮光材料，所述第一支撑结构的延伸方向平行于所述栅线的延伸方向。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的一种显示面板的截面结构示意图；
图2为本公开至少一实施例提供的一种第一基板的平面结构示意图；
图3为本公开至少一实施例提供的再一种显示面板的截面结构示意图；
图4为本公开至少一实施例提供的又一种显示面板的截面结构示意图；
图5为本公开至少一实施例提供的又一种显示面板的截面结构示意图；
图6为图5所示截面结构中第二电极和第三电极的透视图；
图7为本公开至少一实施例提供的又一种显示面板的截面结构示意图；
图8为本公开至少一实施例提供的又一种显示面板的截面结构示意图；
图9为本公开至少一实施例提供的又一种第二电极和第三电极的透视图；
图10为图9中所示结构的截面结构示意图；
图11为本公开至少一实施例提供的又一种显示面板的截面结构示意图；
图12为本公开至少一实施例提供的一种第一支撑结构的扫描电镜图；
图13为本公开至少一实施例提供的一种第一基板的透视结构示意图；
图14为本公开至少一实施例提供的再一种第一基板的透视结构示意图；
图15为本公开至少一实施例提供的一种显示面板的制备方法的过程图；
图16为本公开至少一实施例提供的再一种显示面板的制备方法的过程图；
图17为本公开至少一实施例提供的又一种显示面板的制备方法的过程图；以及
图18为本公开至少一实施例提供的又一种显示面板的制备方法的过程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公 开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示技术的发展，在VR显示、瞄准镜等细分市场领域，提升显示面板的分辨率、开口率和光效等成为本领域技术人员研究的重点。
本公开的发明人注意到，通常显示面板包括的第一基板上具有层间绝缘层，层间绝缘层中设置有过孔结构，过孔结构中设置有电极，支撑结构设置在层间绝缘层的未设置过孔结构的区域，且栅线在衬底基板上的正投影和过孔结构在衬底基板上的正投影不存在交叠部分，从而使得显示面板的分辨率和开口率均较低，因此，可以考虑改变显示面板结构的设计以提高显示面板的分辨率和开口率。
本公开的发明人还注意到，在通常的设计中，将支撑结构仅设置在第一基板或者第二基板上，这样在第一基板和第二基板进行对合的过程中容易对第一基板对应的显示区域或者对第二基板对应的显示区域造成划伤，从而可以考虑在第一基板和第二基板上分别设置第一支撑结构和第二支撑结构，以使得在第一基板和第二基板进行对合的过程中，第一支撑结构的靠近第二基板的表面和第二支撑结构的靠近第一基板的表面接触，以对第二基板进行支撑并在第一基板和第二基板之间形成间隙，从而避免第一基板和第二基板对合的过程中对第一基板对应的显示区域或者对第二基板对应的显示区域造成划伤，进而可以减小边缘漏光的风险。
本公开至少一实施例提供一种显示面板,可以适用于高分辨率液晶显示 面板，该显示面板包括：相互对合的第一基板(如阵列基板)和第二基板以及第一基板和第二基板之间的液晶层，其中，该第一基板包括衬底基板，以及依次设置在衬底基板上的栅线、第一电极、第一层间绝缘层和第二电极；该第一层间绝缘层中具有贯穿第一层间绝缘层的第一过孔，第二电极通过第一过孔与第一电极电连接，在第一过孔对应的区域且在第二电极的远离衬底基板的一侧设置有第一支撑结构；该第一支撑结构的至少部分位于第一过孔内；且第一过孔在衬底基板上的正投影和栅线在衬底基板上的正投影至少部分交叠。本公开的实施例通过使得第一支撑结构的至少部分位于第一过孔内，且使得第一过孔在衬底基板上的正投影和栅线在衬底基板上的正投影至少部分交叠，以提高显示面板的分辨率和开口率。
例如，图1为本公开至少一实施例提供的一种显示面板的截面结构示意图，如图1所示，该显示面板10包括：相互对合的第一基板101和第二基板102，其中，该第一基板101包括衬底基板1011，以及依次设置在衬底基板1011上的栅线1022、第一电极1012、第一层间绝缘层1013和第二电极1014，该第一层间绝缘层1013中具有贯穿第一层间绝缘层1013的第一过孔1015，该第二电极1014通过第一过孔1015与第一电极1012电连接，在第一过孔1015对应的区域且在第二电极1014的远离衬底基板1011的一侧设置有第一支撑结构1016；该第一支撑结构1016的至少部分位于第一过孔1015内；且该第一过孔1015在衬底基板1011上的正投影和栅线1022在衬底基板1011上的正投影至少部分交叠。例如，图1所示的显示面板10通过使得第一支撑结构1016的至少部分位于第一过孔1015内，且使得第一过孔1015在衬底基板1011上的正投影和栅线1022在衬底基板1011上的正投影至少部分交叠，从而提高了显示面板10的分辨率和开口率。
例如，第一支撑结构1016具有靠近衬底基板1011的底部和相对位置的顶部，以及侧部。
例如，需要说明的是，第一支撑结构1016位于与第一过孔1015对应的区域可以是第一支撑结构1016与第一过孔1015具有至少部分交叠的区域。一些实施例中，第一支撑结构1016的投影位于第一支撑结构1016与第一过孔1015的交叠区域内。另一些实施例中，第一支撑结构1016的投影的一部分位于第一支撑结构1016与第一过孔1015的交叠区域内，比如，第一支撑结构1016位于第一过孔1015的开口区域中和从第一过孔1015的开口部区域 延伸至外部的区域。
例如，图2为本公开至少一实施例提供的一种第一基板的平面结构示意图，如图2所示，该第一基板101为阵列基板，该阵列基板包括位于衬底基板1011上的横纵交叉设置的该栅线1022和数据线1024，以及多个像素单元1025，结合图1和图2所示，该像素单元1025包括：第一电极1012、第二电极1014和第一电极1012和第二电极1014之间的第一层间绝缘层1013，该第二电极1014与第一层间绝缘层1013的远离衬底基板1011的表面接触，且第二电极1014由第一层间绝缘层1013的上表面延伸到第一过孔1015的侧壁和下部开口区域并与位于下部开口区域的第一电极1012接触并连接。
一些实施方式中，所述第一层间绝缘层1013为单层膜层，比如，单层平坦层，材质可以为有机透明膜层。
一些实施方式中，所述第一层间绝缘层1013为叠层绝缘层，叠层绝缘层可以为多层(含两层)。在材料上可以是有机和无机绝缘层的叠层，也可以是多层无机绝缘层的叠层。多层无机绝缘层的叠层可以是含有不完全相同的元素类型的膜层，比如氧化硅和氮化硅的叠层，也可以是相同类型元素但是摩尔比不同的膜层叠层，比如，各膜层均为SixOy，但x或y的数值不同。
一些实施方式中，如图1所示，该第一层间绝缘层1013为一层平坦层，具有两个主表面，分别为上表面和下表面，上表面远离所述衬底基板1011，下表面更靠近所述衬底基板1011。该第一层间绝缘层1013具有第一过孔1015，该第一过孔1015具有侧壁、靠近第一层间绝缘层1013的上表面的开口(可以称为上开口或上孔口)、以及靠近第一层间绝缘层1013的下表面的开口(可以称为下开口或下孔口)。
一些实施方式中，第一层间绝缘层1013上面不在设置有其他绝缘层，所述第一支撑结构1016填充于所述第一层间绝缘层1013的第一过孔1015中，用于支撑第一基板101和第二基板102确保一定范围内的盒厚。
一些实施方式中，第一层间绝缘层1013上面可以设置一层或多层绝缘层，多层绝缘层可以不设置开口或部分膜层设置可以露出第一支撑结构1016的开口，至少部分膜层覆盖在所述第一支撑结构1016上，膜层依照所述第一支撑结构1016的形状形成在第一层间绝缘层1013上，使得所述第一支撑结构1016即使被覆盖其他膜层时高度仍然能起到支撑第一基板101和第二基板102的作用，在支撑高度的设计时需要考虑到被覆盖的其他膜层的累计厚度。
一种实施方式中，所述第一支撑结构1016朝向所述第二基板102延伸并具有高出所述第二层间绝缘层1019的突出结构。
一种实施方式中，第一层间绝缘层1013上形成有第二层间绝缘层1019，当第一层间绝缘层1013上通过沉积方法形成有第二层间绝缘层1019时，一种实施方式为，所述第二层间绝缘层1019还位于所述第一过孔1015中，另一种实施方式为，第二层间绝缘层1019对应于第一过孔1015的区域被去除仅保留第一层间绝缘层1013的上表面的部分。
无论第二层间绝缘层1019对应第一过孔1015的区域是否被去除，第二层间绝缘层1019通过沉积的方法形成在具有第一过孔1015的第一层间绝缘层1013上，都会形成相似的过孔，该过孔依然具有几乎类似于第一过孔1015的孔壁形状和大约相同位置的上下两个开口，即可以依照第一过孔1015的形状形成类似的过孔。相应的，第二层间绝缘层1019也具备上表面、下表面、过孔、靠近上表面的开口和靠近下表面的开口。
例如，如图2所示，像素单元1025为横纵交叉设置的栅线1022和数据线1024限定的像素区域中，在像素单元1025中设置有像素结构。
例如，在一个示例中，该第一层间绝缘层1013至少包含平坦化层，该第一过孔1015为贯穿该平坦化层的通孔，该平坦化层可以起到平坦的作用同时可以降低电极或信号线之间的寄生电容，使得显示面板中的电信号更加稳定。
在一个示例中，该第一层间绝缘层1013包括的平坦化层和第一支撑结构1016的材料均为透光材料，比如有机树脂，以提高显示面板的光透过率。该透光材料的第一支撑结构1016在设计尺寸上有较大的自由度，不受下方的栅线的限制。
在另一个示例中，该第一支撑结构1016的材料为遮光材料，该遮光材料可以有效降低所在区域漏光现象，但是为了提高开口率，该第一支撑结构的投影位于其下方的栅线的投影内。
一些实施例中，该第一支撑结构1016位于栅线的上方，至少填充于所述第一过孔1015内在第一层间绝缘层1013或第二层间绝缘层1019的上表面延伸时朝向栅线1022的宽度方向延伸以及长度方向延伸。一些实施例中，第一支撑结构1016可以超过栅线1022的宽度方向的边缘，也可以位于栅线1022的轮廓范围内。一些实施例中，第一支撑结构1016可以朝着栅线1022的长度方向延伸，比如，平行于栅线1022的延伸方向。
在一条栅线1022上方可以设置多个第一支撑结构1016，比如，一个像素单元对应设置一个第一支撑结构1016。则，相邻的第一支撑结构1016可以是相互被隔开独立设置。也可以是彼此相连接的，比如，通过第一支撑结构1016的延伸部分相连接。
例如，在一个示例中，该第一支撑结构1016的靠近第二基板102的表面为平面或者向衬底基板1011的一侧凹陷的凹面，在图1所示的结构中，该第一支撑结构1016的靠近第二基板102的表面为向衬底基板1011的一侧凹陷的凹面。
例如，需要说明的是，该第一支撑结构1016的靠近第二基板102的表面还可以是朝向第二基板102凸起的凸面。
例如，如图1所示，在第一基板101和第二基板102之间，还设置有与第一支撑结构1016相配合以支撑第一基板101和第二基板102的第二支撑结构1021，该第一支撑结构1016和第二支撑结构1021其中一个位于第一基板101上，另一个位于第二基板102上，并且第一支撑结构1016和第二支撑结构1021在第一基板101和第二基板102对合时可以相互接触或保持一定的距离，并在第一基板101和第二基板102之间限定容纳液晶层104的空间，且第一支撑结构1016和第二支撑结构1021的接触位置的形状可以相互适应。比如，第一支撑结构1016的靠近第二基板102的表面为凹面或平面，则第二支撑结构1021的靠近第一基板101的表面可以为凸面或平面；第一支撑结构1016的靠近第二基板102的表面为凸面或平面，则第二支撑结构1021的靠近第一基板101的表面可以为凹面或平面。
需要说明的是，在本公开的实施例中，第一支撑结构1016的靠近第二基板102的表面和第二支撑结构1021的靠近第一基板101的表面接触是指第一支撑结构1016的顶面和第二支撑结构1021的顶面至少部分区域接触，以使得在垂直于衬底基板1011主表面的方向上第一基板101和第二基板102之间具有最大的间隙，或者，第一支撑结构1016的靠近第二基板102的表面和第二支撑结构1021的靠近第一基板101的表面接触还可以是指第一支撑结构1016的靠近第二基板102的表面的其他位置的部分和第二支撑结构1021的靠近第一基板101的表面的其他位置的部分接触，只要使得第一基板101和第二基板102之间具有间隙，当第一基板101和第二基板102对合时，不会使得对第一基板101对应的显示区域或者对第二基板102对应的显示区域进行 划伤，且不会出现边缘区域漏光的问题。并通过将第一支撑结构1016设置在第一过孔1015对应的区域内，可以避免第一过孔1015导致的漏光的问题。
例如，在一个示例中，第一支撑结构1016将第一层间绝缘层1013的第一过孔1015填充完全且突出于第一过孔1015之外，第一支撑结构1016的靠近第二基板102的表面为凹陷面其增加了该表面的表面积，以使得第一支撑结构1016和第二支撑结构1021的接触面积会更大，从而使得第一支撑结构1016对第二基板102的有效支撑面积变大，并可以减小第二支撑结构1021从第一基板101上滑落的风险。而且第一支撑结构1016的大部分结构位于第一过孔1015之中。例如，在一个示例中，第一支撑结构1016的高度为0.6μm左右，可以满足显示面板对间隙大小的要求。
例如,所述第二支撑结构1021与所述第一支撑结构1016的接触面的面积小于第二支撑结构1021或第一支撑结构1016的靠近衬底基板1011区域的横截面的面积。
需要说明的是，该第二基板102可以包括衬底以及设置在衬底上的膜层结构。
例如，如图1所示，第一支撑结构1016的靠近第二基板102的表面向衬底基板1011的一侧凹陷，第二支撑结构1021的靠近第一基板101的表面向靠近第一基板101的一侧凸起，该种结构设计可以使得第二支撑结构1021和第一支撑结构1016的凹陷的部分接触，从而使得第二支撑结构1021要从第一基板101上滑落时必须先向上运动，这样的设计可以使得第二支撑结构1021更不易从第一支撑结构1016上滑落，以使得第一基板101和第二基板102之间的间隙103在垂直于衬底基板1011的主表面上的尺寸可以保持恒定。如图1所示，第一基板101和第二基板102之间的间隙103在垂直于衬底基板1011的主表面上的尺寸为a+b，从而小于尺寸a+c，其中a为第二支撑结构1021在垂直于衬底基板1011主表面上的最大尺寸，b为第一支撑结构1016的远离衬底基板1011的表面到第一过孔1015的远离衬底基板1011的表面的最小距离，c为第一支撑结构1016的远离衬底基板1011的表面到第一过孔1015的远离衬底基板1011的表面的最大距离。
例如，在一个示例中，液晶盒厚为a+b，且c＞b，该液晶盒厚影响液晶的响应速度。第二支撑结构1021高度的最小值a min由工艺条件决定，且a min＝1微米。
例如，在一个示例中，液晶盒厚为1.6微米，a min＝1微米，b值最大0.6微米，a增大，b值可以减小，b的最小取值范围为0～0.6微米。优选地，b值的范围为0.30微米～0.45微米。
例如，如图1所示，第一支撑结构1016的靠近第二基板102的表面和第二支撑结构1021的靠近第一基板101的表面接触，以对第二基板102进行支撑并在第一基板101和第二基板102之间形成间隙。
例如，如图1所示，该第二支撑结构1021在衬底基板1011上的正投影和第一支撑结构1016在衬底基板1011上的正投影至少部分交叠。
例如，如图1所示，该第二支撑结构1021在垂直于衬底基板1011的主表面的平面上的截面形状为半圆形。
例如，在一个示例中，第二支撑结构1021的屈服强度大于第一基板101和第二基板102对合时的对合压力与单个第二支撑结构1021的面积和第二支撑结构1021的个数的乘积。
需要说明的是，第二支撑结构1021的屈服强度是指第二支撑结构1021的材料发生弹性形变的最大压强，以防止第一基板101和第二基板102对合过程中，第二支撑结构1021发生塑性形变，以影响第一基板101和第二基板102对合的效果。
例如，图3为本公开至少一实施例提供的再一种显示面板的截面结构示意图，如图3所示，第一支撑结构1016的靠近第二基板102的表面为凸面，第二支撑结构1021的靠近第一基板101的表面为凹面，第一支撑结构1016的凸面抵靠在第二支撑结构1021的凹面上，该种结构设计可以使得第二支撑结构1021的凹陷的部分和第一支撑结构1016的凸起的部分接触，从而使得第二支撑结构1021要从第一基板101上滑落时必须先向上运动，这样的设计可以使得第二支撑结构1021更不易从第一支撑结构1016上滑落，以使得第一基板101和第二基板102之间的间隙103在垂直于衬底基板1011的主表面上的尺寸可以保持恒定。
需要说明的是，该第一支撑结构1016的靠近第二基板102的表面也可以是大致平行于衬底基板1011的平面。
例如，如图1和图3所示，第二支撑结构1021和第一支撑结构1016一一对应，即每个第一支撑结构1016都与第二支撑结构1021接触，每个第二支撑结构1021都和一个第一支撑结构1016接触，从而第二支撑结构1021和 第一支撑结构1016的个数相等。
例如，如图1所示，该第二支撑结构1021在衬底基板1011上的正投影和第一支撑结构1016在衬底基板1011上的正投影至少部分交叠。例如，在一个示例中，该第二支撑结构1021在衬底基板1011上的正投影位于第一支撑结构1016在衬底基板1011上的正投影之内。该第二支撑结构1021在垂直于衬底基板1011主表面的平面上的截面形状沿着x轴的两个端点A、A’的连线A-A’关于与z轴平行的轴成轴对称，该第一支撑结构1016在垂直于衬底基板1011主表面的平面上的截面形状沿着x轴的两个端点B、B’的连线B-B’关于与z轴平行的轴成轴对称，线A-A’平行于线B-B’，并且线A-A’的长度小于线B-B’的长度。
例如，如图1所示，该第二支撑结构1021在垂直于衬底基板1011主表面的平面且垂直于栅线的方向上的截面形状为半圆形，从而使得第二支撑结构1021与第一支撑结构1016的接触可以为线接触。本公开的实施例不限于此，该第二支撑结构1021在垂直于衬底基板1011主表面的平面上的截面形状还可以为矩形、三角形等，且该第二支撑结构1021与第一支撑结构1016的接触还可以为面接触等，本公开的实施例对此不作限定。
例如，在图1和图3所示的结构中，该第一基板101为阵列基板，第二基板102为彩膜基板，或者，第一基板为阵列基板且彩色滤光功能位于阵列基板上，也称为COA基板(color film on array，COA)，则第二基板102为对置基板。
下述实施例中均以第一基板101为阵列基板，第二基板102为彩膜基板，且在第一基板101和第二基板102之间的间隙103中设置液晶层104为例进行说明，但本公开的实施例不限于此，只要最终形成的结构能够满足显示的功能即可。
例如，如图1和图3所示，该第一层间绝缘层1013具有上表面和下表面，以及第一过孔1015，该第一过孔1015具有侧壁、靠近第一层间绝缘层1013的上表面的开口、以及靠近第一层间绝缘层1013的下表面的开口。
例如，如图1和图3所示，该第一支撑结构1016在第一过孔1015内向下延伸至第一过孔1015下部开口区域。
例如，如图1和图3所示，该第一支撑结构1016从第一层间绝缘层1013的第一过孔1015的底部向上延伸，即沿着远离衬底基板1011主表面的方向 延伸填充第一过孔1015并继续延伸至第一过孔1015的靠近第一层间绝缘层上表面的开口之外，且该第一支撑结构1016在第一层间绝缘层1013的上表面上延伸至第一过孔1015之外，延伸出第一过孔1015之外的部分与第一层间绝缘层1013的上表面交叠。
需要说明的是，不限于图1和图3中所示的结构，如果该第一层间绝缘层1013上未设置其他绝缘层，则该第一支撑结构1016与第一层间绝缘层1013的上表面接触。如果第一层间绝缘层1013上设置有其他绝缘层，例如第二层间绝缘层，该第一支撑结构1016与第二层间绝缘层的上表面接触。该第一支撑结构1016从第一层间绝缘层1013的第一过孔1015的底部向上延伸，即沿着远离衬底基板1011的主表面的方向延伸填充第一过孔1015并继续延伸至第一过孔1015的靠近第一层间绝缘层1013的上表面的上部开口区域并继续向上延伸超过第二层间绝缘层的上表面，使得第一支撑结构1016的至少部分位于第一层间绝缘层1013的第一过孔1015之外并与第二层间绝缘层的上表面接触，从而使得每个第一支撑结构1016的体积更大，且第一支撑结构1016的远离衬底基板1011的表面的面积更大，以使得第二支撑结构1021和第一支撑结构1016可以更加稳定的接触，以使得第一基板101和第二基板102之间的间隙103更加恒定。
如图1和图3所示，该第一支撑结构1016的凹陷的部分位于第一支撑结构1016在垂直于衬底基板1011的主表面的平面上的截面形状的中间区域，该第一支撑结构1016的远离衬底基板1011的表面关于z轴成轴对称，将坐标轴进行平移，该第一支撑结构1016的远离衬底基板1011的表面的最靠近衬底基板1011的位置可以为x轴和z轴的交点，第一支撑结构1016的凹陷的部分关于z轴成轴对称。
例如，上述的第一过孔1015设置在多个像素单元1025对应的栅线区域，一个像素单元1025可以对应一个上述的第一过孔1015以及一个与该第一过孔1015对应的第一支撑结构1016。该第一过孔1015为该像素单元1025中薄膜晶体管的漏极和像素电极的连接孔。
例如，该一个第一过孔1015中的第一电极1012连接该像素单元1025中薄膜晶体管的漏极，或者该第一电极1012直接作为薄膜晶体管的漏极并与薄膜晶体管的半导体层连接。
例如，图4为本公开至少一实施例提供的又一种显示面板的截面结构示 意图，如图4所示，在第一层间绝缘层1013的远离衬底基板1011的一侧，还设置有第二层间绝缘层1019，该第一支撑结构1016与第二层间绝缘层1019的上表面接触。该第一支撑结构1016从第一层间绝缘层1013的第一过孔1015的底部向上延伸，即沿着远离衬底基板1011的主表面的方向延伸填充第一过孔1015并继续延伸至到第一过孔1015的靠近第一层间绝缘层1013的上表面的上部开口区域并继续向上延伸超过第二层间绝缘层1019，该像素单元1025还包括位于第二层间绝缘层1019上表面的第三电极1110，即该第二层间绝缘层1019设置在第三电极1110与第一层间绝缘层1013的上表面上的第二电极1014之间，该第二层间绝缘层1019上包含与第一层间绝缘层1013中的第一过孔1015相贯通的开口，该第一支撑结构1016朝向第二基板102延伸并具有高出第二层间绝缘层1019的突出结构。
例如，如图4所示，该第三电极1110包括位于第二层间绝缘层1019上表面相互间隔分布的金属氧化物条状部分1110a，以及在金属氧化物条状部分1110a之间分布的金属部分1110b。例如，该金属部分1110b的材料包括导电金属，例如铜金属、钼金属等具有遮光性能和导电性能的材料，该金属氧化物条状部分1110a的材料包括透明导电材料，例如氧化铟锡等，该金属部分1110b可以减少不同像素区域中光线的串扰，以提升光效。
例如，在一个示例中，该第一电极1012可以为薄膜晶体管的漏极，一种实施方式中，该漏极与金属氧化物半导体层直接接触，如搭接。另一种实施方式中，该漏极为金属氧化物导体层的局部被导体化的区域。
该第二电极1014可以为像素电极，该第三电极1110可以为像素单元的公共电极。
例如，如图4所示，该第一电极1012和第二电极1014的材料可以为透明的金属氧化物导体材料。该第三电极1110包括的金属氧化物条状部分1110a为导体而非半导体。该第三电极1110包括的金属部分1110b可以遮挡光线，从而可以减少沿着z轴方向不同颜色光线的串色，且该金属部分1110b还可以起到沿着x轴方向黑矩阵的作用，从而可以在形成第二基板102时不用制作沿着x轴方向的黑矩阵，仅需制作在平行于衬底基板1011主表面的方向上与x轴方向交叉的沿着y轴方向的黑矩阵，由于在常规制作黑矩阵的过程中，x轴方向和y轴方向的黑矩阵是在不同的工序中制作的，从而可以减少在第二基板102上形成x轴方向黑矩阵的工艺步骤。
例如，图5为本公开至少一实施例提供的又一种显示面板的截面结构示意图，如图5所示，该第三电极1110包括金属部分1110b和包覆该金属部分1110b的侧表面和上表面的金属氧化物条状部分1110a，且在平行于衬底基板1011的主表面的方向上，该第三电极1110包括相互间隔的多个部分。即金属部分1110b和包覆金属部分1110a的侧表面和远离衬底基板1011的表面的金属氧化物条状部分1110a形成的组合是相互间隔的。
例如，图6为图5所示截面结构中第二电极和第三电极的透视图，如图6所示，作为公共电极的金属部分1110b和金属氧化物条状部分1110a叠层相接触设置，金属部分1110b在衬底基板1011上的正投影位于金属氧化物条状部分1110a在衬底基板1011上的正投影之内，该第二电极1014在衬底基板1011上的正投影和金属氧化物条状部分1110a在衬底基板1011上的正投影至少部分交叠。第二电极1014在衬底基板1011上的正投影跨接在相邻的金属氧化物条状部分1110a在衬底基板1011上的正投影之间。
例如，如图1,4和5所示，第一支撑结构1016的超过第一层间绝缘层1013的上表面和第二层间绝缘层1019的上表面的部分在垂直于衬底基板1011的主表面和垂直于栅线1022延伸的方向上的截面形状为上表面向靠近衬底基板1011的一侧凹陷的类梯形结构。如图3所示，第一支撑结构1016的超过第一层间绝缘层1013的上表面和第二层间绝缘层1019的上表面的部分在垂直于衬底基板1011的主表面和垂直于栅线1022延伸的方向上的截面形状为上表面向远离衬底基板1011的一侧凸起的类梯形结构。在其他的示例中，该第一支撑结构1016的超过第一层间绝缘层1013的上表面和第二层间绝缘层1019的上表面的部分在垂直于衬底基板1011的主表面和垂直于栅线1022延伸的方向上的截面形状还可以为矩形，或者梯形等，本公开的实施例对此不作限定。
例如，如图1，图3，图4和图5所示，该第一支撑结构1016超过第二层间绝缘层1019的上表面朝向第二基板102延伸，且沿着第二层间绝缘层1019的上表面远离第一过孔1015延伸，即该第一支撑结构1016超过第二层间绝缘层1019的上表面向垂直于衬底基板1011的主表面的方向延伸同时向平行于衬底基板1011的主表面的方向延伸，向平行于衬底基板1011的主表面的方向延伸的部分与第二层间绝缘层1019的上表面相接触，使得第一支撑结构1016在衬底基板1011上的正投影覆盖并超出第一过孔1015在衬底基板 1011上的正投影区域。
例如，如图4和图5所示，在第一层间绝缘层1013中还具有贯穿第一层间绝缘层1013的第二过孔1017，第二过孔1017中设置有第三支撑结构1018，且该第二过孔1017对应第三支撑结构1018。
例如，该第二过孔1017和第一过孔1015类似，设置在多个像素单元1025的对应于设置有栅线1022的区域，一个像素单元1025可以对应一个上述的第二过孔1017以及对应的第三支撑结构1018。该第二过孔1017为该像素单元1025中的薄膜晶体管的漏极和像素电极的连接孔。
例如，该第一过孔1015和第二过孔1017为不同区域的孔，对应不同区域的薄膜晶体管，该第一过孔1015和第二过孔1017的形状大小可以相同或者不同，但是第一支撑结构1016和第三支撑结构1018不同，比如第一支撑结构1016与第二支撑结构1021配合支撑第一基板101和第二基板102，但是第三支撑结构1018单独用作支撑第一基板101和第二基板102。或者，第一支撑结构1016和第三支撑结构1018的形状有所区别。第一过孔1015为与第一支撑结构1016对应的孔，第二过孔1017为与第三支撑结构1018对应的孔，但不代表第一过孔1015和第二过孔1017有结构上的差异。在一些实施方式中，第一过孔1015和第二过孔1017的设置位置均位于栅线1022对应的区域，且第一过孔1015和第二过孔1017的大小和形状类似。
例如，在图4和图5所示的结构中，该显示面板10中包括两个像素单元，每个像素单元对应设置有一个第一过孔1016或者一个第二过孔1017。针对每个像素单元都存在一个第一电极1012、一个第二电极1014以及一个薄膜晶体管。
例如，如图4和图5所示，在第二过孔1017对应的区域且在第二电极1014的远离衬底基板1011的一侧设置有第三支撑结构1018，该第三支撑结构1018在衬底基板1011上的正投影和第二支撑结构1021在衬底基板1011上的正投影不具有交叠部分，因为第三支撑结构1018仅与第一支撑结构1016配合形成一个较大的支撑结构支撑第一基板101和第二基板102确保液晶盒的盒厚。第二支撑结构1021不与第三支撑结构1018配合也不会延伸到第三支撑结构1018所在的区域。该第三支撑结构1018至少可以将第二过孔1017进行填平，以减小第二过孔1017发生漏光的风险。
例如，如图4和图5所示，该第三支撑结构1018背离衬底基板1011延 伸至第二过孔1017之外，且第三支撑结构1018填充第二过孔1017使得位于第二过孔1017内的形状与第二过孔1017的形状相适应。如图4和图5所示，该第三支撑结构1018沿着垂直于衬底基板1011主表面的方向延伸至第二过孔1017之外，即在平行于z轴的方向上延伸至第二过孔1017之外，且该第三支撑结构1018在平行于衬底基板1011主表面的方向上的最大尺寸和第二过孔1017在平行于衬底基板1011主表面的方向上的最大尺寸相等。在垂直于衬底基板1011的主表面的平面上，且在平行于x轴的方向上，第三支撑结构1018的相距最远的两个端点的连线为第三支撑结构1018的与第二电极1014接触的两个点的连线，也即第一层间绝缘层1013的远离衬底基板1011的表面沿着x轴方向的最大开口的连线。
例如，如图4和图5所示，该第三支撑结构1018从第二过孔1017内向上延伸并超出该第二过孔1017继续向上延伸且向第二过孔1017所在膜层(例如，第一层间绝缘层1013)的上表面上延伸。
例如，如图4和图5所示，该第一过孔1015和第二过孔1017在同一工艺步骤中形成，该第一过孔1015和第二过孔1017可以采用相同的掩膜板进行构图工艺以形成，且该第一过孔1015和第二过孔1017具有相同的形状和尺寸。
例如，如图4和图5所示，第三支撑结构1018延伸到第二过孔1017之外的部分的纵截面的形状为梯形。例如，如图4和图5所示，该第三支撑结构1018沿着垂直于衬底基板1011主表面的方向延伸至第二过孔1017之外的部分，在垂直于衬底基板1011主表面的平面上的截面形状为正梯形，这样可以使得第三支撑结构1018在垂直于衬底基板1011主表面的平面上的截面形状，沿着z轴方向，且从靠近衬底基板1011的位置到远离衬底基板1011的位置，在x轴方向的尺寸先增大后减小。
例如，如图4和图5所示，该第二电极1014在第一过孔1015的靠近衬底基板1011的表面和第一电极1012面接触以彼此电连接，且该第二电极1014在第二过孔1017的靠近衬底基板1011的表面和第一电极1012面接触以彼此电连接，从而保证第一电极1012与第二电极1014的连接的稳定性，该第二电极1014也可以对第一过孔1015和第二过孔1017的靠近衬底基板1011的表面进行完全覆盖。
例如，如图4和图5所示，该第二层间绝缘层1019还设置在第三支撑结 构1018和第二电极1014之间，该第二层间绝缘层1019中设置有与第二过孔1017相通的过孔，且在第三支撑结构1018的周边在第二层间绝缘层1019的远离衬底基板1011的一侧设置有第三电极1110。该第二层间绝缘层1019可以形成在第一支撑结构1016和第三支撑结构1018的靠近衬底基板101的一侧，也可以形成在第一支撑结构1016和第三支撑结构1018的远离衬底基板101的一侧，本公开的实施例对此不作限定。
例如，如图4和图5所示，该第三支撑结构1018沿着垂直于衬底基板1011的主表面的方向延伸至第二过孔1017之外，且第三支撑结构1018在平行于衬底基板1011的主表面的方向上的最大尺寸和第二过孔1017在平行于衬底基板1011的主表面的方向上的最大尺寸相等。
例如，如图4和图5所示，该第三支撑结构1018沿着垂直于衬底基板1011的主表面的方向延伸至第二过孔1017之外的部分，在垂直于衬底基板1011的主表面的平面上的截面形状为正梯形。
例如，如图4和图5所示，该第一层间绝缘层1013至少包含有机平坦层，第二层间绝缘层1019至少包含无机绝缘层，第三电极1110为各像素单元1025的公共电极，像素电极和公共电极之间形成电场以驱动第一基板101和第二基板102之间的液晶层160中的液晶分子偏转。
例如，图7为本公开至少一实施例提供的又一种显示面板的截面结构示意图，如图7所示，该显示面板100的显示区域为金属氧化物薄膜晶体管。GOA区域的TFT可以为LTPS或金属氧化物薄膜晶体管。
例如，在一些实施例中，第一基板101上的薄膜晶体管的半导体层包含低温多晶硅、金属氧化物半导体。该第一基板101还包括设置在衬底基板1011上的驱动晶体管120和开关晶体管130，该开关晶体管130设置在显示区域AA，该驱动晶体管120设置在环绕显示区域AA的周边区域NA。
例如，如图7所示，该像素单元区域内的开关晶体管130包括依次层叠设置在衬底基板1011上的第一绝缘层1301、遮光层1302、第二绝缘层1303、金属氧化物半导体层1304、栅绝缘层1305、第一栅极(栅线)1306、第三绝缘层1307、第一源极1308、第四绝缘层1309和第一漏极1310，且该第一电极1012通过依次贯穿第四绝缘层1309、第三绝缘层1307和栅绝缘层1305的第五过孔1311与金属氧化物半导体层1304电连接以用作第一漏极1310，该第一源极1308通过依次贯穿第三绝缘层1307和栅绝缘层1305的第七过孔 1312与金属氧化物半导体层1304电连接。该开关晶体管130配置为用于对显示面板的光电介质驱动(例如，液晶分子的偏转)提供开启电压，且该开关晶体管130中的金属氧化物半导体层1304具有透明性可以带来高透过率的显示效果，使得虚拟现实技术的显示效果得到进一步提升。
例如，如图7所示，该驱动晶体管120包括依次层叠设置在衬底基板1011上的第二多晶硅层1201、第一绝缘层1301、第二栅极(栅线)1202、第二绝缘层1303、栅绝缘层1305和源漏电极层1203，源漏电极层1203包括第二源极1203a和第二漏极1203b，且第二源极1203a和第二漏极1203b分别与第二多晶硅层1204电连接，该驱动晶体管120配置为阵列基板用于显示时提供驱动电压，该驱动晶体管120利用第二多晶硅层1204作为半导体层可以提高迁移率并带来窄边框的技术效果。该第二栅极1202与遮光层1302同层设置，即该第二栅极1202与遮光层1302可以采用相同的材料，在同一工艺步骤中形成，且形成在同一层。例如，该第二栅极1202与遮光层1302的材料可以采用铜金属、钼金属等具有遮光性能和导电性能的材料，本公开的实施例对此不作限定。该源漏电极层1203与第一栅极1306同层设置，例如，该源漏电极层1203与第一栅极1306可以采用相同的材料，在同一工艺步骤中形成，且形成在同一层。该源漏电极层1203包括的第二源极1203a和第二漏极1203b分别通过连接孔与第二多晶硅层1204电连接，该连接孔同时穿过栅绝缘层1305、第二绝缘层1303和第一绝缘层1301。
例如，如图7所示，该显示面板100综合了多晶硅材料作为半导体层的驱动晶体管120具有的高迁移率和窄边框的技术效果，以及金属氧化物半导体材料作为半导体层的开关晶体管130具有的高透过率的显示效果，可以使得该显示面板虚拟现实的显示效果得到进一步提升。
例如，在图7中，该第三电极1110包括在平行于衬底基板1011的主表面的方向上相互间隔的金属氧化物条状部分1110a，以及在金属氧化物条状部分1110a之间的金属部分1110b，金属氧化物条状部分1110a和金属部分1110b的材料可以参见上述关于图4的相关描述。
例如，如图7所示，该金属氧化物半导体层1304与第一栅极1306层叠的区域为沟道区域，即椭圆形虚线标注的M区域，其余区域为导体化区域，即椭圆形虚线标注的N区域，沿着x轴的方向，沟道区域(M区域)的长度与导体化区域(N区域)的长度的比值为1/5～1/4，例如，该沟道区域(M区 域)的长度为导体化区域(N区域)的长度的1/5或者1/4等，本公开的实施例对此不作限制，在一个示例中，该沟道区域(M区域)的材料为氧化铟镓锌，其具有半导体特性。该导体化区域(N区域)的材料为被还原的氧化铟镓锌，其具有导体特性。
例如，如图7所示，该第一栅极1306在衬底基板1011上的正投影和遮光层1302在衬底基板1011上的正投影至少部分重叠。在一个示例中，第一栅极1306在衬底基板1011上的正投影位于遮光层1302在衬底基板1011上的正投影之内。在垂直于衬底基板1011主表面的方向上，第一栅极1306到遮光层1302的距离为0微米～5微米。例如，沟道区域(M区域)在衬底基板1011上的正投影与遮光层1302的中部区域在衬底基板1011上的正投影重叠，沟道区域(M区域)在衬底基板1011上的正投影位于遮光层1302在衬底基板1011上的正投影之内。
例如，在一个示例中，该沟道区域(M区域)为双层结构或者三层结构，该沟道区域(M区域)的远离衬底基板1011的层结构的致密度大于该沟道区域(M区域)的靠近衬底基板1011的层结构的致密度。
例如，该导体化区域(N区域)和沟道区域(M区域)的材料不同，沟道区域(M区域)的材料包括氧元素、铟元素、镓元素和锌元素，该导体化区域N的材料包括氧元素、铟元素、镓元素、锌元素以及硼元素或者磷元素等。
例如，在一个示例中，金属氧化物半导体层1304的材料为氧化铟镓锌(IGZO)，该金属氧化物半导体层1304与第一源极1308和第一漏极1310连接的部分是被导体化的，这样可以使得金属氧化物半导体层1304的除了沟道区(M区域)之外的部分与第一源极1308和第一漏极1310的连接更好。
例如，图8为本公开至少一实施例提供的又一种显示面板的截面结构示意图，图8与图7的不同之处在于，在图8中，该第三电极1110包括的金属部分1110b延伸至了第一过孔1015之中，以使得第三电极1110和第二电极1014有更多的交叠区域。在图8中，第二源极1203a包括源极基础部分和源极转接部分，第二漏极1203b包括漏极基础部分和漏极转接部分，源极基础部分和源极基础部分均贯穿栅绝缘层1305、第二绝缘层1303和第一绝缘层1301，并和第一栅极1306同层设置，该源极转接部分和漏极转接部分均贯穿第三绝缘层1307，并和第一源极1308同层设置，将第二源极1063a和第二漏 极1063b均分两步形成，不会增加工艺步骤，且降低了形成连接孔的难度，可以保证第二源极1063a和第二漏极1063b与多晶硅层1061电连接的稳定性。
图8所示显示面板100的其他结构可以参见上述关于图1、图3、图4、图5和图7的相关描述，在此不再赘述。
例如，图9为本公开至少一实施例提供的又一种第二电极和第三电极的透视图，图10为图9中所示结构的截面结构示意图，结合图9和图10，该第三电极1110包括金属氧化物条状部分1110a，以及设置在金属氧化物条状部分1110a的远离衬底基板1011一侧的金属部分1110b，即金属氧化物部分1110a和金属条状部分1110b形成层叠结构，且金属部分1110b在衬底基板1011上的正投影位于金属氧化物条状部分1110a在衬底基板1011上的正投影之内。第二电极1014跨接在相邻的金属氧化物条状部分1110a之间，且第二电极1014在衬底基板1011上的正投影与金属氧化物条状部分1110a在衬底基板1011上的正投影具有交叠部分。
需要说明的是，第三电极1110可以单独由金属氧化物或金属或合金形成。第三电极可以作为公共电极，第二电极1014可以作为像素电极，公共电极与像素电极形成电场驱动液晶分子。此外，第三电极1110可以与第二电极1014位于同层，或者与第二电极1014位于不同层。例如，第三电极1110的金属部分与第二电极1014间隔一层第一绝缘膜，第三电极1110的金属氧化物条状部分与第二电极1014间隔一层第二绝缘膜，第三电极1110的金属部分与金属氧化物条状部分通过贯穿该第一绝缘膜和第二绝缘膜的过孔电性连接。当然，第三电极1110的结构不局限，例如：第三电极1110的显示区为网状结构，或者为狭缝状或板状结构等。
例如，图11为本公开至少一实施例提供的又一种显示面板的截面结构示意图，如图11所示，该显示面板100包括的第一基板101上的沟道层为低温多晶硅(LTPS)，该第一基板101还包括设置在衬底基板1011上的驱动晶体管120和开关晶体管130，开关晶体管130设置在显示区域AA，驱动晶体管120设置在环绕显示区域AA的周边区域NA，该开关晶体管130包括依次层叠设置在衬底基板1011上的遮光层1302、缓冲层1313、第一多晶硅层1314、栅绝缘层1305、第一栅极1306、第三绝缘层1307、基础电极层1315、第四绝缘层1309、第一漏极1310、第五绝缘层1316和第一源极1308，该基础电极层1315包括相对设置的第一基础电极1315a和第二基础电极1315b，且该 第一电极1012通过贯穿第四绝缘层1309的第五过孔1311与第一基础电极1315a电连接以用作第一漏极1310，第一基础电极1315a通过贯穿第三绝缘层1307和栅绝缘层1305的第六过孔1317与第一多晶硅层1314电连接，该第一源极1308通过依次贯穿第五绝缘层1316和第四绝缘层1309的第七过孔1312与第二基础电极1315b电连接，该第二基础电极1315b通过贯穿第三绝缘层1307和栅绝缘层1305的第八过孔1318与第一多晶硅层1314电连接，该驱动晶体管120包括依次层叠设置在衬底基板1011上的缓冲层1313、第二多晶硅层1204、栅绝缘层1305、第二栅极1202、第三绝缘层1307和源漏电极层1203，该源漏电极层1203包括第二源极1203a和第二漏极1203b，且第二源极1203a和第二漏极1203b均与第二多晶硅层1204电连接；该第一栅极1306和第二栅极1202同层设置；该源漏电极层1203与基础电极层1315同层设置，该低温多晶硅(LTPS)的显示面板利用第一多晶硅层1314和第二多晶硅层1204作为半导体层可以提高迁移率并带来窄边框的技术效果。
例如，如图11所示，在平行于衬底基板1011的主表面的方向上，第一电极1012和第二电极1014的接触部分位于第五过孔1311与第七过孔1312之间，且第一电极1012和第二电极1014的接触部分在衬底基板1011上的正投影与第一栅极1306在衬底基板1011上的正投影至少部分交叠。
例如，如图11所示，在平行于衬底基板1011的主表面的方向上，第一电极1012和第二电极1014的接触部分的靠近第五过孔1311的一侧与第六过孔1317之间的距离等于第一电极1012的未覆盖第一栅极1306的长度。
例如，如图11所示，在平行于衬底基板1011的主表面的方向上，遮光层1302的两端的端点位于第七过孔1312与第五过孔1311之间，第一电极1012和第二电极1014的接触部分位于第七过孔1312与遮光层1302的靠近第五过孔1311的端点之间。
例如，在图11中，第一栅极1306包括在平行于衬底基板1011的主表面的方向上两个相互间隔的部分，即形成了双栅结构。
例如，图11所示显示面板100的其他结构可以参见常规的低温多晶硅(LTPS)显示面板的相关结构，本公开的实施例对此不作限定。
例如，如图7、图8和图11所示，该像素单元1025还包括薄膜晶体管，该薄膜晶体管包括开关晶体管130，该薄膜晶体管130包括半导体层1314、间隔设置的第一源极1308和第一漏极1310；该第一源极1308和第一漏极1310 与半导体层1314连接，该第二电极1014为像素单元1025的像素电极；该第一电极1012为第一漏极1310或者为用作连接第一漏极1310与像素电极的转接电极。
例如，如图11所示，该第一漏极1310的材料为透明的导电氧化物。例如，该第一漏极1310的材料包括透明金属氧化物导电材料，例如，氧化铟锡，第二电极1014延伸至第一过孔1015的靠近衬底基板1011的一侧，该第一漏极1310与第二电极1014进行面接触，以使得第一漏极1310与第二电极1014的连接更加稳定，且不会影响显示面板100开口率的大小。
例如，在一个示例中，该第一过孔1015的靠近第一层间绝缘层1013的上表面的开口宽度d满足：d≤(K1*M/PPI)*(1-AR*1/(1-D min*PPI/M))，且M为固定值25400μm；PPI为像素密度，该像素密度是每英寸所具有的像素单元的数量，1英寸＝25400μm；单个像素单元的宽度P＝M/PPI＝25400μm/PPI，K1为单个像素的长宽比值，AR为开口率，PPI为像素密度，D min为工艺曝光极限值。
例如，在一个示例中，该第一过孔1015的靠近第一层间绝缘层1013的上表面的开口宽度d满足：d≈(K1*M/PPI)*(1-AR)，且PPI为像素密度，K1为单个像素的长宽比值，AR为开口率。且在如下的推导过程中，W data为数据线的宽度，W gate为栅线的宽度，单个像素的宽度P＝M/PPI，D min为工艺曝光极限值，近似等于金属线的宽度，例如，等于栅线的宽度。
在一个示例中，上述公式d≈(K1*M/PPI)*(1-AR)由如下过程推导出：M＝25400，AR(开口率)＝(P-W data)*(K1*P-d)/(P*K1*P)，或者AR(开口率)＝(P-W gate)*(K1*P-d)/(P*K1*P)；
以AR与W gate的关系为例，
AR(开口率)＝(P-W gate)*(K1*P-d)/(P*K1*P)公式变形为如下方案：
AR＝((1-W gate)/P)*(1-d/K1*P)＝(1-(W gate*PPI)/M)*(1-(d*PPI)/K1*M)
D min≤W gate，D min≤W data；
实际应用中，D min可以是栅线或数据线的实际测量值中的最小数值。
推导出：d≤(K1*M/PPI)*(1-AR*1/(1-D min*PPI/M))，
0.4≤AR≤0.8，M＝25400，PPI＝1100-2500,K1＝1.0-3,D min＝1.3-2.5μm，
D min≤W gate≤d≤(K1*M/PPI)*(1-P/(1-D min*PPI/M))，
即：d≈(K1*M/PPI)*(1-P)，第一过孔1015的远离衬底基板1011的一 侧的开口宽度d与K1成正比，与像素密度PPI成反比，与透过率成反比。
工艺曝光极限值Dmin的范围为1.3μm-2.5μm，根据公式d≈(K1*M/PPI)*(1-AR)得出的范围为d＝2.0μm-10μm。
例如，在另一个示例中，0.4≤AR≤0.7，M＝25400，PPI＝1130-1500,K1＝1.0～2.5，D min＝1.3～1.8，d＝3.0μm～6.1μm。
例如，0.5≤AR≤0.65，M＝25400，PPI＝1500～2000,K1＝1.0～2.5，D min＝1.3～1.5，d＝4.5μm～5.2μm。
进一步的，第一过孔1015的设计满足(d1-d2)-tanβ1*d3的绝对值范围在0到1.5之间，一种实施方式为：d1-d2＝tanβ1*d3，其中，d1为第一过孔1015的远离衬底基板1011的一侧的开口宽度，所述开口宽度为一个位置测量的直径或不同位置开口宽度的平均值，d2为第一过孔1015的靠近衬底基板1011的一侧的开口宽度，所述开口宽度为一个位置的开口宽度或不同位置开口宽度的平均值，d3为第一层间绝缘层1013的厚度或多个位置点的平均厚度，β1为第一过孔1015的侧表面与衬底基板1011的水平面之间的夹角。
所述第一过孔1015的远离衬底基板1011的一侧的开口宽度或靠近衬底基板1011的一侧的开口宽度可以是第一支撑结构1016的开口宽度，也可以是第一层间绝缘层1013上开口的宽度。
靠近衬底基板1011的一侧的开口宽度可以是第一层间绝缘层1013上开口的宽度，也可以是第一支撑结构1016与第一层间绝缘层1013接触位置的宽度或与第二层间绝缘层1019接触位置的宽度。
所述的宽度可以是一个位置测量的宽度或多个位置测量的平均宽度。
例如，在一个示例中，d1-d2大约在2.0μm左右，该d1-d2小于或者等于第一支撑结构1016的突出于第一过孔1015之外的部分的厚度。
例如，图12为本公开至少一实施例提供的一种第一支撑结构的扫描电镜图，如图12所示，在垂直于衬底基板1011主表面的方向上，该第一过孔1015的靠近第一源极1308的表面与水平面形成的夹角为α，该第一过孔1015的靠近第一漏极1310的表面与水平面形成的夹角为β，在一个示例中α≥β，在另一个示例中α<β。
例如，在一个示例中，α>β，且α-β的差值的范围为0.5-3°。
例如，在一个示例中，D min≤W gate≤d，d＝2.0μm～10μm，D min＝1.5μm～2μm。
例如，在一个示例中，该第一过孔1015的设计满足d1-d2＝tanβ1*d3，d1-d2＝2.0μm，该d1-d2小于或者等于第一支撑结构1016的突出于第一过孔1015之外的部分的厚度，d1为第一过孔1015的远离衬底基板1011的一侧的开口宽度，d2为第一过孔1015的靠近衬底基板1011的一侧的开口宽度，d3为第一层间绝缘1013的厚度，β1为第一过孔1015的侧壁与水平面的夹角。
例如，在一个示例中，α>β，且α-β的差值的范围为0.5-3°，为了使得第一电极1012和第二电极1014的连接更加稳定，第一电极1012延伸至第一栅极1306的正上方，即第一电极1012在衬底基板1011上的正投影和第一栅极1306在衬底基板1011上的正投影至少部分交叠。
例如，如图12所示，第一支撑结构1016的右侧延伸至第一栅极1306之外的宽度为w1，第一层间绝缘层1013的厚度为H1，tanβ＝H1/w1。
经过测试，得到以下结论：第一支撑结构1016的右侧延伸至第一栅极1306之外的最小宽度w1 min为0.15微米，H1的大小为2.41微米,β的大小为84°。w1 max为第一支撑结构1016的右侧延伸至第一栅极1306之外的最大宽度，该w1 max为2.0微米，H1的大小为2.41微米，β的大小为50°。
例如，图13为本公开至少一实施例提供的一种第一基板的透视结构示意图，如图13所示，金属氧化物半导体层1304通过第五过孔1311与第一电极1012电连接，金属氧化物半导体层1304通过第七过孔1312与第一源极1308电连接，遮光层1302的延伸方向和金属氧化物半导体层1304的与第一电极1012电连接的部分的延伸方向垂直的方向平行，且遮光层1302在衬底基板1011上的正投影和第一栅极1306在衬底基板1011上的正投影交叠，图13中虚线圆圈所示部分为第一支撑结构1016。结合图11和图13所示，第一电极1012和第二电极1014的接触部分在衬底基板1011上的正投影位于第一栅极1306在衬底基板1011上的正投影之内。
例如，如图11所示，在平行于衬底基板1011主表面的方向上，第一电极1012和第二电极1014的接触部分的靠近第五过孔1311的一侧与第五过孔1311之间的距离等于第一电极1012的未覆盖第一栅极1306的长度。
例如，如图11所示，在平行于衬底基板1011主表面的方向上，第一电极1012和第二电极1014的第一接触部分E位于第五过孔1311与第七过孔1312之间，且该第一接触部分E在衬底基板1011上的正投影与第一栅极1306在衬底基板1011上的正投影至少部分交叠。在平行于衬底基板1011的主表 面的方向上，遮光层1302的两端的端点位于第五过孔1311与第七过孔1312之间，该第一接触部分E位于第五过孔1311与遮光层1302的靠近第四过孔1312的端点之间。
例如，如图11所示，接触部分在第一栅极1306上的正投影到第一栅极1306最左端的距离为第一栅极1306总长度的1/5～1/3。接触部分在第一栅极1306上的正投影到第七过孔1312之间的距离等于第一电极1012未覆盖第一栅极1306的长度。
例如，如图11所示，遮光层1302左侧端的端点位于第一栅极1306对应的左侧端点的左侧，遮光层1302右侧端的端点位于第一栅极1306对应的右侧端点的右侧，即第一栅极1306在衬底基板1011上的正投影位于遮光层1302在衬底基板1011上的正投影之内。
例如，第一接触部分在衬底基板1011上的正投影位于遮光层1302左侧端的端点在衬底基板1011上的正投影和第五过孔1311在衬底基板1011上的正投影之间。
例如，遮光层1302左侧端的端点在衬底基板1011上的正投影到第一栅极1306最左端的距离为遮光层1302总长度的1/5～1/3。
例如，如图11所示，第五过孔1311和第七过孔1312之间的距离等于遮光层1302右侧端的端点到第一栅极1306右侧端的端点之间的距离。
例如，在一个示例中，第五过孔1311和第七过孔1312之间的距离/像素的宽度＝1.8/6.2＝0.29。
例如，在另一个示例中，第五过孔1311和第七过孔1312之间的距离/像素的宽度＝3.3/13.7＝0.24。
例如，在一个示例中，第一电极1012和金属氧化物半导体层1304的搭接面积满足：S≥(S1*R1)/R max，其中，S1和R1分别为第五过孔1311的面积和第五过孔1311的接触电阻，R max是满足特性需求的最大接触电阻，R max＝2000欧姆，R1＝100-200欧姆，则推导出第一电极1012和金属氧化物半导体层1304的搭接面积S与第五过孔1311的面积的比值满足：S/S1≥1/20～1/10。
需要说明的是，从电阻方面考虑，期望是第一电极1012和金属氧化物半导体层1304整面搭接，且接触电阻小，有利于开关晶体管130的导通特性。半孔搭接是工艺偏差原因，不要超过该方向第五过孔1311与金属氧化物半导 体层1304的覆盖值。半孔搭接的示例如果满足电阻要求，也可以适用。
例如，在一个示例中，第一电极1012与金属氧化物半导体层1304的侧边搭接，第一电极1012未覆盖金属氧化物半导体层1304的长度占金属氧化物半导体层1304的长度的1/4-1/30。例如，第一电极1012未覆盖金属氧化物半导体层1304的长度为0.1微米-0.3微米，其占金属氧化物半导体层1304的长度的1/20-1/9。
例如，如图11所示，在平行于衬底基板1011主表面的方向上，该第一电极1012和第二电极1014的接触部分位于第五过孔1311与第七过孔1312之间，且该接触部分在衬底基板1011上的正投影与第一栅极1306在衬底基板1101上的正投影至少部分交叠。
例如，如图11所示，在一个示例中，第一层间绝缘层1013和第一支撑结构1016的材料相同，均为透光材料。由于第一支撑结构1016有一部分需要占用开口区，因此第一支撑结构1016通常采用透明材料形成，从而使得第一支撑结构1016占用开口区的部分不影响开口率。
例如，图14为本公开至少一实施例提供的再一种第一基板的透视结构示意图，如图14所示，第一支撑结构1016的材料为遮光材料，该第一支撑结构1016的延伸方向平行于栅线的延伸方向，栅线和栅极1306的延伸方向相同，即该第一支撑结构1016的延伸方向平行于栅极1306的延伸方向。该第一支撑结构1016可以遮挡光线从而可以减少相邻像素间的串色，还可以起到横向黑矩阵的作用，这样可以在第二基板102上不用制作横向的黑矩阵，只制作纵向的黑矩阵，因为本来横向和纵向的黑矩阵就是分开制作的，从而减少了第二基板102上的工艺步骤。
本申请上述各实施例中，如图13所示，栅线为具有恒定线宽的直线且沿横向延伸，栅线位于相邻两行像素单元之间，同一列像素单元中具有相邻两个像素区域。假设上一行的像素单元为第一像素单元，下一行的像素单元为第二像素单元。金属氧化物半导体层1304为走线，该走线从所述第一像素单元所在的区域横跨所述栅线延伸到第二像素单元。所述栅线与金属氧化物半导体层的交叠区域为薄膜晶体管的栅极。所述走线从第一像素单元的数据线区域延伸到栅线并延伸到第二像素单元中的第五过孔对应的区域。
数据线通过其下方的过孔与所述金属氧化物半导体层直接接触，数据线的其中一部分为TFT的源极。栅线的一部分为TFT的栅极，该实施例可最大 限度提高像素开口率。
本公开至少一实施例还提供一种显示面板的制备方法，例如，图15为本公开至少一实施例提供的一种显示面板的制备方法的过程图，如图15所示，该制备方法包括如下步骤：
步骤S11：提供衬底基板。
例如，该衬底基板可以为玻璃基板、柔性基板、硅基板等，本公开的实施例对此不作限定。
步骤S12：在衬底基板上形成第一电极。
例如，该第一电极可以为薄膜晶体管的源漏电极，该第一电极的材料可以为透明的金属氧化物，例如可以为氧化铟锡等。
步骤S13：在第一电极上形成第一层间绝缘层。
例如，该第一层间绝缘层的材料可以为透光的无机材料。
步骤S14：对第一层间绝缘层进行构图工艺形成第一过孔。
例如，可以采用常规构图工艺：涂覆光刻胶、采用掩膜板进行遮挡对光刻胶进行紫外线照射以形成光刻胶图案，采用光刻胶图案作为掩膜对第一层间绝缘层进行刻蚀以形成第一过孔。
步骤S15：在第一过孔上形成第二电极，且第二电极和第一电极电连接。
例如，该第二电极可以为像素电极。
步骤S16：在第一过孔对应的区域且在第二电极的远离衬底基板的一侧形成第一支撑结构。
例如，该第一支撑结构将第一过孔填充完全且突出于第一过孔之外，以避免第一过孔导致的漏光的问题。
步骤S17：提供第二基板，在第二基板上形成第二支撑结构，第一支撑结构的靠近第二基板的表面和第二支撑结构的靠近第一基板的表面接触，以对第二基板进行支撑并在第一基板和第二基板之间形成间隙。
例如，第一支撑结构的靠近第二基板的表面和第二支撑结构的靠近第一基板的表面接触，以对第二基板进行支撑，并在第一基板和第二基板之间形成间隙，可以避免第一基板和第二基板对合的过程中对第一基板或者第二基板对应的显示区域造成划伤，进而减小边缘漏光的风险。
例如，该第一支撑结构和第二支撑结构的结构可以参见上述中的相关描述，在此不再赘述。
例如，图16为本公开至少一实施例提供的再一种显示面板的制备方法的过程图，如图16所示，该制备方法包括：
步骤S21：提供衬底基板。
步骤S22：在衬底基板上形成第一电极。
步骤S23：在第一电极上形成第一层间绝缘层。
步骤S24：对第一层间绝缘层进行构图工艺形成第一过孔，且在第一层间绝缘层中形成贯穿第一层间绝缘层的第二过孔。
步骤S25：在第一过孔上形成第二电极，且第二电极和第一电极电连接。
步骤S26：在第二电极的远离衬底基板的一侧形成第一绝缘层。
步骤S27：在第一绝缘层的远离衬底基板的一侧形成第三电极。
例如，该第三电极包括在平行于衬底基板的主表面的方向上，相互间隔的金属氧化物条状部分，以及在金属氧化物条状部分之间的金属部分，或者，第三电极包括金属层和包覆金属层的侧表面和远离衬底基板的表面的金属氧化物，且第三电极包括在平行于衬底基板的主表面的方向上相互间隔的多个部分。
步骤S28：在第一过孔对应的区域且在第二电极的远离衬底基板的一侧形成第一支撑结构，并在第二过孔对应的区域且在第二电极的远离衬底基板的一侧形成第三支撑结构。
例如，该第三支撑结构在衬底基板上的正投影和第二支撑结构在衬底基板上的正投影不具有交叠部分。
步骤S29：提供第二基板，在第二基板上形成第二支撑结构，第一支撑结构的靠近第二基板的表面和第二支撑结构的靠近第一基板的表面接触，以对第二基板进行支撑并在第一基板和第二基板之间形成间隙。
例如，该第一支撑结构的靠近第二基板的表面和第二支撑结构的靠近第一基板的表面接触，以对第二基板进行支撑，并在第一基板和第二基板之间形成间隙，可以避免第一基板和第二基板对合的过程中对第一基板或者第二基板对应的显示区域造成划伤，进而减小边缘漏光的风险。
例如，该第一支撑结构和第二支撑结构的结构可以参见上述中的相关描述，在此不再赘述。
例如，图17为本公开至少一实施例提供的又一种显示面板的制备方法的过程图，如图17所示，该制备方法包括：
步骤S31：提供衬底基板。
步骤S32：在衬底基板上形成第一电极。
步骤S33：在第一电极上形成第一层间绝缘层。
步骤S34：对第一层间绝缘层进行构图工艺形成第一过孔，且在第一层间绝缘层中形成贯穿第一层间绝缘层的第二过孔。
步骤S35：在第一过孔上形成第二电极，且第二电极和第一电极电连接。
步骤S36：在第一过孔对应的区域且在第二电极的远离衬底基板的一侧形成第一支撑结构，并在第二过孔对应的区域且在第二电极的远离衬底基板的一侧形成第三支撑结构。
例如，该第三支撑结构在衬底基板上的正投影和第二支撑结构在衬底基板上的正投影不具有交叠部分。即该第二支撑结构的数量小于第一支撑结构和第三支撑结构的数量之和。
例如，该第三支撑结构沿着垂直于衬底基板的主表面的方向延伸至第二过孔之外，即在平行于z轴的方向上延伸至第二过孔之外，且该第三支撑结构在平行于衬底基板的主表面的方向上的最大尺寸和第二过孔在平行于衬底基板的主表面的方向上的最大尺寸相等。该第三支撑结构至少可以将第二过孔进行填平，以减小第二过孔发生漏光的风险。
步骤S37：在第一支撑结构和第三支撑结构的远离衬底基板的一侧形成第一绝缘层。
步骤S38：在第一绝缘层的远离衬底基板的一侧形成第三电极。
例如，该第三电极包括在平行于衬底基板的主表面的方向上相互间隔的金属氧化物条状部分，以及在金属氧化物条状部分之间的金属部分，或者，第三电极包括金属层和包覆金属层的侧表面和远离衬底基板的表面的金属氧化物条状部分，且第三电极包括在平行于衬底基板的主表面的方向上相互间隔的多个部分。
步骤S39：提供第二基板，在第二基板上形成第二支撑结构，第一支撑结构的靠近第二基板的表面和第二支撑结构的靠近第一基板的表面接触，以对第二基板进行支撑并在第一基板和第二基板之间形成间隙。
即图17和图16的区别在于：在图17中，先形成第一支撑结构和第三支撑结构，再形成第一绝缘层，然后形成第三电极；在图16中，先形成第一绝缘层，再形成第三电极，然后形成第一支撑结构和第三支撑结构。
例如，第三电极等结构可以参见上述中的相关描述，在此不再赘述。
例如，图18为本公开至少一实施例提供的又一种显示面板的制备方法的过程图，如图18所示，该制备方法包括：
步骤S41：提供衬底基板。
步骤S42：在衬底基板上形成第一电极。
步骤S43：在第一电极上形成第一层间绝缘层。
步骤S44：对第一层间绝缘层进行构图工艺形成第一过孔，且在第一层间绝缘层中形成贯穿第一层间绝缘层的第二过孔。
步骤S45：在第一过孔上形成第二电极，且第二电极和第一电极电连接。
步骤S46：在第一过孔对应的区域且在第二电极的远离衬底基板的一侧形成第一支撑结构，在第二过孔对应的区域且在第二电极的远离衬底基板的一侧形成第三支撑结构，且在形成第一支撑结构和第三支撑结构的过程中形成第一绝缘层。
例如，该第三支撑结构在衬底基板上的正投影和第二支撑结构在衬底基板上的正投影不具有交叠部分。
例如，第一支撑结构、第三支撑结构和第一绝缘层同层设置且由相同的材料形成。
步骤S47：在第一绝缘层的远离衬底基板的一侧形成第三电极。
例如，该第三电极包括在平行于衬底基板的主表面的方向上相互间隔的金属氧化物条状部分，以及在金属氧化物条状部分之间的金属部分，或者，第三电极包括金属层和包覆金属层的侧表面和远离衬底基板的表面的金属氧化物，且第三电极包括在平行于衬底基板的主表面的方向上相互间隔的多个部分。
例如，该第一绝缘层夹设在第二电极和第三电极之间，以使得第二电极和第三电极可以在第一过孔或者第二过孔的靠近衬底基板的表面处进行对应，以使得第二电极在衬底基板上的正投影和第三电极在衬底基板上的正投影的交叠面积。
步骤S48：提供第二基板，在第二基板上形成第二支撑结构，第一支撑结构的靠近第二基板的表面和第二支撑结构的靠近第一基板的表面接触，以对第二基板进行支撑并在第一基板和第二基板之间形成间隙。
本公开至少一实施例提供的显示面板，具有以下至少一项有益技术 效果：
(1)本公开至少一实施例提供的显示面板，通过使得第一支撑结构的至少部分位于第一过孔内，且使得第一过孔在衬底基板上的正投影和栅线在衬底基板上的正投影至少部分交叠，以提高显示面板的分辨率和开口率。
(2)本公开至少一实施例提供的显示面板，通过在第一基板上的平坦层包括的第一过孔对应的区域设置第一支撑结构，在第二基板上设置第二支撑结构，第一支撑结构的靠近第二基板的表面和第二支撑结构的靠近第一基板的表面接触，以对第二基板进行支撑并在第一基板和第二基板之间形成间隙，从而可以减小第一基板和第二基板对合过程中对第一基板或者第二基板对应的显示区域造成划伤，进而减小边缘漏光的风险。
(3)本公开至少一实施例提供的显示面板，由于第一支撑结构设置在平坦层包括的第一过孔对应的区域，避免了第一过孔导致的漏光的问题。
(4)本公开至少一实施例提供的显示面板，综合了多晶硅材料作为半导体层的驱动晶体管具有的高迁移率和窄边框的技术效果，以及金属氧化物半导体材料作为半导体层的开关晶体管具有的高透过率的显示效果，使得该显示面板虚拟现实的显示效果得到进一步提升。
(5)本公开至少一实施例提供的显示面板，利用第一多晶硅层和第二多晶硅层作为半导体层可以提高迁移率并带来窄边框的技术效果。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (34)

  1. 一种显示面板,包括：
    相互对合的第一基板和第二基板，其中，所述第一基板包括衬底基板，以及依次设置在所述衬底基板上的栅线、第一电极、第一层间绝缘层和第二电极；
    所述第一层间绝缘层中具有贯穿所述第一层间绝缘层的第一过孔，所述第二电极通过所述第一过孔与所述第一电极电连接，在所述第一过孔对应的区域且在所述第二电极的远离所述衬底基板的一侧设置有第一支撑结构；
    所述第一支撑结构的至少部分位于所述第一过孔内；且所述第一过孔在所述衬底基板上的正投影和所述栅线在所述衬底基板上的正投影至少部分交叠。
  2. 根据权利要求1所述的显示面板，其中，所述第一基板为阵列基板，所述阵列基板包括位于所述衬底基板上的横纵交叉设置的所述栅线和数据线，以及多个像素单元；
    所述像素单元包括：所述第一电极、所述第二电极和所述第一层间绝缘层；
    所述第二电极与所述第一层间绝缘层的远离所述衬底基板的表面接触，且所述第二电极由所述第一层间绝缘层的上表面延伸到所述第一过孔的侧壁和下部开口区域并与位于所述下部开口区域的所述第一电极连接。
  3. 根据权利要求1或2所述的显示面板，其中，所述第一层间绝缘层至少包含平坦化层，所述第一过孔贯穿所述平坦化层。
  4. 根据权利要求1～3中任一项所述的显示面板，其中，所述第一支撑结构的靠近所述第二基板的表面为平面或者向所述衬底基板的一侧凹陷的凹面。
  5. 根据权利要求4所述的显示面板，其中，所述第一支撑结构在所述第一过孔内向下延伸至所述第一过孔的下部开口区域。
  6. 根据权利要求2或3所述的显示面板，其中，所述第一支撑结构在所述第一过孔内向上延伸到所述第一过孔的上部开口区域且所述第一支撑结构的顶部高于所述第一层间绝缘层的上表面。
  7. 根据权利要求6所述的显示面板，其中，所述像素单元还包括位于所 述第一层间绝缘层上表面上方的第三电极，所述第三电极与所述第一层间绝缘层的上表面上的第二电极之间设置有第二层间绝缘层；所述第二层间绝缘层上包含与所述第一层间绝缘层相贯通的开口，所述第一支撑结构朝向所述第二基板延伸并具有高出所述第二层间绝缘层的突出结构。
  8. 根据权利要求7所述的显示面板，其中，所述第三电极包括位于所述第二层间绝缘层上表面相互间隔分布的金属氧化物条状部分，以及在所述金属氧化物条状部分之间分布的金属部分。
  9. 根据权利要求7所述的显示面板，其中，所述第三电极包括金属部分和包覆所述金属部分的侧表面和上表面的金属氧化物条状部分，且在平行于所述衬底基板的主表面的方向上，所述第三电极包括相互间隔的多个部分。
  10. 根据权利要求7所述的显示面板，其中，所述第一支撑结构的超过所述第一层间绝缘层的上表面和所述第二层间绝缘层的上表面的部分在垂直于所述衬底基板的主表面和垂直于所述栅线延伸的方向上的截面形状为矩形或者梯形或者上表面向所述衬底基板的一侧凹陷的类梯形。
  11. 根据权利要求10所述的显示面板，其中，所述第一支撑结构超过所述第二层间绝缘层的上表面朝向所述第二基板延伸，且沿着所述第二层间绝缘层的上表面远离所述第一过孔延伸。
  12. 根据权利要求6～11中任一项所述的显示面板，其中，所述像素单元还包括薄膜晶体管，所述薄膜晶体管包括半导体层、间隔设置的源极和漏极，所述源极和所述漏极与所述半导体层连接；所述第二电极为所述像素单元的像素电极；所述第一电极为所述漏极或者为用作连接所述漏极与所述像素电极的转接电极。
  13. 根据权利要求12所述的显示面板，其中，所述第一层间绝缘层至少包含有机平坦层，所述第二层间绝缘层至少包含无机绝缘层，所述第三电极为所述像素单元的公共电极。
  14. 根据权利要求12或13所述的显示面板，其中，所述漏极的材料包括透明金属氧化物导电材料。
  15. 根据权利要求2所述的显示面板，其中，所述第一过孔的靠近所述第一层间绝缘层的上表面的开口宽度d满足：d≤(K1*M/PPI)*(1-AR*1/(1-D min*PPI/M))，且M为固定值25400μm；PPI为像素密度，所述像素密度是每英寸所具有的所述像素单元的数量，1英寸＝25400μm；单个所 述像素单元的宽度P＝M/PPI＝25400μm/PPI，K1为单个像素的长宽比值，AR为开口率，PPI为像素密度，D min为工艺曝光极限值。
  16. 根据权利要求15所述的显示面板，其中，所述第一过孔的靠近第一层间绝缘层的上表面的开口宽度d满足：d≈(K1*M/PPI)*(1-AR)。
  17. 根据权利要求15所述的显示面板，其中，还包括薄膜晶体管，所述薄膜晶体管包括间隔设置的源极和漏极，在垂直于所述衬底基板的主表面的方向上，所述第一过孔的靠近所述源极的边缘与所述衬底基板的主表面所在的平面形成的夹角为α，所述第一过孔的靠近所述漏极的边缘与所述衬底基板的主表面所在的平面形成的夹角为β，且α≥β。
  18. 根据权利要求17所述的显示面板，其中，α>β，且α-β的差值的范围为0.5-3°。
  19. 根据权利要求15所述的显示面板，其中，D min≤W gate≤d，d＝2.0μm～10μm，D min＝1.5μm～2μm。
  20. 根据权利要求17所述的显示面板，其中，所述第一过孔的设计满足(d1-d2)-tanβ1*d3的绝对值范围在0到1.5之间，d1为所述第一过孔的远离所述衬底基板的一侧的开口宽度，d2为所述第一过孔的靠近所述衬底基板的一侧的开口宽度，d3为所述第一层间绝缘的厚度，β1为所述第一过孔的侧壁与衬底基板的水平面之间的夹角。
  21. 根据权利要求1～20中任一项所述的显示面板，其中，
    所述第一基板还包括设置在所述衬底基板上的开关晶体管；
    所述开关晶体管设置在显示区域；
    所述开关晶体管包括依次层叠设置在所述衬底基板上的第一绝缘层、遮光层、第二绝缘层、金属氧化物半导体层、栅绝缘层、第一栅极、第三绝缘层、第一源极、第四绝缘层和第一漏极，且所述第一电极通过依次贯穿所述第四绝缘层、所述第三绝缘层和所述栅绝缘层的第三过孔与所述金属氧化物半导体层电连接以用作所述第一漏极，所述第一源极通过依次贯穿所述第三绝缘层和所述栅绝缘层的第四过孔与所述金属氧化物半导体层电连接。
  22. 根据权利要求1～20中任一项所述的显示面板，其中，
    所述第一基板还包括设置在所述衬底基板上的开关晶体管；
    所述开关晶体管设置在显示区域；
    所述开关晶体管包括依次层叠设置在所述衬底基板上的遮光层、缓冲层、 第一多晶硅层、栅绝缘层、第一栅极、第三绝缘层、基础电极层、第四绝缘层、第一漏极、第五绝缘层和第一源极，所述基础电极层包括相对设置的第一基础电极和第二基础电极，且所述第一电极通过贯穿所述第四绝缘层的第五过孔与所述第一基础电极电连接以用作所述第一漏极，所述第一基础电极通过贯穿所述第三绝缘层和所述栅绝缘层的第六过孔与所述第一多晶硅层电连接；所述第一源极通过依次贯穿所述第五绝缘层和所述第四绝缘层的第七过孔与所述第二基础电极电连接，所述第二基础电极通过贯穿所述第三绝缘层和所述栅绝缘层的第八过孔与所述第一多晶硅层电连接。
  23. 根据权利要求22所述的显示面板，其中，在平行于所述衬底基板的主表面的方向上，所述第一电极和所述第二电极的接触部分位于所述第五过孔与所述第七过孔之间，且所述第一电极和所述第二电极的所述接触部分在所述衬底基板上的正投影与所述第一栅极在所述衬底基板上的正投影至少部分交叠。
  24. 根据权利要求23所述的显示面板，其中，在平行于所述衬底基板的主表面的方向上，所述第一电极和所述第二电极的接触部分的靠近所述第五过孔的一侧与所述第六过孔之间的距离等于所述第一电极的未覆盖所述第一栅极的长度。
  25. 根据权利要求23所述的显示面板，其中，在平行于所述衬底基板的主表面的方向上，所述遮光层的两端的端点位于所述第七过孔与所述第五过孔之间，所述第一电极和所述第二电极的接触部分位于所述第七过孔与所述遮光层的靠近所述第五过孔的端点之间。
  26. 根据权利要求1～25中任一项所述的显示面板，其中，在所述第二基板上设置有第二支撑结构，所述第一支撑结构的靠近所述第二基板的表面和所述第二支撑结构的靠近所述第一基板的表面接触或保持设定间距。
  27. 根据权利要求26所述的显示面板，其中，所述第二支撑结构在所述衬底基板上的正投影和所述第一支撑结构在所述衬底基板上的正投影至少部分交叠。
  28. 根据权利要求26或27所述的显示面板，其中，所述第二支撑结构与所述第一支撑结构的接触面的面积小于所述第二支撑结构或所述第一支撑结构的靠近所述衬底基板的区域的横截面的面积。
  29. 根据权利要求26～28中任一项所述的显示面板，其中，所述第一层 间绝缘层中具有贯穿所述第一层间绝缘层的第二过孔，所述第二过孔中设置有第三支撑结构，所述第三支撑结构在所述衬底基板上的正投影和所述第二支撑结构在所述衬底基板上的正投影不具有交叠部分。
  30. 根据权利要求29所述的显示面板，其中，所述第三支撑结构背离所述衬底基板延伸至所述第二过孔之外，且所述第三支撑结构填充所述第二过孔使得位于所述第二过孔内的形状与所述第二过孔的形状相适应。
  31. 根据权利要求30所述的显示面板，其中，所述第三支撑结构延伸到所述第二过孔之外的部分的纵截面的形状为梯形。
  32. 根据权利要求26～31中任一项所述的显示面板，其中，所述第二支撑结构的屈服强度大于所述第一基板和所述第二基板对合时的对合压力与单个所述第二支撑结构的面积和所述第二支撑结构的个数的乘积。
  33. 根据权利要求3所述的显示面板，其中，所述平坦化层和所述第一支撑结构的材料均为透光材料。
  34. 根据权利要求1～33中任一项所述的显示面板，其中，所述第一支撑结构的材料为遮光材料，所述第一支撑结构的延伸方向平行于所述栅线的延伸方向。
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