WO2023133980A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2023133980A1
WO2023133980A1 PCT/CN2022/078651 CN2022078651W WO2023133980A1 WO 2023133980 A1 WO2023133980 A1 WO 2023133980A1 CN 2022078651 W CN2022078651 W CN 2022078651W WO 2023133980 A1 WO2023133980 A1 WO 2023133980A1
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layer
groove
doped region
semiconductor structure
manufacturing
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PCT/CN2022/078651
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English (en)
French (fr)
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沈宇桐
汤继峰
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长鑫存储技术有限公司
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Priority to US17/661,340 priority Critical patent/US20230231050A1/en
Publication of WO2023133980A1 publication Critical patent/WO2023133980A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2015—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate the substrate being of crystalline semiconductor material, e.g. lattice adaptation, heteroepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and method of making the same.
  • a doping structure can be embedded in the base of the semiconductor structure, thereby improving the device performance of the semiconductor structure.
  • the disclosure provides a semiconductor structure and a manufacturing method thereof.
  • a first aspect of the present disclosure provides a semiconductor structure comprising:
  • a substrate comprising a doped region
  • a graded layer fills the groove, and the doping concentration of the graded layer changes gradually upward from the bottom of the groove.
  • the graded layer includes a multi-layer structure layer and a protection layer stacked in sequence, and adjacent structure layers have different doping concentrations.
  • the doping concentration of the multilayer structure layer first increases and then decreases upward from the bottom of the groove.
  • the multilayer structure layer is a multilayer silicon germanium layer
  • the protective layer is a silicon layer
  • the thickness of each structural layer is 2-10 nm.
  • the semiconductor structure further includes a conductive layer and a metal layer
  • the protective layer includes a through hole
  • the conductive layer fills the through hole
  • the metal layer is disposed on the conductive layer, And electrically connected with the conductive layer.
  • the material of the conductive layer includes cobalt silicide or nickel silicide
  • the material of the metal layer includes tungsten, copper, gold or aluminum.
  • the doped region includes a heavily doped region and a lightly doped region, both of the heavily doped region and the lightly doped region are located at the periphery of the groove, and the heavily doped region The doped region is closer to the bottom of the groove.
  • a second aspect of the present disclosure provides a transistor comprising the semiconductor structure as described above, the semiconductor structure being located in a source region and a drain region of the transistor.
  • a third aspect of the present disclosure provides a method for fabricating a semiconductor structure, the method for fabricating the semiconductor structure comprising:
  • a graded layer is formed, the graded layer fills the groove, and the doping concentration of the graded layer gradually changes upward from the bottom of the groove.
  • the formation of the gradient layer includes:
  • a laminated structure is formed in the groove, the laminated structure includes multilayer structural layers stacked, and the doping concentrations of adjacent structural layers are different;
  • a protective layer is formed, the protective layer covers the stacked structure, and fills up the groove.
  • the doping concentration of the multilayer structure layer first increases and then decreases upward from the bottom of the groove.
  • the forming a stacked structure in the groove includes:
  • each round of epitaxial growth forms one layer of the structure layer.
  • the multilayer structure layer is a multilayer silicon germanium layer.
  • the difference in germanium content between adjacent silicon germanium layers is 1wt% to 5wt%.
  • the germanium content in the silicon germanium layer near the bottom of the groove is 25wt% to 30wt%, and the silicon germanium layer with the largest germanium content is The content of germanium in the layer is 35wt% to 40wt%, and the content of germanium in the silicon germanium layer near the top of the groove is 25wt% to 30wt%.
  • the manufacturing method of the semiconductor structure further includes:
  • a metal layer is formed on the conductive layer.
  • the manufacturing method of the semiconductor structure before forming the graded layer, further includes:
  • the second region near the bottom of the groove is doped with heavy ions to form a heavily doped region.
  • the heavy ions include at least one of germanium, carbon, and helium.
  • the manufacturing method of the semiconductor structure before forming the groove on the substrate, the manufacturing method of the semiconductor structure further includes:
  • a groove is provided in the doped region of the substrate, and a graded layer is filled in the groove.
  • the doping concentration of the graded layer gradually changes from the bottom of the groove upwards, and
  • the graded layer with gradually changing impurity concentration can better match the groove wall, while improving the carrier mobility, it can reduce the leakage problem caused by the lattice mismatch between the groove wall and the graded layer .
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in the related art
  • Fig. 2 is a schematic structural diagram of a semiconductor structure shown according to an exemplary embodiment
  • Fig. 3 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment
  • Fig. 4 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment
  • Fig. 5 is a flow chart showing a method for fabricating a semiconductor structure according to an exemplary embodiment
  • FIG. 6 is a flowchart of a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 7 is a flow chart showing a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 8 is a schematic diagram of a substrate provided in a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 9 is a schematic diagram of forming grooves in a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • Fig. 10 is a schematic diagram of forming a heavily doped region in a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • Fig. 11 is a schematic diagram of forming a first structure layer in a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 12 is a schematic diagram of forming a multilayer structure layer in a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 13 is a schematic diagram of forming a protective layer in a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 14 is a schematic diagram of forming a through hole in a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • Fig. 15 is a schematic diagram of forming a conductive layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • a doping structure is embedded in the substrate.
  • a drain region and a channel region a gate oxide layer 20' is formed on the channel region, and a gate 30' is formed on the gate oxide layer 20'.
  • the source region and the drain region are embedded with a doped structure 40', the doped structure 40' is, for example, a SiGe structure.
  • the material of the substrate 10' is usually silicon, there will be a problem of lattice mismatch between the silicon and the silicon germanium structure, which will cause uneven growth morphology and also cause leakage, which will affect the stability of the transistor structure sex.
  • an exemplary embodiment of the present disclosure provides a semiconductor structure, as shown in FIG. 2 , the semiconductor structure includes: a substrate 100 , a groove 200 disposed on the substrate 100 , and a graded layer 300 filled in the groove 200 .
  • the material of the substrate 100 is, for example, silicon
  • the substrate 100 includes a doped region, for example, the doped region is used to form a source/drain region of a transistor.
  • the groove 200 is arranged in the doped region, and the graded layer fills the groove 200, and the doping concentration of the graded layer 300 gradually changes upward from the bottom of the groove 200, and the doping concentration mentioned here refers to the proportion of dopant in the total
  • the ratio of materials for example, when the graded layer 300 is a SiGe structure, the doping concentration is the germanium content in the SiGe structure.
  • the gradual change mentioned here can be gradually smaller or larger, or first smaller and then larger, or first larger and then smaller, which is not limited in this embodiment.
  • a groove 200 is provided in the doped region of the substrate 100, and a graded layer 300 is filled in the groove 200.
  • the doping concentration of the graded layer 300 gradually changes from the bottom of the groove 200 upwards.
  • the graded layer 300 whose concentration gradually changes can better match the groove wall of the groove 200, while increasing carrier mobility, it reduces the lattice mismatch between the groove wall of the groove 200 and the graded layer 300. leakage problem.
  • the graded layer 300 is an integral structure, in which the doping concentration gradually changes along the upward direction from the bottom of the groove 200 .
  • the graded layer 300 is a multilayer structure, and the doping concentration of the graded layer 300 is gradually increased from the bottom of the groove 200 upwards by setting different doping concentrations in different layer structures in the multilayer structure. Variety.
  • the graded layer 300 includes sequentially stacked multilayer structural layers 310, and the doping concentrations of adjacent structural layers 310 are different, that is, for each structural layer 310 itself, The doping concentration is the same, and the doping concentration of adjacent structural layers 310 is different, so as to realize the desired change of doping concentration.
  • the number of layers of the structural layer 310 is not limited, and can be set according to specific requirements. For example, in the embodiment shown in FIG.
  • the doping concentration of the multilayer structure layer 310 gradually increases from the bottom of the groove 200 upwards, for example, as shown in FIG.
  • the doping concentration of the third structure layer 313 is greater than that of the second structure layer 312 , and the doping concentration of the second structure layer 312 is greater than that of the first structure layer 311 .
  • the doping concentration of the graded layer 300 gradually decreases upward from the bottom of the groove 200, the doping concentration of the first structure layer 311 is greater than that of the second structure layer 312, and the doping concentration of the second structure layer 312 The dopant concentration is greater than the dopant concentration of the third structure layer 313 .
  • the doping concentration of the second structure layer 312 is greater than the doping concentration of the first structure layer 311 and greater than the doping concentration of the third structure layer 313 .
  • the doping concentration of the second structure layer 312 is lower than the doping concentration of the first structure layer 311 and lower than the doping concentration of the third structure layer 313 .
  • the graded layer 300 also includes a protection layer 320 disposed on the multilayer structure layer 310 , and the protection layer 320 can form a good protection effect on the multilayer structure layer 310 .
  • the doping concentration of the multilayer structure layer 310 first increases and then decreases upward from the bottom of the groove 200, that is, in the multilayer structure layer 310, the doping concentration of the structure layer 310 close to the protective layer 320 is higher than that of the protective layer 320.
  • the doping concentration of the structural layer 310 close to the substrate 100 is small to form a good match with the substrate 100, and the doping concentration of the structural layer 310 far away from the protective layer 320 and the substrate 100
  • the impurity concentration is relatively high, thereby increasing the carrier mobility of the graded layer 300 .
  • each structural layer 310 is 2-10 nm, so as to ensure the reliability of the formation process of each structural layer 310 and ensure that the number of structural layers 310 in the gradient layer 300 is controllable.
  • the multilayer structure layer 310 is a multilayer silicon germanium layer, that is, each layer structure layer 310 is a structure layer 310 obtained by doping germanium material in silicon, and the protection layer 320 is a silicon layer.
  • the germanium content in the multilayer structure layer 310 first increases and then decreases upward from the bottom of the groove 200, that is, in the multilayer structure layer 310, the germanium content in the upper structural layer 310 is smaller, and the lower structure layer 310 has a smaller germanium content.
  • the content of germanium in the layer 310 is small, and the content of germanium in the structural layer 310 located in the middle is relatively large.
  • the multi-layer structure layer 310 includes a first structure layer 311, a second structure layer 312 and a third structure layer 313 in sequence, and the germanium content in the second structure layer 312 is greater than that in the first structure layer 311, and greater than Germanium content in the third structure layer 313 .
  • the structural layer 310 in this embodiment is a silicon germanium layer
  • the protective layer 320 is a silicon layer.
  • the germanium content in the structural layer 310 on the upper side is relatively small, so that it can form a good relationship with the silicon layer (protective layer 320) above.
  • Matching, the germanium content in the structural layer 310 located on the lower side is also small, so that it can form a good match with the silicon layer (substrate 100) on the lower side, and the germanium content in the structural layer 310 located in the middle is relatively large, because the middle
  • the structural layer 310 is not in contact with the silicon layer (the protective layer 320 and the substrate 100 ), so more germanium content can be doped in the middle structural layer 310 to increase its carrier mobility and further improve its electrical conductivity.
  • the germanium content in the silicon germanium layer near the bottom of the groove 200 is 25wt% to 30wt%, and the germanium content in the silicon germanium layer with the highest germanium content is 35wt% to 40wt%. %, the content of germanium in the silicon germanium layer near the top of the groove 200 is 25wt% to 30wt%.
  • the germanium content difference between adjacent silicon germanium layers is 1wt% to 5wt%, so that it can ensure that the mismatch between the silicon germanium layers will not be affected by the large germanium content difference between the silicon germanium layers, and
  • the germanium content in the silicon germanium layer in the middle layer can be prevented from being affected by the too small germanium content difference between the silicon germanium layers, thereby taking into account the reliability and conductivity of the semiconductor structure.
  • the semiconductor structure further includes a conductive layer 400 and a metal layer 500
  • the protective layer 320 includes a via hole 321
  • the conductive layer 400 fills the via hole 321
  • the metal layer 500 is disposed on the conductive layer 400. , and electrically connected to the conductive layer 400 .
  • the material of the conductive layer 400 is a metal compound.
  • the material of the conductive layer 400 is cobalt silicide or nickel silicide.
  • the metal layer 500 and the structural layer 310 are electrically conductive through the metal silicide, which can reduce the contact resistance and improve the semiconductor structure. device performance.
  • the metal layer 500 can be made of tungsten, copper, gold, silver and other materials.
  • the setting of the protective layer 320 can also help the formation of the metal compound, that is, the conductive layer 400.
  • metal materials such as cobalt and nickel can be filled in the through hole 321 of the protective layer 320, and then undergo high-temperature annealing to make the conductive layer 400.
  • the metal material in the hole 321 reacts with the material of the protective layer 320 to generate a metal compound for reducing contact resistance.
  • the doped region includes a heavily doped region 110 and a lightly doped region 120, wherein both the heavily doped region 110 and the lightly doped region 120 are located at the periphery of the groove, and The heavily doped region 110 is closer to the bottom of the groove 200 .
  • the lightly doped (Light Dope Drain, LDD) region 120 is a structure adopted by the MOSFET in order to weaken the electric field in the drain region and improve the hot carrier injection effect, that is, a low
  • the doped region allows the region to bear part of the voltage, thereby effectively preventing the hot carrier injection effect.
  • the heavily doped region 110 is closer to the bottom of the groove 200, for example, the groove bottom of the groove 200 is higher than the lowest point of the heavily doped region 110, so that the groove bottom wall of the groove 200 and the sidewall region near the groove bottom wall are formed
  • vacancies or defects are formed in the heavily doped region 110 formed by heavy ion doping, so that the stress of lattice mismatch can be released, so that a gap is formed between the groove wall of the groove 200 and the graded layer 300. better match.
  • a heavily doped Halo region 130 is also provided under the lightly doped region 120 , so as to reduce the short channel effect of the device and suppress the threshold voltage drop.
  • this embodiment provides a transistor.
  • the transistor structure includes: a substrate 10 , a channel disposed in the substrate 10 , and a gate oxide layer 20 located above the channel. and the gate 30 , the two sides of the gate oxide layer 20 and the gate 30 are provided with dielectric layer spacers 40 .
  • the source region and the drain region of the substrate 10 are provided with the above-mentioned semiconductor structure, that is, grooves 200 are arranged in the source region and the drain region, and the grooves 200 are filled with a graded layer 300, and the doped layer 300 is The impurity concentration gradually changes upward from the bottom of the groove 200 .
  • the graded layer 300 By setting the graded layer 300 in the source region and the drain region, the graded layer 300 with gradually changing doping concentration can better match the groove wall of the groove 200, and while improving the carrier mobility, reduce the The leakage problem caused by the lattice mismatch between the groove wall of the 200 and the graded layer 300 improves the device performance of the transistor.
  • the substrate 10 includes a semiconductor substrate 11 and a well region 12 having a first conductivity type on the semiconductor substrate 11 , such as an N-type well region or a P-type well region.
  • the lightly doped region 120 is formed by doping ions of the first conductivity type
  • the Halo region 130 is formed by doping ions of the second conductivity type, that is, the first conductivity type is opposite to the second conductivity type, if If the ions of the first conductivity type are N-type ions, then the ions of the second conductivity type are P-type ions; if the ions of the first conductivity type are P-type ions, then the ions of the second conductivity type are N-type ions.
  • FIG. 5 shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIG. 8 - FIG. 15 is a schematic diagram of various stages of the manufacturing method of the semiconductor structure, and the manufacturing method of the semiconductor structure will be introduced below in conjunction with FIGS. 8-15 .
  • a method for preparing a semiconductor structure includes the following steps:
  • Step S10 providing a substrate, the substrate has a doped region.
  • the substrate 100 is used as a supporting component for supporting other components disposed thereon.
  • the substrate 100 can be made of semiconductor materials, and the semiconductor materials can be silicon, germanium, silicon-germanium compounds, and silicon-carbon one or more of the compounds.
  • a lightly doped (Light Dope Drain, LDD) region 120 is formed by doping the first region located on the surface layer of the substrate 100.
  • a first region is adopted for the first region. Ions of the conductivity type are doped to form a lightly doped region 120, the heavily doped region 110 is located below the lightly doped region 120, the groove 200 is at least partially formed in the heavily doped region 110 and the lightly doped region 120, and the groove 200 The bottom of the trench is higher than the lowest point of the heavily doped region 110 .
  • the lightly doped region 120 is a structure adopted by the MOSFET to weaken the electric field of the drain region and improve the hot carrier injection effect, that is, a lowly doped region is set near the source region and the drain region, so that the region can bear part of the voltage, thus effectively preventing the hot carrier injection effect.
  • a heavily doped Halo region 130 may also be provided under the lightly doped region 120 , as an example, the Halo region 130 is formed by doping with ions of the second conductivity type. That is, the first conductivity type is opposite to the second conductivity type, if the ions of the first conductivity type are N-type ions, then the ions of the second conductivity type are P-type ions; if the ions of the first conductivity type are P-type ions, then The ions of the second conductivity type are N-type ions.
  • Step S20 forming a groove in the doped region of the substrate.
  • the groove 200 may be formed in the doped region of the substrate 100 by means of photolithography (Litho), etching (ETCH) and the like. As shown in FIG. 9 , the groove 200 is at least partially formed in the heavily doped region 110 and the lightly doped region 120 , and the bottom of the groove 200 is higher than the lowest point of the heavily doped region 110 .
  • Step S30 forming a graded layer, the graded layer fills the groove, and the doping concentration of the graded layer gradually changes from the bottom of the groove upwards.
  • a doped semiconductor material can be deposited to form the graded layer 300, or an undoped semiconductor material can be deposited to fill the groove 200 to form a semiconductor material layer, and then doped impurities can be implanted into the semiconductor material layer by a thermal diffusion process or an ion implantation process A gradient layer 300 is formed.
  • a groove 200 is formed in the doped region of the substrate 100, and a graded layer 300 is formed in the groove 200.
  • the doping concentration of the graded layer 300 gradually changes from the bottom of the groove 200 upwards, and the doping
  • the graded layer 300 whose concentration gradually changes can better match the groove wall of the groove 200, while increasing carrier mobility, it reduces the lattice mismatch between the groove wall of the groove 200 and the graded layer 300. leakage problem.
  • this embodiment is a further description of step S30 in the above embodiment.
  • forming a gradient layer includes:
  • the laminated structure includes multiple structural layers stacked, and adjacent structural layers have different doping concentrations.
  • the doping concentration of the graded layer 300 gradually changes from the bottom of the groove 200 upwards.
  • the doping concentrations of adjacent structural layers 310 are different, that is, for each structural layer 310 itself, its doping concentration is the same, and the doping concentrations of adjacent structural layers 310 are different, so as to achieve the desired doping concentration. concentration changes.
  • the number of layers of the structural layer 310 is not limited, and can be set according to specific requirements. For example, in the embodiment shown in FIG.
  • the semiconductor material layer may be formed by depositing by atomic layer deposition (Atomic layer deposition, ALD for short), chemical vapor deposition (Chemical Vapor Deposition, CVD for short), and the semiconductor material layer is doped to form the structure layer 310 .
  • ALD atomic layer deposition
  • CVD chemical Vapor Deposition
  • step S31 multiple rounds of epitaxial growth are performed in the groove 200, each round of epitaxial growth forms a layer of structure layer 310, and the required doping is achieved by controlling the material content in it during the epitaxial growth process. impurity concentration.
  • the structure layer 310 is formed by epitaxial growth, so that the doping concentration of each structure layer 310 can be controlled more precisely, thereby improving process controllability.
  • the protective layer covers the laminated structure, and fills the grooves.
  • the protective layer 320 can be deposited by atomic layer deposition (Atomic layer deposition, ALD for short), chemical vapor deposition (Chemical Vapor Deposition, CVD for short), or the protective layer 320 can be formed by epitaxial growth. Layer 320.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the protective layer 320 can be formed by epitaxial growth.
  • Layer 320 By forming a protective layer 320 on the laminated structure, the laminated structure is well protected, and the groove 200 is filled up with the protective layer 320 to ensure flatness.
  • the doping concentration of the multilayer structure layer 310 first increases and then decreases from the bottom of the groove 200, that is, in the multilayer structure layer 310, the doping concentration of the structure layer 310 close to the protective layer 320 is relatively small.
  • the doping concentration of the structural layer 310 close to the substrate 100 is small to form a good match with the substrate 100, and the doping concentration of the structural layer 310 far away from the protective layer 320 and the substrate 100
  • the device performance of the formed semiconductor structure can be ensured, leakage caused by lattice mismatch can be avoided, and at the same time, it can be improved.
  • Conductivity of the graded layer 300 By first increasing and then decreasing the doping concentration of the multilayer structure layer 310 from the bottom of the groove 200 upwards, the device performance of the formed semiconductor structure can be ensured, leakage caused by lattice mismatch can be avoided, and at the same time, it can be improved.
  • the structural layer 310 is a silicon germanium layer
  • the protective layer 320 is a silicon layer.
  • the germanium content in the structural layer 310 on the upper side is relatively small, so that it can be compared with the silicon layer (protective layer 320) on the upper side.
  • a good match is formed, and the content of germanium in the structural layer 310 located on the lower side is also small, so that it can form a good match with the silicon layer (substrate 100) on the lower side, and the content of germanium in the structural layer 310 located in the middle is relatively small.
  • the middle structural layer 310 is not in contact with the silicon layer (protective layer 320 and substrate 100), more germanium content can be doped in the middle structural layer 310 to increase its carrier mobility, thereby improving its conductivity. performance.
  • step 31 includes:
  • the second structure layer 312 is selectively epitaxially formed on the first structure layer 311
  • the third structure layer 313 is selectively epitaxially formed on the second structure layer 312 .
  • the doping concentration of the second structure layer 312 is greater than the doping concentration of the first structure layer 311 and greater than the doping concentration of the third structure layer 313 .
  • the germanium content in the silicon germanium layer near the groove bottom of the groove 200 is 25wt% to 30wt%, and the germanium content in the silicon germanium layer with the largest germanium content is 35wt% to 40wt%.
  • the content of germanium in the silicon germanium layer at the top of the groove is 25wt% to 30wt%.
  • the germanium content difference between adjacent silicon germanium layers is 1wt% to 5wt%, so that it can ensure that the mismatch between the silicon germanium layers will not be affected by the large germanium content difference between the silicon germanium layers, and
  • the germanium content in the silicon germanium layer in the middle layer can be prevented from being affected by the too small germanium content difference between the silicon germanium layers, thereby taking into account the reliability and conductivity of the semiconductor structure.
  • via holes 321 may be formed on the protective layer 320 by means of photolithography (Litho), etching (ETCH), and the like.
  • a BARC layer Bottom Anti-Reflective Coatings, bottom anti-reflective coating
  • a patterned photoresist layer is formed on the BARC layer
  • the patterned photoresist layer is formed by dry etching. The patterns in are transferred to the passivation layer 320 to form via holes 321 in the passivation layer 320 .
  • the metal material is filled in the through hole 321, and the metal material in the through hole is combined with the protective layer 320 to form a metal compound through a high-temperature annealing process, and the structural layer 310 and the subsequent process are realized through the metal compound.
  • the conduction between the formed metal layers 500 can reduce the contact resistance, thereby improving the device performance of the semiconductor structure.
  • the metal material is, for example, cobalt or nickel, which can combine with silicon in the protection layer 320 to form cobalt silicide or nickel silicide.
  • the material of the metal layer 500 is, for example, tungsten, copper, gold, and silver, and the metal layer can be formed by depositing by atomic layer deposition (Atomic layer deposition, ALD for short), chemical vapor deposition (Chemical Vapor Deposition, CVD for short), etc. 500.
  • atomic layer deposition Atomic layer deposition, ALD for short
  • chemical vapor deposition Chemical Vapor Deposition, CVD for short
  • the following steps are further performed:
  • heavy ion doping is performed on the region near the bottom of the groove 200 , thereby forming a heavily doped region 110 , which constitutes the bottom of the groove 200
  • the walls and part of the side walls near the bottom are formed by heavy ion doping in the heavily doped region 110 to form vacancies or defects, so that the stress of lattice mismatch can be released, so that the groove walls of the groove 200 and the graded layer 300 form a better match.
  • the heavy ions used for heavy ion doping include at least one of germanium, carbon, and helium.
  • the heavily doped region 110 is in contact with the first structure layer 311, for example, the bottom surface of the first structure layer 311 is in contact with the bottom of the heavily doped region 110, and the side surface of the first structure layer 311 is in contact with the heavily doped contact with the side surfaces of the impurity region 110 , so as to release the stress generated by lattice mismatch when forming the first structure layer 311 .
  • the following steps are further performed:
  • heavy ions are used to dope the third region, thereby forming vacancies or defects in the sidewalls of the groove 200, so that when the subsequent structural layers 310 are formed, the structure layers 310 due to the crystal lattice The stress generated by the fitting is released, so that a better match is formed between the groove wall of the groove 200 and the gradient layer 300 .
  • the heavy ions forming the heavily doped region 110 may be the same as or different from the heavy ions forming the stress release region.
  • the heavy ions used for heavy ion doping include at least one of germanium, carbon, and helium.
  • the stress release area can be an integral cylindrical structure, so as to completely surround each structural layer above the first structural layer 311 in the gradient layer 300.
  • the stress release area surrounds the second structural layer 312 and a third structural layer 313 surround.
  • the stress release area can also be arranged upwards from the bottom of the groove 200, and each stress release area corresponds to a structural layer 310, that is, each stress release area is connected to a structural layer 310 respectively. sidewall contact.
  • the doping concentration of the stress release region may be the same as that of the heavily doped region 110 , or may be different from that of the heavily doped region 110 .
  • the doping concentration of the heavily doped region 110 matches the doping concentration of the structural layer 310 in contact with it, and the doping concentration of the stress relief region matches the doping concentration of the structural layer 310 in contact with it,
  • the doping concentration of the stress release region corresponding to the structural layer with a higher doping concentration is also relatively high
  • the doping concentration of the stress releasing region corresponding to the structural layer with a lower doping concentration is also relatively low.
  • the multi-layer structure layer 310 of the graded layer 300 includes a first structure layer 311, a second structure layer 312 and a third structure layer 313 which are sequentially stacked, and the doping concentration of the second structure layer 312 is higher than that of the first structure layer 311 and greater than the doping concentration of the third structure layer 313 .
  • the stress release area includes a first stress release area corresponding to the second structural layer 312 and a second stress release area corresponding to the third structural layer 313, that is, the first stress release area is in contact with the sidewall of the second structural layer 312, and the second stress release area is in contact with the side wall of the second structural layer 312.
  • the two stress release regions are in contact with the sidewalls of the third structure layer 313 .
  • the doping concentration of the first stress releasing region is greater than that of the heavily doped region and greater than that of the second stress releasing region.
  • the lattice mismatch between it and the sidewall of the groove is relatively serious.
  • the first stress release region that will be in contact with the second structure layer 312 The doping concentration is set higher, so that more vacancies or defects are formed in the first stress release region, and then the stress generated by the formation of the second structure layer 312 is released.
  • the lattice mismatch between them and the bottom wall and sidewall of the groove is also relatively light, correspondingly, the first structure layer 311, and the doping concentration of the second stress release region in contact with the third structure layer 313 is set to be relatively small, so as to ensure stress release (the stress generated during the formation of the first structure layer 311 and the formation of the third The stress generated in the structure layer 313) while avoiding too many vacancies or defects to affect the reliability of the semiconductor structure.
  • the stress release region can also be formed by doping after the formation of the first structural layer. between.
  • the stress release region includes a first stress release region in contact with the second structure layer 312 and a second stress release region in contact with the third structure layer 313, after the formation of the first structure layer 311, doping can be formed The first stress release region, and after forming the second structure layer 312 , doping to form the second stress release region, and then forming the third structure layer 313 .
  • a method for manufacturing a semiconductor structure is provided, and the method is used for manufacturing a transistor.
  • a gate oxide layer and a gate are formed on the base, and before the groove is formed, ion implantation is performed on the base on both sides of the gate oxide layer and the gate to form the source and the gate.
  • ion implantation may be performed on the graded layer to form the source and the gate.
  • a groove is provided in the doped region of the substrate, and a graded layer is filled in the groove.
  • the doping concentration of the graded layer gradually changes from the bottom of the groove upwards, and
  • the graded layer with gradually changing impurity concentration can better match the groove wall, while improving the carrier mobility, it can reduce the leakage problem caused by the lattice mismatch between the groove wall and the graded layer .
  • a groove is provided in the doped region of the substrate, and a graded layer is filled in the groove.
  • the doping concentration of the graded layer gradually changes from the bottom of the groove upwards, and
  • the graded layer with gradually changing impurity concentration can better match the groove wall, while improving the carrier mobility, it can reduce the leakage problem caused by the lattice mismatch between the groove wall and the graded layer .

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Abstract

本公开提供一种半导体结构及其制作方法，涉及半导体技术领域，所述半导体结构包括：基底，基底包括掺杂区域；凹槽，凹槽位于掺杂区域；渐变层，渐变层填充凹槽，且渐变层的掺杂浓度自凹槽的底部向上逐渐变化。本公开实施例所提供的半导体结构及其制备方法中，在基底的掺杂区域设置凹槽，并在凹槽内填充渐变层，渐变层的掺杂浓度自凹槽的底部向上逐渐变化，掺杂浓度逐渐变化的渐变层能够与凹槽的槽壁更好的匹配，在提高载流子迁移率的同时，减少因凹槽的槽壁与渐变层之间的晶格失配导致的漏电问题。

Description

半导体结构及其制作方法
本公开基于申请号为202210047626.2、申请日为2022年01月17日、申请名称为“半导体结构及其制作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构及其制作方法。
背景技术
在半导体结构的制备过程中，为了提高载流子迁移率，可以在半导体结构的基底中嵌入掺杂结构，从而提高半导体结构的器件性能。
上述的半导体结构中，掺杂结构与原有的基底会存在晶格失配的问题，不仅会造成生长形貌的不平整，还会造成漏电，影响器件的稳定性。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种半导体结构及其制作方法。
本公开的第一方面提供一种半导体结构，所述半导体结构包括：
基底，所述基底包括掺杂区域；
凹槽，所述凹槽位于所述掺杂区域；
渐变层，所述渐变层填充所述凹槽，且所述渐变层的掺杂浓度自所述凹槽的底部向上逐渐变化。
根据本公开的一些实施例，所述渐变层包括依次堆叠的多层结构层以及保护层，相邻所述结构层的掺杂浓度不同。
根据本公开的一些实施例，所述多层结构层的掺杂浓度自所述凹槽的底部向上先增大后减小。
根据本公开的一些实施例，所述多层结构层为多层硅锗层，所述保护层为硅层。
根据本公开的一些实施例，每层所述结构层的厚度为2-10nm。
根据本公开的一些实施例，所述半导体结构还包括导电层和金属层，所述保护层包括通孔，所述导电层填充所述通孔，所述金属层设置于所述导电层上，并与所述导电层电连接。
根据本公开的一些实施例，所述导电层的材料包括硅化钴或者硅化镍；
所述金属层的材料包括钨、铜、金或铝。
根据本公开的一些实施例，所述掺杂区域包括重掺杂区域和轻掺杂区域，所述重掺杂区域和所述轻掺杂区域均位于所述凹槽的周边，且所述重掺杂区域更靠近所述凹槽底部。
本公开的第二方面提供一种晶体管，所述晶体管包括如上所述的半导体结构，所述半导体结构位于所述晶体管的源极区域和漏极区域。
本公开的第三方面提供一种半导体结构的制作方法，所述半导体结构的制作方法包括：
提供基底，所述基底具有掺杂区；
在所述基底的掺杂区形成凹槽；
形成渐变层，所述渐变层填充所述凹槽，且所述渐变层的掺杂浓度自所述凹槽的底部向上逐渐变化。
根据本公开的一些实施例，所述形成渐变层，包括：
在所述凹槽内形成叠层结构，所述叠层结构包括堆叠设置的多层结构层，相邻所述结构层的掺杂浓度不同；
形成保护层，所述保护层覆盖所述叠层结构，并将所述凹槽填平。
根据本公开的一些实施例，所述多层结构层的掺杂浓度自所述凹槽的底部向上先增大后减小。
根据本公开的一些实施例，所述在所述凹槽内形成叠层结构，包括：
在所述凹槽内进行多轮外延生长，每一轮外延生长形成一层所述结构层。
根据本公开的一些实施例，所述多层结构层为多层硅锗层。
根据本公开的一些实施例，相邻的所述硅锗层之间的锗含量之差为1wt％至5wt％。
根据本公开的一些实施例，所述多层硅锗层中，靠近所述凹槽的槽底的所述硅锗层中的锗含量为25wt％至30wt％，锗含量最大的所述硅锗层中的锗含量为35wt％至40wt％，靠近所述凹槽的槽顶的所述硅锗层中的锗含量为25wt％至30wt％。
根据本公开的一些实施例，在形成渐变层之后，所述半导体结构的制作方法还包括：
去除所述保护层的部分结构，以形成通孔，所述通孔暴露出所述叠层结构的部分顶面；
在所述通孔内填充金属材料，并通过高温退火工艺使得所述金属材料与所述保护层的材料结合形成导电层；
在所述导电层上形成金属层。
根据本公开的一些实施例，在形成渐变层之前，所述半导体结构的制作方法还包括：
采用重离子对位于所述凹槽底部附近的第二区域掺杂形成重掺杂区域。
根据本公开的一些实施例，所述重离子包括锗、碳、氦中的至少一种。
根据本公开的一些实施例，在所述基底上形成凹槽之前，所述半导体结构的制作方法还包括：
对位于所述基底的表层的第一区域掺杂形成轻掺杂区域，所述重掺杂区域位于所述轻掺杂区域下方。
本公开实施例所提供的半导体结构及其制备方法中，在基底的掺杂区域设置凹槽，并在凹槽内填充渐变层，渐变层的掺杂浓度自凹槽的底部向上逐渐变化，掺杂浓度逐渐变化的渐变层能够与凹槽的槽壁更好的匹配，在提高载流子迁移率的同时，减少因凹槽的槽壁与渐变层之间的晶格失配导致的漏电问题。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是相关技术中半导体结构的结构示意图；
图2是根据一示例性实施例示出的一种半导体结构的结构示意图；
图3是根据一示例性实施例示出的一种半导体结构的结构示意图；
图4是根据一示例性实施例示出的一种半导体结构的结构示意图；
图5是根据一示例性实施例示出的一种半导体结构的制作方法的流程图；
图6是根据一示例性实施例示出的一种半导体结构的制作方法的流程图；
图7是根据一示例性实施例示出的一种半导体结构的制作方法的流程图；
图8是根据一示例性实施例示出的半导体结构的制作方法中提供的基底的示意图；
图9是根据一示例性实施例示出的半导体结构的制作方法中形成凹槽的示意图；
图10是根据一示例性实施例示出的半导体结构的制作方法中形成重掺杂区域的示意图；
图11是根据一示例性实施例示出的半导体结构的制作方法中形成第一结构层的示意图；
图12是根据一示例性实施例示出的半导体结构的制作方法中形成多层结构层的示意图；
图13是根据一示例性实施例示出的半导体结构的制作方法中形成保护层的示意图；
图14是根据一示例性实施例示出的半导体结构的制作方法中形成通孔的示意图；
图15是根据一示例性实施例示出的半导体结构的制作方法中形成导电层的示意图。
附图标记：
100、基底；110、重掺杂区域；120、轻掺杂区域；130、Halo区域；200、凹槽；300、渐变层；310、结构层；311、第一结构层；312、第二结构层；313、第三结构层；320、保护层；321、通孔；400、导电层；500、金属层；
10、基底；11、半导体衬底；12、阱区；20、栅氧层；30、栅极；40、介质层侧墙；
10’、基底；20’、栅氧层；30’、栅极；40’、掺杂结构。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
现有半导体结构中，为了提高载流子迁移率，在基底中嵌入掺杂结构，例如，如图1所示，半导体结构为晶体管结构，该晶体管结构包括基底10’，基底10’具有源区、漏区和沟道区，沟道区上形成栅氧层20’，栅氧层20’上形成栅极30’。源区和漏区嵌入有掺杂结构40’，掺杂结构40’例如为硅锗结构。申请人发现，由于基底10’的材料通常为硅，硅与硅锗结构之间会存在晶格失配的问题，从而造成生长形貌的不平整，同时还会造成漏电，影响晶体管结构的稳定性。
基于此，本公开示例性的实施例中提供一种半导体结构，如图2所示，该半导体结构包括：基底100、设置于基底100上凹槽200以及填充于凹槽200内的渐变层300。其中，基底100的材料例如为硅，基底100包括掺杂区域，掺杂区域例如用于形成晶体管的源/漏区。凹槽200设置在掺杂区域，渐变层填充凹槽200，且渐变层300的掺杂浓度自凹槽200的底部向上逐渐变化，此处所述的掺杂浓度指的是掺杂剂占总材料的比例，例如，当渐变层300为硅锗结构时，掺杂浓度即为硅锗结构中的锗含量。此处所述的逐渐变化，可以为逐渐变小，也可以为逐渐变大，还可以为先变小后变大，或者是先变大后变小，本实施例中对此不作限制。
本实施例的半导体结构中，在基底100的掺杂区域设置凹槽200，并在凹槽200内填充渐变层300，渐变层300的掺杂浓度自凹槽200的底部向上逐渐变化，掺杂浓度逐渐变化的渐变层300能够与凹槽200的槽壁更好的匹配，在提高载流子迁移率的 同时，减少因凹槽200的槽壁与渐变层300之间的晶格失配导致的漏电问题。
在一些实施例中，渐变层300为一整体结构，在该整体结构中，沿自凹槽200的底部向上的方向，其掺杂浓度逐渐变化。在另一些实施例中，渐变层300为多层结构，通过将多层结构中的不同层结构层设置不同的掺杂浓度，实现渐变层300的掺杂浓度自凹槽200的底部向上的逐渐变化。
根据一示例性实施例，如图2所示，渐变层300包括依次堆叠的多层结构层310，相邻的结构层310的掺杂浓度不同，即，对于每个结构层310自身而言，其掺杂浓度是相同的，相邻的结构层310的掺杂浓度不同，从而实现希望的掺杂浓度变化。结构层310的层数不做限制，可根据具体需求进行设置，例如，在图2所示的实施例中，在凹槽200的底部向上，多层结构层310依次包括第一结构层311、第二结构层312和第三结构层313，其中，第一结构层311与第二结构层312的掺杂浓度不同，第二结构层312与第三结构层313的掺杂浓度不同，第一结构层311与第三结构层313的掺杂浓度可以相等，也可以不同。在渐变层300的掺杂浓度自凹槽200的底部向上逐渐增大的实施例中，多层结构层310的掺杂浓度自凹槽200的底部向上逐渐增大，例如，在图2所示的实施例中，第三结构层313的掺杂浓度大于第二结构层312的掺杂浓度，第二结构层312的掺杂浓度大于第一结构层311的掺杂浓度。在渐变层300的掺杂浓度自凹槽200的底部向上逐渐减小的实施例中，第一结构层311的掺杂浓度大于第二结构层312的掺杂浓度，第二结构层312的掺杂浓度大于第三结构层313的掺杂浓度。在渐变层300的掺杂浓度先变大后变小的实施例中，第二结构层312的掺杂浓度大于第一结构层311的掺杂浓度，且大于第三结构层313的掺杂浓度。在渐变层300的掺杂浓度先变小后变大的实施例中，第二结构层312的掺杂浓度小于第一结构层311的掺杂浓度，且小于第三结构层313的掺杂浓度。
渐变层300还包括设置于多层结构层310上的保护层320，保护层320能够对多层结构层310形成很好的保护作用。在该实施例中，多层结构层310的掺杂浓度自凹槽200的底部向上先增大后减小，即多层结构层310中，靠近保护层320的结构层310的掺杂浓度较小，以与保护层320形成很好的匹配，靠近基底100的结构层310的掺杂浓度较小，以与基底100形成很好的匹配，远离保护层320和基底100的结构层310的掺杂浓度较大，从而提高渐变层300的载流子迁移率。通过将多层结构层310的掺杂浓度自凹槽200的底部向上先增大后减小，既能够保证半导体结构的器件性能，避免因晶格失配导致漏电，并同时又能提高渐变层300的导电性能。
一实施例中，每层结构层310的厚度为2-10nm，从而保证各层结构层310形成过程的可靠性，且能够保证渐变层300中的结构层310的层数可控。
根据一个示例性实施例，多层结构层310为多层硅锗层，即各层结构层310均为硅中掺杂锗材料得到的结构层310，保护层320为硅层。多层结构层310中的锗含量自凹槽200的底部向上先增大后减小，即多层结构层310中，位于上侧的结构层310中的锗含量较小，位于下侧的结构层310中的锗含量较小，位于中部的结构层310中的锗含量较大。作为示例，多层结构层310依次包括第一结构层311、第二结构层312和第三结构层313，第二结构层312中的锗含量大于第一结构层311中的锗含量，且大于第三结构层313中的锗含量。
本实施例中的结构层310为硅锗层，保护层320为硅层，位于上侧的结构层310中的锗含量较小，从而能够与其上的硅层(保护层320)形成很好的匹配，位于下侧的结构层310中的锗含量也较小，从而能够与其下侧的硅层(基底100)形成很好的匹配，位于中部的结构层310中的锗含量较大，由于中部的结构层310不与硅层(保护层320和基底100)接触，因此中部结构层310中可以掺杂更多的锗含量，以提高其载流子迁移率，进而提高其导电性能。
一实施例中，多层硅锗层中，靠近凹槽200的槽底的硅锗层中的锗含量为25wt％至30wt％，锗含量最大的硅锗层中的锗含量为35wt％至40wt％，靠近凹槽200的槽顶的硅锗层中的锗含量为25wt％至30wt％。相邻的硅锗层之间的锗含量之差为1wt％至5wt％，如此，既能够保证硅锗层之间不会因锗含量差距太大而影响硅锗层之间的失配，又能够避免硅锗层之间锗含量差距太小而影响中间层的硅锗层中的锗含量，从而兼顾了半导体结构的可靠性和导电性能。
根据一个示例性实施例，如图2所示，半导体结构还包括导电层400和金属层500，保护层320包括通孔321，导电层400填充通孔321，金属层500设置于导电层400上，并与导电层400电连接。通过设置金属层500和导电层400并经通孔321与结构层310接触，以实现结构层310与其他各层结构的电连接。其中，导电层400的材料为金属化合物，例如，导电层400的材料为硅化钴或硅化镍，通过金属硅化物实现金属层500与结构层310的导电，能够减小接触电阻，进而提高半导体结构的器件性能。金属层500可以采用钨、铜、金、银等材料。
在本实施例中，保护层320的设置还能够帮助金属化合物即导电层400的形成，作为示例，可以在保护层320的通孔321内填充钴、镍等金属材料，之后经过高温退火使得通孔321内的金属材料与保护层320的材料发生反应，从而生成用于减小接触电阻的金属化合物。
根据一个示例性实施例，如图3所示，掺杂区域包括重掺杂区域110和轻掺杂区域120，其中，重掺杂区域110和轻掺杂区域120均位于凹槽的周边，且重掺杂区域110更靠近凹槽200底部。其中，轻掺杂(Light Dope Drain，LDD)区域120是MOSFET为了减弱漏区电场、以改进热载流子注入效应所采取的一种结构，即在靠近源区和漏区的附近设置一个低掺杂的区域，让该区域承受部分电压，从而有效防止热载流子注入效应。重掺杂区域110更靠近凹槽200底部，例如，凹槽200的槽底高于重掺杂区域110的最低点，从而使得凹槽200的槽底壁以及靠近槽底壁的侧壁区域形成重掺杂区域110，采用重离子掺杂形成的重掺杂区域110中形成空位或缺陷，从而能够对晶格失配的应力进行释放，使得凹槽200的槽壁与渐变层300之间形成更好的匹配。继续参考图3，在轻掺杂区域120下方还设置有重掺杂的Halo区域130，从而降低器件的短沟道效应，抑制阈值电压跌落。
根据本公开一个示例性的实施例，本实施例提供了一种晶体管，如图4所示，晶体管结构包括：基底10、设置在基底10中的沟道以及位于沟道上方的栅氧层20和栅极30，栅氧层20和栅极30的两侧设置有介质层侧墙40。基底10的源极区域和漏极区域设置有上述的半导体结构，即在源极区域和漏极区域均设置有凹槽200，并在凹槽200内填充有渐变层300，渐变层300的掺杂浓度自凹槽200的底部向上逐渐变化。通过在源极区域和漏极区域设置渐变层300，掺杂浓度逐渐变化的渐变层300能够与凹槽200的槽壁更好的匹配，在提高载流子迁移率的同时，减少因凹槽200的槽壁与渐变层300之间的晶格失配导致的漏电问题，从而提高晶体管的器件性能。
示例性地，如图4所示，基底10包括半导体衬底11以及半导体衬底11上的具有第一导电类型的阱区12，例如为N型阱区或者P型阱区。在本实施例中，轻掺杂区域120为掺杂第一导电类型的离子形成，Halo区域130为掺杂第二导电类型的离子形成，即，第一导电类型与第二导电类型相反，若第一导电类型的离子为N型离子，则第二导电类型的离子为P型离子；若第一导电类型的离子为P型离子，则第二导电类型的离子为N型离子。
本公开示例性的实施例中提供一种半导体结构的制备方法，如图5所示，图5示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图，图8-图15为半导体结构的制作方法的各个阶段的示意图，下面结合图8-图15对半导体结构 的制作方法进行介绍。
如图5所示，本公开一示例性的实施例提供的一种半导体结构的制备方法，包括如下的步骤：
步骤S10：提供基底，基底具有掺杂区。
示例性地，如图8所示，基底100作为支撑部件，用于支撑设在其上的其他部件，基底100可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
根据一个示例性实施例，如图8所示，对位于基底100的表层的第一区域掺杂形成有轻掺杂(Light Dope Drain，LDD)区域120，作为示例，对第一区域采用第一导电类型的离子进行掺杂形成轻掺杂区域120，重掺杂区域110位于轻掺杂区域120下方，凹槽200至少部分形成于重掺杂区域110和轻掺杂区域120，且凹槽200的槽底高于重掺杂区域110的最低点。轻掺杂区域120是MOSFET为了减弱漏区电场、以改进热载流子注入效应所采取的一种结构，即在靠近源区和漏区的附近设置一个低掺杂的区域，让该区域承受部分电压，从而有效防止热载流子注入效应。
进一步地，还可在轻掺杂区域120下方设置重掺杂的Halo区域130，作为示例，采用第二导电类型的离子进行掺杂形成Halo区域130。即，第一导电类型与第二导电类型相反，若第一导电类型的离子为N型离子，则第二导电类型的离子为P型离子；若第一导电类型的离子为P型离子，则第二导电类型的离子为N型离子。通过设置Halo区域130，能够降低器件的短沟道效应，抑制阈值电压跌落。
步骤S20：在基底的掺杂区形成凹槽。
在该步骤中，可在基底100的掺杂区采用光刻(Litho)、刻蚀(ETCH)等方式形成凹槽200。如图9所示，凹槽200至少部分形成于重掺杂区域110和轻掺杂区域120，且凹槽200的槽底高于重掺杂区域110的最低点。
步骤S30：形成渐变层，渐变层填充凹槽，且渐变层的掺杂浓度自凹槽的底部向上逐渐变化。
在该步骤中，可以沉积掺杂半导体材料形成渐变层300，或者沉积无掺杂半导体材料填充凹槽200形成半导体材料层，再通过热扩散工艺或离子注入工艺向半导体材料层中注入掺杂杂质形成渐变层300。
本实施例形成的半导体结构，在基底100的掺杂区形成凹槽200，并在凹槽200内形成渐变层300，渐变层300的掺杂浓度自凹槽200的底部向上逐渐变化，掺杂浓度逐渐变化的渐变层300能够与凹槽200的槽壁更好的匹配，在提高载流子迁移率的同时，减少因凹槽200的槽壁与渐变层300之间的晶格失配导致的漏电问题。
根据本公开一个示例性的实施例，本实施例是对上述实施例中步骤S30的进一步说明。
如图6所示，形成渐变层包括：
S31、在凹槽内形成叠层结构，叠层结构包括堆叠设置的多层结构层，相邻结构层的掺杂浓度不同。
该步骤中，如图12所示，通过将多层结构310中的不同层结构层310设置不同的掺杂浓度，实现渐变层300的掺杂浓度自凹槽200的底部向上的逐渐变化。相邻的结构层310的掺杂浓度不同，即，对于每个结构层310自身而言，其掺杂浓度是相同的，相邻的结构层310的掺杂浓度不同，从而实现希望的掺杂浓度变化。结构层310的层数不做限制，可根据具体需求进行设置，例如，在图12所示的实施例中，在凹槽200的底部向上，多层结构层310依次包括第一结构层311、第二结构层312和第三结构层313，其中，第一结构层311与第二结构层312的掺杂浓度不同，第二结构层312与第三结构层313的掺杂浓度不同，第一结构层311与第三结构层313的掺杂 浓度可以相等，也可以不同。
作为示例，可采用原子层沉积(Atomic layer deposition，简称ALD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)等工艺沉积形成半导体材料层，并在半导体材料层中进行掺杂形成结构层310。另一实施例中，步骤S31中，在凹槽200内进行多轮外延生长，每一轮外延生长形成一层结构层310，通过在外延生长过程中控制其中的材料含量，达到所需的掺杂浓度。采用外延生长形成结构层310，能够更加精准地控制各结构层310的掺杂浓度，进而提高工艺可控性。
S32、形成保护层，保护层覆盖叠层结构，并将凹槽填平。
该步骤中，如图13所示，可采用原子层沉积(Atomic layer deposition，简称ALD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)等工艺沉积形成保护层320，也可以采用外延生长形成保护层320。通过在叠层结构上形成保护层320，来对叠层结构形成很好的保护，并且利用保护层320将凹槽200填平，以保证平整性。
本实施例中，多层结构层310的掺杂浓度自凹槽200的底部向上先增大后减小，即多层结构层310中，靠近保护层320的结构层310的掺杂浓度较小，以与保护层320形成很好的匹配，靠近基底100的结构层310的掺杂浓度较小，以与基底100形成很好的匹配，远离保护层320和基底100的结构层310的掺杂浓度较大，从而提高渐变层300的载流子迁移率。通过将多层结构层310的掺杂浓度自凹槽200的底部向上先增大后减小，既能够保证形成的半导体结构的器件性能，避免因晶格失配导致漏电，并同时又能提高渐变层300的导电性能。
根据一个示例性实施例，结构层310为硅锗层，保护层320为硅层，如此，位于上侧的结构层310中的锗含量较小，从而能够与其上的硅层(保护层320)形成很好的匹配，位于下侧的结构层310中的锗含量也较小，从而能够与其下侧的硅层(基底100)形成很好的匹配，位于中部的结构层310中的锗含量较大，由于中部的结构层310不与硅层(保护层320和基底100)接触，因此中部结构层310中可以掺杂更多的锗含量，以提高其载流子迁移率，进而提高其导电性能。
本实施例中，步骤31包括：
S311、在400℃至1000℃条件下，在凹槽内选择性外延硅锗，并通过控制硅锗中的锗含量，得到所需掺杂浓度的第一结构层，参见图11；
S312、在第一结构层之上继续进行多轮选择性外延，每一轮硅锗生长厚度控制在2-10nm范围内，从而形成多层结构层。
作为示例，如图12所示，在第一结构层311之上选择性外延形成第二结构层312，并在第二结构层312之上选择性外延形成第三结构层313。第二结构层312的掺杂浓度大于第一结构层311的掺杂浓度，且大于第三结构层313的掺杂浓度。
本实施例中，靠近凹槽200的槽底的硅锗层中的锗含量为25wt％至30wt％，锗含量最大的硅锗层中的锗含量为35wt％至40wt％，靠近凹槽200的槽顶的硅锗层中的锗含量为25wt％至30wt％。相邻的硅锗层之间的锗含量之差为1wt％至5wt％，如此，既能够保证硅锗层之间不会因锗含量差距太大而影响硅锗层之间的失配，又能够避免硅锗层之间锗含量差距太小而影响中间层的硅锗层中的锗含量，从而兼顾了半导体结构的可靠性和导电性能。
根据一个示例性实施例，如图7所示，在形成渐变层之后，还进行如下步骤：
S40、去除保护层的部分结构，以形成通孔，通孔暴露出叠层结构的部分顶面。
该步骤中，如图14所示，可在保护层320上采用光刻(Litho)、刻蚀(ETCH)等方式形成通孔321。作为示例，于保护层320上表面形成BARC层(Bottom Anti-Reflective Coatings，底部抗反射涂层)，于BARC层上形成图形化光刻胶层，利用干 法刻蚀将图形化光刻胶层中的图形转移至保护层320中，以于保护层320中形成通孔321。
S50、在通孔内填充金属材料，并通过高温退火工艺使得金属材料与保护层的材料结合形成导电层。
本实施例中，如图15所示，在通孔321内填充金属材料，并通过高温退火工艺使得通孔内金属材料与保护层320结合形成金属化合物，通过金属化合物实现结构层310与后续工艺形成的金属层500之间的导电，能够减小接触电阻，进而提高半导体结构的器件性能。金属材料例如为钴或镍，其能够与保护层320中的硅结合形成硅化钴或硅化镍。
S60、在导电层上形成金属层。
该步骤中，金属层500的材料例如为钨、铜、金、银，可采用原子层沉积(Atomic layer deposition，简称ALD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)等工艺沉积形成金属层500。
根据一个示例性实施例，在形成渐变层300之前，如图6所示，还进行如下步骤：
S70、采用重离子对位于凹槽底部附近的第二区域掺杂形成重掺杂区域。
该步骤中，如图9所示，在形成渐变层300之前，在凹槽200的底部附近区域进行重离子掺杂，从而形成重掺杂区域110，重掺杂区域110构成凹槽200的底壁以及靠近底部的部分侧壁，采用重离子掺杂形成的重掺杂区域110中形成空位或缺陷，从而能够对晶格失配的应力进行释放，使得凹槽200的槽壁与渐变层300之间形成更好的匹配。其中，进行重离子掺杂所采用的重离子包括锗、碳、氦中的至少一种。
在一实施例中，重掺杂区域110与第一结构层311接触，示例性地，第一结构层311的底面与重掺杂区域110的底部接触，第一结构层311的侧面与重掺杂区域110的侧面接触，从而对形成第一结构层311时因晶格失配而产生的应力进行释放。
根据本公开的一个示例性的实施例，在形成重掺杂区域110之后、形成渐变层300之前，还进行如下步骤：
S80、采用重离子对凹槽侧部附近的第三区域掺杂形成应力释放区域。
该步骤中，采用重离子对第三区域进行掺杂，从而在凹槽200的侧壁中形成空位或缺陷，从而在形成后续的结构层310时，能够对形成各结构层310时因晶格适配而产生的应力进行释放，从而使得凹槽200的槽壁与渐变层300之间形成更好的匹配。形成重掺杂区域110的重离子与形成应力释放区域的重离子可以相同，可以不同，示例性地，进行重离子掺杂所采用的重离子包括锗、碳、氦中的至少一种。
应力释放区域可以为一个整体筒形结构，从而将渐变层300中第一结构层311以上的各结构层整体包围，例如，在图3所示的实施例中，应力释放区域将第二结构层312和第三结构层313包围。在另外的实施例中，应力释放区域也可以为自凹槽200的底部向上排布的多个，每个应力释放区域对应一个结构层310，即每个应力释放区域分别与一个结构层310的侧壁接触。
应力释放区域的掺杂浓度可以与重掺杂区域110的掺杂浓度相同，也可以与重掺杂区域110的掺杂浓度不同。在一些实施例中，重掺杂区域110的掺杂浓度和与其接触的结构层310的掺杂浓度相匹配，应力释放区域的掺杂浓度和与其接触的结构层310的掺杂浓度相匹配，例如，与掺杂浓度较高的结构层对应的应力释放区域其掺杂浓度也相应较高，与掺杂浓度较低的结构层对应的应力释放区域其掺杂浓度也相应较低。
示例性地，渐变层300的多层结构层310包括依次层叠设置的第一结构层311、第二结构层312和第三结构层313，第二结构层312的掺杂浓度大于第一结构层311 的掺杂浓度，且大于第三结构层313的掺杂浓度。应力释放区域包括与第二结构层312对应的第一应力释放区域以及与第三结构层313对应的第二应力释放区域，即第一应力释放区域与第二结构层312的侧壁接触，第二应力释放区域与第三结构层313的侧壁接触。第一应力释放区域的掺杂浓度大于重掺杂区域的掺杂浓度，且大于第二应力释放区域的掺杂浓度。
由于第二结构层312的掺杂浓度较高，其与凹槽侧壁之间的晶格失配情况也相对较为严重，对应地，将与第二结构层312接触的第一应力释放区域的掺杂浓度设置地较大，从而在第一应力释放区域形成更多的空位或缺陷，进而释放因形成第二结构层312而产生应力。由于第一结构层311以及第三结构层313的掺杂浓度较低，其与凹槽底壁以及侧壁之间的晶格失配情况也相对较轻，对应地，将与第一结构层311接触的重掺杂区域、以及与第三结构层313接触的第二应力释放区域的掺杂浓度设置地较小，在保证应力释放(形成第一结构层311时产生的应力以及形成第三结构层313时产生的应力)的同时，避免产生的空位或缺陷过多而影响半导体结构的可靠性。
当然，可以理解的是，应力释放区域也可以是在形成了第一结构层之后掺杂形成，在应力释放区域包括多个时，各个应力释放区域的形成步骤也可以是穿插在结构层形成步骤之间。作为示例，在应力释放区域包括与第二结构层312接触的第一应力释放区域以及与第三结构层313接触的第二应力释放区域时，可以在形成第一结构层311之后，掺杂形成第一应力释放区域，并在形成第二结构层312之后，掺杂形成第二应力释放区域，再形成第三结构层313。
根据本公开一个示例性的实施例，提供了一种半导体结构的制作方法，该制作方法用于制作晶体管。该制作方法中，基底上形成有栅氧层和栅极，在形成凹槽之前，在栅氧层和栅极的两侧的基底上进行离子注入形成源极和栅极。在另一实施例中，也可以是在形成渐变层之后，在渐变层上进行离子注入形成源极和栅极。
本公开实施例所提供的半导体结构及其制备方法中，在基底的掺杂区域设置凹槽，并在凹槽内填充渐变层，渐变层的掺杂浓度自凹槽的底部向上逐渐变化，掺杂浓度逐渐变化的渐变层能够与凹槽的槽壁更好的匹配，在提高载流子迁移率的同时，减少因凹槽的槽壁与渐变层之间的晶格失配导致的漏电问题。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明 起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构及其制备方法中，在基底的掺杂区域设置凹槽，并在凹槽内填充渐变层，渐变层的掺杂浓度自凹槽的底部向上逐渐变化，掺杂浓度逐渐变化的渐变层能够与凹槽的槽壁更好的匹配，在提高载流子迁移率的同时，减少因凹槽的槽壁与渐变层之间的晶格失配导致的漏电问题。

Claims (20)

  1. 一种半导体结构，所述半导体结构包括：
    基底，所述基底包括掺杂区域；
    凹槽，所述凹槽位于所述掺杂区域；
    渐变层，所述渐变层填充所述凹槽，且所述渐变层的掺杂浓度自所述凹槽的底部向上逐渐变化。
  2. 根据权利要求1所述的半导体结构，其中，所述渐变层包括依次堆叠的多层结构层以及保护层，相邻所述结构层的掺杂浓度不同。
  3. 根据权利要求2所述的半导体结构，其中，所述多层结构层的掺杂浓度自所述凹槽的底部向上先增大后减小。
  4. 根据权利要求2所述的半导体结构，其中，所述多层结构层为多层硅锗层，所述保护层为硅层。
  5. 根据权利要求2所述的半导体结构，其中，每层所述结构层的厚度为2-10nm。
  6. 根据权利要求2所述的半导体结构，其中，所述半导体结构还包括导电层和金属层，所述保护层包括通孔，所述导电层填充所述通孔，所述金属层设置于所述导电层上，并与所述导电层电连接。
  7. 根据权利要求6所述的半导体结构，其中，所述导电层的材料包括硅化钴或者硅化镍；
    所述金属层的材料包括钨、铜、金或铝。
  8. 根据权利要求1或2所述的半导体结构，其中，所述掺杂区域包括重掺杂区域和轻掺杂区域，所述重掺杂区域和所述轻掺杂区域均位于所述凹槽的周边，且所述重掺杂区域更靠近所述凹槽底部。
  9. 一种晶体管，所述晶体管包括如权利要求1至8任一项所述的半导体结构，所述半导体结构位于所述晶体管的源极区域和漏极区域。
  10. 一种半导体结构的制作方法，所述半导体结构的制作方法包括：
    提供基底，所述基底具有掺杂区；
    在所述基底的掺杂区形成凹槽；
    形成渐变层，所述渐变层填充所述凹槽，且所述渐变层的掺杂浓度自所述凹槽的底部向上逐渐变化。
  11. 根据权利要求10所述的制作方法，其中，所述形成渐变层，包括：
    在所述凹槽内形成叠层结构，所述叠层结构包括堆叠设置的多层结构层，相邻所述结构层的掺杂浓度不同；
    形成保护层，所述保护层覆盖所述叠层结构，并将所述凹槽填平。
  12. 根据权利要求11所述的制作方法，其中，所述多层结构层的掺杂浓度自所述凹槽的底部向上先增大后减小。
  13. 根据权利要求11所述的制作方法，其中，所述在所述凹槽内形成叠层结构，包括：
    在所述凹槽内进行多轮外延生长，每一轮外延生长形成一层所述结构层。
  14. 根据权利要求11所述的制作方法，其中，所述多层结构层为多层硅锗层。
  15. 根据权利要求14所述的制作方法，其中，相邻的所述硅锗层之间的锗含量之差为1wt％至5wt％。
  16. 根据权利要求14所述的制作方法，其中，所述多层硅锗层中，靠近所述凹槽的槽底的所述硅锗层中的锗含量为25wt％至30wt％，锗含量最大的所述硅锗层中的锗含量为35wt％至40wt％，靠近所述凹槽的槽顶的所述硅锗层中的锗含量为25wt％至30wt％。
  17. 根据权利要求11所述的制作方法，其中，在形成渐变层之后，所述半导体结构的制作方法还包括：
    去除所述保护层的部分结构，以形成通孔，所述通孔暴露出所述叠层结构的部分顶面；
    在所述通孔内填充金属材料，并通过高温退火工艺使得所述金属材料与所述保护层的材料结合形成导电层；
    在所述导电层上形成金属层。
  18. 根据权利要求10至17任一项所述的制作方法，其中，在形成渐变层之前，所述半导体结构的制作方法还包括：
    采用重离子对位于所述凹槽底部附近的第二区域掺杂形成重掺杂区域。
  19. 根据权利要求18所述的制作方法，其中，所述重离子包括锗、碳、氦中的至少一种。
  20. 根据权利要求18所述的制作方法，其中，在所述基底上形成凹槽之前，所述半导体结构的制作方法还包括：
    对位于所述基底的表层的第一区域掺杂形成轻掺杂区域，所述重掺杂区域位于所述轻掺杂区域下方。
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