TWI596705B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TWI596705B TWI596705B TW105138221A TW105138221A TWI596705B TW I596705 B TWI596705 B TW I596705B TW 105138221 A TW105138221 A TW 105138221A TW 105138221 A TW105138221 A TW 105138221A TW I596705 B TWI596705 B TW I596705B
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- Prior art keywords
- gate
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- hard mask
- mask layer
- dielectric layer
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Description
本發明實施例係關於一種半導體技術,且特別是關於一種具有自對準接觸窗結構的半導體裝置及其製造方法。
半導體裝置係使用於各式各樣的電子應用產品中,例如個人電腦、手機、數位相機及其他電子設備。半導體裝置的製造通常依序藉由沉積絕緣或介電層、導電層及半導體材料層於一半導體基底上,並利用微影來圖案化各個不同的材料層,以在其上形成電路部件及元件。
半導體產業透過持續縮小最小特徵尺寸(其容許更多部件整合於一給定區域內)而不停地改進各個不同的電子部件(例如,電晶體、二極體、電阻器、電容器等等)的集積密度。
具體來說,當設計縮小時,連接至上方或下方膜層的導電特徵部件在誤對準的情形下可能發生短路。一般來說,上述情形發生於進行蝕刻製程穿過膜層發生誤對準,使導電特徵部件露出位於下方膜層上鄰近的導電特徵部件的一部分。
根據一些實施例,本揭露提供一種半導體裝置之
製造方法,包括:形成一第一閘極於一基底上方,第一閘極具有複數第一閘極間隙壁位於第一閘極的相對側壁上;形成一第一硬式罩幕層於第一閘極上方;形成一第二硬式罩幕層於第一硬式罩幕層上方,第二硬式罩幕層具有不同於第一硬式罩幕層的一材料組成;形成一第一介電層鄰近第一閘極且位於其上方;蝕刻出穿過第一介電層的一第一開口,以露出一部分的基底,至少一部分的第二硬式罩幕層露出於第一開口內;填入一導電材料於第一開口內;以及去除第二硬式罩幕層以及去除導電材料與第一介電層位於第一硬式罩幕層上方的部分,以形成一第一導電接觸窗於餘留的第一介電層內。
根據一些實施例,本揭露提供一種半導體裝置之製造方法,包括:形成一第一金屬閘極及一第二金屬閘極於一基底上方,第一金屬閘極及第二金屬閘極各自具有複數閘極間隙壁位於對應的金屬閘極的相對側壁上;形成一第一介電層於基底上方且鄰近第一金屬閘極及第二金屬閘極;下凹第一金屬閘極及第二金屬閘極,使其具有上表面低於第一介電層的上表面;形成一第一硬式罩幕層於下凹的第一金屬閘極及第二金屬閘極的上表面上方;下凹第一硬式罩幕層,使其具有上表面低於第一介電層的上表面;形成一第二硬式罩幕層於下凹的第一硬式罩幕層的上表面上方,第二硬式罩幕層具有不同於第一硬式罩幕層的一材料組成;以及平坦化第二硬式罩幕層,使其具有上表面與第一介電層的上表面為共平面。
根據一些實施例,本揭露提供一種半導體裝置,包括:一第一閘極堆疊,位於一基底上,第一閘極堆疊包括一
第一高介電常數閘極介電層及一第一金屬閘極電極;一第一硬式罩幕層,位於第一閘極堆疊上;一第一組閘極間隙壁,位於第一閘極堆疊及第一硬式罩幕層的相對側壁上;一第一蝕刻停止層,位於第一組閘極間隙壁的側壁上;一第一內層介電層,圍繞第一蝕刻停止層及第一閘極堆疊,第一內層介電層接觸至少一部分的第一蝕刻停止層;一第一導電接觸窗,延伸穿過第一內層介電層,以接觸基底的上表面,第一導電接觸窗具有側壁與第一蝕刻停止層的側壁接觸;一第二蝕刻停止層,位於第一蝕刻停止層、第一組閘極間隙壁、第一硬式罩幕層及第一內層介電層的上表面上方,且與其接觸;一第二內層介電層,位於第二蝕刻停止層上方;以及一第二導電接觸窗,延伸穿過第二內層介電層及第二蝕刻停止層,以接觸第一導電接觸窗。
20‧‧‧基底
20S‧‧‧表面
22‧‧‧虛置閘極介電層
24‧‧‧虛置閘極電極
24S、26T、32S、34S、38S、40S、46S‧‧‧上表面
26‧‧‧閘極間隙壁
26S‧‧‧內表面
28、28A、28B‧‧‧閘極堆疊
30‧‧‧源極/汲極區
30S‧‧‧表面
32、62‧‧‧蝕刻停止層
34、54、64‧‧‧內層介電(ILD)層
36‧‧‧凹口
38‧‧‧閘極介電層
40‧‧‧閘極電極
42、42A、42B‧‧‧取代閘極
44、50‧‧‧凹口
46‧‧‧第一硬式罩幕層
48‧‧‧縫隙及/或孔洞
52‧‧‧第二硬式罩幕層
56‧‧‧硬式罩幕層
58A、58B、58C‧‧‧開口
60、66‧‧‧導電層
60A、60A1、60A2、60B、60C、66A1、66A2、66B、66C‧‧‧導電特徵部件/接觸窗
第1至16圖係繪示出根據本揭露一些實施例之半導體裝置製造方法的中間階段剖面示意圖。
以下的揭露內容提供許多不同的實施例或範例,以實施本發明的不同特徵部件。而以下的揭露內容是敘述各個構件及其排列方式的特定範例,以求簡化本揭露內容。當然,這些僅為範例說明並非用以限定本發明。舉例來說,若是以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方,即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例,亦包含了尚可將附加的
特徵部件形成於上述第一特徵部件與上述第二特徵部件之間,而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。另外,本揭露內容在各個不同範例中會重複標號及/或文字。重複是為了達到簡化及明確目的,而非自行指定所探討的各個不同實施例及/或配置之間的關係。
再者,在空間上的相關用語,例如”之下”、”下方”、”下”、”上方”、”上”等等在此處係用以容易表達出本說明書中所繪示的圖式中元件或特徵部件與另外的元件或特徵部件的關係。這些空間上的相關用語除了涵蓋圖式所繪示的方位外,還涵蓋裝置於使用或操作中的不同方位。此裝置可具有不同方位(旋轉90度或其他方位)且此處所使用的空間上的相關符號同樣有相應的解釋。
以下將要說明的實施例係有關於特定的背景,亦即二個膜層之間的自對準設計。然而,也可應用於其他實施例,以對準三或多個膜層。在一些實施例中,自對準結構利用位於下方膜層的導電特徵部件上方的多層罩幕層來保護導電特徵部件在進行接觸開口蝕刻製程期間不會意外露出。在一些實施例中,多層罩幕層的至少一者為金屬氮化物或金屬氧化物罩幕層,並在進行接觸開口蝕刻製程期間提供足夠的保護與蝕刻選擇性。
此處所討論的一些實施例係以使用後閘極(gate-last)製程形成的場效電晶體(field-effect transistor,FET)為背景。在其他實施例中,也可使用先閘極(gate-first)製程。同樣地,一些實施例型態係用於平面式裝置,例如平面
式FET,或鰭式裝置,例如FinFET。
請參照第1圖,第1圖繪示出一基底20、虛置閘極堆疊28A及28B以及源極/汲極區30。基底20可為一半導體基底,例如塊材半導體、一絕緣層覆矽(silicon-on-insulator,SOI)基底等等,其可為摻雜(例如,具有p型或n型摻雜物)或未摻雜。基底20可為一晶圓,例如矽晶圓。一般來說,一SOI基底包括一半導體材料層形成於一絕緣層上。上述絕緣層可為埋入式氧化(buried oxide,BOX)層、一氧化矽層等等。絕緣層形成於一基底(通常為矽或玻璃基底)上。也可採用其他基底,例如多層或漸變(gradient)基底。在一些實施例中,基底20的半導體材料可包括矽、鍺、化合物半導體(包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、合金半導體(包括鍺化矽(SiGe)、磷砷化鎵(GaAsP)、砷銦化鋁(AlInAs)、砷鎵化鋁(AlGaAs)、砷銦化鎵(GaInAs)、磷銦化鎵(GaInP)及/或磷砷銦化鎵(GaInAsP)或其組合。
基底20內可形成適當的井區。舉例來說,一P型井區可形成於基底20的一第一區內,而一N型井區可形成於基底20的一第二區內。
用於不同井區的不同佈植步驟可使用光阻或其他罩幕(未繪示)來進行。舉例來說,形成並圖案化一光阻以露出基底20待佈植的區域。可利用旋塗(spin-on)技術形成上述光阻並透過可接受的微影技術而圖案化上述光阻。一旦圖案化光阻之後,可於露出區域內進行n型摻雜物及/或p型摻雜物佈植,而光阻作為一罩幕,以大體上防止摻雜物進入遮蔽區。n
型摻雜物可為磷、砷等等,植入於第一區至濃度等於或小於1018cm-3,例如在1017cm-3至1018cm-3的範圍。p型摻雜物可為硼、BF2等等,植入於第一區至濃度等於或小於1018cm-3,例如在1017cm-3至1018cm-3的範圍。在完成佈植之後,藉由可接受的灰化製程去除光阻。
在進行井區的佈植之後,可進行退火以活化所植入的p型及/或n型摻雜物。在一些實施例中,基底20可包括磊晶成長區,其可於成長期間進行原位(in situ)摻雜而免除進行佈植。然而也可一起使用原位摻雜及佈植。
基底20可包括主動及被動裝置(未繪示於第1圖)。如所屬領域具有通常知識者所知的各種不同的裝置,諸如電晶體、電容器、電阻器或其組合或相似裝置,可用於產生半導體裝置的結構及功能需求。可使用任何適當方法形成這些裝置。圖式中僅繪示出一部分的基底20,其足以充分說明所述的實施例。
基底20也可包括金屬化層(未繪示)。金屬化層可形成於主動及被動裝置上方且設計成連接不同的裝置以形成功能性電路。金屬化層可由交替的介電層(例如,低介電常數介電材料)與導電材料(例如,銅)所構成,且可經由任何適當的方法(諸如,沉積、鑲嵌、雙鑲嵌等等)形成。
在一些實施例中,基底20可為一或多個鰭部,其自相鄰的隔離區之間突出於其上方。舉例來說,第1圖的剖面可為沿著一鰭部的縱軸。這些一或多個鰭部可形成於不同的製程中。在一範例中,鰭部的製作可藉由在基底中蝕刻出溝槽以
形成半導體條帶;這些溝槽可填入介電層;以及可下凹介電層,使半導體條帶自介電層突出而形成鰭部。在另一範例中,一介電層可形成於一基底的上表面上;可經由蝕刻介電層而形成溝槽;可在溝槽內進行磊晶成長而形成同質磊晶結構;以及下凹介電層,使同質磊晶結構自介電層突出而形成鰭部。又另一範例中,同質磊晶結構可用於鰭部。舉例來說,可下凹半導體條帶,並可在其位置內磊晶成長不同於半導體條帶的一材料。又另一範例中,一介電層可形成於一基底的上表面上;可經由蝕刻介電層而形成溝槽;可使用不同於基底的材料在溝槽內進行磊晶成長而形成同質磊晶結構;以及下凹介電層,使同質磊晶結構自介電層突出而形成鰭部。在進行同質磊晶結構或異質磊晶結構的磊晶成長的一些實施例中,成長期間可對成長材料進行原位摻雜,其免除了先行或於後續進行佈植。然而也可一起使用原位摻雜及佈植。再者,在NMOS區磊晶成長的材料不同於在PMOS區磊晶成長的材料是有利的。在不同的實施例中,鰭部可包括鍺化矽(SixGe1-x,其中x可介於0至100之間)、碳化矽、純鍺或實質上為純鍺、三五族化合物半導體、二四族化合物半導體等等。舉例來說,形成三五族化合物半導體的可用材料包括但不限於InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP等等。
閘極堆疊28(包括28A及28B)形成於基底20上方。閘極堆疊28可包括一虛置閘極介電層22、一硬式罩幕(未繪示)以及一虛置閘極電極24。虛置閘極介電材料層(未繪示)可藉由熱氧化、化學氣相沉積(chemical vapor deposition,CVD)、
濺鍍、或任何其他用以形成閘極介電材料的習知及習用方法而形成。在一些實施例中,虛置閘極介電材料層包括具有高介電常數(k值)的介電材料,例如大於3.9。虛置閘極介電材料包括氮化矽、氮氧化矽(諸如HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx等等)或其組合或其多層結構。
虛置閘極電極層(未繪示)可形成於虛置閘極介電材料層上方。虛置閘極電極層可包括一導電材料且可選自包括多晶矽(polysilicon)、多晶鍺化矽(poly-SiGe)、金屬氮化物、金屬矽化物、金屬氧化物及金屬的群組。在一實施例中,沉積非晶矽並經再結晶而形成多晶矽。虛置閘極電極層可藉由物理氣相沉積(physical vapor deposition,PVD)、CVD、濺鍍沉積或其他用以形成閘極電極層的習知及習用技術而形成。在沉積之後,虛置閘極電極層的上表面通常為非平坦的上表面且可在圖案化虛置閘極電極層或進行閘極蝕刻之前進行平坦化,例如進行化學機械研磨(chemical mechanical polishing,CMP)製程。此時可將或不將離子導入虛置閘極電極層內。舉例來說,可藉由離子佈植技術將離子導入。
硬式罩幕層(未繪示)形成於虛置閘極電極層上方。硬式罩幕層可由SiN、SiON、SiO2等等或其組合所製成。接著圖案化硬式罩幕層。硬式罩幕層的圖案化可藉由沉積罩幕材料(未繪示)(例如,光阻)於硬式罩幕層上而形成。接著圖案化罩幕材料,並依據圖案蝕刻硬式罩幕層以形成硬式罩幕。可圖案化虛置閘極電極層及虛置閘極介電材料層以分別形成虛置閘極電極24及虛置閘極介電層22。閘極圖案化製程可藉
由使用硬式罩幕為圖案並蝕刻虛置閘極電極層及虛置閘極介電材料層來進行而形成閘極堆疊28。
在形成閘極堆疊28之後,可在基底20內形成源極/汲極區30。源極/汲極區30可藉由進行佈植製程來進行摻雜,以植入適當的摻雜物而在基底20內補充摻雜物。在另一實施例中,源極/汲極區30可藉由在基底20內形成凹口(未繪示)並於凹口內磊晶成長一材料而形成。可經由上述佈植方法或在成長上述材料時進行原位摻雜進行源極/汲極區30摻雜。在此實施例中,磊晶源極/汲極區30可包括任何可接受的材料,例如適用於n型FET及/或p型FET。舉例來說,在n型配置中,若基底20為矽,磊晶源極/汲極區30可包括矽、SiC、SiCP、SiP等等。舉例來說,在n型配置中,若基底20為矽,磊晶源極/汲極區30可包括SiGe、SiGeB、Ge、GeSn等等。磊晶源極/汲極區30可具有上升於基底20上表面之上的表面,且可具有晶面(facet)。
在一實施例中,閘極堆疊28及源極/汲極區30可形成電晶體,例如金屬-氧化物-半導體FET(MOSFET)。在這些實施例中,MOSFET的配置可為PMOS配置或NMOS配置。在PMOS配置中,基底20摻雜n型摻雜物,而源極/汲極區30摻雜p型摻雜物。在NMOS配置中,基底20摻雜p型摻雜物,而源極/汲極區30摻雜n型摻雜物。
閘極間隙壁26形成於閘極堆疊28的相對側。閘極間隙壁26藉由毯覆式沉積一間隔層(未繪示)於先前形成的閘極堆疊28而形成。在一實施例中,閘極間隙壁26包括一間隔襯層(spacer liner)(未繪示)。間隔襯層可由SiN、SiC、SiGe、
氮氧化物、氧化物等等或其組合。間隔層可包括SiN、氮氧化物、SiC、SiON、氧化物等等或或其組合,且可藉由用以形成上述膜層的方法而形成,諸如CVD、電漿輔助CVD(plasma enhanced CVD,PECVD)、低壓CVD(low-pressure CVD,LPCVD)、原子層沉積(atomic layer deposition,ALD)、濺鍍等等或或其組合。接著圖案化閘極間隙壁26,例如藉由異向性蝕刻自水平表面(例如閘極堆疊28的上表面及基底20的上表面)去除間隔層。
在另一實施例中,源極/汲極區30可包括一輕摻雜區(有時稱為LDD區)及一重摻雜區。在此實施例中,在形成閘極間隙壁26之前,利用閘極堆疊28作為罩幕進行佈植製程,以對源極/汲極區30進行輕摻雜。在形成閘極間隙壁26之後,利用閘極堆疊28及閘極間隙壁26作為罩幕進行佈植製程,以對源極/汲極區30進行重摻雜。上述佈植製程形成了輕摻雜區及重摻雜區。輕摻雜區主要位於閘極間隙壁26下方,而重摻雜區沿著基底20位於閘極間隙壁26外側。
儘管上述說明閘極堆疊28的製作,但上述結構不限於閘極結構。在一些實施例中,上述結構可為導線,其藉由後續形成導電特徵部件而對準且耦接於其他導電特徵部件。
如第1圖所示,閘極堆疊28B具有一寬度,其大於虛置閘極堆疊28A的寬度。另外,閘極堆疊28B與最靠近的虛置閘極堆疊28A之間的間距大於虛置閘極堆疊28A彼此之間的間距。這些不同類型的閘極堆疊28的位置表示出所述實施例的各種不同配置,且各種不同的閘極堆疊28的位置並不限於這些
位置。
第2圖繪示出在基底20、閘極堆疊28、閘極間隙壁26及源極/汲極區30上方形成一蝕刻停止層32。蝕刻停止層32可順應性沉積於基底20上的部件上方。在一些實施例中,蝕刻停止層32可為氮化矽、碳化矽、氧化矽、低介電常數介電材料(例如,碳摻雜氧化物)、超低介電常數介電材料(例如,多孔碳摻雜二氧化矽)等等或其組合,且可藉由CVD、PVD、ALD、旋塗介電(spin-on dielectric,SOD)製程等等或其組合來進行沉積。
在第3圖中,一內層介電(interlayer dielectric,ILD)層134沉積於第2圖所示的結構上方。在一實施例中,ILD層34為藉由流動式CVD(flowable CVD)所形成的流動的膜層。在一些實施例中,ILD層34由氧化物所構成,例如氧化矽、磷摻雜矽玻璃(PSG)、硼摻雜矽玻璃(BSG)、硼摻雜磷矽玻璃(BPSG)、未摻雜矽玻璃(USG)、低介電常數介電材料(例如,碳摻雜氧化物)、超低介電常數介電材料(例如,多孔碳摻雜二氧化矽)、高分子(例如,聚醯亞胺(polyimide))等等或其組合。低介電常數介電材料的k值小於3.9。可藉由適當的方法來沉積ILD層34,諸如CVD、ALD、SOD製程等等或其組合來進行沉積。
又在第3圖中,可進行一平坦化製程,例如CMP製程,使ILD層34的上表面34S切齊於虛置閘極電極24的上表面24S與蝕刻停止層32的上表面32S。虛置閘極電極24上方若存在硬式罩幕,上述CMP製程也可將其去除。因此,虛置閘極電極
24的上表面24S露出於ILD層34。
在第4圖中,虛置閘極電極24及位於虛置閘極電極24正下方的虛置閘極介電層22去除於蝕刻步驟中而形成凹口36。在形成MOSFET的實施例中每一凹口36露出對應的FET的通道區。每一通道區設置於相鄰的成對的源極/汲極區30之間。在去除期間,當蝕刻虛置閘極電極24時,虛置閘極介電層22可作為一蝕刻停止層。於去除虛置閘極電極24之後接著去除虛置閘極介電層22。藉由基底20的露出表面20S及閘極間隙壁26的露出內表面26S而定義出凹口36。
在第5圖中,形成閘極介電層38及閘極電極40作為取代閘極。閘極介電層38順應性沉積於凹口36內,例如基底20的上表面及閘極間隙壁26的側壁以及ILD層34的上表面。根據一些實施例,閘極介電層38包括氧化矽、氮化矽或其多層結構。在其他實施例中,閘極介電層38包括高介電常數介電材料,且在這些實施例中,閘極介電層38可具有一k值大於7.0,且可包括由Hf、Al、Zr、La、Mg、Ba、Ti、Pb即其組合所構成的金屬氧化物或矽化物。閘極介電層38的製造方法可包括分子束沉積(molecular-beam deposition,MBD)、ALD、PECVD等等。
接著,閘極電極40分別沉積於閘極介電層38上方且填入凹口36的剩餘部分。閘極電極40可由含金屬材料所構成,諸如TiN、TaN、TaC、Co、Ru、Al或其組合或其多層結構。在填入閘極電極40之後,進行依平坦化製程,例如CMP製程,以去除閘極介電層38及閘極電極40的多餘部分,多餘部分係位
於ILD層34的上表面。最終閘極介電層38及閘極電極40的餘留部分形成取代閘極42(包括取代閘極42A及42B)。
在具有NMOS裝置及PMOS裝置兩者於基底20上的一互補式MOS(CMOS)實施例中,可同時形成閘極介電層38於PMOS區及NMOS區兩者內,使位於PMOS區及NMOS區兩者內的閘極介電層38由相同材料所構成,且可同時形成閘極電極40於PMOS區及NMOS區兩者內,使位於PMOS區及NMOS區兩者內的閘極電極40由相同材料所構成。然而,在其他實施例中,可藉由不同製程於NMOS區及PMOS區內形成閘極介電層38,使位於NMOS區及PMOS區內的閘極介電層38由不同材料所構成,且可藉由不同製程於NMOS區及PMOS區內形成閘極電極40,使位於NMOS區及PMOS區內的閘極電極40由不同材料所構成。當使用不同製程時,不同的遮蔽步驟可用於遮蔽或露出適當區域。
在第6圖中,在蝕刻步驟中下凹閘極電極40及閘極介電層38,以形成凹口44。凹口44容許於後續形成的硬式罩幕形成於凹口44內,以保護取代閘極42。凹口44由閘極間隙壁26的露出內表面26S、閘極電極40及閘極介電層38各自的下凹上表面40S及38S所定義出。
再者,凹口44的下表面可具有一平坦表面(如圖所示)、一凸面、一凹面(例如,碟化)或其組合。凹口44的下表面可藉由適當的蝕刻而形成平坦、向上凸及/或向下凹。可藉由可接受的蝕刻製程來下凹閘極電極40及閘極介電層38,例如一種會選擇閘極電極40及閘極介電層38的材料。
在第7圖中,一第一硬式罩幕層46形成於ILD層34上及閘極電極40及閘極介電層38上方凹口44內。第一硬式罩幕層46可由SiN、SiON、SiO2等等或其組合所構成。第一硬式罩幕層46可由CVD、PVD、ALD、SOD製程等等或其組合所形成。形成位於凹口44內的第一硬式罩幕層46可能會在較小的技術世代,例如10nm或以下的世代中,因凹口深寬比造成縫隙及/或孔洞48形成於第一硬式罩幕層46內。這些縫隙及/或孔洞48成為第一硬式罩幕層46內的弱點,其可能造成閘極電極40及/或閘極介電層38於後續蝕刻製程期間不小心露出。
第8圖繪示出下凹第一硬式罩幕層46以形成凹口50。在一些實施例中,下凹第一硬式罩幕層46、蝕刻停止層32及閘極間隙壁32,使第一硬式罩幕層46、蝕刻停止層32及閘極間隙壁26各自的上表面46S、32S及26T低於ILD層34的上表面34S。在一些實施例中,下凹第一硬式罩幕層46完全去除了位於第一硬式罩幕層46內的縫隙及/或孔洞48,且在其他實施例中,在進行下凹製程後,殘留至少一部分的縫隙及/或孔洞48。
再者,凹口50的下表面可具有一平坦表面(如圖所示)、一凸面、一凹面(例如,碟化)或其組合。凹口50的下表面可藉由適當的蝕刻而形成平坦、向上凸及/或向下凹。可藉由可接受的蝕刻製程來下凹第一硬式罩幕層46,例如一種會選擇第一硬式罩幕層46、蝕刻停止層32及閘極間隙壁26的材料。舉例來說,蝕刻製程可包括利用電漿形成來自蝕刻氣體的反應性物種(reactive species)。在一些實施例中,電漿可為遠距(remote)電漿。蝕刻氣體可包括氟碳化學,諸如
C4F6/CF4/CF5及NF3/O2/N2/Ar/H3/H2等等或其組合。在一些實施例中。蝕刻氣體可提供至蝕刻反應室,總氣體流量約在100至1000sccm的範圍。在一些實施例中,進行蝕刻製程期間蝕刻反應室的壓力約在10mtorr至50mtorr的範圍。在一些實施例中,蝕刻氣體可包括約在10%至90%的範圍的氫氣。在一些實施例中,蝕刻氣體可包括約在20%至80%的範圍的惰性氣體。
在第9圖中,一第二硬式罩幕層52形成於第一硬式罩幕層46、閘極間隙壁26、蝕刻停止層32及ILD層34上方,且位於凹口50內。第二硬式罩幕層52於後續自對準接觸窗蝕刻(請參照第12圖)期間提供對第一硬式罩幕層46、閘極間隙壁26、蝕刻停止層32的保護,以確保自對準接觸窗不會使其中一閘極電極40與對應的源極/汲極區30發生短路。第二硬式罩幕層52可由金屬、金屬氧化物、金屬氮化物、純矽等等或其組合所構成。金屬氧化物及金屬氮化物的一些範例為TiO、HfO、AlO、ZrO、ZrN等等或其組合。第二硬式罩幕層52的材料組成很重要,因其確保高膜密度及非揮發蝕刻副產品,例如金屬氟化物蝕刻副產品。再者,可用於第二硬式罩幕層52的材料多於可用於第一硬式罩幕層46的材料,因為後續將會去除第二硬式罩幕層52(請參照第15圖),因此這些材料將不會影響後續的製程。第二硬式罩幕層52可由CVD、PVD、ALD、SOD製程等等或其組合所形成。
在第10圖中,可進行一平坦化製程,例如CMP製程,使ILD層34的上表面34S切齊於第二硬式罩幕層52的上表面52S。因此,露出ILD層34的上表面34S。
在第11圖中,一ILD層54沉積於第10圖的結構上方。在一實施例中,ILD層54為藉由流動式CVD所形成的流動的膜層。在一些實施例中,ILD層54由氧化物所構成,例如氧化矽、磷摻雜矽玻璃(PSG)、硼摻雜矽玻璃(BSG)、硼摻雜磷矽玻璃(BPSG)、未摻雜矽玻璃(USG)、低介電常數介電材料(例如,碳摻雜氧化物)、超低介電常數介電材料(例如,多孔碳摻雜二氧化矽)、高分子(例如,聚醯亞胺)等等或其組合。低介電常數介電材料的k值小於3.9。可藉由適當的方法來沉積ILD層54,諸如CVD、ALD、SOD製程等等或其組合來進行沉積。在一些實施例中,ILD層54可藉由CMP製程或蝕刻製程來進行平坦化,以形成一大體上平坦的上表面。
又在第11圖中,一硬式罩幕層56形成於ILD層54上方並圖案化。硬式罩幕層56可由SiN、SiON、SiO2等等或其組合所製成。硬式罩幕層56可由CVD、PVD、ALD、SOD製程等等或其組合所形成。接著圖案化硬式罩幕層56。硬式罩幕層56的圖案化可藉由沉積罩幕材料(未繪示)(例如,光阻)於硬式罩幕層56上而形成。接著圖案化罩幕材料,並依據圖案蝕刻硬式罩幕層56而形成圖案化的硬式罩幕層56。
第12圖繪示出以圖案化的硬式罩幕層56作為罩幕形成穿過ILD層54及ILD層34的開口58A及58B而露出部分的基底20。在繪示的實施例中,開口58A及58B露出源極/汲極區30的部分表面30S,且在其他實施例(不存在源極/汲極區30)中,開口58A及58B可露出其他特徵部件,例如位於基底20內的金屬特徵部件。雖然部分的開口58A延伸於閘極堆疊42A上表面
上,但第二硬式罩幕層52及蝕刻停止層32將相鄰的成對的閘極堆疊42A之間的開口58A自對準於基底20。在繪示的實施例中,當閘極堆疊42B與最靠近的閘極堆疊42A之間的間距大於閘極堆疊42A彼此之間的間距時,開口58B並未自對準,且自對準開口無須用於上述較大的間距中。開口58A及58B可利用可接受的蝕刻技術而形成。在一實施例中,開口58A及58B以異向性乾蝕刻製程形成。舉例來說,蝕刻製程可包括一乾蝕刻製程,其使用的反應氣體選擇性蝕刻ILD層54及34而不蝕刻第二硬式罩幕層52。舉例來說,蝕刻製程可包括利用電漿形成來自蝕刻氣體的反應性物種。在一些實施例中,電漿可為遠距電漿。蝕刻氣體可包括氟碳化學,諸如C4F6/CF4/CF5及NF3/O2/N2/Ar/H3/H2等等或其組合。在一些實施例中。蝕刻氣體可提供至蝕刻反應室,總氣體流量約在100至1000sccm的範圍。在一些實施例中,進行蝕刻製程期間蝕刻反應室的壓力約在10mtorr至50mtorr的範圍。第二硬式罩幕層52好比作為一蝕刻停止層且有利於防止下方特徵部件(例如,閘極間隙壁26、第一硬式罩幕層46及閘極堆疊42)受損,即使發生圖案化誤對準的錯誤。缺少第二硬式罩幕層52,閘極間隙壁26、第一硬式罩幕層46及閘極堆疊42可能因蝕刻製程而在無意中受損。在一些實施例中,用於自對準開口58A的蝕刻製程可去除些許的第二硬式罩幕層52的上部,但不會完全蝕穿第二硬式罩幕層52,因而使第一硬式罩幕層46、閘極間隙壁26及蝕刻停止層32的覆蓋部分在蝕刻期間受到保護。
在第13圖中,進一步圖案化蝕刻硬式罩幕層56,
並利用圖案化的硬式罩幕層56作為罩幕而形成穿過ILD層54、閘極堆疊42B上方的第二蝕刻硬式罩幕層52以及閘極堆疊42B上方的第一蝕刻硬式罩幕層46的開口58C,以露出閘極堆疊42B的閘極電極40的部分表面40S。硬式罩幕層56的圖案化可藉由沉積罩幕材料(未繪示)(例如,光阻)於硬式罩幕層56上而形成。接著圖案化罩幕材料,並依據圖案蝕刻硬式罩幕層56而形成圖案化的硬式罩幕層56。罩幕材料可在形成開口58C期間留於開口58A及58B上方,以保護開口58A及58B內的結構。在繪示的實施例中,開口58C不為自對準。開口58C可藉由可接受的蝕刻技術形成。在一實施例中,開口58C可藉由異向性乾蝕刻製程形成。
第14圖繪示出在開口58A、58B及58C內形成一導電層60。開口58A內的導電層60接觸基底20的露出表面,並沿著蝕刻停止層32、ILD層34及54及第二硬式罩幕層52的露出表面。開口58B內的導電層60接觸基底20的露出表面,並沿著蝕刻停止層32及ILD層34及54的露出表面。在繪示的實施例中,開口58A及58B內的導電層60接觸源極/汲極區30的露出表面,且在其他實施例(不存在源極/汲極區30)中,開口58A及58B內的導電層60接觸其他特徵部件,例如位於基底20內的金屬特徵部件。開口58C內的導電層60接觸閘極堆疊42B的閘極電極40的露出表面,並沿著第一及第二硬式罩幕層46及52及ILD層54的露出表面。
在一些實施例中,導電層60包括一阻障層(未繪示)。阻障層有助於阻擋後續形成的導電層60擴散於相鄰的介
電材料(例如,ILD層34及54)內。阻障層可由鈦、氮化鈦、鉭、氮化鉭、錳、氧化錳、鈷、氧化鈷、氮化鈷、鎳、氧化鎳、氮化鎳、碳化矽、氧摻雜碳化矽、氮摻雜碳化矽、氮化矽、氧化鋁、氮化鋁、氮氧化鋁、高分子(例如,聚醯亞胺)、聚苯噁唑(polybenzoxazole,PBO)等等或其組合。可藉由適當的方法來沉積阻障層,諸如CVD、PVD、PECVD、ALD、SOD等等或其組合。在一些實施例中,可省略阻障層。
導電層60可由鎢、銅、鋁等等或其組合所構成。導電層60可經由沉積製程而形成,諸如電化學電鍍、PVD、CVD等等或其組合。在一些實施例中,導電層60形成於一含銅晶種層(例如,AlCu)上。
在一些實施例中,形成的導電層60具有多餘的材料位於ILD層54的上表面。在這些實施例中,藉由研磨製程(例如,CMP製程)對導電層60進行平坦化以分別於開口58A、58B及58C內形成導電特徵部件60A、60B及60C。在一些實施例中,在進行平坦化製程之後,導電特徵部件60A、60B及60C的上表面切齊於ILD層54的上表面。
第15圖繪示出去除ILD層54、第二硬式罩幕層52及ILD層34與導電特徵部件60A、60B及60C位於第一硬式罩幕層46上表面上方的部分。上述之去除可藉由一或多道蝕刻製程及/或研磨製程(例如,CMP製程)來進行。在進行去除製程之後,導電特徵部件60A被分離成導電特徵部件60A1及60A2,且導電特徵部件60C埋入位於閘極堆疊42B上的第一硬式罩幕46內。另外,在進行去除製程之後,導電特徵部件60A1、60A2、
60B及60C的上表面切齊於ILD層34及第一硬式罩幕46的上表面。
第16圖繪示出形成一蝕刻停止層62於第15圖的結構上。蝕刻停止層62形成於ILD層34、蝕刻停止層32、第一蝕刻罩幕層46及閘極間隙壁26上方。蝕刻停止層62可順應性沉積於這些部件上方。在一些實施例中,蝕刻停止層62可為氮化矽、碳化矽、氧化矽、低介電常數介電材料(例如,碳摻雜氧化物)、超低介電常數介電材料(例如,多孔碳摻雜二氧化矽)等等或其組合,且可藉由CVD、PVD、ALD、SOD製程等等或其組合來進行沉積。
再者,在第16圖中,一ILD層64沉積於蝕刻停止層62上方。在一實施例中,ILD層64為藉由流動式CVD所形成的流動的膜層。在一些實施例中,ILD層64由氧化物所構成,例如氧化矽、磷摻雜矽玻璃(PSG)、硼摻雜矽玻璃(BSG)、硼摻雜磷矽玻璃(BPSG)、未摻雜矽玻璃(USG)、低介電常數介電材料(例如,碳摻雜氧化物)、超低介電常數介電材料(例如,多孔碳摻雜二氧化矽)、高分子(例如,聚醯亞胺)等等或其組合。低介電常數介電材料的k值小於3.9。可藉由適當的方法來沉積ILD層64,諸如CVD、ALD、SOD製程等等或其組合來進行沉積。
又在第16圖中,形成的接觸窗66A1、66A2、66B及66C穿過ILD層64及蝕刻停止層62,以電性且實體接觸對應的導電特徵部件(接觸窗)60A1、60A2、60B及60C。用於接觸窗66A1、66A2、66B及66C的開口可藉由可接受的蝕刻技術形
成。在一實施例中,藉由異向性乾蝕刻形成開口。於這些開口填入一導電層66。在一些實施例中,導電層66包括一阻障層(未繪示)。阻障層有助於阻擋後續形成的導電層66擴散於相鄰的介電材料(例如,ILD層64及蝕刻停止層62)內。阻障層可由鈦、氮化鈦、鉭、氮化鉭、錳、氧化錳、鈷、氧化鈷、氮化鈷、鎳、氧化鎳、氮化鎳、碳化矽、氧摻雜碳化矽、氮摻雜碳化矽、氮化矽、氧化鋁、氮化鋁、氮氧化鋁、高分子(例如,聚醯亞胺)、聚苯噁唑(PBO)等等或其組合。可藉由適當的方法來沉積阻障層,諸如CVD、PVD、PECVD、ALD、SOD等等或其組合。在一些實施例中,可省略阻障層。
導電層66可由鎢、銅、鋁等等或其組合所構成。導電層60可經由沉積製程而形成,諸如電化學電鍍、PVD、CVD等等或其組合。在一些實施例中,導電層66形成於一含銅晶種層(例如,AlCu)上。
在一些實施例中,形成的導電層66具有多餘的材料位於ILD層64的上表面。在這些實施例中,藉由研磨製程(例如,CMP製程)對導電層66進行平坦化以形成接觸窗(導電特徵部件)66A1、66A2、66B及66C。在一些實施例中,在進行平坦化製程之後,導電特徵部件66A1、66A2、66B及66C的上表面切齊於ILD層64的上表面。
本揭露的實施例可獲得諸多優點,亦即位於二個膜層之間的自對準接觸窗結構能夠保護下方特徵部件。在一些實施例中,自對準結構利用位於下方膜層的導電特徵部件上方的多層罩幕層來保護導電特徵部件在進行接觸開口蝕刻製程
期間不會意外露出。在一些實施例中,多層罩幕層的至少一者為金屬氮化物或金屬氧化物罩幕層,並在進行接觸開口蝕刻製程期間提供足夠的保護與蝕刻選擇性。在具有二個硬式罩幕層的FET實施例中,上層硬式罩幕層由金屬氮化物或金屬氧化物所構成,確保自對準接觸窗不會使其中一閘極電極與對應的源極/汲極區發生短路。另外,在一些實施例中,在提供上層硬式罩幕層之前,先下凹下層硬式罩幕層,上述下凹下層硬式罩幕層可大體上(若未完全地)去除位於下層硬式罩幕層內的任何縫隙及/或孔洞。再者,上層硬式罩幕層的材料組成很重要,因其確保高膜密度及非揮發蝕刻副產品,例如金屬氟化物蝕刻副產品。再者,可用於上層硬式罩幕層的材料多於可用於下層硬式罩幕層的材料,因為後續將會去除上層硬式罩幕層,因此其材料將不會影響後續的製程。
根據一實施例,一種半導體裝置之製造方法,包括:形成一第一閘極於一基底上方,第一閘極具有複數第一閘極間隙壁位於第一閘極的相對側壁上;形成一第一硬式罩幕層於第一閘極上方;形成一第二硬式罩幕層於第一硬式罩幕層上方,第二硬式罩幕層具有不同於第一硬式罩幕層的一材料組成;形成一第一介電層鄰近第一閘極且位於其上方;蝕刻出穿過第一介電層的一第一開口,以露出一部分的基底,至少一部分的第二硬式罩幕層露出於第一開口內;填入一導電材料於第一開口內;以及去除第二硬式罩幕層以及去除導電材料與第一介電層位於第一硬式罩幕層上方的部分,以形成一第一導電接觸窗於餘留的第一介電層內。
根據另一實施例,一種半導體裝置之製造方法,包括:形成一第一金屬閘極及一第二金屬閘極於一基底上方,第一金屬閘極及第二金屬閘極各自具有複數閘極間隙壁位於對應的金屬閘極的相對側壁上;形成一第一介電層於基底上方且鄰近第一金屬閘極及第二金屬閘極;下凹第一金屬閘極及第二金屬閘極,使其具有上表面低於第一介電層的上表面;形成一第一硬式罩幕層於下凹的第一金屬閘極及第二金屬閘極的上表面上方;下凹第一硬式罩幕層,使其具有上表面低於第一介電層的上表面;形成一第二硬式罩幕層於下凹的第一硬式罩幕層的上表面上方,第二硬式罩幕層具有不同於第一硬式罩幕層的一材料組成;以及平坦化第二硬式罩幕層,使其具有上表面與第一介電層的上表面為共平面。
又根據另一實施例,一種半導體裝置,包括:一第一閘極堆疊,位於一基底上,第一閘極堆疊包括一第一高介電常數閘極介電層及一第一金屬閘極電極;一第一硬式罩幕層,位於第一閘極堆疊上;一第一組閘極間隙壁,位於第一閘極堆疊及第一硬式罩幕層的相對側壁上;一第一蝕刻停止層,位於第一組閘極間隙壁的側壁上;一第一內層介電層,圍繞第一蝕刻停止層及第一閘極堆疊,第一內層介電層接觸至少一部分的第一蝕刻停止層;一第一導電接觸窗,延伸穿過第一內層介電層,以接觸基底的上表面,第一導電接觸窗具有側壁與第一蝕刻停止層的側壁接觸;一第二蝕刻停止層,位於第一蝕刻停止層、第一組閘極間隙壁、第一硬式罩幕層及第一內層介電層的上表面上方,且與其接觸;一第二內層介電層,位於第二
蝕刻停止層上方;以及一第二導電接觸窗,延伸穿過第二內層介電層及第二蝕刻停止層,以接觸第一導電接觸窗。
以上概略說明了本發明數個實施例的特徵,使所屬技術領域中具有通常知識者對於本揭露的型態可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到可輕易利用本揭露作為其它製程或結構的變更或設計基礎,以進行相同於此處所述實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構並未脫離本揭露之精神和保護範圍內,且可在不脫離本揭露之精神和範圍內,當可作更動、替代與潤飾。
20‧‧‧基底
30‧‧‧源極/汲極區
34、64‧‧‧內層介電(ILD)層
38‧‧‧閘極介電層
40‧‧‧閘極電極
46‧‧‧第一硬式罩幕層
60A1、60A2、60B、60C、66A1、66A2、66B、66C‧‧‧導電特徵部件/接觸窗
62‧‧‧蝕刻停止層
Claims (15)
- 一種半導體裝置之製造方法,包括:形成一第一閘極於一基底上方,該第一閘極具有複數第一閘極間隙壁位於該第一閘極的相對側壁上;形成一第一硬式罩幕層於該第一閘極上方;形成一第二硬式罩幕層於該第一硬式罩幕層上方,該第二硬式罩幕層具有不同於該第一硬式罩幕層的一材料組成;形成一第一介電層鄰近該第一閘極且位於其上方;蝕刻出穿過該第一介電層的一第一開口,以露出一部分的該基底,至少一部分的該第二硬式罩幕層露出於該第一開口內;填入一導電材料於該第一開口內;以及去除該第二硬式罩幕層以及去除該導電材料與該第一介電層位於該第一硬式罩幕層上方的部分,以形成一第一導電接觸窗於餘留的該第一介電層內。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該第二硬式罩幕層包括一金屬氮化物或一金屬氧化物,且其中該第二硬式罩幕層包括TiO、HfO、AlO、ZrO、ZrN或其組合。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該等第一閘極間隙壁沿著該第一閘極的相對側壁延伸,且其中該第二硬式罩幕層位於該等第一閘極間隙壁的上表面上。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中 形成該第一閘極於該基底上方的步驟包括:形成一第一虛置閘極於該基底上方,該第一虛置閘極包括一虛置閘極介電層位於該基底上以及一第一虛置閘極電極位於該虛置閘極介電層上;形成該等第一閘極間隙壁於該第一虛置閘極的相對側壁上;利用該第一虛置閘極及該等第一閘極間隙壁作為罩幕,形成複數源極/汲極區於該基底內;形成一第一蝕刻停止層於該基底、該第一虛置閘極以及該等第一閘極間隙壁上方;形成該第一介電層的一第一部於該第一蝕刻停止層上方;平坦化該第一介電層的該第一部,以露出一部分的該第一虛置閘極;以及以該第一閘極取代該第一虛置閘極。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,更包括:下凹該第一閘極,使其具有一上表面低於該第一介電層的一第一部的一上表面,該第一硬式罩幕層形成於下凹的該第一閘極的該上表面上;下凹該第一硬式罩幕層,使其具有一上表面低於該第一介電層的該第一部的該上表面,該第二硬式罩幕層形成於下凹的該第一硬式罩幕層的該上表面上;以及平坦化該第二硬式罩幕層,使其具有一上表面與該第一介電層的該第一部的該上表面為共平面。
- 如申請專利範圍第5項所述之半導體裝置之製造方法,更包括:形成該第一介電層的一第二部於平坦化的該第二硬式罩幕層及該第一介電層的該第一部的上方,該第一開口延伸穿過該第一介電層的該第二部及該第一部;在去除該第二硬式罩幕層之後,形成一第二蝕刻停止層於該第一硬式罩幕層及該第一介電層的該第一部的上方;形成一第二介電層於該第二蝕刻停止層上方;以及形成一第二導電接觸窗,其穿過該第二介電層及該第二蝕刻停止層而至該第一導電接觸窗。
- 如申請專利範圍第6項所述之半導體裝置之製造方法,其中該第二導電接觸窗的一下表面接觸該第一硬式罩幕層的一上表面及該第一導電接觸窗的一上表面。
- 一種半導體裝置之製造方法,包括:形成一第一金屬閘極及一第二金屬閘極於一基底上方,該第一金屬閘極及該第二金屬閘極各自具有複數閘極間隙壁位於對應的金屬閘極的相對側壁上;形成一第一介電層於該基底上方且鄰近該第一金屬閘極及該第二金屬閘極;下凹該第一金屬閘極及該第二金屬閘極,使其具有上表面低於該第一介電層的上表面;形成一第一硬式罩幕層於下凹的該第一金屬閘極及該第二金屬閘極的上表面上方;下凹該第一硬式罩幕層,使其具有上表面低於該第一介電 層的上表面;形成一第二硬式罩幕層於下凹的該第一硬式罩幕層的上表面上方,該第二硬式罩幕層具有不同於該第一硬式罩幕層的一材料組成;以及平坦化該第二硬式罩幕層,使其具有上表面與該第一介電層的上表面為共平面。
- 如申請專利範圍第8項所述之半導體裝置之製造方法,更包括:形成一第二介電層於該平坦化的第二硬式罩幕層與該第一硬式罩幕層上方;蝕刻出穿過該第二及該第一介電層的一第一開口,以露出一部分的該基底,而位於該第一金屬閘極上方至少一部分的該第二硬式罩幕層露出於該第一開口內;填入一導電材料於該第一開口內;以及去除該第二硬式罩幕層以及去除該導電材料與該第二及該第一介電層位於該第一硬式罩幕層上方的部分,以形成一第一導電接觸窗於該第一介電層內。
- 如申請專利範圍第9項所述之半導體裝置之製造方法,其中位於該第一金屬閘極上方的該第二硬式罩幕層的整個上表面露出於該第一開口內。
- 如申請專利範圍第9項所述之半導體裝置之製造方法,更包括:蝕刻出穿過該第二介電層、該第二硬式罩幕層及該第一硬式罩幕層的一第二開口,以露出一部分的該第二金屬閘 極;以及填入該導電材料於該第二開口內,去除該第二硬式罩幕層以及去除該導電材料與該第二及該第一介電層位於該第一硬式罩幕層上方的部分,以形成一第二導電接觸窗於該第一硬式罩幕層內。
- 如申請專利範圍第8項所述之半導體裝置之製造方法,其中該第一金屬閘極包括一高介電常數閘極介電層位於該基底上,並沿著該等閘極間隙壁的內側壁,且包括一金屬閘極電極位於該高介電常數閘極介電層上。
- 如申請專利範圍第8項所述之半導體裝置之製造方法,其中形成該第一金屬閘極及該第二金屬閘極於該基底上方的步驟包括:形成一第一虛置閘極及一第二虛置閘極於該基底上方;形成該等閘極間隙壁於該第一虛置閘極及該第二虛置閘極的相對側壁上;形成一第一蝕刻停止層於該基底、該第一虛置閘極、該第二虛置閘極及該等閘極間隙壁上方;形成該第一介電層於該第一蝕刻停止層上方;平坦化該第一介電層,以露出部分的該第一虛置閘極及該第二虛置閘極;以及以該第一金屬閘極取代該第一虛置閘極,且以該第二金屬閘極取代該第二虛置閘極。
- 一種半導體裝置,包括:一第一閘極堆疊,位於一基底上,該第一閘極堆疊包括一 第一高介電常數閘極介電層及一第一金屬閘極電極;一第一硬式罩幕層,位於該第一閘極堆疊上;一第一組閘極間隙壁,位於該第一閘極堆疊及該第一硬式罩幕層的相對側壁上;一第一蝕刻停止層,位於該第一組閘極間隙壁的側壁上;一第一內層介電層,圍繞該第一蝕刻停止層及該第一閘極堆疊,該第一內層介電層接觸至少一部分的該第一蝕刻停止層;一第一導電接觸窗,延伸穿過該第一內層介電層,以接觸該基底的上表面,該第一導電接觸窗具有側壁與該第一蝕刻停止層的側壁接觸;一第二蝕刻停止層,位於該第一蝕刻停止層、該第一組閘極間隙壁、該第一硬式罩幕層及該第一內層介電層的上表面上方,且與其接觸;一第二內層介電層,位於該第二蝕刻停止層上方;以及一第二導電接觸窗,延伸穿過該第二內層介電層及該第二蝕刻停止層,以接觸該第一導電接觸窗。
- 如申請專利範圍第14項所述之半導體裝置,其中該第二導電接觸窗的一下表面接觸該第一硬式罩幕層、該第一組閘極間隙壁、該第一蝕刻停止層及該第一導電接觸窗的上表面上方。
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Also Published As
Publication number | Publication date |
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US20170288031A1 (en) | 2017-10-05 |
CN107275281B (zh) | 2019-12-20 |
US9548366B1 (en) | 2017-01-17 |
TW201810532A (zh) | 2018-03-16 |
CN107275281A (zh) | 2017-10-20 |
US9859386B2 (en) | 2018-01-02 |
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