CN107275281A - 自对准接触方案、半导体结构及其形成方法 - Google Patents
自对准接触方案、半导体结构及其形成方法 Download PDFInfo
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- CN107275281A CN107275281A CN201710202525.7A CN201710202525A CN107275281A CN 107275281 A CN107275281 A CN 107275281A CN 201710202525 A CN201710202525 A CN 201710202525A CN 107275281 A CN107275281 A CN 107275281A
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- 238000000034 method Methods 0.000 title claims abstract description 87
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 239000000463 material Substances 0.000 claims abstract description 45
- 239000004020 conductor Substances 0.000 claims abstract description 18
- 238000011049 filling Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 371
- 238000005530 etching Methods 0.000 claims description 76
- 229910052751 metal Inorganic materials 0.000 claims description 65
- 239000002184 metal Substances 0.000 claims description 65
- 125000006850 spacer group Chemical group 0.000 claims description 42
- 230000015572 biosynthetic process Effects 0.000 claims description 36
- 239000011229 interlayer Substances 0.000 claims description 22
- 239000003989 dielectric material Substances 0.000 claims description 19
- 229910044991 metal oxide Inorganic materials 0.000 claims description 10
- 150000004706 metal oxides Chemical class 0.000 claims description 10
- 230000005611 electricity Effects 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910017464 nitrogen compound Inorganic materials 0.000 claims 1
- 150000002830 nitrogen compounds Chemical class 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 26
- 230000008569 process Effects 0.000 description 26
- 238000005229 chemical vapour deposition Methods 0.000 description 20
- 239000000377 silicon dioxide Substances 0.000 description 14
- 238000000231 atomic layer deposition Methods 0.000 description 13
- 229910010271 silicon carbide Inorganic materials 0.000 description 13
- 230000004888 barrier function Effects 0.000 description 11
- 238000002347 injection Methods 0.000 description 11
- 239000007924 injection Substances 0.000 description 11
- 238000000059 patterning Methods 0.000 description 11
- 238000005240 physical vapour deposition Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052799 carbon Inorganic materials 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- -1 carborundum Chemical compound 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 5
- 230000009969 flowable effect Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910004541 SiN Inorganic materials 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000005388 borosilicate glass Substances 0.000 description 4
- 239000006227 byproduct Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 4
- 239000010941 cobalt Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- AMWRITDGCCNYAT-UHFFFAOYSA-L hydroxy(oxo)manganese;manganese Chemical compound [Mn].O[Mn]=O.O[Mn]=O AMWRITDGCCNYAT-UHFFFAOYSA-L 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 229910000480 nickel oxide Inorganic materials 0.000 description 4
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000001657 homoepitaxy Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910003465 moissanite Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229920002577 polybenzoxazole Polymers 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 229910016570 AlCu Inorganic materials 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 241001012508 Carpiodes cyprinus Species 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 229910000428 cobalt oxide Inorganic materials 0.000 description 2
- IVMYJDGYRUAWML-UHFFFAOYSA-N cobalt(ii) oxide Chemical compound [Co]=O IVMYJDGYRUAWML-UHFFFAOYSA-N 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 2
- 229910001512 metal fluoride Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920002647 polyamide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 108010022579 ATP dependent 26S protease Proteins 0.000 description 1
- 229910017115 AlSb Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910005898 GeSn Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910020751 SixGe1-x Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011469 building brick Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000000802 nitrating effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract
实施例是一种方法,包括:在衬底上方形成第一栅极,第一栅极具有位于相对侧壁上的第一栅极间隔件;在第一栅极上方形成第一硬掩模层;在第一硬掩模层上方形成第二硬掩模层,第二硬掩模层具有与第一硬掩模层不同的材料组分;邻近并且在第一栅极上方形成第一介电层;蚀刻穿过第一介电层的第一开口以暴露衬底的一部分,第二硬掩模层的至少一部分暴露在第一开口中;利用导电材料填充第一开口;以及去除第二硬掩模层并且去除导电材料和第一介电层的位于第一硬掩模层上面的部分以在剩余的第一介电层中形成第一导电接触件。本发明还提供了自对准接触方案、半导体结构及其形成方法。
Description
技术领域
本发明的实施例一般地涉及半导体技术领域,更具体地,涉及半导体结构及其形成方法。
背景技术
半导体器件用于各种电子应用,例如,诸如个人计算机、手机、数码相机和其他电子设备。通常通过以下步骤来制造半导体器件:在半导体衬底上方相继沉积绝缘或介电层、导电层和半导体材料层;以及使用光刻来图案化该多个材料层,以在其上形成电路组件和元件。
半导体工业通过不断减小最小部件尺寸持续地改进各个电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度,从而允许更多的组件集成至给定的区域中。
特别地,随着设计缩小,如果导电部件未对准,则连接至上面和下面的层的导电部件可能短路。通常,当穿过层的蚀刻工艺未对准使得导电部件暴露下面的层上的邻近的导电部件的一部分时会出现这种情况。
发明内容
根据本发明的一方面,提供了一种形成半导体器件的方法,包括:在衬底上方形成第一栅极,所述第一栅极具有位于所述第一栅极的相对侧壁上的第一栅极间隔件;在所述第一栅极上方形成第一硬掩模层;在所述第一硬掩模层上方形成第二硬掩模层,所述第二硬掩模层具有与所述第一硬掩模层不同的材料组分;邻近所述第一栅极并且在所述第一栅极上方形成第一介电层;蚀刻穿过所述第一介电层的第一开口以暴露所述衬底的一部分,所述第二硬掩模层的至少一部分暴露在所述第一开口中;利用导电材料填充所述第一开口;以及去除所述第二硬掩模层并且去除所述导电材料和所述第一介电层的位于所述第一硬掩模层上面的部分,以在剩余的第一介电层中形成第一导电接触件。
根据本发明的另一方面,提供了一种形成半导体器件的方法,包括:在衬底上方形成第一金属栅极和第二金属栅极,所述第一金属栅极和所述第二金属栅极的每一个都具有位于相应的金属栅极的相对侧壁上的栅极间隔件;在所述衬底上方并且邻近所述第一金属栅极和所述第二金属栅极形成第一介电层;使所述第一金属栅极和所述第二金属栅极凹进以具有位于所述第一介电层的顶面之下的顶面;在所述第一金属栅极和所述第二金属栅极的凹进的顶面上形成第一硬掩模层;使所述第一硬掩模层凹进以具有位于所述第一介电层的顶面之下的顶面;在所述第一硬掩模层的凹进的顶面上形成第二硬掩模层,所述第二硬掩模层具有与所述第一硬掩模层不同的材料组分;以及平坦化所述第二硬掩模层以具有与所述第一介电层的顶面共面的顶面。
根据本发明的又一方面,提供了一种半导体结构,包括:第一栅极堆叠件,位于衬底上,所述第一栅极堆叠件包括第一高k栅极介电层和第一金属栅电极;第一硬掩模层,位于所述第一栅极堆叠件上;第一组栅极间隔件,位于所述第一栅极堆叠件和所述第一硬掩模层的相对侧壁上;第一蚀刻停止层,位于所述第一组栅极间隔件的侧壁上;第一层间电介质,围绕所述第一蚀刻停止层和所述第一栅极堆叠件,所述第一层间电介质接触所述第一蚀刻停止层的至少一部分;第一导电接触件,延伸穿过所述第一层间电介质以接触所述衬底的顶面,所述第一导电接触件的侧壁接触所述第一蚀刻停止层的侧壁;第二蚀刻停止层,位于所述第一蚀刻停止层、所述第一组栅极间隔件、所述第一硬掩模层和所述第一层间电介质的顶面上方并且接触所述第一蚀刻停止层、所述第一组栅极间隔件、所述第一硬掩模层和所述第一层间电介质的顶面;第二层间电介质,位于所述第二蚀刻停止层上方;以及第二导电接触件,延伸穿过所述第二层间电介质和所述第二蚀刻停止层以接触所述第一导电接触件。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以最好地理解本发明的各个实施例。应该注意,根据工业中的标准实践,各种部件没有被按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增加或减少。
图1至图16示出了根据一些实施例的在半制造导体器件过程中的中间阶段的截面图。
具体实施方式
以下公开内容提供了多种不同实施例或实例,以实现本发明的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然,这些仅是实例并且不意欲限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例,也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且,本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚,其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外,为了便于描述,本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语,以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外,空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位),并且在本文中使用的空间关系描述符可以同样地作相应地解释。
实施例将关于具体的环境进行描述,即,两层之间的自对准方案。然而,其他实施例也可以应用于对准三层或更多层。在一些实施例中,自对准方案使用位于下层的导电部件上方的多个掩模层以在接触开口蚀刻工艺期间保护导电部件避免被无意的暴露。在一些实施例中,多掩模层中的至少一个为金属氮化物或金属氧化物掩模层,并且在接触开口蚀刻工艺期间提供足够的保护和蚀刻选择性。
在使用后栅极工艺形成的鳍式场效应晶体管(FET)的背景下讨论了本文中讨论的一些实施例。在其他实施例中,可以使用先栅极工艺。同样,一些实施例预期在诸如平面FET的平面器件、诸如FinFET的鳍式器件中使用的各个方面。
参考图1,图1示出了衬底20、伪栅极堆叠件28A和28B以及源极/漏极区域30。衬底20可以是掺杂的(例如,掺杂有p型或n型掺杂剂)或未掺杂的半导体衬底,诸如块状半导体、绝缘体上半导体(SOI)衬底等。衬底20可以是晶圆,诸如硅晶圆。通常,SOI衬底包括形成在绝缘体层上的半导体材料的层。例如,绝缘体层可为埋氧(BOX)层、氧化硅层等。在通常为硅或玻璃衬底的衬底上提供绝缘层。还可以使用诸如多层或梯度衬底的其他衬底。在一些实施例中,衬底20的半导体材料可包括硅;锗;包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体;包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体;或它们的组合。
可以在衬底20中形成适当的阱。例如,可以在衬底20的第一区域中形成P阱,并且可以在衬底20的第二区域中形成N阱。
可以使用光刻胶或其他掩模(未示出)实现用于不同阱的不同注入步骤。例如,形成并且图案化光刻胶以暴露衬底20的要被注入的区域。可通过使用旋涂技术形成光刻胶并且可使用可接受的光刻技术图案化该光刻胶。一旦图案化光刻胶,就可以在暴露区域中执行n型杂质和/或p型杂质注入,并且光刻胶可以用作掩模以基本上防止杂质注入到被掩蔽的区域中。n型杂质可以是注入第一区域磷、砷等,其浓度等于或小于1018cm-3(诸如在大约1017cm-3至大约1018cm-3的范围内)。p型杂质可以是注入第一区域的硼、BF2等,其浓度等于或小于1018cm-3(诸如在大约1017cm-3至大约1018cm-3的范围内)。在注入后,例如通过可接受的灰化工艺将光刻胶去除。
在阱的注入之后,可以实施退火以激活注入的p型和n型杂质。在一些实施例中,虽然衬底20可以包括在生长期间被原位掺杂的外延生长的区域(这可避免注入),但是可同时使用原位掺杂和注入掺杂。
衬底20可以包括有源和无源器件(未在图1中示出)。作为本领域的普通技术人员将会意识到,可以使用各种器件(诸如晶体管、电容器、电阻器、它们的组合等)来满足半导体器件的结构和功能要求。可以使用任何合适的方法来形成器件。在图中仅示出衬底20的一部分,因为这足以完全描述示出的实施例。
衬底20也可以包括金属化层(未示出)。金属化层可以形成在有源和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由介电材料(例如,低k介电材料)和导电材料(例如,铜)的交替层形成,并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成该金属化层。
在一些实施例中,衬底20可以包括在隔离区域上面并且从相邻的隔离区域之间突出的一个或多个鳍。例如,图1的截面图可以沿着鳍的纵轴。可以在各个不同的工艺中形成这些一个或多个鳍。在一个实例中,可以通过以下步骤形成鳍:在衬底中蚀刻沟槽以形成半导体带;可以利用介电层来填充沟槽;以及可以使介电层凹进使得半导体带从介电层突出以形成鳍。在另一实例中,可在衬底的顶面上方形成介电层;可穿过介电层蚀刻沟槽;可在沟槽中外延生长同质外延结构;并且可使介电层凹进使得同质外延结构从介电层突出以形成鳍。在又一实例中,异质外延结构可用于鳍。例如,可使半导体带凹进,并且可在它们的适当位置外延生长不同于半导体带的材料。在又一实例中,可在衬底的顶面上方形成介电层;可穿过介电层蚀刻沟槽;可使用不同于衬底的材料在沟槽中外延生长异质外延结构;并且可使介电层凹进使得异质外延结构从介电层突出以形成鳍。在其中外延生长同质外延结构或异质外延结构的一些实施例中,可在生长期间对生长的材料进行原位掺杂,这可避免之前和之后的注入,但是可同时使用原位掺杂和注入掺杂。此外,在NMOS区域中外延生长与PMOS区域中的材料不同的材料可能是有利的。在各个实施例中,鳍可包括硅锗(SixGe1-x,其中x可为约0至100)、碳化硅、纯锗或基本上纯的锗、III-V族化合物半导体、II-VI族化合物半导体等。例如,形成III-V族化合物半导体的可使用的材料包括但不限于InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP等。
栅极堆叠件28(包括28A和28B)形成在衬底20上方。栅极堆叠件28可以包括伪栅极介电层22、硬掩模(未示出)、以及伪栅电极24。可以通过热氧化、化学汽相沉积(CVD)、溅射或者本领域已知的和用于形成栅极电介质的其他方法来形成伪栅极电介质(未示出)。在一些实施例中,伪栅极介电层包括具有高介电常数(k值)(例如,大于3.9)的介电材料。伪栅极介电材料包括氮化硅、氮氧化物、金属氧化物(诸如HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx等)、或其组合以及多层。
伪栅电极层(未示出)形成在伪栅极介电层上方。栅电极层可以包括导电材料,并且可以从包括多晶硅(polysilicon)、多晶硅锗(poly-SiGe)、金属氮化物、金属硅化物、金属氧化物和金属的组中选择该导电材料。在一个实例中,非晶硅被沉积并再结晶以创建多晶硅。可以通过物理汽相沉积(PVD)、CVD、溅射沉积或本领域中已知的和已经使用的用于沉积导电材料的其他的技术来沉积伪栅电极层。在沉积之后,伪栅电极层的顶面通常具有非平坦顶面,并且例如,可以在伪栅电极层的图案化或栅极蚀刻之前,通过化学机械抛光(CMP)工艺进行平坦化。此时,可以向伪栅电极层中引入或者不引入离子。例如,可以通过离子注入技术引入离子。
硬掩模层(未示出)形成在伪栅电极层上方。硬掩模层可以由SiN、SiON、SiO2等或它们的组合制成。然后,图案化硬掩模层。可以通过在硬掩模层上方沉积诸如光刻胶的掩模材料(未示出)来完成硬掩模层的图案化。然后,图案化掩模材料并且根据图案来蚀刻硬掩模层以形成硬掩模。可以图案化伪栅电极层和伪栅极介电层以分别形成伪栅电极24和伪栅极电介质22。可以通过使用硬掩模作为图案并且蚀刻伪栅电极层和伪栅极介电层来完成栅极图案化工艺以形成栅极堆叠件28。
在形成栅极堆叠件28之后,可以在衬底20中形成源极/漏极区域30。可以通过执行注入工艺来注入适当的掺杂剂,以补偿衬底20中的掺杂剂,从而掺杂源极/漏极区域30。在另一实施例中,可以通过在衬底20中形成凹槽(未示出)并且在凹槽中外延生长材料来形成源极/漏极区域30。可以通过以上所讨论的注入方法或通过随着材料生长进行原位掺杂来掺杂源极/漏极区域30。在该实施例中,外延的源极/漏极区域30可包括诸如适用于n型FET和/或p型FET的任何可接受的材料。例如,在n型配置中,如果衬底20为硅,则外延的源极/漏极区30可包括硅、SiC、SiCP、SiP等。例如,在n型配置中,如果衬底20为硅,则外延源极/漏极区30可包括SiGe、SiGeB、Ge、GeSn等。外延的源极/漏极区域30可具有提升到衬底20的顶面之上的表面并且可具有刻面(facets)。
在实施例中,栅极堆叠件28和源极/漏极区域30可以形成晶体管,诸如金属氧化物半导体FET(MOSFET)。在这些实施例中,MOSFET可以配置为PMOS或NMOS配置。在PMOS配置中,衬底20掺杂有n型掺杂剂并且源极/漏极区域30掺杂有p型掺杂剂。在NMOS配置中,衬底掺杂有p型掺杂剂并且源极/漏极区域30掺杂有n型掺杂剂。
栅极间隔件26形成在栅极堆叠件28的相对侧部上。可以通过在先前形成的栅极堆叠件28上毯式沉积间隔件层(未示出)来形成栅极间隔件26。在实施例中,栅极间隔件26包括间隔件衬里(未示出)。间隔件衬里可以由SiN、SiC、SiGe、氮氧化物、氧化物等或它们的组合制成。间隔件层可以包括SiN、氮氧化物、SiC、SiON、氧化物、它们的组合等,并且可以通过用于形成这种层的方法(诸如CVD、等离子体增强的CVD(PECVD)、低压CVD(LPCVD)、原子层沉积(ALD)、溅射等或它们的组合)来形成该间隔件层。然后,例如,通过各向异性蚀刻来图案化栅极间隔件26,以从诸如栅极堆叠件28的顶面和衬底20的顶面的水平表面去除间隔件层。
在另一实施例中,源极/漏极区域30可以包括轻掺杂区域(有时称为LDD区域)和重掺杂区域。在该实施例中,在形成栅极间隔件26之前,使用栅极堆叠件28作为掩模利用注入工艺轻掺杂源极/漏极区域30。在形成栅极间隔件26之后,然后,使用栅极堆叠件28和栅极间隔件26作为掩模利用注入工艺重掺杂源极/漏极区域30。这形成了轻掺杂区域和重掺杂区域。轻掺杂区域主要位于栅极间隔件26下方,而重掺杂区域沿着衬底20位于栅极间隔件外部。
虽然以上描述了栅极28的形成,但是结构28不限于栅极。在一些实施例中,结构28为通过随后形成的导电部件与其他导电部件对准并且耦合的导线28。
如图1所示,栅极堆叠件28B的宽度大于伪栅极堆叠件28A的宽度。另外,伪栅堆叠件28B和最近的伪栅堆叠件28A之间的间距大于伪栅堆叠件28A之间的间距。这些不同类型的栅极堆叠件28的位置用于说明所讨论的实施例的各种配置,并且各个栅极堆叠件28的位置不限于这些实际位置。
图2示出了衬底20、栅极堆叠件28、侧壁间隔件26和源极/漏极区域30上方的蚀刻停止层32的形成。蚀刻停止层32可以共形地沉积在衬底20上的组件上方。在一些实施例中,蚀刻停止层32可以是氮化硅、碳化硅、氧化硅、低k电介质(诸如掺杂碳的氧化物)、极低k电介质(诸如多孔碳掺杂的二氧化硅)等或它们的组合,并且可以使用CVD、PVD、ALD、旋涂电介质工艺等或它们的组合来形成蚀刻停止层32。
在图3中,层间电介质(ILD)34沉积在图2中示出的结构上方。在实施例中,ILD 34为通过可流动CVD形成的可流动膜。在一些实施例中,ILD 34由诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼的磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)、诸如掺碳氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、诸如聚酰亚胺的聚合物等、或它们的组合形成。低k介电材料可以具有低于3.9的k值。可以通过诸如CVD、ALD、旋涂电介质(SOD)工艺等或它们的组合的任何合适的方法来形成ILD 34。
还在图3中,可以执行诸如CMP工艺的平坦化工艺以使ILD 34的顶面34S与伪栅电极24的顶面24S和蚀刻停止层32的顶面32S齐平。CMP工艺还可以去除伪栅电极24上的硬掩模(如果存在)。因此,通过ILD 34暴露伪栅电极24的顶面24S。
在图4中,在蚀刻步骤中去除伪栅电极24和直接位于伪栅电极24下方的伪栅极电介质22,从而形成凹槽36。在其中形成MOSFET的实施例中,每一个凹槽36都暴露相应的FET的沟道区域。每一个沟道区域都设置在相邻的一对源极/漏极区30之间。在去除期间,当蚀刻伪栅电极24时,伪栅极电介质22可以用作蚀刻停止层。然后,在去除伪栅电极24之后,可以去除伪栅极电介质22。通过衬底20的暴露的表面20S和栅极间隔件26的暴露的内表面26S来限定凹槽36。
在图5中,形成栅极介电层38和栅电极40以用于替换栅极。在凹槽36中共形沉积栅极介电层38,诸如在衬底的顶面上和在栅极间隔件26的侧壁上,以及在ILD 34的顶面上。根据一些实施例,栅极介电层38包括氧化硅、氮化硅或它们的多层。在其他实施例中,栅极介电层38包括高-k介电材料,并且在这些实施例中,栅极介电层38可具有大于约7.0的k值,并且可包括Hf、Al、Zr、La、Mg、Ba、Ti、Pb的金属氧化物或硅酸盐及其组合。栅极介电层38的形成方法可以包括分子束沉积(MBD)、ALD、PECVD等。
接下来,栅电极40分别沉积在栅极介电层38上方并且填充凹槽36的剩余部分。栅电极40可以由含金属的材料制成,诸如TiN、TaN、TaC、Co、Ru、Al、它们的组合或它们的多层。在栅电极40的填充之后,可以实施诸如CMP工艺的平坦化工艺以去除栅极介电层38和栅电极40的材料的过量部分,其中该过量部分位于ILD 34的顶面上方。产生的栅电极40和栅极介电层38的材料的剩余部分因此形成替换栅极42(包括替换栅极42A和42B)。
在具有位于衬底20上的NMOS和PMOS器件这两者的互补MOS(CMOS)实施例中,在PMOS和NMOS区域中的栅极介电层38的形成可以同时发生,使得PMOS和NMOS区域两者中的栅极介电层38由相同的材料制成,并且PMOS和NMOS区域两者中的栅电极40的形成可以同时发生,使得PMOS和NMOS区域两者中的栅电极40由相同的材料制成。然而,在其他实施例中,可通过不同的工艺形成NMOS区域和PMOS区域中的栅极介电层38,使得NMOS区域和PMOS区域中的栅极介电层38可由不同的材料制成,并且可通过不同的工艺形成NMOS和PMOS区域中的栅电极40,使得NMOS区域和PMOS区域中的栅电极40可由不同材料制成。当使用不同工艺时,各种掩蔽步骤可用于掩蔽和暴露适当区域。
在图6中,在蚀刻步骤中使栅电极40和栅极电介质38凹进,从而形成凹槽44。凹槽44允许随后形成的硬掩模形成在凹槽44内以保护替换栅极42。分别通过栅极间隔件26的暴露的内表面26S、栅电极40和栅极电介质38的凹进的顶面40S和38S来限定凹槽44。
此外,凹槽44的底面可以具有如图所示的平坦的表面、凸形表面、凹形表面(诸如凹陷的)或它们的组合。可通过适当的蚀刻将凹槽44的底面形成为平面、凸面和/或凹面。可使用可接受的蚀刻工艺(诸如对栅电极和栅极电介质38的材料进行的选择性的蚀刻工艺)使栅电极40和栅极电介质38凹进。
在图7中,第一硬掩模层46形成在ILD 34上方以及栅电极40和栅极电介质38上方的凹槽44内。第一硬掩模层46可以由SiN、SiON、SiO2等或它们的组合制成。可以通过CVD、PVD、ALD、旋涂电介质工艺等或它们的组合形成第一硬掩模层46。由于在更小的技术节点(诸如10nm或以下的节点)下的凹槽的高宽比,所以凹槽44内的第一硬掩模层46的形成可以使得缝隙(seam)和/或空隙48形成在第一硬掩模层46内。这些缝隙和/或空隙48可以是第一硬掩模层46内的薄弱点,从而在随后的蚀刻工艺期间使得栅电极40和/或栅极电介质38无意地暴露。
图8示出了使第一硬掩模层46凹进以形成凹槽50。在一些实施例中,使第一硬掩模层46、蚀刻停止层32、以及栅极间隔件26凹进,从而分别使得第一硬掩模层46的顶面46S、蚀刻停止层32的顶面32S以及栅极间隔件26的顶面26S位于ILD 34的顶面34S下面。在一些实施例中,第一硬掩模层46的凹进完全地去除了第一硬掩模层46中的缝隙和/或空隙48,并且在其他的实施例中,在凹进工艺之后保留缝隙和/或空隙48的至少一部分。
此外,凹槽50的底面可以具有平坦的表面(如图所示)、凸表面、凹表面(诸如凹陷的)或它们的组合。可通过适当的蚀刻将凹槽50的底面形成为平面、凸面和/或凹面。可以使用诸如对于第一硬掩模层46、蚀刻停止层32和栅极间隔件26的材料具有选择性的工艺的可接受的蚀刻工艺来使第一硬掩模层46凹进。例如,蚀刻工艺可以包括来自使用等离子体的蚀刻剂气体的反应物的形成。在一些实施例中,等离子体可以为远程等离子体。蚀刻剂气体可以包括碳氟化合物化学制剂,诸如C4F6/CF4/C5F和NF3/O2/N2/Ar/H3/H2等或它们的组合。在一些实施例中,可以在大约100sccm至大约1000sccm的总气体流量下将蚀刻剂气体供应至蚀刻室。在一些实施例中,在蚀刻工艺期间,蚀刻室的压力为大约10mtorr至大约50mtorr。在一些实施例中,蚀刻剂气体可以包括介于大约10%至大约90%之间的氢气。在一些实施例中,蚀刻剂气体可以包括介于大约20%至大约80%之间的惰性气体。
在图9中,第二硬掩模层52形成在第一硬掩模层46、栅极间隔件26、蚀刻停止层32和ILD 34上方并且形成在凹槽50内。第二硬掩模层52在随后的自对准接触蚀刻(见图12)期间对于第一硬掩模层46、栅极间隔件26和蚀刻停止层32提供保护,以确保自对准接触件不会使栅电极40之一与对应的源极/漏极区域30短路。第二硬掩模层52可以由金属、金属氧化物、金属氮化物、纯硅等或它们的组合制成。金属氧化物和金属氮化物的一些实例为TiO、HfO、AlO、ZrO、ZrN等或它们的组合。第二硬掩模层52的材料组分很重要,这是因为其确保高膜密度和非挥发的蚀刻副产物,诸如例如金属氟化物蚀刻副产物。此外,因为随后将去除第二硬掩模层52(见图15),所以可用于第二硬掩模层52中的材料比可用于第一硬掩模层46中的材料大,并且因此这些材料将不会影响随后的工艺。可以通过CVD、PVD、ALD、旋涂电介质工艺等或它们的组合形成第二硬掩模层52。
在图10中,可以执行诸如CMP工艺的平坦化工艺以使ILD 34的顶面34S与第二硬掩模层52的顶面52S齐平。因此,暴露ILD 34的顶面34S。
在图11中,ILD 54沉积在图10中示出的结构上方。在实施例中,ILD 54为通过可流动CVD形成的可流动膜。在一些实施例中,ILD 54由诸如氧化硅的氧化物、PSG、BSG、BPSG、USG、诸如掺碳氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、诸如聚酰亚胺的聚合物等、或它们的组合形成。低k介电材料可以具有低于3.9的k值。可以通过诸如CVD、ALD、SOD工艺等或它们的组合的任何合适的方法来沉积ILD 54。在一些实施例中,通过CMP工艺或蚀刻工艺来平坦化ILD 54以形成基本平坦的顶面。
还在图11中,硬掩模层56形成在ILD 54上方并且被图案化。硬掩模层可以由SiN、SiON、SiO2等或它们的组合制成。可以通过CVD、PVD、ALD、SOD工艺等或它们的组合形成硬掩模层56。然后,图案化硬掩模层56。可以通过在硬掩模层56上方沉积诸如光刻胶的掩模材料(未示出)来完成硬掩模层56的图案化。然后,图案化掩模材料并且根据图案来蚀刻硬掩模层56以形成图案化的硬掩模层56。
图12示出了使用图案化的硬掩模层56作为掩模形成穿过ILD 54并且穿过ILD 34的开口58A和58B的以暴露衬底20的一部分。在示出的实施例中,开口58A和58B暴露源极/漏极区域30的部分表面30S,并且在其中不存在源极/漏极区域30的其他的实施例中,例如,开口58A和58B可以暴露诸如衬底20中的金属部件的其他部件。虽然开口58A的部分延伸至栅极堆叠件42A的顶面上方,但是第二硬掩模层52和蚀刻停止层32将介于邻近的成对的栅极堆叠件42A之间的开口58A与衬底20自对准。在示出的实施例中,由于栅极堆叠件42B和最近的栅极堆叠件42A之间的间距比栅极堆叠件42A之间的间距大,所以开口58B未自对准,并且自对准的开口没有必要用于该更大的间距。通过使用可接受的蚀刻技术来形成开口58A和58B。在实施例中,通过各向异性干蚀刻工艺形成开口58A和58B。例如,蚀刻工艺可以包括使用选择性蚀刻ILD 54和34而未蚀刻第二硬掩模层52的反应气体的干蚀刻工艺。例如,蚀刻工艺可以包括来自使用等离子体的蚀刻剂气体的反应物的形成。在一些实施例中,等离子体可以为远程等离子体。蚀刻剂气体可以包括碳氟化合物化学制剂,诸如C4F6/CF4/C5F和NF3/O2/N2/Ar/H3/H2等或它们的组合。在一些实施例中,可以在大约100sccm至大约1000sccm的总气体流量下将蚀刻剂气体供应至蚀刻室。在一些实施例中,在蚀刻工艺期间,蚀刻室的压力为大约10mtorr至大约50mtorr。第二硬掩模层52用作蚀刻停止层并且即使在出现图案化未对准误差时也有利地防止对下面的部件(如,栅极间隔件26、第一硬掩模层46和栅极堆叠件42)的损害。不利地,不存在第二硬掩模层52,蚀刻工艺会损害栅极间隔件26、第一硬掩模层46和栅极堆叠件42。在一些实施例中,用于自对准的开口58A的蚀刻工艺可以去除第二硬掩模层52的一些上部部分,但是未完全蚀刻穿过第二硬掩模层52,使得在蚀刻工艺期间保护第一硬掩模层46、栅极间隔件26和被覆盖的蚀刻停止层32的部分。
在图13中,还图案化硬掩模层56,并且使用图案化的硬掩模层56作为掩模来形成穿过ILD 54、栅极堆叠件42B上方的第二硬掩模层52、以及栅极堆叠件42B上方的第一硬掩模层46的开口58C,以暴露栅极堆叠件42B的栅电极40的表面40S的一部分。可以通过在硬掩模层56上方沉积诸如光刻胶的掩模材料(未示出)来完成硬掩模层56的图案化。然后,图案化掩模材料并且根据图案来蚀刻硬掩模层56以形成图案化的硬掩模层56。在开口58C的形成期间,掩模材料可以保留在开口58A和58B上方以保护开口58A和58B内的结构。在示出的实施例中,开口58C未自对准。可以通过使用可接受的蚀刻技术来形成开口58C。在实施例中,通过各向异性干蚀刻工艺形成开口58C。
图14示出了开口58A、58B和58C中的导电层60的形成。开口58A中的导电层60接触衬底20的暴露的表面并且沿着蚀刻停止层32、ILD 34和54的暴露的表面以及第二硬掩模层的顶面。开口58B中的导电层60接触衬底20的暴露的表面并且沿着蚀刻停止层32、ILD 34和54的暴露的表面。在示出的实施例中,开口58A和58B中的导电层接触源极/漏极区域30的暴露的表面,并且在其中不存在源极/漏极区域30的其他实施例中,例如,开口58A和58B中的导电层60接触诸如衬底20中的金属部件的其他部件。开口58C中的导电层60接触栅极堆叠件42B的栅电极40的暴露的表面并且沿着第一和第二硬掩模层46和52以及ILD 54的暴露的表面。
在一些实施例中,导电层60包括阻挡层(未示出)。阻挡层有助于阻挡随后形成的导电层60扩散进诸如ILD 34和54的邻近的介电材料中。阻挡层可以由钛、氮化钛、钽、氮化钽、锰、氧化锰、钴、氧化钴、氮化钴、镍、氧化镍、氮化镍、碳化硅、掺杂氧的碳化硅、掺杂氮的碳化硅、氮化硅、氧化铝、氮化铝、氮氧化铝、诸如聚酰亚胺、聚苯并恶唑(PBO)等的聚合物或它们的组合制成。可以通过CVD、PVD、PECVD、ALD、SOD等或它们的组合形成阻挡层。在一些实施例中,省略阻挡层。
导电层60可以由钨、铜、铝等或它们的组合制成。可以通过诸如电化学镀、PVD、CVD等或它们的组合的沉积工艺形成导电层60。在一些实施例中,导电层60形成在诸如AlCu的含铜晶种层上。
在一些实施例中,形成导电层60以具有位于ILD 54的顶面上方的多余的材料。在这些实施例中,通过诸如CMP工艺的研磨工艺来平坦化导电层60以分别在开口58A、58B和58C中形成导电部件60A、60B和60C。在一些实施例中,在平坦化工艺之后,导电部件60A、60B和60C的顶面与ILD 54的顶面齐平。
图15示出了ILD 54、第二硬掩模层52和部分ILD 34以及位于第一硬掩模层46的顶面之上的平面处的导电部件60A、60B和60C的去除。可以通过一个或多个蚀刻工艺和/或诸如CMP工艺的研磨工艺来执行该去除。在去除工艺之后,导电部件60A现在为两个分离的导电部件60A1和60A2,并且导电部件60C现在嵌入栅极堆叠件42B上方的第一硬掩模层46中。另外,在去除工艺之后,导电部件60A1、60A2、60B和60C的顶面与ILD 34和第一硬掩模层46的顶面齐平。
图16示出了图15的结构上方的蚀刻停止层62的形成。蚀刻停止层62形成在ILD34、蚀刻停止层32、第一硬掩模层46和栅极间隔件26上方。蚀刻停止层62可以共形沉积在这些组件上方。在一些实施例中,蚀刻停止层62可以是氮化硅、碳化硅、氧化硅、低k电介质(诸如掺杂碳的氧化物)、极低k电介质(诸如多孔碳掺杂的二氧化硅)等或它们的组合,并且可以使用CVD、PVD、ALD、旋涂电介质工艺等或它们的组合来形成。
还在图16中,ILD 64沉积在蚀刻停止层62上方。在实施例中,ILD 64为通过可流动CVD形成的可流动膜。在一些实施例中,ILD 64由诸如氧化硅的氧化物、PSG、BSG、BPSG、USG、诸如掺碳的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、诸如聚酰亚胺的聚合物等、或它们的组合形成。低k介电材料可以具有低于3.9的k值。可以通过诸如CVD、ALD、SOD工艺等或它们的组合的任何合适的方法来沉积ILD 64。
还在图16中,接触件66A1、66A2、66B和66C形成为穿过ILD 64和蚀刻停止层62以电接触并且物理接触相应的接触件60A1、60A2、60B和60C。通过使用可接受的蚀刻技术来形成用于接触件66的开口。在实施例中,通过各向异性干蚀刻工艺形成开口。这些开口填充有导电层66。在一些实施例中,导电层66包括阻挡层(未示出)。阻挡层有助于阻挡随后形成的导电层66扩散进诸如ILD 64和蚀刻停止层62的邻近的介电材料中。阻挡层可以由以下材料制成:钛、氮化钛、钽、氮化钽、锰、氧化锰、钴、氧化钴、氮化钴、镍、氧化镍、氮化镍、碳化硅、掺氧的碳化硅、掺氮的碳化硅、氮化硅、氧化铝、氮化铝、氮氧化铝、诸如聚酰亚胺、PBO等的聚合物或它们的组合。可以通过CVD、PVD、PECVD、ALD、SOD等或它们的组合形成阻挡层。在一些实施例中,省略阻挡层。
导电层66可以由钨、铜、铝等或它们的组合制成。可以通过诸如电化学镀、PVD、CVD等或它们的组合的沉积工艺形成导电层66。在一些实施例中,导电层66形成在诸如AlCu的含铜晶种层上。
在一些实施例中,形成导电层66以具有位于ILD 64的顶面上方的多余的材料。在这些实施例中,通过诸如CMP工艺的研磨工艺来平坦化导电层66以形成导电部件66A1、66A2、66B和66C。在一些实施例中,在平坦化工艺之后,导电部件66A1、66A2、66B和66C的顶面与ILD 64的顶面齐平。
本发明的实施例可以实现以下优势,即,两层之间的自对准方法以允许保护下面的部件。在一些实施例中,自对准方案使用位于下层的导电部件上方的多掩模层来保护导电部件以避免在接触开口蚀刻工艺期间被无意的暴露。在一些实施例中,多掩模层中的至少一个为金属氮化物或金属氧化物掩模层并且在自对准接触开口蚀刻工艺期间提供足够的保护和蚀刻选择性。在具有两个硬掩模层的FET实施例中,由金属氮化物或金属氧化物制成的上部硬掩模层确保自对准接触件不会将栅电极中的一个短接至对应的源极/漏极区域。另外,在一些实施例中,在应用上部硬掩模层之前,使下部硬掩模层凹进,并且下部硬掩模层的这种凹进可以基本(如果未完全去除)去除下部硬掩模层中的任何缝隙和/或空隙。此外,上部硬掩模层的材料组分非常重要,这是因为它确保高膜密度和非挥发的蚀刻副产物,诸如金属氟化物蚀刻副产物。此外,因为随后将去除上部硬掩模层,所以可用于上部硬掩模层中的材料的范围比可用于下部硬掩模层中的材料的范围大,并且因此这些材料将不会影响随后的工艺。
实施例是一种方法,包括:在衬底上方形成第一栅极,第一栅极具有位于第一栅极的相对侧壁上的第一栅极间隔件;在第一栅极上方形成第一硬掩模层;在第一硬掩模层上方形成第二硬掩模层,第二硬掩模层具有与第一硬掩模层不同的材料组分;邻近第一栅极并且在第一栅极上方形成第一介电层;蚀刻穿过第一介电层的第一开口以暴露衬底的一部分,第二硬掩模层的至少一部分暴露在第一开口中;利用导电材料填充第一开口;以及去除第二硬掩模层并且去除导电材料和第一介电层的位于第一硬掩模层上面的部分以在剩余的第一介电层中形成第一导电接触件。
在实施例中,所述第二硬掩模层包括金属氮化物或金属氧化物。
在实施例中,所述第二硬掩模层包括TiO、HfO、AlO、ZrO、ZrN或它们的组合。
在实施例中,所述第一栅极间隔件沿着所述第一硬掩模层的相对侧壁延伸。
在实施例中,所述第二硬掩模层位于所述第一栅极间隔件的顶面上。
在实施例中,所述第一栅极包括位于所述衬底上并且沿着所述第一栅极间隔件的内部侧壁的高k栅极介电层以及位于所述高k栅极介电层上的金属栅电极。
在实施例中,在所述衬底上方形成所述第一栅极包括:在所述衬底上方形成第一伪栅极,所述第一伪栅极包括位于所述衬底上的第一伪栅极电介质和位于所述第一伪栅极电介质上的第一伪栅电极;在所述第一伪栅极的相对侧壁上形成所述第一栅极间隔件;使用所述第一伪栅极和所述第一栅极间隔件作为掩模在所述衬底中形成源极/漏极区域;在所述衬底、所述第一伪栅极和所述第一栅极间隔件上方形成第一蚀刻停止层;在所述第一蚀刻停止层上方形成所述第一介电层的第一部分;平坦化所述第一介电层的第一部分以暴露所述第一伪栅极的一部分;以及利用所述第一栅极替换所述第一伪栅极。
在实施例中,形成半导体器件的方法还包括:使所述第一栅极凹进以具有位于所述第一介电层的第一部分的顶面之下的顶面,所述第一硬掩模层形成在所述第一栅极的凹进的顶面上;使所述第一硬掩模层凹进以具有位于所述第一介电层的第一部分的顶面之下的顶面,所述第二硬掩模层形成在所述第一硬掩模层的凹进的顶面上;以及平坦化所述第二硬掩模层以具有与所述第一介电层的第一部分的顶面共面的顶面。
在实施例中,形成半导体器件的方法还包括:在平坦化的第二硬掩模层上方以及所述第一介电层的第一部分上方形成第一介电层的第二部分,所述第一开口延伸穿过所述第一介电层的第二部分和第一部分;在去除所述第二硬掩模层之后,在所述第一介电层的第一部分和所述第一硬掩模层上方形成第二蚀刻停止层;在所述第二蚀刻停止层上方形成第二介电层;以及形成第二导电接触件,所述第二导电接触件穿过所述第二介电层和所述第二蚀刻停止层到达所述第一导电接触件。
在实施例中,所述第二导电接触件的底面接触所述第一硬掩模层的顶面和所述第一导电接触件的顶面。
另一实施例是一种方法,包括:在衬底上方形成第一金属栅极和第二金属栅极,第一金属栅极和第二金属栅极的每一个都具有位于相应的金属栅极的相对侧壁上的栅极间隔件;在衬底上方并且邻近第一和第二金属栅极形成第一介电层;使第一金属栅极和第二金属栅极凹进以具有位于第一介电层的顶面之下的顶面;在第一金属栅极和第二金属栅极的凹进的顶面上形成第一硬掩模层;使第一硬掩模层凹进以具有位于第一介电层的顶面之下的顶面;在第一硬掩模层的凹进的顶面上形成第二硬掩模层,第二硬掩模层具有与第一硬掩模层不同的材料组分;以及平坦化第二硬掩模层以具有与第一介电层的顶面共面的顶面。
在实施例中,形成半导体器件的方法还包括:在平坦化的第二硬掩模层和第一硬掩模层上方形成第二介电层;蚀刻穿过所述第二介电层和所述第一介电层的第一开口以暴露所述衬底的一部分,位于所述第一金属栅极上方的第二硬掩模层的至少一部分暴露在所述第一开口中;利用导电材料填充所述第一开口;以及去除所述第二硬掩模层并且去除所述导电材料、所述第二介电层、所述第一介电层的位于所述第一硬掩模层上面的部分,以在所述第一介电层中形成第一导电接触件。
在实施例中,位于所述第一金属栅极上方的第二硬掩模层的整个顶面暴露在所述第一开口中。
在实施例中,形成半导体器件的方法还包括:蚀刻穿过所述第二介电层、所述第二硬掩模层、以及所述第一硬掩模层的第二开口,以暴露所述第二金属栅极的一部分;以及利用所述导电材料填充所述第二开口,去除所述第二硬掩模层并且去除所述导电材料、所述第二介电层、所述第一介电层的位于所述第一硬掩模层上面的一部分以在所述第一硬掩模层中形成第二导电接触件。
在实施例中,所述第二硬掩模层包括金属氮化物或金属氧化物。
在实施例中,所述第一金属栅极包括位于所述衬底上并且沿着所述栅极间隔件的内部侧壁的高k栅极介电层和位于所述高k栅极介电层上的金属栅电极。
在实施例中,在所述衬底上方形成所述第一金属栅极和所述第二金属栅极包括:在所述衬底上方形成第一伪栅极和第二伪栅极;在所述第一伪栅极和所述第二伪栅极的相对侧壁上形成栅极间隔件;在所述衬底、所述第一伪栅极、所述第二伪栅极、以及所述栅极间隔件上方形成第一蚀刻停止层;在所述第一蚀刻停止层上方形成所述第一介电层;平坦化所述第一介电层以暴露所述第一伪栅极和所述第二伪栅极的一部分;以及利用所述第一金属栅极替换所述第一伪栅极,并且利用所述第二金属栅极替换所述第二伪栅极。
又一实施例是一种结构,包括:第一栅极堆叠件,位于衬底上,第一栅极堆叠件包括第一高k栅极介电层和第一金属栅电极;第一硬掩模层,位于第一栅极堆叠件上;第一组栅极间隔件,位于第一栅极堆叠件的相对侧壁上;第一蚀刻停止层,位于第一组栅极间隔件的侧壁上;第一层间电介质,围绕第一蚀刻停止层和第一栅极堆叠件,第一层间电介质接触第一蚀刻停止层的至少一部分;第一导电接触件,延伸穿过第一层间电介质以接触衬底的顶面,第一导电接触件的侧壁接触第一蚀刻停止层的侧壁;第二蚀刻停止层,位于第一蚀刻停止层、第一组栅极间隔件、第一硬掩模层和第一层间电介质的顶面上方并且接触第一蚀刻停止层、第一组栅极间隔件、第一硬掩模层和第一层间电介质的顶面;第二层间电介质,位于第二蚀刻停止层上方;以及第二导电接触件,延伸穿过第二层间电介质和第二蚀刻停止层以接触第一导电接触件。
在实施例中,所述第二导电接触件的底面接触所述第一硬掩模层、所述第一组栅极间隔件、所述第一蚀刻停止层、以及所述第一导电接触件的顶面。
在实施例中,半导体结构还包括:第一源极/漏极区域,位于所述衬底中,所述第一导电接触件接触所述第一源极/漏极区域。
以上论述了若干实施例的部件,使得本领域的技术人员可以更好地理解本发明的各个实施例。本领域技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到,这些等效结构并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (10)
1.一种形成半导体器件的方法,包括:
在衬底上方形成第一栅极,所述第一栅极具有位于所述第一栅极的相对侧壁上的第一栅极间隔件;
在所述第一栅极上方形成第一硬掩模层;
在所述第一硬掩模层上方形成第二硬掩模层,所述第二硬掩模层具有与所述第一硬掩模层不同的材料组分;
邻近所述第一栅极并且在所述第一栅极上方形成第一介电层;
蚀刻穿过所述第一介电层的第一开口以暴露所述衬底的一部分,所述第二硬掩模层的至少一部分暴露在所述第一开口中;
利用导电材料填充所述第一开口;以及
去除所述第二硬掩模层并且去除所述导电材料和所述第一介电层的位于所述第一硬掩模层上面的部分,以在剩余的第一介电层中形成第一导电接触件。
2.根据权利要求1所述的形成半导体器件的方法,其中,所述第二硬掩模层包括金属氮化物或金属氧化物。
3.根据权利要求2所述的形成半导体器件的方法,其中,所述第二硬掩模层包括TiO、HfO、AlO、ZrO、ZrN或它们的组合。
4.根据权利要求1所述的形成半导体器件的方法,其中,所述第一栅极间隔件沿着所述第一硬掩模层的相对侧壁延伸。
5.根据权利要求4所述的形成半导体器件的方法,其中,所述第二硬掩模层位于所述第一栅极间隔件的顶面上。
6.根据权利要求1所述的形成半导体器件的方法,其中,所述第一栅极包括位于所述衬底上并且沿着所述第一栅极间隔件的内部侧壁的高k栅极介电层以及位于所述高k栅极介电层上的金属栅电极。
7.根据权利要求1所述的形成半导体器件的方法,其中,在所述衬底上方形成所述第一栅极包括:
在所述衬底上方形成第一伪栅极,所述第一伪栅极包括位于所述衬底上的第一伪栅极电介质和位于所述第一伪栅极电介质上的第一伪栅电极;
在所述第一伪栅极的相对侧壁上形成所述第一栅极间隔件;
使用所述第一伪栅极和所述第一栅极间隔件作为掩模在所述衬底中形成源极/漏极区域;
在所述衬底、所述第一伪栅极和所述第一栅极间隔件上方形成第一蚀刻停止层;
在所述第一蚀刻停止层上方形成所述第一介电层的第一部分;
平坦化所述第一介电层的第一部分以暴露所述第一伪栅极的一部分;以及
利用所述第一栅极替换所述第一伪栅极。
8.根据权利要求1所述的形成半导体器件的方法,还包括:
使所述第一栅极凹进以具有位于所述第一介电层的第一部分的顶面之下的顶面,所述第一硬掩模层形成在所述第一栅极的凹进的顶面上;
使所述第一硬掩模层凹进以具有位于所述第一介电层的第一部分的顶面之下的顶面,所述第二硬掩模层形成在所述第一硬掩模层的凹进的顶面上;以及
平坦化所述第二硬掩模层以具有与所述第一介电层的第一部分的顶面共面的顶面。
9.一种形成半导体器件的方法,包括:
在衬底上方形成第一金属栅极和第二金属栅极,所述第一金属栅极和所述第二金属栅极的每一个都具有位于相应的金属栅极的相对侧壁上的栅极间隔件;
在所述衬底上方并且邻近所述第一金属栅极和所述第二金属栅极形成第一介电层;
使所述第一金属栅极和所述第二金属栅极凹进以具有位于所述第一介电层的顶面之下的顶面;
在所述第一金属栅极和所述第二金属栅极的凹进的顶面上形成第一硬掩模层;
使所述第一硬掩模层凹进以具有位于所述第一介电层的顶面之下的顶面;
在所述第一硬掩模层的凹进的顶面上形成第二硬掩模层,所述第二硬掩模层具有与所述第一硬掩模层不同的材料组分;以及
平坦化所述第二硬掩模层以具有与所述第一介电层的顶面共面的顶面。
10.一种半导体结构,包括:
第一栅极堆叠件,位于衬底上,所述第一栅极堆叠件包括第一高k栅极介电层和第一金属栅电极;
第一硬掩模层,位于所述第一栅极堆叠件上;
第一组栅极间隔件,位于所述第一栅极堆叠件和所述第一硬掩模层的相对侧壁上;
第一蚀刻停止层,位于所述第一组栅极间隔件的侧壁上;
第一层间电介质,围绕所述第一蚀刻停止层和所述第一栅极堆叠件,所述第一层间电介质接触所述第一蚀刻停止层的至少一部分;
第一导电接触件,延伸穿过所述第一层间电介质以接触所述衬底的顶面,所述第一导电接触件的侧壁接触所述第一蚀刻停止层的侧壁;
第二蚀刻停止层,位于所述第一蚀刻停止层、所述第一组栅极间隔件、所述第一硬掩模层和所述第一层间电介质的顶面上方并且接触所述第一蚀刻停止层、所述第一组栅极间隔件、所述第一硬掩模层和所述第一层间电介质的顶面;
第二层间电介质,位于所述第二蚀刻停止层上方;以及
第二导电接触件,延伸穿过所述第二层间电介质和所述第二蚀刻停止层以接触所述第一导电接触件。
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US20170288031A1 (en) | 2017-10-05 |
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TWI596705B (zh) | 2017-08-21 |
US9859386B2 (en) | 2018-01-02 |
US9548366B1 (en) | 2017-01-17 |
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