WO2023130489A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

Info

Publication number
WO2023130489A1
WO2023130489A1 PCT/CN2022/071574 CN2022071574W WO2023130489A1 WO 2023130489 A1 WO2023130489 A1 WO 2023130489A1 CN 2022071574 W CN2022071574 W CN 2022071574W WO 2023130489 A1 WO2023130489 A1 WO 2023130489A1
Authority
WO
WIPO (PCT)
Prior art keywords
groove
layer
passivation layer
semiconductor chip
passivation
Prior art date
Application number
PCT/CN2022/071574
Other languages
English (en)
French (fr)
Inventor
吕开敏
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2023130489A1 publication Critical patent/WO2023130489A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular, to semiconductor structures and manufacturing methods thereof.
  • the flip chip mounting method is widely used to mount semiconductor chips on package substrates such as printed circuit boards (PCBs).
  • PCBs printed circuit boards
  • the disclosure provides a semiconductor structure and a manufacturing method thereof, so as to improve the bonding force between the sealing layer and the semiconductor chip.
  • the specific technical scheme is as follows:
  • the first aspect of the present disclosure provides a semiconductor structure comprising:
  • a semiconductor chip comprising a passivation layer and a protection layer on the chip, the protection layer being located on the passivation layer;
  • the groove structure includes a first groove, and the first groove exposes the surface of the passivation layer.
  • the groove structure further includes a second groove, the second groove communicates with the first groove, and extends to the inside of the passivation layer without through the passivation layer.
  • the passivation layer includes a first material layer and a second material layer, wherein the first groove exposes the surface of the second material layer, and the second groove exposes the The surface of the first material layer.
  • the groove structure further includes a third groove, the third groove communicates with the second groove and the first groove, wherein the third A groove runs through the passivation layer.
  • a transverse dimension of the first groove is smaller than a transverse dimension of the second groove, and a transverse dimension of the second groove is smaller than a transverse dimension of the third groove.
  • first groove, the second groove, and the third groove are arranged adjacent to each other, wherein the second groove is arranged between the first groove and the third groove. between the third grooves.
  • the semiconductor structure further includes:
  • a sealing layer is on the protective layer and fills the groove structure.
  • the adhesion strength between the sealing layer and the protective layer is smaller than the adhesion strength between the sealing layer and the second material layer.
  • the adhesion strength between the sealing layer and the second material layer is smaller than the adhesion strength between the sealing layer and the first material layer.
  • the material of the protection layer is polyimide PI
  • the material of the first material layer is silicon dioxide
  • the material of the second material layer is silicon nitride.
  • a second aspect of the present disclosure provides a method of fabricating a semiconductor structure, comprising:
  • a semiconductor chip comprising a passivation layer and a protective layer on top; wherein the protective layer is located on the passivation layer;
  • a groove structure is formed in the protection layer; wherein, the groove structure includes a first groove, and the first groove exposes the surface of the passivation layer.
  • the forming a groove structure in the protective layer includes:
  • the protection layer is etched to form a groove structure including a first groove in the protection layer.
  • the second groove communicates with the first groove and extends to the inside of the passivation layer without penetrating through the passivation layer.
  • the passivation layer includes a first material layer and a second material layer, wherein the first groove exposes the surface of the second material layer, and the second groove exposes the The surface of the first material layer.
  • the method further includes:
  • the third groove communicates with the second groove and the first groove, wherein the third groove penetrates the passivation layer.
  • the forming a groove structure in the protective layer includes:
  • At least one groove structure is formed in the protective layer; the at least one groove structure is disposed at the 4 corners of the semiconductor chip and/or at the center of the semiconductor chip.
  • a semiconductor structure provided by the present disclosure includes a semiconductor chip and a groove structure, the semiconductor chip includes a passivation layer and a protective layer on the chip, the groove structure includes a first groove exposing the surface of the passivation layer, because the groove
  • the existence of the structure allows the sealing layer to contact the passivation layer through the groove structure, because the bonding force between the sealing layer and the passivation layer is greater than the bonding force between the sealing layer and the protective layer.
  • the contact area between the sealing layer and the semiconductor chip is also increased, so that the bonding force between the sealing layer and the semiconductor chip can be improved.
  • Fig. 1 is a structural schematic diagram of a 3DIC device
  • FIG. 2 is a schematic structural diagram of a semiconductor structure in the related art
  • FIG. 3 is a schematic structural diagram of a first semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a second semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a third semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a fourth semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 7(1) is a schematic diagram of a groove structure distribution provided by an embodiment of the present disclosure.
  • FIG. 7(2) is a schematic diagram of another groove structure distribution provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a fifth semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 9 is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • 312 protective layer
  • 32 groove structure
  • 321 the first groove
  • 322 the second groove
  • 323 the third groove
  • 3111 the first material layer
  • Flip chip assembly is an assembly method in which the semiconductor chip is connected downward to the substrate, carrier or circuit board through the bumps on the chip top (Chip Top) of the semiconductor chip.
  • a semiconductor chip that is directly connected to a substrate, carrier, or circuit board through bumps on the top of the chip is called a flip chip.
  • FIG. 1 it is a schematic structural diagram of a 3DIC device.
  • a semiconductor chip 1 and a semiconductor chip 2 are stacked, the bumps on the top of the semiconductor chip 1 are directly connected to the substrate, and the bumps on the top of the semiconductor chip 2 are connected to the semiconductor chip 1 .
  • FIG. 2 it is a schematic structural diagram of a semiconductor structure in the related art.
  • the sealing layer is in contact with said protective layer of the semiconductor chip. Therefore, in the related art, the bonding force between the sealing layer and the semiconductor chip is the bonding force between the sealing layer and the protective layer, which is often relatively small.
  • an embodiment of the present disclosure provides a semiconductor structure, which may include:
  • a semiconductor chip including a passivation layer and a protective layer on top of the chip, the protective layer being located on the passivation layer;
  • the groove structure includes a first groove, and the first groove exposes the surface of the passivation layer.
  • the semiconductor structure provided by the present disclosure includes a semiconductor chip and a groove structure, the semiconductor chip includes a passivation layer and a protective layer on the chip, and the groove structure includes a first groove exposing the surface of the passivation layer, because the groove structure
  • the existence of the sealing layer can contact the passivation layer through the groove structure, because the bonding force between the sealing layer and the passivation layer is greater than the bonding force between the sealing layer and the protective layer.
  • the contact area between the sealing layer and the semiconductor chip is also increased, so that the bonding force between the sealing layer and the semiconductor chip can be improved.
  • an embodiment of the present disclosure provides a semiconductor structure, including:
  • the semiconductor chip 31 includes a passivation layer 311 and a protection layer 312 on the top, and the protection layer 312 is on the passivation layer 311;
  • the groove structure 32 includes a first groove 321 , and the first groove 321 exposes the surface of the passivation layer 311 .
  • the above-mentioned semiconductor chip 31 is a semiconductor device that can realize a certain function and is made by etching and wiring on a semiconductor sheet.
  • a semiconductor chip After forming structures such as a device structure and an interconnection structure, in order to protect the semiconductor chip, it is necessary to form a passivation layer and a protective layer with protective capabilities on the surface of the semiconductor chip.
  • the surface and internal properties are different, so that the surface condition of the semiconductor chip has an important impact on the performance of the semiconductor chip.
  • the passivation layer 311 on the semiconductor chip 31 can be formed by a passivation process, for example, the surface on the electrical side of the semiconductor chip 31 is treated by a passivation process to form a layer covering the semiconductor chip 31.
  • the surface passivation film on one side of the electrical surface of the electric plane, the surface passivation film is the passivation layer 311 .
  • the above-mentioned passivation process can adopt oxidation thermal decomposition deposition, sputtering, vacuum evaporation, anodic oxidation, epitaxial deposition and so on.
  • the material of the passivation layer 311 can be silicon dioxide or silicon nitride, of course, the material of the passivation layer 311 can also be other materials such as phosphosilicate glass, borosilicate glass, semi-insulating polysilicon and the like.
  • the semiconductor chip 31 is on the passivation layer 311 and further includes a protection layer 312 .
  • the protection layer 312 is located on the passivation layer 311 , which can further enhance the protection of the semiconductor chip 31 .
  • the material of the protective layer 312 can be a composite material such as polyimide (Polyimide, referred to as PI), wherein polyimide is a kind of material with good high temperature resistance, low temperature resistance, radiation resistance and excellent electrical insulation performance. composite material.
  • the semiconductor structure further includes a groove structure 32 , the groove structure includes a first groove 321 , and the first groove 321 exposes the surface of the passivation layer 311 .
  • the first groove When filling material is used to fill the gap between the semiconductor chip and the packaging substrate, the first groove will be filled with the filling material, so that the formed sealing layer can contact the passivation layer through the groove structure, because the sealing layer and The bonding force between the passivation layers is greater than the bonding force between the sealing layer and the protective layer.
  • the contact area between the sealing layer and the semiconductor chip is also increased, so that it can Improve the bonding force between the sealing layer and the semiconductor chip.
  • the second groove 322 can further increase the contact area between the sealing layer and the passivation layer 311 , thereby further increasing the bonding force between the sealing layer and the passivation layer 311 .
  • the transverse dimension of the first groove 321 may be smaller than the transverse dimension of the second groove 322 , so that the sealing layer forms a barb structure, further increasing the bonding force between the sealing layer and the passivation layer 311 .
  • the lateral dimension of the first groove 321 may also be greater than or equal to the lateral dimension of the second groove 322 .
  • the passivation layer 311 includes a first material layer 3111 and a second material layer 3112, wherein the first groove 321 exposes the surface of the second material layer 3112, and the second groove 322 exposes the first material layer Layer 3111 surface.
  • the material of the first material layer 3111 may be silicon dioxide
  • the material of the second material layer 3112 may be silicon nitride.
  • FIG. 322 In order to further improve the bonding force between the sealing layer and the semiconductor chip, as shown in FIG. 322 communicates with the first groove 321 , wherein the third groove 322 penetrates the passivation layer 311 , and of course the third groove 322 may not penetrate the passivation layer 311 .
  • the first groove 321 , the second groove 322 , and the third groove 323 are arranged adjacently, wherein the second groove 322 is arranged between the first groove 321 and the third groove 323 .
  • the third groove 323 can further increase the contact area between the sealing layer and the passivation layer 311 , thereby further increasing the bonding force between the sealing layer and the passivation layer 311 .
  • the transverse dimension of the first groove 321 is smaller than the transverse dimension of the second groove 322, and the transverse dimension of the second groove 322 is smaller than the transverse dimension of the third groove 323, so that the sealing layer forms a multi-layer barb structure , the bonding force between the sealing layer and the passivation layer 311 can be further increased.
  • the lateral dimension of the first groove 321 can also be greater than or equal to the lateral dimension of the second groove 322, and the lateral dimension of the second groove 322 can also be greater than or equal to the lateral dimension of the third groove 323, This is all possible.
  • the above groove structure 32 may be any type of groove.
  • the shape of the opening of the above-mentioned groove structure 32 on the surface of the protective layer is a rectangle or a circle, of course, it can also be other shapes, such as triangles, irregular shapes, etc., which are all possible.
  • there is at least one groove structure 32 which is arranged at the four corners of the semiconductor chip and/or the center of the semiconductor chip.
  • the number of the groove structures 32 may be 4, 5 or 6 and so on.
  • the semiconductor structure has multiple groove structures 32
  • the symmetrical distribution of the plurality of groove structures 32 on the surface of the protective layer 312 may include left-right symmetrical distribution, vertical symmetrical distribution, or central symmetrical distribution, and which symmetrical distribution is used may be determined according to requirements and actual conditions.
  • FIG. 7(1) it is a schematic diagram of the distribution of a groove structure 32 provided by an embodiment of the present disclosure, which has four groove structures 32 distributed at four corners of the protective layer 312, form central symmetry.
  • the top corner of the protection layer 312 is a position in the protection layer 312 that is near a right angle. Since it is necessary to ensure that the four groove structures 32 are distributed symmetrically, the distances between the four groove structures 32 and the boundaries at the corners thereof are consistent.
  • FIG. 7(2) it is a schematic diagram of the distribution of another groove structure 32 provided by the embodiment of the present disclosure, which has 5 groove structures 32 distributed at the 4 corners of the protective layer 312 Four groove structures 32 at the center and one groove structure 32 at the center of the protective layer 312 form a central symmetry.
  • the distance between the left vertical edge of the groove structure 32 in the upper left corner and the left vertical edge of the protective layer 312, the distance between the left vertical edge of the groove structure 32 in the lower left corner and the left vertical edge of the protective layer 312 The distance between the right vertical edge of the upper right groove structure 32 and the right vertical edge of the protective layer 312, the distance between the right vertical edge of the lower right groove structure 32 and the right vertical edge of the protective layer 312 are all the same.
  • the distance between the upper lateral edge of the upper left corner groove structure 32 and the upper lateral edge of the protective layer 312, the distance between the lower lateral edge of the lower left corner groove structure 32 and the lower lateral edge of the protective layer 312, the upper right groove The distance between the upper lateral side of the structure 32 and the upper lateral side of the protective layer 312 and the distance between the lower lateral side of the lower right corner groove structure 32 and the lower lateral side of the protective layer 312 are the same.
  • the distance between any groove structure 32 and the edge of the protective layer should not be too small.
  • the distance between the upper lateral edge and the upper lateral edge of the protective layer 312 should be greater than a specified distance.
  • the designated distance may be determined based on the actual area of the semiconductor chip, the larger the area of the semiconductor chip, the larger the designated distance may be, conversely, the smaller the area of the semiconductor chip, the smaller the designated distance.
  • the specified distance may be 100 microns.
  • the protective layer 312 has five groove structures 32, then four groove structures 32 may be distributed at the four corners of the protective layer 312, while another groove structure 32 is distributed with the protective layer 312. central location.
  • the total opening area of the plurality of groove structures 32 is greater than 100,000 square micrometers and less than 500,000 square micrometers.
  • the total opening area of the plurality of groove structures 32 is: the sum of the opening areas of each groove structure 32 on the surface of the protection layer 312 away from the passivation layer 311 .
  • the opening areas of each groove structure 32 are the same, that is, the opening area of each groove structure 32 is greater than 100000/N square microns, and Less than 500000/N square microns, where N is the number of groove structures 32 .
  • the opening area of each groove structure 32 is greater than 25000 square micrometers and less than 125000 square micrometers.
  • the semiconductor structure provided in the present disclosure includes a groove structure 32 , so that the passivation layer 311 can be exposed by the passivation layer 312 at the position of the groove structure.
  • the filling material can contact the exposed passivation layer 311 through the groove structure 32 on the protective layer 312, so that the sealing layer formed by the filling material filling can cover the passivation layer 311.
  • the above-mentioned underfill process may be a MUF (Molded Under fill, molded underfill) process, a capillary tube underfill process, and other filling processes.
  • the semiconductor structure above further includes: a sealing layer 33 , the sealing layer 33 is on the protective layer 312 and in contact with the protective layer 321 , and fills the groove structure 32 .
  • the adhesion strength between the sealing layer 33 and the protective layer 312 is smaller than the adhesion strength between the sealing layer 33 and the second material layer 3112 . Therefore, the bonding force between the sealing layer 33 and the semiconductor chip can be increased through the groove structure 32 .
  • the adhesion strength between the sealing layer 33 and the second material layer 3112 is smaller than the adhesion strength between the sealing layer 33 and the first material layer 3111, so that the bonding force between the sealing layer 33 and the semiconductor chip can be further improved.
  • the protective layer material is PI (epoxy resin) or underfill glue, such as resin, thermally conductive silica gel, thermally conductive black glue, etc.
  • the material of the first material layer is silicon dioxide
  • the material of the second material layer is nitrogen Silicon.
  • the semiconductor structure provided by the present disclosure includes a semiconductor chip and a groove structure, the semiconductor chip includes a passivation layer and a protective layer on the chip, and the groove structure includes a first groove exposing the surface of the passivation layer, because the groove structure
  • the existence of the sealing layer can contact the passivation layer through the groove structure, because the bonding force between the sealing layer and the passivation layer is greater than the bonding force between the sealing layer and the protective layer.
  • the contact area between the sealing layer and the semiconductor chip is also increased, so that the bonding force between the sealing layer and the semiconductor chip can be improved.
  • the embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, including:
  • S901 providing a semiconductor chip topped with a passivation layer and a protection layer; wherein the protection layer is located on the passivation layer.
  • the semiconductor chip before performing the method for manufacturing the semiconductor structure, may have a passivation layer formed on the top of the chip in advance, and a protective layer on the passivation layer.
  • passivation processes such as oxidative thermal decomposition deposition, sputtering, vacuum evaporation, anodic oxidation, and epitaxial deposition can be performed first.
  • a passivation layer is formed on one side of the electrical side, and then a liquid mold compound is applied on the passivation layer to form a protective layer.
  • the material of the passivation layer may be silicon dioxide and/or silicon nitride, and the liquid mold compound may be polyimide.
  • FIG. 6 it is a schematic diagram of a semiconductor chip provided by an embodiment of the present disclosure.
  • 31 is a semiconductor chip
  • 311 is a passivation layer
  • 312 is a protection layer.
  • the protection layer may be etched to form a groove structure including the first groove in the protection layer.
  • step 1-step 2 In order to form the groove structure including the first groove by etching the protective layer, step 1-step 2 can be adopted:
  • Step 1 Provide a mask plate with a mask structure on the mask plate.
  • the position, quantity and pattern shape of the mask structure on the provided mask plate need to be consistent with the position, quantity and opening shape of the groove structure to be formed in the protective layer.
  • the provided mask will also It is necessary to have a mask structure with a pattern shape of a rectangle and a size of 100 microns x 50 microns at the four corners of the mask.
  • the mask plate is divided into a light-shielding area and a non-light-shielding area, and the mask structure referred to in the present disclosure is also different according to the difference of the photoresist used subsequently.
  • the above-mentioned photoresist can be divided into positive photoresist and negative photoresist. Among them, the part of the positive photoresist that is not exposed to light will be retained after development, while the part of the negative photoresist that is exposed to light will be retained after development. is reserved.
  • the above-mentioned mask structure is a non-shielding area on the mask plate; otherwise, if the photoresist used is a negative photoresist, the above-mentioned mask structure is a mask structure. Shading area on the stencil.
  • Step 2 using the mask as a mask, etching the protective layer covered by the mask structure to form a first groove in the protective layer; wherein, the first groove exposes the surface of the passivation layer;
  • the photoresist can be evenly spread on the protective layer, and then the mask plate is covered on the protective layer.
  • photolithography can be performed first, that is, the mask can be irradiated with light of a specific wavelength.
  • the photoresist under it Light will be received, and the photosensitive agent in the photoresist will react photochemically.
  • the photoresist is a positive photoresist
  • the chemical composition of the irradiated area of the positive photoresist changes, so that it can be dissolved in the developer, while the unirradiated area (corresponding to the non-shielding area of the mask) changes.
  • the shading area in the stencil has the same chemical composition and is insoluble in the developer solution.
  • the chemical composition of the non-irradiated area of the negative photoresist changes, so that it can be dissolved in the developer, while the irradiated area (corresponding to the mask area)
  • the non-shielding area in the plate has the same chemical composition and is insoluble in the developer.
  • etching is performed on the area on the protective layer not covered by the photoresist. According to different usage scenarios and requirements, different methods can be used for etching.
  • dry etching can be performed on the areas of the protective layer not covered by the photoresist.
  • dry etching there are many ways of dry etching, such as sputtering and ion beam milling, plasma etching (Plasma etching), high pressure plasma etching, high density plasma etching, reactive ion etching and so on.
  • wet etching may be performed on the area on the protective layer not covered by the photoresist.
  • wet etching is a pure chemical reaction process, which means to use the chemical reaction between the solution and the material to be etched to remove the area not covered by the photoresist to achieve the purpose of etching.
  • the solution used may be a solution that reflects the material of the protective layer.
  • a first groove exposing the surface of the passivation layer can be formed in the protective layer.
  • the groove structure when the groove structure only includes the first groove, that is, the groove structure does not need to extend to the inside of the passivation layer, then only the protective layer needs to be etched, and there is no need to etch the passivation layer at this time. etch.
  • an etching process is used to etch a first groove 321 on the protection layer 312 .
  • the surface of the passivation layer exposed by the first groove can also be used to etch the passivation layer.
  • the passivation layer is used to form a groove structure in the passivation layer which also includes a second groove; the second groove communicates with the first groove and extends to the inside of the passivation layer without penetrating through the passivation layer.
  • the protective layer needs to be etched, but also the passivation layer needs to be etched. Further, as shown in FIG. 4 , after the etching of the protective layer 312 is completed, the etching is continued on the passivation layer 311 to form the second groove 322 . It should be noted that, since the materials of the protection layer 312 and the passivation layer 311 are different, the specific etching method of the protection layer 312 may be different from the specific etching method of the passivation layer 311 and may be determined according to actual conditions.
  • the passivation layer 311 may include a first material layer 3111 and a second material layer 3112, wherein the first groove 321 exposes the surface 3112 of the second material layer, and the second material layer 3112 is exposed.
  • the second groove 322 exposes the surface of the first material layer 3111 .
  • the aforementioned etching of the passivation layer may only etch the second material layer without etching the first material layer, thereby forming a second groove exposing the surface of the first material layer.
  • the second recess to The surface of the first material layer exposed by the groove is etched to form a groove structure including a third groove in the first material layer; the third groove is the same as the second groove and the first groove The grooves are connected, and the third groove runs through the passivation layer.
  • the exposed first material layer 3111 can also be etched to utilize the exposed area of the second groove.
  • the surface of the first material layer 3111 is etched to form a third groove 323 .
  • the specific etching methods of the second material layer 3112 and the first material layer 3111 may be different from those of the protective layer 312 .
  • the etching methods are different and can be determined according to the actual situation.
  • At least one groove structure can be formed in the protective layer; at least one groove structure is arranged at the four corners of the semiconductor chip and/or the center of the semiconductor chip.
  • the above-mentioned method for manufacturing a semiconductor structure can form a semiconductor chip and a groove structure.
  • the semiconductor chip includes a passivation layer and a protective layer on the chip. Groove, due to the existence of the groove structure, the sealing layer can contact the passivation layer through the groove structure, because the bonding force between the sealing layer and the passivation layer is greater than the bonding force between the sealing layer and the protective layer, and at the same time, Compared with the semiconductor chip without the groove structure, the contact area between the sealing layer and the semiconductor chip is also increased, so that the bonding force between the sealing layer and the semiconductor chip can be improved.
  • a filling material may also be filled to form a sealing layer on and in contact with the protection layer and fill the groove structure.
  • the semiconductor chip can be filled with an underfill, that is, filled with a filling material, so as to form a sealing layer covering the protective layer and filling the groove structure.
  • the above-mentioned underfilling may adopt a filling process such as a MUF process, a capillary tube underfilling process, or the like.
  • a layer of sealing layer 33 will be covered on the protective layer 312, and the sealing layer 33 fills the groove structure 32, so that the sealing layer 33 can be in contact with the protective layer 312, and also The groove structure 32 can be in contact with the passivation layer 311 , so that the bonding force between the sealing layer 33 and the semiconductor chip 31 can be increased.
  • each embodiment in this specification is described in a related manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for relevant parts, please refer to part of the description of the method embodiments.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本公开实施例提供了半导体结构及其制造方法，应用于半导体技术领域。该半导体结构包括：半导体芯片，包括位于芯片上的钝化层与保护层，保护层位于钝化层之上；凹槽结构，包括第一凹槽，第一凹槽暴露钝化层表面。通过本方案，可以提升密封层与半导体芯片之间的结合力。

Description

半导体结构及其制造方法
本公开要求于2022年01月05日提交中国专利局、申请号为202210004276.1发明名称为“半导体结构及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，特别是涉及半导体结构及其制造方法。
背景技术
倒装芯片安装方法广泛地用来将半导体芯片安装在诸如印刷电路板(PCB)的封装基板上。在采用倒装芯片安装方法的封装半导体芯片的过程中，需要使用填充料填充半导体芯片与封装基板之间的空隙，以增大封装后器件的可靠性。
相关研究表明，通过填充料所形成的密封层与半导体芯片之间的结合力越大，封装后器件的可靠性越好，因此，如何提升密封层与半导体芯片之间的结合力是亟需解决的技术问题。
发明内容
本公开提供一种半导体结构及其制造方法，以提升密封层与半导体芯片之间的结合力。具体技术方案如下：
根据一些实施例，本公开第一方面提供一种半导体结构，包括：
半导体芯片，包括位于芯片上的钝化层与保护层，所述保护层位于所述钝化层之上；
凹槽结构，包括第一凹槽，所述第一凹槽暴露所述钝化层表面。
在一种可能的实施方式中，所述凹槽结构，还包括第二凹槽，所述第二凹槽与所述第一凹槽相连通，并延伸至所述钝化层的内部且不贯穿所述钝化层。
在一种可能的实施方式中，所述钝化层包括第一材料层和第二材料层，其中所述第一凹槽暴露所述第二材料层表面，所述第二凹槽暴露所述第一材料层表面。
在一种可能的实施方式中，所述凹槽结构，还包括第三凹槽，所述第三凹槽与所述第二凹槽及所述第一凹槽相连通，其中所述第三凹槽贯穿所述钝化层。
在一种可能的实施方式中，所述第一凹槽的横向尺寸小于所述第二凹槽的横向尺寸，所述第二凹槽的横向尺寸小于所述第三凹槽的横向尺寸。
在一种可能的实施方式中，所述第一凹槽、所述第二凹槽、所述第三凹槽相邻设置，其中所述第二凹槽设于所述第一凹槽与所述第三凹槽之间。
在一种可能的实施方式中，所述凹槽结构为至少一个，且设置在所述半导体芯片的4个顶角和/或所述半导体芯片的中心处。
在一种可能的实施方式中，所述半导体结构，还包括：
密封层，所述密封层在所述保护层之上，且填充所述凹槽结构。
在一种可能的实施方式中，所述密封层与保护层的黏附强度小于所述密封层与所述第二材料层的黏附强度。
在一种可能的实施方式中，所述密封层与所述第二材料层的黏附强度小于所述密封层与所述第一材料层的黏附强度。
在一种可能的实施方式中，所述保护层材料是聚酰亚胺PI，所述第一材料层的材料为二氧化硅，所述第二材料层的材料为氮化硅。
根据一些实施例，本公开第二方面提供一种制作半导体结构的方法，包括：
提供顶部包括钝化层与保护层的半导体芯片；其中，所述保护层位于所述钝化层之上；
在所述保护层中形成凹槽结构；其中，所述凹槽结构包括第一凹槽，所述第一凹槽暴露所述钝化层表面。
在一种可能的实施方式中，所述在所述保护层中形成凹槽结构，包括：
刻蚀所述保护层，以在所述保护层中形成包括第一凹槽的凹槽结构。
在一种可能的实施方式中，在所述刻蚀所述保护层之后，还包括：
利用所述第一凹槽所暴露的所述钝化层的表面，刻蚀所述钝化层，以在所述钝化层中形成还包括第二凹槽的所述凹槽结构；所述第二凹槽与所述第一凹槽相连通，并延伸至所述钝化层的内部且不贯穿所述钝化层。
在一种可能的实施方式中，所述钝化层包括第一材料层和第二材料层，其中所述第一凹槽暴露所述第二材料层表面，所述第二凹槽暴露所述第一材料层表面。
在一种可能的实施方式中，在所述利用所述第一凹槽所暴露的所述钝化层的表面，刻蚀所述钝化层之后，还包括：
利用所述第二凹槽所暴露的所述第一材料层的表面，刻蚀所述第一材料层，以在所述第一材料层中形成还包括第三凹槽的所述凹槽结构；所述第三凹槽与所述第二凹槽及所述第一凹槽相连通，其中所述第三凹槽贯穿所述钝化层。
在一种可能的实施方式中，所述在所述保护层中形成凹槽结构，包括：
在所述保护层中形成至少一个凹槽结构；所述至少一个凹槽结构设置在所述半导体芯片的4个顶角和/或所述半导体芯片的中心处。
本公开实施例有益效果：
本公开所提供的一种半导体结构，包括半导体芯片和凹槽结构，半导体芯片包括位于芯片上的钝化层与保护层，凹槽结构包括暴露钝化层表面的第一凹槽，由于凹槽结构的存在，使得密封层可以通过凹槽结构与钝化层接触，由于密封层与钝化层之间的结合力大于密封层与保护层的之间的结合力，同时，与不具有凹槽结构的半导体芯片相比，也增大了密封层与半导体芯片的接触面积，从而可以提升密封层与半导体芯片之间的结合力。
当然，实施本公开的任一产品或方法并不一定需要同时达到以上所述的所有优点。
附图说明
为了更清楚地说明本公开实施例和现有技术的技术方案，下面对实施例和现有技术中所需要使用的附图作简单地介绍，显而易见地，下面描述中的 附图仅仅是本公开的一些实施例，本领域普通技术人员来讲还可以根据这些附图获得其他的附图。
图1为一种3DIC器件的结构示意图；
图2为相关技术中半导体结构的结构示意图；
图3为本公开实施例提供的第一种半导体结构的结构示意图；
图4为本公开实施例提供的第二种半导体结构的结构示意图；
图5为本公开实施例提供的第三种半导体结构的结构示意图；
图6为本公开实施例提供的第四种半导体结构的结构示意图；
图7(1)为本公开实施例提供的一种凹槽结构分布示意图；
图7(2)为本公开实施例提供的另一种凹槽结构分布示意图；
图8为本公开实施例提供的第五种半导体结构的结构示意图；
图9为本公开实施例提供的一种制作半导体结构的方法的流程图；
31：半导体芯片；                     311：钝化层；
312：保护层；                        32：凹槽结构；
321：第一凹槽；                      322：第二凹槽；
323：第三凹槽；                      3111：第一材料层；
3112：第二材料层；                   33：密封层。
具体实施方式
为使本公开的目的、技术方案、及优点更加清楚明白，以下参照附图并举实施例，对本公开进一步详细说明。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。本领域普通技术人员基于本公开中的实施例所获得的所有其他实施例，都属于本公开保护的范围。
倒装芯片(Flip Chip)组装为通过半导体芯片的芯片顶部(Chip Top)上的凸点，将半导体芯片朝下连接到基板、载体或者电路板上的组装方式。而通过芯片顶部上的凸点直接连接在基板、载体或者电路板上的半导体芯片被 称为倒装芯片。
需要说明的是，对于3D-IC(Three Dimensional Integrated Circuits，三维集成电路)器件而言，由于3D-IC是将多个半导体芯片垂直堆叠在一个封装器件中，因此，对于半导体芯片而言，其衬底可能是基板，也可能是其他半导体芯片。示例性的，如图1所示，为一种3DIC器件的结构示意图。图1中，半导体芯片1与半导体芯片2堆叠，半导体芯片1的芯片顶部上的凸点直接连接在基板上，半导体芯片2的芯片顶部上的凸点则连接在半导体芯片1上。
在将半导体芯片的芯片顶部上的凸点连接在基板、载体或者电路板上后，由于半导体芯片与连接的基板、载体或者电路板之间存在间隙，因此，需要使用填充材料填充半导体芯片与基板、载体或者电路板之间的空隙，以增大封装后器件的可靠性。
相关研究表明，通过填充料所形成的密封层与半导体芯片之间的结合力越大，封装后器件的可靠性越好。因此，如何提升密封层与半导体芯片之间的结合力是亟需解决的技术问题。
如图2所示，为相关技术中半导体结构的结构示意图。对于半导体芯片而言，密封层与半导体芯片的所述保护层接触。因此，相关技术中，密封层与半导体芯片之间的结合力为密封层与保护层之间的结合力，往往较小。
为了提升密封层与半导体芯片之间的结合力，本公开实施例提供一种半导体结构，可以包括：
半导体芯片，包括位于芯片顶部的钝化层与保护层，保护层位于钝化层之上；
凹槽结构，包括第一凹槽，第一凹槽暴露钝化层表面。
本公开所提供的半导体结构中，包括半导体芯片和凹槽结构，半导体芯片包括位于芯片上的钝化层与保护层，凹槽结构包括暴露钝化层表面的第一凹槽，由于凹槽结构的存在，使得密封层可以通过凹槽结构与钝化层接触，由于密封层与钝化层之间的结合力大于密封层与保护层的之间的结合力，同时，与不具有凹槽结构的半导体芯片相比，也增大了密封层与半导体芯片的接触面积，从而可以提升密封层与半导体芯片之间的结合力。
下面结合附图对本公开实施例所提供的半导体结构进行介绍。
如图3所示，本公开实施例提供一种半导体结构，包括：
半导体芯片31，包括位于上的钝化层311与保护层312，保护层312位于钝化层311之上；
凹槽结构32，包括第一凹槽321，第一凹槽321暴露钝化层311表面。
上述半导体芯片31为在半导体片材上进行浸蚀、布线，制成的能实现某种功能的半导体器件。在半导体芯片制作过程中，当形成器件结构和互连结构等结构后，为了保护半导体芯片，需要在半导体芯片的表面形成具有防护能力的钝化层与保护层。简单而言，由于半导体芯片的表面与内部结构的差异，导致表面与内部性质不同，使得半导体芯片的表面状况对半导体芯片的性能有重要影响，例如，半导体芯片的表面只要有微量的沾污(如有害的杂质离子、水汽、尘埃等)，就可能导致半导体芯片功能异常。因此，为提高半导体芯片性能的稳定性和可靠性，需要在半导体芯片的表面形成钝化层与保护层。
在一实现方式中，半导体芯片31上的钝化层311可以通过钝化工艺形成，例如通过钝化工艺对半导体芯片31的电气面一侧的表面进行处理，以形成一层覆盖在半导体芯片31的电气面一侧表面的表面钝化膜，该表面钝化膜即为钝化层311。
上述钝化工艺可以采用氧化热分解淀积、溅射、真空蒸发、阳极氧化、外延淀积等。钝化层311的材料可以为二氧化硅或氮化硅，当然，钝化层311的材料也可以为磷硅玻璃、硼硅玻璃、半绝缘多晶硅等其他材料。
半导体芯片31在钝化层311之上，还包含保护层312。如图3所示，保护层312位于钝化层311之上，可以进一步的增强对半导体芯片31的保护。保护层312的材料可以为聚酰亚胺(Polyimide，简称PI)等复合材料，其中，聚酰亚胺是一种具有很好的耐高温、耐低温、耐辐射性能和优良的电气绝缘性能的复合材料。
为了提升密封层与半导体芯片之间的结合力，半导体结构中还包括凹槽结构32，该凹槽结构包括第一凹槽321，第一凹槽321暴露钝化层311表面。
当使用填充料填充半导体芯片与封装基板之间的空隙时，该第一凹槽将被填充料所填充，从而使得所形成的密封层可以通过凹槽结构与钝化层接触， 由于密封层与钝化层之间的结合力大于密封层与保护层的之间的结合力，同时，与不具有凹槽结构的半导体芯片相比，也增大了密封层与半导体芯片的接触面积，从而可以提升密封层与半导体芯片之间的结合力。
为了进一步的提升密封层与半导体芯片之间的结合力，如图4所示，本公开实施例中，凹槽结构32，还包括第二凹槽322，第二凹槽322与第一凹槽321相连通，并延伸至钝化层311的内部且不贯穿钝化层。
通过第二凹槽322可以进一步增大密封层与钝化层311之间的接触面积，从而进一步增大密封层与钝化层311之间的结合力。可选的，第一凹槽321的横向尺寸可以小于第二凹槽322的横向尺寸，进而使得密封层形成倒钩结构，进一步增大密封层与钝化层311之间的结合力。当然，为了简化工艺，第一凹槽321的横向尺寸也可以大于或等于第二凹槽322的横向尺寸。
可选的，如图5所示，钝化层311包括第一材料层3111和第二材料层3112，其中第一凹槽321暴露第二材料层3112表面，第二凹槽322暴露第一材料层3111表面。可选的，一种实现方式中，第一材料层3111的材料可以为二氧化硅，第二材料层3112的材料可以为氮化硅。
为了进一步的提升密封层与半导体芯片之间的结合力，如图6所示，本公开实施例中，凹槽结构32，还包括第三凹槽323，第三凹槽323与第二凹槽322及第一凹槽321相连通，其中第三凹槽322贯穿钝化层311，当然述第三凹槽322也可以不贯穿钝化层311。可选的，第一凹槽321、第二凹槽322、第三凹槽323相邻设置，其中第二凹槽322设于第一凹槽321与第三凹槽323之间。
通过第三凹槽323可以进一步增大密封层与钝化层311之间的接触面积，从而进一步增大密封层与钝化层311之间的结合力。可选的，第一凹槽321的横向尺寸小于第二凹槽322的横向尺寸，而第二凹槽322的横向尺寸小于第三凹槽323的横向尺寸，使得密封层形成多层倒钩结构，可以进一步增大密封层与钝化层311之间的结合力。当然，为了简化工艺，第一凹槽321的横向尺寸也可以大于或等于第二凹槽322的横向尺寸，第二凹槽322的横向尺寸也可以大于或等于第三凹槽323的横向尺寸，这都是可以的。
可选的，上述凹槽结构32可以任意类型的凹槽。在一种实现方式中，上 述凹槽结构32在保护层表面的开口形状为矩形或圆形，当然也可以为其他形状，例如三角形、不规则形状等，这都是可以的。
本公开实施例中，凹槽结构32为至少一个，且设置在半导体芯片的4个顶角和/或半导体芯片的中心。示例性的，凹槽结构32的数量可以为4个、5个或6个等。
在半导体结构具有多个凹槽结构32的情况下，为了确保半导体芯片31的芯片顶部的应力平衡，需要确保多个凹槽结构32在保护层312表面对称分布。其中，多个凹槽结构32在保护层312表面的对称分布可以包括左右对称分布、上下对称分布或中心对称分布，具体采用哪种对称分布，可以根据需求与实际情况确定。
在一示例中，如图7(1)所示，为本公开实施例提供的一种凹槽结构32分布示意图，具有4个凹槽结构32，分布于保护层312的4个顶角处，形成中心对称。其中，保护层312的顶角为保护层312中位于直角附近的位置。由于需要确保4个凹槽结构32对称分布，因此，该4个凹槽结构32与所在顶角处边界的距离是一致的。
在另一示例中，如图7(2)所示，为本公开实施例提供的另一种凹槽结构32分布示意图，具有5个凹槽结构32，分布于保护层312的4个顶角处4个凹槽结构32，以及位于保护层312中心位置处的1个凹槽结构32，形成中心对称。
以图7(1)为例，左上角凹槽结构32左竖边与保护层312的左竖边之间的距离、左下角凹槽结构32左竖边与保护层312的左竖边之间的距离、右上角凹槽结构32右竖边与保护层312的右竖边之间的距离、右下角凹槽结构32右竖边与保护层312的右竖边之间的距离均相同。同时，左上角凹槽结构32上横边与保护层312的上横边之间的距离、左下角凹槽结构32下横边与保护层312的下横边之间的距离、右上角凹槽结构32上横边与保护层312的上横边之间的距离、右下角凹槽结构32下横边与保护层312的下横边之间的距离均相同。
需要说明的是，为了避免破坏保护层的结构，任意一个凹槽结构32与保护层的边缘的距离不应太小。以图7(1)或图7(2)左上角凹槽结构32为 例，该凹槽结构32的左竖边与保护层312的左竖边之间的距离，以及该凹槽结构32的上横边与保护层312的上横边之间的距离均应当大于指定距离。其中，该指定距离可以基于半导体芯片的实际面积确定，半导体芯片的面积越大，该指定距离可以越大，反之，半导体芯片的面积越小，该指定距离可以越小。举例而言，该指定距离可以为100微米。
在另一示例中，若保护层312具有5个凹槽结构32，则可以在保护层312的4个顶角处分布4个凹槽结构32，而另一个凹槽结构32分布与保护层312的中心位置。
为了确保能够提升足够的结合力，在一种实现方式中，多个凹槽结构32的总开口面积大于100000平方微米，且小于500000平方微米。上述多个凹槽结构32的总开口面积为：各个凹槽结构32在保护层312远离钝化层311的一侧表面上开口面积之和。可选的，在一种实现方式中，为了确保半导体芯片31芯片顶部的应力平衡，各个凹槽结构32的开口面积相同，即每个凹槽结构32的开口面积大于100000/N平方微米，且小于500000/N平方微米，其中N为凹槽结构32的数量。示例性的，以图7(1)具有4个凹槽结构32为例，每个凹槽结构32的开口面积大于25000平方微米，且小于125000平方微米。
本公开所提供的半导体结构包含凹槽结构32，可以使得保护层312在凹槽结构的位置处可以暴露钝化层311。这样，在采用底部填充工艺对半导体芯片31进行底部填充时，填充料可以通过保护层312上的凹槽结构32与暴露的钝化层311接触，使得填充料填充所形成的密封层可以覆盖钝化层311暴露的表面。上述底部填充工艺可以为MUF(Molded Under fill，模塑底部填充)工艺、毛细管底部填充工艺等填充工艺。
如图8所示，上述半导体结构还包括：密封层33，密封层33在保护层312之上并与保护层321接触，且填充凹槽结构32。可选的，密封层33与保护层312的黏附强度小于密封层33与第二材料层3112的黏附强度。从而可以通过凹槽结构32可以增大密封层33与半导体芯片之间的结合力。可选的，密封层33与第二材料层3112的黏附强度小于密封层33与第一材料层3111的黏附强度，从而可以进一步的提升密封层33与半导体芯片之间的结合力。 示例性的，保护层材料是PI(环氧树脂)或底部填充胶，例如树脂，导热硅胶、导热黑胶等，上述第一材料层的材料为二氧化硅，第二材料层的材料为氮化硅。
本公开所提供的半导体结构中，包括半导体芯片和凹槽结构，半导体芯片包括位于芯片上的钝化层与保护层，凹槽结构包括暴露钝化层表面的第一凹槽，由于凹槽结构的存在，使得密封层可以通过凹槽结构与钝化层接触，由于密封层与钝化层之间的结合力大于密封层与保护层的之间的结合力，同时，与不具有凹槽结构的半导体芯片相比，也增大了密封层与半导体芯片的接触面积，从而可以提升密封层与半导体芯片之间的结合力。
相应于本公开实施例提供的半导体结构，如图9所示，本公开实施例还提供一种制作半导体结构的方法，包括：
S901，提供顶部包括钝化层与保护层的半导体芯片；其中，保护层位于钝化层之上。
其中，在执行制作半导体结构的方法之前，半导体芯片可以预先在芯片顶部形成钝化层，以及位于钝化层之上保护层。示例性的，半导体芯片在进行浸蚀、布线完成内部器件的构建之后，可以先通过氧化热分解淀积、溅射、真空蒸发、阳极氧化、外延淀积等钝化处理工艺，在半导体芯片的电气面一侧表面形成钝化层，进而在钝化层之上涂抹液态模复合物，形成一层保护层。其中，钝化层的材料可以为二氧化硅和/或氮化硅，液态模复合物可以为聚酰亚胺。
示例性的，如图6所示，为本公开实施例提供的半导体芯片示意图。其中，31为半导体芯片，311为钝化层，312为保护层。
S902，在保护层中形成凹槽结构；其中，凹槽结构包括第一凹槽，第一凹槽暴露钝化层表面。
可选的，在一种实现方式中，如图3所示，可以刻蚀保护层，以在保护层中形成包括第一凹槽的凹槽结构。
为了通过刻蚀保护层，形成包含第一凹槽的凹槽结构，可以采用步骤1-步骤2：
步骤1：提供掩膜版，掩膜版上具有掩膜结构。
其中，所提供的掩膜版上的掩膜结构的位置、数量以及图案形状，需要与保护层中所需形成的凹槽结构的位置、数量以及开口形状保持一致。举例而言，当需要在保护层的4个顶角处上分别形成4个，开口形状为矩形且单个大小为100微米×50微米的凹槽结构时，则所提供的掩膜版上，也需要在掩膜版的4个顶角处具有图案形状为矩形、大小为100微米×50微米的掩膜结构。
其中，掩膜版上分为遮光区与非遮光区，根据后续使用光刻胶的不同，本公开所指掩膜结构也不同。上述光刻胶可以分为正光刻胶和负光刻胶两种，其中，正光刻胶未被光照的部分在显影后会被保留，而负光刻胶被感光的部分在显影后会被保留。若所使用的光刻胶为正光刻胶，则上述掩膜结构为掩膜版上的非遮光区，反之，若所使用的光刻胶为负光刻胶，则上述掩膜结构为掩膜版上的遮光区。
步骤2：以掩膜版作为掩膜，刻蚀被掩膜结构遮挡的保护层，以在保护层中形成第一凹槽；其中，第一凹槽暴露钝化层表面；
在提供掩膜版之后，可以将光刻胶均匀涂抹在保护层上，进而将掩膜版覆盖保护层之上。再将掩膜版覆盖在保护层之上后，可以先进行光刻，即可以使用特定波长的光对掩膜版进行照射，对于掩膜版上非遮光区而言，其下的光刻胶将接收到光照，进而光刻胶中的感光剂会发生光化学反应。
若光刻胶为正光刻胶，则正光刻胶被照射区域(对应掩膜版中的非遮光区域)化学成分发生变化，从而可以溶于显影液中，而未被照射区域(对应掩膜版中的遮光区域)化学成分不变，不溶于显影液中。若光刻胶为负光刻胶，则负光刻胶未被照射区域(对应掩膜版中的遮光区域)化学成分发生变化，从而可以溶于显影液中，而被照射区域(对应掩膜版中的非遮光区域)化学成分不变，不溶于显影液中。
光照结束后，使用显影液清洗保护层之上的光刻胶，进而在对应掩膜版上的掩膜结构的位置处的光刻胶将被清洗，而其他位置处的光刻胶将被保留。
进一步的，对保护层上未被光刻胶覆盖的区域进行刻蚀。根据不同的使用场景和需求，可以采用不同的方式进行刻蚀。
在一种实现方式中，可以对保护层上未被光刻胶覆盖的区域进行干法刻 蚀。其中，干法刻蚀的方式有多种，例如溅射与离子束铣蚀、等离子刻蚀(Plasma Etching)、高压等离子刻蚀、高密度等离子体刻蚀、反应离子刻蚀等。
在一种实现方式中，可以对保护层上未被光刻胶覆盖的区域进行湿法刻蚀。其中，湿法法刻蚀是一个纯粹的化学反应过程，是指利用溶液与待刻蚀材料之间的化学反应来去除未被光刻胶覆盖的区域而达到刻蚀目的。在本公开实施例中，所利用的溶液可以为与保护层的材料反映的溶液。
在对保护层刻蚀结束之后，即可在保护层中形成暴露钝化层表面的第一凹槽。
在一种实现方式中，凹槽结构仅包含第一凹槽时，即凹槽结构无需延伸至钝化层的内部，则仅需要对保护层进行蚀刻即可，此时无需对钝化层进行蚀刻。示例性的，如图3所示，使用刻蚀工艺，在保护层312上刻蚀出第一凹槽321。
可选的，一种实现方式中，为了进一步增强密封层与半导体芯片之间的结合力，在刻蚀保护层之后，还可以利用第一凹槽所暴露的钝化层的表面，刻蚀钝化层，以在钝化层中形成还包括第二凹槽的凹槽结构；第二凹槽与第一凹槽相连通，并延伸至钝化层的内部且不贯穿钝化层。
本实现方式中不仅需要对保护层进行蚀刻，还需要对钝化层进行蚀刻。进一步的，如图4所示，在保护层312刻蚀结束后，继续在钝化层311上进行刻蚀，以形成第二凹槽322。需要说明的是，由于保护层312与钝化层311的材料不同，因此，保护层312具体的刻蚀方式可以与钝化层311具体刻蚀方式不同，可以根据实际情况确定。
可选的，在一种实现例中，如图5所示，钝化层311可以包括第一材料层3111和第二材料层3112，其中第一凹槽321暴露第二材料层表面3112，第二凹槽322暴露第一材料层3111表面。本实现方式中，上述对钝化层进行刻蚀可以仅对第二材料层进行刻蚀，而不对第一材料层进行刻蚀，从而形成暴露第一材料层表面的第二凹槽。
可选的，一种实现方式中，为了进一步增强密封层与半导体芯片之间的结合力，在利用第一凹槽所暴露的钝化层的表面，刻蚀钝化层之后，利用第二凹槽所暴露的第一材料层的表面，刻蚀第一材料层，以在第一材料层中形 成还包括第三凹槽的凹槽结构；第三凹槽与第二凹槽及第一凹槽相连通，其中第三凹槽贯穿钝化层。
如图6所示，本实现方式中，在对第二材料层3112进行刻蚀形成第二凹槽322之后，还可以对暴露的第一材料层3111进行刻蚀，利用第二凹槽所暴露的第一材料层3111的表面，刻蚀第一材料层3111，以形成第三凹槽323。
需要说明的是，由于保护层312、第二材料层3112以及第一材料层3111的材料各不同，因此，第二材料层3112以及第一材料层3111具体的刻蚀方式可以与保护层312具体刻蚀方式不同，可以根据实际情况确定。
如图7(1)-图7(2)所示，可以在保护层中形成至少一个凹槽结构；至少一个凹槽结构设置在半导体芯片的4个顶角和/或半导体芯片的中心。
本公开实施例提供的上述制作半导体结构的方法，可以形成包括半导体芯片和凹槽结构，半导体芯片包括位于芯片上的钝化层与保护层，凹槽结构包括暴露钝化层表面的第一凹槽，由于凹槽结构的存在，使得密封层可以通过凹槽结构与钝化层接触，由于密封层与钝化层之间的结合力大于密封层与保护层的之间的结合力，同时，与不具有凹槽结构的半导体芯片相比，也增大了密封层与半导体芯片的接触面积，从而可以提升密封层与半导体芯片之间的结合力。
在刻蚀凹槽结构之后，还可以填充填充料，以形成在保护层之上并与保护层接触，且填充凹槽结构的密封层。
在形成凹槽结构之后，即可对半导体芯片进行底料填充，即填充填充料，以使形成覆盖保护层上，且填充凹槽结构的密封层。上述底部填充可以采用MUF工艺、毛细管底部填充工艺等填充工艺。
如图8所示，在填充填充料后，将在保护层312之上覆盖一层密封层33，且密封层33填充凹槽结构32，从而使得密封层33即可以与保护层312接触，也可以通过凹槽结构32与钝化层311接触，从而可以增大密封层33与半导体芯片31之间的结合力。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、 “包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要素。
本说明书中的各个实施例均采用相关的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于装置、设备、系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅为本公开的较佳实施例，并非用于限定本公开的保护范围。凡在本公开的精神和原则之内所作的任何修改、等同替换、改进等，均包含在本公开的保护范围内。

Claims (17)

  1. 一种半导体结构，包括：
    半导体芯片，包括位于芯片上的钝化层与保护层，所述保护层位于所述钝化层之上；
    凹槽结构，包括第一凹槽，所述第一凹槽暴露所述钝化层表面。
  2. 根据权利要求1所述的半导体结构，其中，
    所述凹槽结构，还包括第二凹槽，所述第二凹槽与所述第一凹槽相连通，并延伸至所述钝化层的内部且不贯穿所述钝化层。
  3. 根据权利要求2所述的半导体结构，其特征在于，所述钝化层包括第一材料层和第二材料层，其中所述第一凹槽暴露所述第二材料层表面，所述第二凹槽暴露所述第一材料层表面。
  4. 根据权利要求2所述的半导体结构，其中，
    所述凹槽结构，还包括第三凹槽，所述第三凹槽与所述第二凹槽及所述第一凹槽相连通，其中所述第三凹槽贯穿所述钝化层。
  5. 根据权利要求4所述的半导体结构，其中，所述第一凹槽的横向尺寸小于所述第二凹槽的横向尺寸，所述第二凹槽的横向尺寸小于所述第三凹槽的横向尺寸。
  6. 根据权利要求4所述的半导体结构，其中，所述第一凹槽、所述第二凹槽、所述第三凹槽相邻设置，其中所述第二凹槽设于所述第一凹槽与所述第三凹槽之间。
  7. 根据权利要求4所述的半导体结构，其中，所述凹槽结构为至少一个，且设置在所述半导体芯片的4个顶角和/或所述半导体芯片的中心。
  8. 根据权利要求3所述的半导体结构，其中，所述半导体结构，还包括：
    密封层，所述密封层在所述保护层之上并与所述保护层接触，且填充所述凹槽结构。
  9. 根据权利要求8所述的半导体结构，其中，所述密封层与保护层的黏附强度小于所述密封层与所述第二材料层的黏附强度。
  10. 根据权利要求9所述的半导体结构，其中，所述密封层与所述第二材料层的黏附强度小于所述密封层与所述第一材料层的黏附强度。
  11. 根据权利要求3-8任一项所述的半导体结构，其中，所述保护层材料是PI，所述第一材料层的材料为二氧化硅，所述第二材料层的材料为氮化硅。
  12. 一种制作半导体结构的方法，包括：
    提供顶部包括钝化层与保护层的半导体芯片；其中，所述保护层位于所述钝化层之上；
    在所述保护层中形成凹槽结构；其中，所述凹槽结构包括第一凹槽，所述第一凹槽暴露所述钝化层表面。
  13. 根据权利要求12所述的方法，其中，所述在所述保护层中形成凹槽结构，包括：
    刻蚀所述保护层，以在所述保护层中形成包括第一凹槽的凹槽结构。
  14. 根据权利要求13所述的方法，其中，在所述刻蚀所述保护层之后，还包括：
    利用所述第一凹槽所暴露的所述钝化层的表面，刻蚀所述钝化层，以在所述钝化层中形成还包括第二凹槽的所述凹槽结构；所述第二凹槽与所述第一凹槽相连通，并延伸至所述钝化层的内部且不贯穿所述钝化层。
  15. 根据权利要求14所述的方法，其中，所述钝化层包括第一材料层和第二材料层，其中所述第一凹槽暴露所述第二材料层表面，所述第二凹槽暴露所述第一材料层表面。
  16. 根据权利要求15所述的方法，其中，在所述利用所述第一凹槽所暴露的所述钝化层的表面，刻蚀所述钝化层之后，还包括：
    利用所述第二凹槽所暴露的所述第一材料层的表面，刻蚀所述第一材料层，以在所述第一材料层中形成还包括第三凹槽的所述凹槽结构；所述第三凹槽与所述第二凹槽及所述第一凹槽相连通，其中所述第三凹槽贯穿所述钝化层。
  17. 根据权利要求12-16任一项所述的方法，其中，所述在所述保护层中形成凹槽结构，包括：
    在所述保护层中形成至少一个凹槽结构；所述至少一个凹槽结构设置在所述半导体芯片的4个顶角和/或所述半导体芯片的中心。
PCT/CN2022/071574 2022-01-05 2022-01-12 半导体结构及其制造方法 WO2023130489A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210004276.1 2022-01-05
CN202210004276.1A CN114300424A (zh) 2022-01-05 2022-01-05 半导体结构及其制造方法

Publications (1)

Publication Number Publication Date
WO2023130489A1 true WO2023130489A1 (zh) 2023-07-13

Family

ID=80974752

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/071574 WO2023130489A1 (zh) 2022-01-05 2022-01-12 半导体结构及其制造方法

Country Status (2)

Country Link
CN (1) CN114300424A (zh)
WO (1) WO2023130489A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070108623A1 (en) * 2005-11-11 2007-05-17 Jui-Meng Jao Chip and package structure
US20070120269A1 (en) * 2005-11-30 2007-05-31 Advanced Semiconductor Engineering, Inc. Flip chip package and manufacturing method of the same
US20080073780A1 (en) * 2006-09-21 2008-03-27 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20090032909A1 (en) * 2007-08-03 2009-02-05 Brofman Peter J Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners
US20120018875A1 (en) * 2010-07-21 2012-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing Delamination Between an Underfill and a Buffer layer in a Bond Structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070108623A1 (en) * 2005-11-11 2007-05-17 Jui-Meng Jao Chip and package structure
US20070120269A1 (en) * 2005-11-30 2007-05-31 Advanced Semiconductor Engineering, Inc. Flip chip package and manufacturing method of the same
US20080073780A1 (en) * 2006-09-21 2008-03-27 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20090032909A1 (en) * 2007-08-03 2009-02-05 Brofman Peter J Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners
US20120018875A1 (en) * 2010-07-21 2012-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing Delamination Between an Underfill and a Buffer layer in a Bond Structure

Also Published As

Publication number Publication date
CN114300424A (zh) 2022-04-08

Similar Documents

Publication Publication Date Title
US10796970B2 (en) Method for fabricating electronic package
US7208335B2 (en) Castellated chip-scale packages and methods for fabricating the same
KR20200106055A (ko) 웨이퍼 레벨 시스템 패키지 방법 및 패키지 구조
US8759685B2 (en) Wiring substrate and method of manufacturing the wiring substrate
TWI626717B (zh) 半導體封裝結構
KR20080106082A (ko) 다이 수용 오프닝을 갖는 ｃｍｏｓ 이미지 센서 칩 스케일패키지 및 그 방법
TWI614848B (zh) 電子封裝結構及其製法
JP2008244437A (ja) ダイ収容開口部を備えたイメージセンサパッケージおよびその方法
TWI698968B (zh) 封裝結構以及封裝方法
TWI728924B (zh) 封裝結構及其製造方法
CN108831870A (zh) 具有ubm的封装件和形成方法
TW201332071A (zh) 承載板、半導體封裝件及其製法
TW201507064A (zh) 半導體封裝件及其製法
US20130322023A1 (en) Integrated circuit packaging system with heatsink cap and method of manufacture thereof
KR20210084195A (ko) 팬 아웃 패키지 및 이의 형성 방법
US11854941B2 (en) Method for packaging semiconductor, semiconductor package structure, and package
WO2023130489A1 (zh) 半导体结构及其制造方法
CN105655365B (zh) 半导体芯片封装结构及其封装方法
US10418296B2 (en) Semiconductor chip package structure and packaging method therefor
CN111146099B (zh) 半导体结构及其制作方法
TWI515841B (zh) 半導體封裝件及其製法
CN215183944U (zh) 晶圆扇出型封装互联结构
CN111627857A (zh) 封装方法及封装结构
TWI839810B (zh) 半導體封裝載板結構及其製法
TWI843580B (zh) 影像感測器及其製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22917958

Country of ref document: EP

Kind code of ref document: A1