WO2023125250A2 - 一种无过冲快速启动带隙基准电路、芯片及电子设备 - Google Patents

一种无过冲快速启动带隙基准电路、芯片及电子设备 Download PDF

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WO2023125250A2
WO2023125250A2 PCT/CN2022/141152 CN2022141152W WO2023125250A2 WO 2023125250 A2 WO2023125250 A2 WO 2023125250A2 CN 2022141152 W CN2022141152 W CN 2022141152W WO 2023125250 A2 WO2023125250 A2 WO 2023125250A2
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Prior art keywords
pmos transistor
circuit
current
transistor
bias current
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PCT/CN2022/141152
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English (en)
French (fr)
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WO2023125250A3 (zh
Inventor
陈成
李春领
王永寿
高晨阳
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唯捷创芯(天津)电子技术股份有限公司
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Priority to KR1020247000195A priority Critical patent/KR20240015138A/ko
Publication of WO2023125250A2 publication Critical patent/WO2023125250A2/zh
Publication of WO2023125250A3 publication Critical patent/WO2023125250A3/zh
Priority to US18/413,036 priority patent/US20240152172A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the invention relates to a no-overshoot quick-start bandgap reference circuit, and also relates to an integrated circuit chip including the no-overshoot quick-start bandgap reference circuit and corresponding electronic equipment, belonging to the technical field of analog integrated circuits.
  • the primary technical problem to be solved by the present invention is to provide a fast-start bandgap reference circuit without overshoot (bandgap reference circuit for short).
  • This bandgap reference circuit enables fast start-up without overshoot under all PVT (process, supply voltage, temperature) conditions.
  • Another technical problem to be solved by the present invention is to provide an integrated circuit chip including a non-overshoot quick-start bandgap reference circuit and corresponding electronic equipment.
  • a no-overshoot quick-start bandgap reference circuit including a bias current generation unit 101 and a reference core unit 102, the output terminal of the bias current generation unit 101 is connected to the The input end of reference core unit 102 is connected;
  • the bias current generation unit 101 generates a bias current that is independent of the power supply voltage and has a zero temperature coefficient as an input signal of the reference core unit 102;
  • the reference core unit 102 generates a pre-charging current according to the bias current, and adopts a pre-charging method to realize fast startup without overshoot.
  • the bias current generation unit 101 includes a first startup circuit 201 and a bias current generation circuit 202; wherein, the output terminal of the first startup circuit 201 is connected to the input of the bias current generation circuit 202 end connected.
  • the first start-up circuit 201 includes a start-up current generation branch 301, a proportional mirror injection branch 302 and a feedback current shutdown control branch 303; wherein the start-up current generation branch 301 generates a start-up current,
  • the proportional mirror injection branch 302 injects the startup current into the bias current generation circuit 202 after proportional mirroring, and the feedback current shutdown control branch 303 is activated after the bias current generation circuit 202 completes startup. , using the function of feedback current cut-off control to reduce the proportional mirror injection current to zero finally.
  • the bias current generating circuit 202 includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a first PMOS transistor MP1 and a second PMOS transistor MP2.
  • the PMOS current proportional mirror pair transistors, the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 form a cascode structure PMOS current proportional mirror pair transistors.
  • the bias current generating circuit 202 further includes a first resistor R1, a second resistor R2 and a third resistor R3; wherein, one end of the first resistor R1 is connected to the source of the third PMOS transistor MP3, and the other end connected to the power supply terminal; one end of the second resistor R2 is connected to the drain of the fifth NMOS transistor MN5, and the other end is respectively connected to the drain of the sixth PMOS transistor MP6 and the gate of the fifth PMOS transistor MP5; one end of the third resistor R3 is respectively The drain of the sixth NMOS transistor MN6 is connected to the gate of the fourth NMOS transistor MN4, and the other end is respectively connected to the gate of the sixth NMOS transistor MN6 and the drain of the fourth PMOS transistor MP4.
  • a first resistor R1 is connected to the source of the third PMOS transistor MP3, and the other end connected to the power supply terminal
  • one end of the second resistor R2 is connected to the drain of the fifth NMOS transistor MN5, and the other end
  • the first resistor R1, the second resistor R2 and the third resistor R3 have different temperature coefficients respectively.
  • the reference core unit 102 includes a second start-up circuit 401 and a reference core circuit 402 ; wherein, the output end of the second start-up circuit 401 is connected to the input end of the reference core circuit 402 .
  • the second startup circuit 401 includes a bias current injection branch 501, a proportional mirror injection branch 502 and a feedback current shutdown control branch 503; wherein, the bias current injection branch 501 receives the The bias current output by the bias current generation unit 101; the proportional mirror injection branch 502 mirrors the bias current proportionally to form a pre-charge current and injects it into the reference core circuit 402; the feedback current is off
  • the off control branch 503 reduces the pre-charging current to zero after the reference core circuit 402 starts up.
  • the pre-charging current is divided into three paths; wherein, the first pre-charging current is the drain output current of the thirty-third PMOS transistor MP13, which is injected into the output end of the reference core circuit 402; the second path The precharge current is the drain output current of the thirty-fourth PMOS transistor MP14, which is injected into the non-inverting input terminal of the first operational amplifier in the reference core circuit 402; the third precharge current is the drain current of the thirty-fifth PMOS transistor MP15 The pole output current is injected into the inverting input terminal of the first operational amplifier in the reference core circuit 402 .
  • the feedback current shutdown control branch 503 is composed of the twenty-second NMOS transistor MN2, the thirty-first PMOS transistor MP11, and the thirty-second PMOS transistor MP12; wherein, the twenty-second NMOS transistor MN2
  • the drain of the thirty-first PMOS transistor MP11 is connected to the drain of the thirty-second PMOS transistor MP12, the source of the thirty-first PMOS transistor MP11 is connected to the power terminal, and the thirty-first PMOS transistor MP11 is connected to the power supply terminal.
  • the gate of the pipe MP11 is connected to the output end of the first operational amplifier in the reference core circuit 402;
  • the current on the thirty-first PMOS transistor MP11 is greater than the current on the twenty-second NMOS transistor MN2, and the gate voltage of the thirty-second PMOS transistor MP12 is pulled up to VDD, and the The precharge current is reduced to zero.
  • an integrated circuit chip including the above-mentioned no-overshoot quick-start bandgap reference circuit.
  • an electronic device including the above-mentioned no-overshoot quick-start bandgap reference circuit.
  • the non-overshoot quick-start bandgap reference circuit provided by the present invention realizes bias current It has nothing to do with the power supply voltage and has the characteristics of zero temperature coefficient; on the other hand, by adopting the pre-charging method, the establishment process of the loop bias point voltage and the output voltage of the operational amplifier is accelerated, so that the bandgap reference circuit can be used in all Fast startup without overshoot under PVT (process, power supply voltage, temperature), so that electronic equipment has low power consumption and low delay performance.
  • PVT process, power supply voltage, temperature
  • Fig. 1 is the circuit block diagram of the non-overshoot quick-start bandgap reference circuit provided by the present invention
  • FIG. 2 is a schematic circuit diagram of a bias current generating unit in an embodiment of the present invention.
  • FIG. 3 is a circuit schematic diagram of a reference core unit in an embodiment of the present invention.
  • Fig. 4 is a comparison diagram of curves of bias current changing with temperature in an embodiment of the present invention.
  • Fig. 6 is a comparison diagram of the non-overshoot starting voltage waveform and the overshoot starting voltage waveform in the embodiment of the present invention.
  • FIG. 7 is a waveform diagram of the starting voltage of the bandgap reference circuit under different PVTs in an embodiment of the present invention.
  • FIG. 8 is an example diagram of an electronic device using the non-overshoot quick-start bandgap reference circuit.
  • the no-overshoot quick-start bandgap reference circuit 100 provided by the embodiment of the present invention includes a bias current generation unit 101 and a reference core unit 102 .
  • the output terminal of the bias current generation unit 101 is connected to the input terminal of the reference core unit 102 .
  • the bias current generation unit 101 generates a bias current I BIAS that is independent of the power supply voltage and has a zero temperature coefficient as an input signal of the reference core unit 102 .
  • the reference core unit 102 generates a pre-charging current and a current required for the operation of the operational amplifier according to the input bias current I BIAS , and adopts a pre-charging method to realize fast startup without overshoot.
  • the bias current generating unit 101 includes a first start-up circuit 201 and a bias current generating circuit 202 .
  • the output terminal of the first start-up circuit 201 is connected with the input terminal of the bias current generating circuit 202 .
  • the bias current generating circuit 202 generates a bias current I BIAS that is independent of the power supply voltage and has a zero temperature coefficient.
  • the bias current I BIAS is an input signal of the reference core unit 102 .
  • the first start-up circuit 201 includes a start-up current generating branch 301, a proportional mirror injection branch 302 and a feedback current cut-off control branch 303.
  • the starting current generation branch 301 generates the starting current; the proportional mirror injection branch 302 injects the starting current into the bias current generating circuit 202 after proportional mirroring.
  • the feedback current shutdown control branch 303 uses feedback current shutdown control to reduce the proportional mirror injection current to zero.
  • the startup current generating branch 301 is composed of an eleventh PMOS transistor MP11 , a twelfth PMOS transistor MP12 , a first NMOS transistor MN1 and a first switch transistor.
  • the first switch tube receives the input of the enable signal, one end of the first switch tube is connected to the drain of the twelfth PMOS transistor MP12, the drain of the twelfth PMOS transistor MP12 is short-circuited to the gate, and the twelfth PMOS transistor MP12
  • the source of the eleventh PMOS transistor MP11 is connected to the drain of the eleventh PMOS transistor MP11, the drain of the eleventh PMOS transistor MP11 is short-circuited to the gate, and the source of the eleventh PMOS transistor MP11 is connected to the power supply terminal VDD.
  • the other end of the first switch transistor is connected to the drain of the first NMOS transistor MN1, the drain of the first NMOS transistor MN1 is short-circuited to the gate, and the source of the first NMOS transistor MN1 is connected to the common ground terminal VSS.
  • the proportional mirror injection branch 302 is composed of a first NMOS transistor MN1, a second NMOS transistor MN2, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, and a tenth PMOS transistor MP10.
  • the first NMOS transistor MN1 and the second NMOS transistor MN2 form an NMOS current proportional mirror pair
  • the eighth PMOS transistor MP8 , the ninth PMOS transistor MP9 , and the tenth PMOS transistor MP10 form a PMOS current proportional mirror pair.
  • the gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1
  • the source of the second NMOS transistor MN2 is connected to the common ground terminal VSS
  • the drain of the second NMOS transistor MN2 is connected to the eighth PMOS transistor MP8.
  • the gate of the eighth PMOS transistor MP8 is connected to the power supply terminal VDD, the drain of the eighth PMOS transistor MP8 is short-circuited to the gate, and the sources of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are respectively connected to the power supply terminal VDD , the gates of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are connected to the drain of the second NMOS transistor MN2, and the drains of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are respectively connected to the bias current generating circuit 202 .
  • the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 have no current injected into the bias current generating circuit 202; when the circuit is enabled, the NMOS current proportional mirror pair (MN1, MN2) and the PMOS current
  • the proportional mirror pair tubes MP8, MP9, MP10) proportionally mirror the start-up current of the branch where the first switch tube is located, and then inject it into the bias current generation circuit 202 in two ways, so that the fourth NMOS tube MN4 and the sixth NMOS tube
  • the gate voltage of MN6 rises rapidly.
  • the feedback current shutdown control branch 303 is composed of the second NMOS transistor MN2, the seventh PMOS transistor MP7, and the eighth PMOS transistor MP8.
  • the source of the seventh PMOS transistor MP7 is connected to the power supply terminal VDD
  • the drain of the seventh PMOS transistor MP7 is connected to the drain and gate of the eighth PMOS transistor MP8 and the drain of the second NMOS transistor MN2
  • the seventh PMOS transistor MP7 The gate of MP7 is connected to the bias current generation circuit 202 .
  • I MN2 I MP7 +I MP8 .
  • the current on the seventh PMOS transistor MP7 is smaller than the current on the second NMOS transistor MN2, that is, I MP7 ⁇ I MN2 , and at this time, I MP8 is proportionally mirrored to generate two injection currents , injected into the bias current generating circuit 202 .
  • the bias current generating circuit 202 is composed of a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a first PMOS transistor MP1, a second PMOS transistor Tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4, the fifth PMOS tube MP5, the sixth PMOS tube MP6, the thirteenth PMOS tube MP13, and the first resistor R1, the second resistor R2, and the third resistor R3 .
  • the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 form an NMOS current proportional mirror pair transistor with a cascode structure
  • the third PMOS transistor MP3 and the fourth PMOS transistor MP4 , the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 form a PMOS current ratio mirror pair of cascode structures
  • the gate of the third NMOS transistor MN3 is connected to the gate of the fourth NMOS transistor MN4, and then they are jointly connected to one output of the proportional mirror injection branch 302, that is, the drain of the tenth PMOS transistor MP10, and the third NMOS transistor MN3
  • the source of the fourth NMOS transistor MN4 is connected to the common ground terminal VSS respectively
  • the drain of the third NMOS transistor MN3 is connected to the source of the fifth NMOS transistor MN5
  • the drain of the fourth NMOS transistor MN4 is connected to the sixth NMOS transistor MN4.
  • the source of the transistor MN6 is connected, the gate of the fifth NMOS transistor MN5 is connected to the gate of the sixth NMOS transistor MN6, and then they are jointly connected to the other output of the proportional mirror injection branch 302, that is, the drain of the ninth PMOS transistor MP9.
  • the drain of the sixth NMOS transistor MN6 is connected to the gate of the fourth NMOS transistor MN4 and the third resistor R3, and the other end of the third resistor R3 is connected to the gate of the sixth NMOS transistor MN6 and the drain of the fourth PMOS transistor MP4.
  • the gate of the four PMOS transistor MP4 is connected to the gate of the sixth PMOS transistor MP6 and the gate of the second PMOS transistor MP2, the source of the fourth PMOS transistor MP4 is connected to the drain of the third PMOS transistor MP3, and the third PMOS transistor MP3
  • the gate of MP3 is connected to the gate of the fifth PMOS transistor MP5 and the gate of the first PMOS transistor MP1
  • the source of the third PMOS transistor MP3 is connected to the first resistor R1
  • the other end of the first resistor R1 is connected to the power supply terminal VDD
  • the drain of the fifth NMOS transistor MN5 is connected to the gate of the second resistor R2 and the fourth PMOS transistor MP4, and the other end of the second resistor R2 is connected to the drain of the sixth PMOS transistor MP6 and the gate of the fifth PMOS transistor MP5 respectively.
  • the source of the sixth PMOS transistor MP6 is connected to the drain of the fifth PMOS transistor MP5, and the source of the fifth PMOS transistor MP5 is connected to the power supply terminal VDD; on the one hand, the gate of the fifth PMOS transistor MP5 is turned off from the feedback current
  • the gate of the seventh PMOS transistor MP7 in the control branch 303 is connected, and on the other hand is connected to the drain of the thirteenth PMOS transistor MP13, the source of the thirteenth PMOS transistor MP13 is connected to the power supply terminal VDD, and the thirteenth PMOS transistor MP13
  • the gate of the gate is connected to the enable signal input terminal EN; the source of the first PMOS transistor MP1 is connected to the power supply terminal VDD, the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2, and the drain of the second PMOS transistor MP2 It is connected to the input end of the reference core unit 102 , that is, the input bias current I BIAS .
  • the proportional mirror injection branch 302 injects the mirror image injection current into the branch where the fourth NMOS transistor MN4 and the sixth NMOS transistor MN6 are located.
  • the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 of the current proportional mirror pair of the source common gate structure copy the proportional mirror to inject current to cause the fifth PMOS transistor MP5, the sixth
  • the PMOS transistor MP6 , the second resistor R2 , the fifth NMOS transistor MN5 , and the third NMOS transistor MN3 branch generate currents, and the gate voltages of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 will be pulled down.
  • the current proportional mirror pair of the cascode structure mirrors the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6, and again proportionally mirrors the fifth PMOS transistor MP5, the sixth PMOS transistor
  • the current of the branch where the PMOS transistor MP6 is located, the current formed by the third PMOS transistor MP3 and the fourth PMOS transistor MP4 is superimposed on the current injected by the tenth PMOS transistor MP10 and the ninth PMOS transistor MP9, and is again absorbed by the fifth NMOS transistor MN5,
  • the branch where the third NMOS transistor MN3 is located is replicated to form a positive feedback, so that the bias current can be quickly established.
  • the seventh PMOS transistor MP7 which is the current proportional mirror pair.
  • the proportional currents of the branches where the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are located are mirrored and injected into the drain terminal of the second NMOS transistor MN2.
  • the cascode bias current structure ensures that the generated bias current has nothing to do with the power supply voltage; on the other hand, the first resistor R1, the second resistor R2, and the third resistor R3 use different temperature coefficients type of resistor.
  • the first resistor R1 can choose a resistor with a positive temperature coefficient
  • the second resistor R2 and the third resistor R3 can choose a resistor with a negative temperature coefficient
  • the first resistor R1 can choose a resistor with a negative temperature coefficient
  • the second resistor R2 and the third resistor R3 can choose a resistor with a negative temperature coefficient.
  • the third resistor R3 can be a resistor with a positive temperature coefficient, so as to ensure that the generated bias current can have a characteristic of zero temperature coefficient.
  • the current mirror pair of the cascode structure, the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 mirror the bias current ratio to form the output bias current I BIAS , provided to the benchmark core unit 102.
  • the reference core unit 102 includes a second startup circuit 401 and a reference core circuit 402 .
  • the output terminal of the second start-up circuit 401 is connected with the input terminal of the reference core circuit 402 .
  • the second start-up circuit 401 receives the bias current I BIAS output by the bias current generation unit 101, mirrors the bias current I BIAS in proportion to generate a pre-charge current and injects it into the reference core circuit 402, and the pre-charge current is finally turned off by the feedback current The effect of the off control is reduced to zero; the reference core circuit 402 generates an output voltage without overshoot and quick start after receiving the pre-charging current.
  • the second startup circuit 401 includes a bias current injection branch 501, a proportional mirror injection branch 502 and a feedback current shutdown control branch 503;
  • the bias current injection branch 501 receives the bias current The bias current I BIAS output by the generation unit 101;
  • the proportional mirror injection branch 502 mirrors the I BIAS current ratio to form a pre-charge current and injects it into the reference core circuit 402;
  • the feedback current shutdown control branch 503 is in the reference core circuit 402 After startup is complete, reduce the precharge current to zero.
  • the bias current injection branch 501 is composed of a twenty-first NMOS transistor MN1 and a second switch transistor (Switch).
  • the second switch tube receives the input of the enable signal, one end of which is connected to the output end of the bias current generating unit 101 , and the other end is connected to the drain of the twenty-first NMOS transistor MN1 .
  • the source of the twenty-first NMOS transistor MN1 is connected to the common ground terminal VSS, the drain of the twenty-first NMOS transistor MN1 is short-circuited to the gate, and the gate of the twenty-first NMOS transistor MN1 is injected into the branch 502 with a proportional mirror image.
  • the gate of the twenty-second NMOS transistor MN2 is connected.
  • the proportional mirror injection branch 502 includes the twenty-first NMOS transistor MN1, the twenty-second NMOS transistor MN2, the thirty-second PMOS transistor MP12, the thirty-third PMOS transistor MP13, the third The fourteenth PMOS tube MP14 and the thirty-fifth PMOS tube MP15 are composed.
  • the twenty-first NMOS transistor MN1 and the twenty-second NMOS transistor MN2 form an NMOS current proportional mirror pair;
  • the thirty-second PMOS transistor MP12, the thirty-third PMOS transistor MP13, the thirty-fourth PMOS transistor MP14, the Thirty-five PMOS transistors MP15 form a PMOS current proportional mirror pair.
  • the gate of the twenty-first NMOS transistor MN1 is connected to the gate of the twenty-second NMOS transistor MN2
  • the source of the twenty-second NMOS transistor MN2 is connected to the common ground terminal VSS
  • the gate of the twenty-second NMOS transistor MN2 The drain is in phase with the drain and gate of the thirty-second PMOS transistor MP12, the gate of the thirty-third PMOS transistor MP13, the gate of the thirty-fourth PMOS transistor MP14, and the gate of the thirty-fifth PMOS transistor MP15 Connection, the source of the thirty-second PMOS transistor MP12, the source of the thirty-third PMOS transistor MP13, the source of the thirty-fourth PMOS transistor MP14, the source of the thirty-fifth PMOS transistor MP15 are all connected to the power supply terminal VDD
  • the drain of the thirty-third PMOS transistor MP13 is connected to the output terminal Vref of the reference core circuit 402, and the drain of the thirty-fourth PMOS transistor MP14 is connected to the non-inverting
  • the first pre-charging current is the drain output current of the thirty-third PMOS transistor MP13, which is injected into the output terminal Vref of the reference core circuit 402, so that the output voltage rises rapidly;
  • the second pre-charging current is the thirty-fourth
  • the drain output current of the PMOS transistor MP14 is injected into the non-inverting input terminal VA of the first operational amplifier OPA in the reference core circuit 402;
  • the inverting input terminal VB of the first operational amplifier OPA in the reference core circuit 402 enables the loop voltage controlled by the first operational amplifier OPA to quickly build up, thereby quickly starting the bandgap reference circuit.
  • the feedback current shutdown control branch 503 is composed of the twenty-second NMOS transistor MN2, the thirty-first PMOS transistor MP11, and the thirty-second PMOS transistor MP12; the twenty-second NMOS transistor MN2
  • the drain of the thirty-first PMOS transistor MP11 is connected to the drain of the thirty-second PMOS transistor MP12, the source of the thirty-first PMOS transistor MP11 is connected to the power supply terminal VDD, and the thirty-first PMOS transistor MP11 is connected to the power supply terminal VDD.
  • the gate of the PMOS transistor MP11 is connected to the output terminal V_BIAS of the first operational amplifier OPA in the reference core circuit 402 .
  • I MN2 I MP11 +I MP12
  • the current on the thirty-first PMOS transistor MP11 is smaller than that on the twenty-second NMOS transistor MN2 current, that is, I MP11 ⁇ I MN2 .
  • I MP12 is proportionally mirrored to form a pre-charge current, which is injected into the reference core circuit 402 .
  • the reference core circuit 402 is composed of the twenty-first PMOS transistor MP1, the twenty-second PMOS transistor MP2, the twenty-third PMOS transistor MP3, the twenty-fourth PMOS transistor MP4, the twenty-fifth PMOS transistor PMOS transistor MP5, twenty-sixth PMOS transistor MP6, twenty-seventh PMOS transistor MP7, twenty-eighth PMOS transistor MP8, twenty-ninth PMOS transistor MP9, thirtieth PMOS transistor MP10, and twenty-first resistor R1 , the twenty-second resistor R2, and the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the first capacitor C1, and the first operational amplifier OPA; the base and collector of the first transistor Q1 are connected to the common ground terminal VSS, the emitter of the first transistor Q1 is connected to the base of the second transistor Q2 and the twentieth The drain of the first PMOS transistor MP1 is connected, the source of the twenty-first PMOS transistor MP1 is connected to the drain of the thi
  • the twenty-second resistor R2 is connected, the other end of the twenty-second resistor R2 is connected with the non-inverting input terminal VA of the first operational amplifier OPA and the drain of the twenty-third PMOS transistor MP3, and the source of the twenty-third PMOS transistor MP3
  • the pole is connected to the drain of the twenty-eighth PMOS transistor MP8, the source of the twenty-eighth PMOS transistor MP8 is connected to the power supply terminal VDD; the base and collector of the fifth triode Q5 are connected to the common ground terminal VSS, and the source of the twenty-eighth PMOS transistor MP8 is connected to the common ground terminal VSS.
  • the emitter of the triode Q5 is connected to the twenty-first resistor R1, the other end of the twenty-first resistor R1 is connected to the drain of the twenty-fifth PMOS transistor MP5 and the output terminal Vref, and the twenty-fifth PMOS transistor MP5
  • the source of the twenty-sixth PMOS transistor MP6 is connected to the drain of the twenty-sixth PMOS transistor MP6, and the source of the twenty-sixth PMOS transistor MP6 is connected to the power supply terminal VDD; one end of the first capacitor C1 is connected to the common ground terminal VSS, and the first capacitor C1 The other end is connected with the output end Vref.
  • the output terminal V_BIAS of the first operational amplifier OPA is connected to the gate of the twenty-sixth PMOS transistor MP6, the gate of the twenty-seventh PMOS transistor MP7, the gate of the twenty-eighth PMOS transistor MP8, the gate of the twenty-ninth PMOS transistor MP9
  • the grid of the 30th PMOS transistor MP10 is connected.
  • the gates of MP5 are respectively connected to the signal input terminal Vb1.
  • the output voltage V_BIAS of the first operational amplifier OPA starts to drop from VDD, the twenty-sixth PMOS transistor MP6, the twenty-seventh PMOS transistor MP7, the twenty-eighth PMOS transistor MP8, the twenty-ninth PMOS transistor MP8, and the twenty-nine
  • Each branch of the PMOS transistor MP9, the 30th PMOS transistor MP10, and the 31st PMOS transistor MP11 generates a current, and the current and proportional mirroring of the 28th PMOS transistor MP8 and the 29th PMOS transistor MP9 branch are injected into the branch After the precharge current injected by 502 into the non-inverting input terminal VA and the inverting input terminal VB is superimposed, the voltage establishment process of the non-inverting input terminal VA and the inverting input terminal VB is further accelerated.
  • FIG. 4 is a graph comparing curves of bias current changing with temperature in an embodiment of the present invention. From the comparison of the curve of bias current changing with temperature in the present invention and the curve of bias current changing with temperature in the prior art, it can be seen that the bias current in the present invention has the characteristics of zero temperature coefficient, which is different from that of the prior art. The bias current in the change is smaller than that.
  • Fig. 5 is a graph showing the variation of bias current with temperature under different PVTs in the embodiment of the present invention. As shown in FIG. 5 , under different PVT conditions, the bias current in the present invention has a characteristic of zero temperature coefficient.
  • Fig. 6 is a comparison diagram of the non-overshoot startup voltage waveform and the overshoot startup voltage waveform in the embodiment of the present invention.
  • the voltage waveform directly approaches 1.2V and quickly stabilizes at 1.2V; after the overshoot startup circuit in the prior art is enabled, the voltage waveform When the reference voltage reaches about 2.6V, it finally stabilizes at 1.2V.
  • FIG. 7 is a waveform diagram of the start-up voltage of the bandgap reference circuit under different PVTs in the embodiment of the present invention. As shown in FIG. 7 , the output voltage of the bandgap reference circuit provided by the present invention can realize fast startup without overshoot under different PVTs.
  • the no-overshoot quick-start bandgap reference circuit provided in the embodiment of the present invention can be used in an integrated circuit chip.
  • the specific structure of the no-overshoot quick-start bandgap reference circuit in the integrated circuit chip will not be described in detail here.
  • the above-mentioned no-overshoot quick-start bandgap reference circuit can also be used in electronic equipment as an important part of an analog integrated circuit.
  • the electronic devices mentioned here refer to computer devices that can be used in a mobile environment and support GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE and other communication standards, including mobile phones, notebook computers, tablet computers, vehicle-mounted computers, etc.
  • the technical solutions provided by the embodiments of the present invention are also applicable to other applications of analog integrated circuits, such as communication base stations.
  • the electronic device includes at least a processor and a memory, and may further include a communication component, a sensor component, a power supply component, a multimedia component, and an input/output interface according to actual needs.
  • a communication component a sensor component
  • a power supply component a multimedia component
  • an input/output interface a multimedia component
  • memory, communication components, sensor components, power supply components, multimedia components and input/output interfaces are all connected with the processor.
  • the memory can be Static Random Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), magnetic memory, flash memory, etc.
  • the processor can be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable logic gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing ( DSP) chips, etc.
  • CPU central processing unit
  • GPU graphics processing unit
  • FPGA field programmable logic gate array
  • ASIC application-specific integrated circuit
  • DSP digital signal processing
  • the non-overshoot quick-start bandgap reference circuit provided by the present invention realizes bias current It has nothing to do with the power supply voltage and has the characteristics of zero temperature coefficient; on the other hand, by adopting the pre-charging method, the establishment process of the loop bias point voltage and the output voltage of the operational amplifier is accelerated, so that the bandgap reference circuit can be used in all
  • the fast start-up without overshoot under PVT enables the electronic equipment to have low power consumption and low delay performance.

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Abstract

本发明公开了一种无过冲快速启动带隙基准电路、芯片及电子设备。该带隙基准电路包括偏置电流产生单元(101)和基准核心单元(102)；其中，偏置电流产生单元(101)的输出端与基准核心单元(102)的输入端连接；偏置电流产生单元(101)产生与电源电压无关并且具有零温度系数的偏置电流，偏置电流为基准核心单元(102)的输入信号；基准核心单元(102)根据输入的偏置电流产生预充电电流，并采用预充电方式实现无过冲的快速启动。

Description

一种无过冲快速启动带隙基准电路、芯片及电子设备 技术领域
本发明涉及一种无过冲快速启动带隙基准电路，同时也涉及包括该无过冲快速启动带隙基准电路的集成电路芯片及相应的电子设备，属于模拟集成电路技术领域。
背景技术
随着集成电路技术的不断发展，电子设备越来越追求低功耗以及低延时的性能。当电子设备处于空闲状态时，整个系统中各个电路模块均处于关断状态，能够有效地降低待机功耗；当使能信号来临时，整个系统中各个电路模块能够快速启动进入正常的工作状态。因此，电子设备对启动过程的要求越来越高。带隙基准电路作为整个模拟电路系统中最重要的一个组成部分，它的启动时间将在很大程度上影响整个系统的启动速度。
发明内容
本发明所要解决的首要技术问题在于提供一种无过冲快速启动带隙基准电路(简称带隙基准电路)。该带隙基准电路能够在所有PVT(工艺、电源电压、温度)条件下，实现快速无过冲的启动。
本发明所要解决的另一技术问题在于提供一种包括无过冲快速启动带隙基准电路的集成电路芯片及相应的电子设备。
为了实现上述目的，本发明采用下述的技术方案：
根据本发明实施例的第一方面，提供一种无过冲快速启动带隙基准电路，包括偏置电流产生单元101和基准核心单元102，所述偏置电流产生单元101的输出端与所述基准核心单元102的输入端相连接；其中，
所述偏置电流产生单元101产生与电源电压无关并且具有零温度系数的偏置电流，作为所述基准核心单元102的输入信号；
所述基准核心单元102根据所述偏置电流产生预充电电流，并采用预充电方式实现无过冲的快速启动。
其中较优地，所述偏置电流产生单元101包括第一启动电路201 和偏置电流产生电路202；其中，所述第一启动电路201的输出端与所述偏置电流产生电路202的输入端相连接。
其中较优地，所述第一启动电路201包括启动电流产生支路301、比例镜像注入支路302和反馈电流关断控制支路303；其中，所述启动电流产生支路301产生启动电流，所述比例镜像注入支路302将所述启动电流比例镜像后注入到所述偏置电流产生电路202中，所述反馈电流关断控制支路303在所述偏置电流产生电路202完成启动后，利用反馈电流关断控制的作用将该比例镜像注入电流最终减小为零。
其中较优地，所述偏置电流产生电路202包括第三NMOS管MN3、第四NMOS管MN4、第五NMOS管MN5、第六NMOS管MN6，以及第一PMOS管MP1、第二PMOS管MP2、第三PMOS管MP3、第四PMOS管MP4、第五PMOS管MP5、第六PMOS管MP6、第十三PMOS管MP13；其中，第三NMOS管MN3、第四NMOS管MN4、第五NMOS管MN5、第六NMOS管MN6组成共源共栅结构的NMOS电流比例镜像对管，第三PMOS管MP3、第四PMOS管MP4、第五PMOS管MP5、第六PMOS管MP6组成共源共栅结构的PMOS电流比例镜像对管，第一PMOS管MP1、第二PMOS管MP2、第三PMOS管MP3、第四PMOS管MP4组成共源共栅结构的PMOS电流比例镜像对管。
其中较优地，所述偏置电流产生电路202还包括第一电阻R1、第二电阻R2和第三电阻R3；其中，第一电阻R1的一端连接第三PMOS管MP3的源极，另一端连接电源端；第二电阻R2的一端连接第五NMOS管MN5的漏极，另一端分别与第六PMOS管MP6的漏极及第五PMOS管MP5的栅极连接；第三电阻R3的一端分别连接第六NMOS管MN6的漏极与第四NMOS管MN4的栅极，另一端分别连接第六NMOS管MN6的栅极及第四PMOS管MP4的漏极。
其中较优地，所述第一电阻R1、所述第二电阻R2以及所述第三电阻R3分别具有不同的温度系数。
其中较优地，所述基准核心单元102包括第二启动电路401和基准核心电路402；其中，所述第二启动电路401的输出端与所述基准核心电路402的输入端相连接。
其中较优地，所述第二启动电路401包括偏置电流注入支路501、 比例镜像注入支路502和反馈电流关断控制支路503；其中，所述偏置电流注入支路501接收所述偏置电流产生单元101输出的偏置电流；所述比例镜像注入支路502将所述偏置电流比例镜像后形成预充电电流并注入到所述基准核心电路402中；所述反馈电流关断控制支路503在基准核心电路402完成启动后，将预充电电流减小为零。
其中较优地，所述预充电电流分为三路；其中，第一路预充电电流为第三十三PMOS管MP13的漏极输出电流，注入到基准核心电路402的输出端；第二路预充电电流为第三十四PMOS管MP14的漏极输出电流，注入到基准核心电路402中的第一运算放大器的同相输入端；第三路预充电电流为第三十五PMOS管MP15的漏极输出电流，注入到基准核心电路402中的第一运算放大器的反相输入端。
其中较优地，所述反馈电流关断控制支路503由第二十二NMOS管MN2和第三十一PMOS管MP11、第三十二PMOS管MP12组成；其中，第二十二NMOS管MN2的漏极与第三十一PMOS管MP11的漏极、第三十二PMOS管MP12的栅极和漏极相连接，第三十一PMOS管MP11的源极连接电源端，第三十一PMOS管MP11的栅极与基准核心电路402中的第一运算放大器的输出端连接；
当所述基准核心电路402启动完成时，第三十一PMOS管MP11上的电流大于第二十二NMOS管MN2上的电流，第三十二PMOS管MP12的栅极电压拉升至VDD，将所述预充电电流减小为零。
根据本发明实施例的第二方面，提供一种集成电路芯片，包括上述的无过冲快速启动带隙基准电路。
根据本发明实施例的第三方面，提供一种电子设备，包括上述的无过冲快速启动带隙基准电路。
与现有技术相比较，本发明所提供的无过冲快速启动带隙基准电路一方面通过采用自偏置的共源共栅电流镜结构和具有不同温度系数类型的电阻，实现了偏置电流与电源电压无关并且具有零温度系数的特性；另一方面，通过采用预充电的方式，加速运算放大器的环路偏置点电压和输出电压的建立过程，从而实现了带隙基准电路能够在所有PVT(工艺、电源电压、温度)下无过冲的快速启动,使电子设备具有低功耗以及低延时的性能。
附图说明
图1为本发明所提供的无过冲快速启动带隙基准电路的电路原理框图；
图2为本发明实施例中，偏置电流产生单元的电路原理图；
图3为本发明实施例中，基准核心单元的电路原理图；
图4为本发明实施例中，偏置电流随温度变化的曲线对比图；
图5为本发明实施例中，在不同PVT下偏置电流随温度变化的曲线图；
图6为本发明实施例中，无过冲启动电压波形与过冲启动电压波形对比图；
图7为本发明实施例中，在不同PVT下带隙基准电路启动电压波形图；
图8为采用本无过冲快速启动带隙基准电路的电子设备的示例图。
具体实施方式
下面结合附图和具体实施例对本发明的技术方案做进一步的详细说明。
如图1所示，本发明实施例提供的无过冲快速启动带隙基准电路100，包括偏置电流产生单元101和基准核心单元102。其中，偏置电流产生单元101的输出端与基准核心单元102的输入端相连接。偏置电流产生单元101产生与电源电压无关并且具有零温度系数的偏置电流I BIAS，作为基准核心单元102的输入信号。基准核心单元102根据输入的偏置电流I BIAS产生预充电电流以及运算放大器工作所需的电流，并采用预充电方式实现无过冲的快速启动。
下面，对偏置电流产生单元101和基准核心单元102的电路结构及其工作原理进行详细说明。
在本发明的一个实施例中,偏置电流产生单元101包括第一启动电路201和偏置电流产生电路202。其中，第一启动电路201的输出端与偏置电流产生电路202的输入端相连接。偏置电流产生电路202产生与电源电压无关并且具有零温度系数的偏置电流I BIAS，该偏置电流I BIAS为基准核心单元102的输入信号。
第一启动电路201包括启动电流产生支路301、比例镜像注入支 路302和反馈电流关断控制支路303。启动电流产生支路301产生启动电流；比例镜像注入支路302将启动电流比例镜像后注入到偏置电流产生电路202中。反馈电流关断控制支路303在偏置电流产生电路202完成启动后，利用反馈电流关断控制的作用将该比例镜像注入电流最终减小为零。
如图2所示，在本发明的一个实施例中,启动电流产生支路301由第十一PMOS管MP11、第十二PMOS管MP12，第一NMOS管MN1以及第一开关管组成。其中，第一开关管接收使能信号的输入，第一开关管一端连接第十二PMOS管MP12的漏极，第十二PMOS管MP12的漏极与栅极短接，第十二PMOS管MP12的源极连接第十一PMOS管MP11的漏极，第十一PMOS管MP11的漏极与栅极短接，第十一PMOS管MP11的源极连接电源端VDD。第一开关管另一端连接第一NMOS管MN1的漏极，第一NMOS管MN1的漏极与栅极短接,第一NMOS管MN1的源极连接公共接地端VSS。
当电路未使能时，即EN＝0V，第一开关管关断，第一开关管所在支路电流为零，不产生启动电流；当电路使能时，即EN＝VDD，第一开关管导通，第一开关管所在支路产生启动电流，该启动电流输入至比例镜像注入支路302。
在本发明的一个实施例中,比例镜像注入支路302由第一NMOS管MN1、第二NMOS管MN2以及第八PMOS管MP8、第九PMOS管MP9、第十PMOS管MP10组成。其中，第一NMOS管MN1、第二NMOS管MN2组成NMOS电流比例镜像对管，第八PMOS管MP8、第九PMOS管MP9、第十PMOS管MP10组成PMOS电流比例镜像对管。具体地说，第二NMOS管MN2的栅极连接第一NMOS管MN1的栅极，第二NMOS管MN2的源极连接公共接地端VSS，第二NMOS管MN2的漏极连接第八PMOS管MP8的栅极，第八PMOS管MP8的源极连接电源端VDD，第八PMOS管MP8的漏极与栅极短接，第九PMOS管MP9、第十PMOS管MP10的源极分别连接电源端VDD，第九PMOS管MP9、第十PMOS管MP10的栅极均与第二NMOS管MN2的漏极连接，第九PMOS管MP9的漏极、第十PMOS管MP10的漏极分别连接至偏置电流产生电路202。
当电路未使能时，第九PMOS管MP9、第十PMOS管MP10无电流注 入到偏置电流产生电路202中；当电路使能时，NMOS电流比例镜像对管(MN1、MN2)和PMOS电流比例镜像对管(MP8、MP9、MP10)，将第一开关管所在支流的启动电流进行比例镜像后分两路注入到偏置电流产生电路202中，使第四NMOS管MN4、第六NMOS管MN6的栅极电压快速上升。
在本发明的一个实施例中,反馈电流关断控制支路303由第二NMOS管MN2和第七PMOS管MP7、第八PMOS管MP8组成。其中，第七PMOS管MP7的源极连接电源端VDD，第七PMOS管MP7的漏极与第八PMOS管MP8的漏极、栅极及第二NMOS管MN2的漏极连接，第七PMOS管MP7的栅极连接至偏置电流产生电路202。
根据KCL(基尔霍夫)定律，可知I MN2＝I MP7+I MP8。当偏置电流产生电路202未启动完成时，第七PMOS管MP7上的电流小于第二NMOS管MN2上的电流，即I MP7<I MN2，此时I MP8被比例镜像后产生两路注入电流，注入到偏置电流产生电路202中。当偏置电流产生电路启动完成时，第七PMOS管MP7上的电流大于第二NMOS管MN2上的电流，即I MP7>I MN2,将第八PMOS管MP8栅极电压拉升至电源端VDD，从而I MP7＝I MN2，此时I MP8＝0，即比例镜像注入电流减小为零。
在本发明的一个实施例中,偏置电流产生电路202由第三NMOS管MN3、第四NMOS管MN4、第五NMOS管MN5、第六NMOS管MN6，以及第一PMOS管MP1、第二PMOS管MP2、第三PMOS管MP3、第四PMOS管MP4、第五PMOS管MP5、第六PMOS管MP6、第十三PMOS管MP13，以及第一电阻R1、第二电阻R2、第三电阻R3组成。其中，第三NMOS管MN3、第四NMOS管MN4、第五NMOS管MN5、第六NMOS管MN6组成共源共栅结构的NMOS电流比例镜像对管，第三PMOS管MP3、第四PMOS管MP4、第五PMOS管MP5、第六PMOS管MP6组成共源共栅结构的PMOS电流比例镜像对管，第一PMOS管MP1、第二PMOS管MP2、第三PMOS管MP3、第四PMOS管MP4组成共源共栅结构的PMOS电流比例镜像对管。具体地说，第三NMOS管MN3的栅极和第四NMOS管MN4的栅极相连接后共同连接比例镜像注入支路302的一路输出即第十PMOS管MP10的漏极，第三NMOS管MN3的源极和第四NMOS管MN4的源极分别连接公共接地端VSS，第三NMOS管MN3的漏极与第五NMOS管MN5的源极连 接，第四NMOS管MN4的漏极与第六NMOS管MN6的源极连接，第五NMOS管MN5的栅极和第六NMOS管MN6的栅极相连接后共同连接比例镜像注入支路302的另一路输出即第九PMOS管MP9的漏极，第六NMOS管MN6的漏极与第四NMOS管MN4的栅极及第三电阻R3连接，第三电阻R3的另一端连接第六NMOS管MN6的栅极及第四PMOS管MP4的漏极，第四PMOS管MP4的栅极与第六PMOS管MP6的栅极及第二PMOS管MP2的栅极连接，第四PMOS管MP4的源极与第三PMOS管MP3的漏极连接，第三PMOS管MP3的栅极与第五PMOS管MP5的栅极及第一PMOS管MP1的栅极连接,第三PMOS管MP3的源极与第一电阻R1连接，第一电阻R1的另一端连接电源端VDD；第五NMOS管MN5的漏极与第二电阻R2及第四PMOS管MP4的栅极连接，第二电阻R2的另一端分别与第六PMOS管MP6的漏极及第五PMOS管MP5的栅极连接，第六PMOS管MP6的源极与第五PMOS管MP5的漏极连接，第五PMOS管MP5的源极连接电源端VDD；第五PMOS管MP5的栅极一方面与反馈电流关断控制支路303中第七PMOS管MP7的栅极连接，另一方面与第十三PMOS管MP13的漏极连接，第十三PMOS管MP13的源极连接电源端VDD，第十三PMOS管MP13的栅极连接使能信号输入端EN；第一PMOS管MP1的源极连接电源端VDD，第一PMOS管MP1的漏极连接第二PMOS管MP2的源极，第二PMOS管MP2的漏极连接基准核心单元102的输入端，即输入偏置电流I BIAS。
当电路未使能时，即EN＝0V，第十三PMOS管MP13导通，使得第三PMOS管MP3、第五PMOS管MP5的栅极拉升至高电位，因此第五PMOS管MP5、第六PMOS管MP6所在支路的电流均为零电流。此时，第四NMOS管MN4、第六NMOS管MN6的栅极处于低电位状态，整个电路均处在稳定的零电流状态中。当电路使能时，即EN＝VDD，第十三PMOS管MP13关断，此时比例镜像注入支路302将镜像注入电流注入到第四NMOS管MN4、第六NMOS管MN6所在支路，共源共栅结构的电流比例镜像对管第三NMOS管MN3、第四NMOS管MN4、第五NMOS管MN5、第六NMOS管MN6，将比例镜像复制注入电流而导致第五PMOS管MP5、第六PMOS管MP6、第二电阻R2、第五NMOS管MN5、第三NMOS管MN3支路上产生电流，第五PMOS管MP5、第六PMOS管MP6的栅极电压将会被下拉。同 理，共源共栅结构的电流比例镜像对管第三PMOS管MP3、第四PMOS管MP4、第五PMOS管MP5、第六PMOS管MP6，再次比例镜像复制第五PMOS管MP5、第六PMOS管MP6所在支路的电流，第三PMOS管MP3、第四PMOS管MP4形成的电流与第十PMOS管MP10和第九PMOS管MP9注入的电流相叠加，并再次被第五NMOS管MN5、第三NMOS管MN3所在支路复制形成正反馈，使偏置电流快速建立。随着第五PMOS管MP5、第六PMOS管MP6、第二电阻R2、第五NMOS管MN5、第三NMOS管MN3所在支路电流的增大，电流比例镜像对管第七PMOS管MP7将第五PMOS管MP5、第六PMOS管MP6所在支路的电流比例镜像后注入到第二NMOS管MN2的漏端。当I MP7＞I MN2时，第八PMOS管MP8的栅极电压被迅速拉升至VDD，则I MP7＝I MN2，根据I MN2＝I MP8+I MP7得出I MP8＝0，因此第九PMOS管MP9、第十PMOS管MP10注入到第四NMOS管MN4、第六NMOS管MN6所在支路的注入电流减小为零，使偏置电流产生单元101进入正常工作状态。
同时，一方面共源共栅型的偏置电流结构保证了产生的偏置电流和电源电压无关；另一方面，第一电阻R1、第二电阻R2以及第三电阻R3分别采用了不同温度系数的电阻类型。例如，第一电阻R1可以选择正温度系数的电阻，第二电阻R2和第三电阻R3可以选择负温度系数的电阻；或者，第一电阻R1可以选择负温度系数的电阻，第二电阻R2和第三电阻R3可以选择正温度系数的电阻，从而保证所产生的偏置电流能够具有零温度系数的特性。最后，共源共栅结构的电流镜像对管第一PMOS管MP1、第二PMOS管MP2、第三PMOS管MP3、第四PMOS管MP4，将偏置电流比例镜像形成输出的偏置电流I BIAS，提供给基准核心单元102。
如图3所示，在本发明的一个实施例中，基准核心单元102包括第二启动电路401和基准核心电路402。其中，第二启动电路401的输出端与基准核心电路402的输入端相连接。第二启动电路401接收偏置电流产生单元101输出的偏置电流I BIAS，将偏置电流I BIAS比例镜像后产生预充电电流并注入到基准核心电路402中，预充电电流最终因反馈电流关断控制的作用减小为零；基准核心电路402接收预充电电流后，产生无过冲快速启动的输出电压。
在本发明的一个实施例中,第二启动电路401包括偏置电流注入支路501、比例镜像注入支路502和反馈电流关断控制支路503；偏置电流注入支路501接收偏置电流产生单元101输出的偏置电流I BIAS；比例镜像注入支路502将I BIAS电流比例镜像后形成预充电电流并注入到基准核心电路402中；反馈电流关断控制支路503在基准核心电路402完成启动后，将预充电电流减小为零。
在本发明的一个实施例中，偏置电流注入支路501由第二十一NMOS管MN1以及第二开关管(Switch)组成。其中，第二开关管接收使能信号的输入，它的一端连接偏置电流产生单元101的输出端，另一端连接第二十一NMOS管MN1的漏极。第二十一NMOS管MN1的源极连接公共接地端VSS，第二十一NMOS管MN1的漏极与栅极短接，第二十一NMOS管MN1的栅极与比例镜像注入支路502中第二十二NMOS管MN2的栅极连接。
当电路未使能时，即EN＝0V，第二开关管关断，第二开关管所在支路的电流为零，其他支路的电流均为零；当电路使能时，即EN＝VDD，第二开关管导通，偏置电流产生电路单元101输出的I BIAS电流通过第二开关管注入到第二十一NMOS管MN1中。
在本发明的一个实施例中,比例镜像注入支路502包括第二十一NMOS管MN1、第二十二NMOS管MN2以及第三十二PMOS管MP12、第三十三PMOS管MP13、第三十四PMOS管MP14、第三十五PMOS管MP15组成。其中，第二十一NMOS管MN1、第二十二NMOS管MN2组成NMOS电流比例镜像对管；第三十二PMOS管MP12、第三十三PMOS管MP13、第三十四PMOS管MP14、第三十五PMOS管MP15组成PMOS电流比例镜像对管。具体地说，第二十一NMOS管MN1的栅极连接第二十二NMOS管MN2的栅极，第二十二NMOS管MN2的源极连接公共接地端VSS，第二十二NMOS管MN2的漏极与第三十二PMOS管MP12的漏极及栅极、第三十三PMOS管MP13的栅极、第三十四PMOS管MP14的栅极、第三十五PMOS管MP15的栅极相连接，第三十二PMOS管MP12的源极、第三十三PMOS管MP13的源极、第三十四PMOS管MP14的源极、第三十五PMOS管MP15的源极均与电源端VDD相连接，第三十三PMOS管MP13的漏极与基准核心电路402的输出端Vref连接，第三 十四PMOS管MP14的漏极与基准核心电路402中的第一运算放大器OPA的同相输入端VA连接，第三十五PMOS管MP15的漏极与基准核心电路402中的第一运算放大器OPA的反相输入端VB连接。
当电路未使能时，即EN＝0V，第二开关管关断，第二十一NMOS管MN1、第二十二NMOS管MN2所在支路的电流均为零，因此第三十三PMOS管MP13、第三十四PMOS管MP14和第三十五PMOS管MP15无电流注入到第一运算放大器OPA的同相输入端VA、反相输入端VB以及基准核心电路402的输出端Vref中。当电路使能时，即EN＝VDD，第二开关管导通,偏置电流产生电路单元101输出的I BIAS电流注入到第二十一NMOS管MN1中,电流比例镜像对管第二十一NMOS管MN1、第二十二NMOS管MN2，以及电流比例镜像对管第三十二PMOS管MP12、第三十三PMOS管MP13、第三十四PMOS管MP14、第三十五PMOS管MP15，将I BIAS电流进行比例镜像复制后形成三路预充电电流。其中，第一路预充电电流即第三十三PMOS管MP13的漏极输出电流，注入到基准核心电路402的输出端Vref，使输出电压快速上升；第二路预充电电流即第三十四PMOS管MP14的漏极输出电流，注入到基准核心电路402中的第一运算放大器OPA的同相输入端VA；第三路预充电电流即第三十五PMOS管MP15的漏极输出电流，注入到基准核心电路402中的第一运算放大器OPA的反相输入端VB，使第一运算放大器OPA所控制的环路电压快速建立，从而快速启动带隙基准电路。
在本发明的一个实施例中,反馈电流关断控制支路503由第二十二NMOS管MN2和第三十一PMOS管MP11、第三十二PMOS管MP12组成；第二十二NMOS管MN2的漏极与第三十一PMOS管MP11的漏极、第三十二PMOS管MP12的栅极和漏极相连接，第三十一PMOS管MP11的源极连接电源端VDD，第三十一PMOS管MP11的栅极与基准核心电路402中的第一运算放大器OPA的输出端V_BIAS连接。
根据KCL(基尔霍夫)定律，可知I MN2＝I MP11+I MP12，当基准核心电路402未启动完成时，第三十一PMOS管MP11上的电流小于第二十二NMOS管MN2上的电流，即I MP11<I MN2。此时，I MP12被比例镜像形成预充电电流,注入到基准核心电路402中。当基准核心电路402启动完成时， 第三十一PMOS管MP11上的电流大于第二十二NMOS管MN2上的电流，即I MP11>I MN2，则第三十二PMOS管MP12的栅极电压拉升至电源端VDD，从而I MP11＝I MN2，此时I MP12＝0，即预充电电流减小为零。
在本发明的一个实施例中,基准核心电路402由第二十一PMOS管MP1、第二十二PMOS管MP2、第二十三PMOS管MP3、第二十四PMOS管MP4、第二十五PMOS管MP5、第二十六PMOS管MP6、第二十七PMOS管MP7、第二十八PMOS管MP8、第二十九PMOS管MP9、第三十PMOS管MP10,以及第二十一电阻R1、第二十二电阻R2,以及第一三极管Q1、第二三极管Q2、第三三极管Q3、第四三极管Q4、第五三极管Q5，以及第一电容C1，以及第一运算放大器OPA组成；第一三极管Q1的基极和集电极与公共接地端VSS连接，第一三极管Q1的发射极与第二三极管Q2的基极及第二十一PMOS管MP1的漏极连接，第二十一PMOS管MP1的源极与第三十PMOS管MP10的漏极连接，第三十PMOS管MP10的源极与电源端VDD连接；第二三极管Q2的集电极与公共接地端VSS连接，第二三极管Q2的发射极与第一运算放大器OPA的反相输入端VB及第二十二PMOS管MP2的漏极连接，第二十二PMOS管MP2的源极与第二十九PMOS管MP9的漏极连接，第二十九PMOS管MP9的源极与电源端VDD连接；第三三极管Q3的基极和集电极与公共接地端VSS连接，第三三极管Q3的发射极与第四三极管Q4的基极及第二十四PMOS管MP4漏极连接，第二十四PMOS管MP4的源极与第二十七PMOS管MP7的漏极连接，第二十七PMOS管MP7的源极与电源端VDD连接；第四三极管Q4的集电极与公共接地端VSS连接，第四三极管Q4的发射极与第二十二电阻R2连接，第二十二电阻R2的另一端与第一运算放大器OPA的同相输入端VA及第二十三PMOS管MP3的漏极连接，第二十三PMOS管MP3的源极与第二十八PMOS管MP8的漏极连接，第二十八PMOS管MP8的源极与电源端VDD连接；第五三极管Q5的基极和集电极与公共接地端VSS连接，第五三极管Q5的发射极与第二十一电阻R1连接，第二十一电阻R1的另一端与第二十五PMOS管MP5的漏极及输出端Vref连接，第二十五PMOS管MP5的源极与第二十六PMOS管MP6的漏极连接，第二十六PMOS管MP6的源极与电源端VDD连接；第一电容C1的一端与公共接地端VSS连接，第一电容C1的另一端与输出端Vref 连接。第一运算放大器OPA的输出端V_BIAS与第二十六PMOS管MP6的栅极、第二十七PMOS管MP7的栅极、第二十八PMOS管MP8的栅极、第二十九PMOS管MP9的栅极、第三十PMOS管MP10的栅极连接。第二十一PMOS管MP1的栅极、第二十二PMOS管MP2的栅极、第二十三PMOS管MP3的栅极、第二十四PMOS管MP4的栅极、第二十五PMOS管MP5的栅极分别与信号输入端Vb1连接。
当电路未使能时，即EN＝0V，电路中所有支路电流为零。当电路使能时，即EN＝VDD，比例镜像注入支路502的三路预充电电路分别注入到第一运算放大器OPA的同相输入端VA、反相输入端VB以及基准核心电路402的输出端Vref处，使同相输入端VA、反相输入端VB的电压快速升高，从而加速第一运算放大器OPA的环路偏置点电压的建立过程。第一运算放大器OPA的输出电压V_BIAS从VDD开始下降，由V_BIAS电压提供偏置信号的第二十六PMOS管MP6、第二十七PMOS管MP7、第二十八PMOS管MP8、第二十九PMOS管MP9、第三十PMOS管MP10以及第三十一PMOS管MP11的各个支路产生电流，第二十八PMOS管MP8、第二十九PMOS管MP9支路的电流和比例镜像注入支路502注入到同相输入端VA、反相输入端VB的预充电电流叠加后,进一步加速同相输入端VA、反相输入端VB的电压建立过程。在第一运算放大器OPA环路向稳定状态建立的过程中，由于比例镜像注入支路502中的第三十三PMOS管MP13注入的预充电电流和由V_BIAS偏置形成的第二十六PMOS管MP6支路电流的叠加，使输出电压快速上升。同时，在带隙基准电路的输出电压不断建立的过程中，由于反馈电流关断控制支路503的作用，预充电电流逐渐降低至零，保证了整体电路中各个偏置点电压和输出电压能够快速稳定下来。
下面，通过图4～图7所示的对比实验进一步验证本发明所提供的带隙基准电路的优异性能。
图4为本发明实施例中，偏置电流随温度变化的曲线对比图。从本发明中的偏置电流随温度变化的曲线与现有技术中的偏置电流随温度变化的曲线对比可以看出，本发明中的偏置电流具有零温度系数的特性，与现有技术中的偏置电流相比变化更小。
图5为本发明实施例中，在不同PVT下偏置电流随温度变化的曲 线图。如图5所示，在不同的PVT条件下，本发明中的偏置电流都具有零温度系数的特性。
图6为本发明实施例中，无过冲启动电压波形与过冲启动电压波形对比图。如图6所示，本发明所提供的带隙基准电路在使能之后，电压波形直接向1.2V接近并且快速稳定在1.2V；现有技术中的过冲启动电路在使能之后，电压波形超过基准电压达到2.6V左右最后才稳定在1.2V。
图7为本发明实施例中，在不同PVT下带隙基准电路启动电压波形图。如图7所示，本发明所提供的带隙基准电路的输出电压能够在不同的PVT下实现无过冲快速启动。
另外，本发明实施例中提供的无过冲快速启动带隙基准电路可以被用在集成电路芯片中。对于该集成电路芯片中无过冲快速启动带隙基准电路的具体结构，在此不再一一详述。
上述无过冲快速启动带隙基准电路还可以被用在电子设备中，作为模拟集成电路的重要组成部分。这里所说的电子设备是指可以在移动环境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信制式的计算机设备，包括移动电话、笔记本电脑、平板电脑、车载电脑等。此外，本发明实施例提供的技术方案也适用于其他模拟集成电路应用的场合，例如通信基站等。
如图8所示，该电子设备至少包括处理器和存储器，还可以根据实际需要进一步包括通信组件、传感器组件、电源组件、多媒体组件及输入/输出接口。其中，存储器、通信组件、传感器组件、电源组件、多媒体组件及输入/输出接口均与该处理器连接。存储器可以是静态随机存取存储器(SRAM)、电可擦除可编程只读存储器(EEPROM)、可擦除可编程只读存储器(EPROM)、可编程只读存储器(PROM)、只读存储器(ROM)、磁存储器、快闪存储器等，处理器可以是中央处理器(CPU)、图形处理器(GPU)、现场可编程逻辑门阵列(FPGA)、专用集成电路(ASIC)、数字信号处理(DSP)芯片等。其它通信组件、传感器组件、电源组件、多媒体组件等均可以采用通用部件实现，在此就不具体说明了。
与现有技术相比较，本发明所提供的无过冲快速启动带隙基准电路一方面通过采用自偏置的共源共栅电流镜结构和具有不同温度系数 类型的电阻，实现了偏置电流与电源电压无关并且具有零温度系数的特性；另一方面，通过采用预充电的方式，加速运算放大器的环路偏置点电压和输出电压的建立过程，从而实现了带隙基准电路能够在所有PVT下无过冲的快速启动,使电子设备具有低功耗以及低延时的性能。
以上对本发明所提供的无过冲快速启动带隙基准电路、芯片及电子设备进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质内容的前提下对它所做的任何显而易见的改动，都将属于本发明专利权的保护范围。

Claims (12)

  1. 一种无过冲快速启动带隙基准电路，其特征在于包括偏置电流产生单元(101)和基准核心单元(102)，所述偏置电流产生单元(101)的输出端与所述基准核心单元(102)的输入端相连接；其中，
    所述偏置电流产生单元(101)产生与电源电压无关并且具有零温度系数的偏置电流，作为所述基准核心单元(102)的输入信号；
    所述基准核心单元(102)根据所述偏置电流产生预充电电流，并采用预充电方式实现无过冲的快速启动。
  2. 如权利要求1所述的无过冲快速启动带隙基准电路，其特征在于：
    所述偏置电流产生单元(101)包括第一启动电路(201)和偏置电流产生电路(202)；其中，所述第一启动电路(201)的输出端与所述偏置电流产生电路(202)的输入端相连接。
  3. 如权利要求2所述的无过冲快速启动带隙基准电路，其特征在于：
    所述第一启动电路(201)包括启动电流产生支路(301)、比例镜像注入支路(302)和反馈电流关断控制支路(303)；其中，所述启动电流产生支路(301)产生启动电流，所述比例镜像注入支路(302)将所述启动电流比例镜像后注入到所述偏置电流产生电路(202)中，所述反馈电流关断控制支路(303)在所述偏置电流产生电路(202)完成启动后，利用反馈电流关断控制的作用将该比例镜像注入电流减小为零。
  4. 如权利要求2所述的无过冲快速启动带隙基准电路，其特征在于：
    所述偏置电流产生电路(202)包括第三NMOS管(MN3)、第四NMOS管(MN4)、第五NMOS管(MN5)、第六NMOS管(MN6)，以及第一PMOS管(MP1)、第二PMOS管(MP2)、第三PMOS管(MP3)、第四PMOS管(MP4)、第五PMOS管(MP5)、第六PMOS管(MP6)、第十三PMOS管(MP13)；其中，第三NMOS管(MN3)、第四NMOS管(MN4)、第五NMOS管(MN5)、第六NMOS管(MN6)组成共源共栅结构的NMOS电流比例镜 像对管，第三PMOS管(MP3)、第四PMOS管(MP4)、第五PMOS管(MP5)、第六PMOS管(MP6)组成共源共栅结构的PMOS电流比例镜像对管，第一PMOS管(MP1)、第二PMOS管(MP2)、第三PMOS管(MP3)、第四PMOS管(MP4)组成共源共栅结构的PMOS电流比例镜像对管。
  5. 如权利要求4所述的无过冲快速启动带隙基准电路，其特征在于：
    所述偏置电流产生电路(202)还包括第一电阻(R1)、第二电阻(R2)和第三电阻(R3)；其中，第一电阻(R1)的一端连接第三PMOS管(MP3)的源极，另一端连接电源端；第二电阻(R2)的一端连接第五NMOS管(MN5)的漏极，另一端分别与第六PMOS管(MP6)的漏极及第五PMOS管(MP5)的栅极连接；第三电阻(R3)的一端分别连接第六NMOS管(MN6)的漏极与第四NMOS管(MN4)的栅极，另一端分别连接第六NMOS管(MN6)的栅极及第四PMOS管(MP4)的漏极。
  6. 如权利要求5所述的无过冲快速启动带隙基准电路，其特征在于：
    所述第一电阻(R1)、所述第二电阻(R2)以及所述第三电阻(R3)分别具有不同的温度系数。
  7. 如权利要求1所述的无过冲快速启动带隙基准电路，其特征在于：
    所述基准核心单元(102)包括第二启动电路(401)和基准核心电路(402)；其中，所述第二启动电路(401)的输出端与所述基准核心电路(402)的输入端相连接。
  8. 如权利要求7所述的无过冲快速启动带隙基准电路，其特征在于：
    所述第二启动电路(401)包括偏置电流注入支路(501)、比例镜像注入支路(502)和反馈电流关断控制支路(503)；其中，所述偏置电流注入支路(501)接收所述偏置电流产生单元(101)输出的偏置电流；所述比例镜像注入支路(502)将所述偏置电流比例镜像后形成预充电电流并注入到所述基准核心电路(402)中；所述反馈电流关断控制支路(503)在基准核心电路(402)完成启动后，将预充电电流减小为零。
  9. 如权利要求8所述的无过冲快速启动带隙基准电路，其特征在于：
    所述预充电电流分为三路；其中，第一路预充电电流为第三十三PMOS管(MP13)的漏极输出电流，注入到基准核心电路(402)的输出端；第二路预充电电流为第三十四PMOS管(MP14)的漏极输出电流，注入到基准核心电路(402)中的第一运算放大器的同相输入端；第三路预充电电流为第三十五PMOS管(MP15)的漏极输出电流，注入到基准核心电路(402)中的第一运算放大器的反相输入端。
  10. 如权利要求8所述的无过冲快速启动带隙基准电路，其特征在于：
    所述反馈电流关断控制支路(503)由第二十二NMOS管(MN2)和第三十一PMOS管(MP11)、第三十二PMOS管(MP12)组成；其中，第二十二NMOS管(MN2)的漏极与第三十一PMOS管(MP11)的漏极、第三十二PMOS管(MP12)的栅极和漏极相连接，第三十一PMOS管(MP11)的源极连接电源端，第三十一PMOS管(MP11)的栅极与基准核心电路(402)中的第一运算放大器的输出端连接；
    当所述基准核心电路(402)启动完成时，第三十一PMOS管(MP11)上的电流大于第二十二NMOS管(MN2)上的电流，第三十二PMOS管(MP12)的栅极电压拉升至VDD，将所述预充电电流减小为零。
  11. 一种集成电路芯片，其特征在于包括权利要求1～10中任意一项所述的无过冲快速启动带隙基准电路。
  12. 一种电子设备，其特征在于包括权利要求1～10中任意一项所述的无过冲快速启动带隙基准电路。
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