WO2021196233A1 - 低压差线性稳压电路 - Google Patents

低压差线性稳压电路 Download PDF

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Publication number
WO2021196233A1
WO2021196233A1 PCT/CN2020/083370 CN2020083370W WO2021196233A1 WO 2021196233 A1 WO2021196233 A1 WO 2021196233A1 CN 2020083370 W CN2020083370 W CN 2020083370W WO 2021196233 A1 WO2021196233 A1 WO 2021196233A1
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WO
WIPO (PCT)
Prior art keywords
circuit
module
energy storage
voltage
switch unit
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Application number
PCT/CN2020/083370
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English (en)
French (fr)
Inventor
薛建锋
张孟文
李运宁
吴与伦
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2020/083370 priority Critical patent/WO2021196233A1/zh
Priority to CN202080001564.0A priority patent/CN111801639B/zh
Priority to EP20922475.7A priority patent/EP3923111A4/en
Priority to US17/469,627 priority patent/US20210405674A1/en
Publication of WO2021196233A1 publication Critical patent/WO2021196233A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Definitions

  • the embodiments of the present application relate to the field of electronic technology, and in particular to a low-dropout linear voltage stabilizing circuit.
  • N-type metal oxide half field effect transistors (English: Metal Oxide Semiconductor Field Effect Transistor, MOS) are usually used as output power tubes . Because the N-type MOS tube has a greater mobility, it can provide a larger current under the same area, and the source negative feedback also makes the N-type MOS tube stronger in transient response. However, the N-type MOS tube needs to consume more voltage margin and is difficult to apply under low power supply voltage.
  • one of the technical problems solved by the embodiments of the present application is to provide a low-dropout linear regulator circuit to overcome the defect that the N-type MOS tube in the low-dropout linear regulator in the prior art is difficult to apply.
  • the embodiment of the application provides a low-dropout linear voltage stabilizing circuit, including: an error amplifying circuit, a charge pump circuit, and an output feedback circuit;
  • the output terminal of the error amplifier circuit is connected to the input terminal of the charge pump circuit
  • the charge pump circuit includes a first switch module, a first energy storage module, a third switch module, a parasitic capacitor, a second switch module, a second energy storage module, and a clock control circuit.
  • the first energy storage module Parasitic capacitance is formed between the component and the ground point;
  • the first switch module is connected with the first energy storage module to form a first charging branch;
  • the third switch module is connected with one end of the first energy storage module, and the third switch module and the parasitic capacitance form a third charging branch;
  • An energy storage module is connected with the second switch module and the second energy storage module to form a second charging branch;
  • the clock control circuit is respectively connected with the first switch module, the third switch module and the second switch module, and is used for controlling whether the first switch module, the third switch module and the second switch module are closed;
  • the output end of the charge pump circuit is connected with the output feedback circuit, and the output feedback circuit is connected with the error amplifier circuit.
  • the error amplifier circuit includes an amplifier and a voltage replication module, and the voltage replication module outputs the same output voltage as the amplifier;
  • the inverting input terminal of the amplifier is connected with the output feedback circuit, the forward input terminal of the amplifier is input with a reference voltage, and the output terminal of the amplifier is connected with the second charging branch;
  • the output terminal of the voltage replication module is connected to the third charging branch.
  • the first switch module includes a first switch unit and a second switch unit; one end of the first switch unit is grounded, and the other end is connected to the first end of the first energy storage module ;
  • One end of the second switch unit is connected with the second end of the first energy storage module, and the other end of the second switch unit is connected to a regulated voltage.
  • the first switch unit is a first field effect transistor
  • the second switch unit is a second field effect transistor
  • the second switch module includes a third switch unit and a fourth switch unit;
  • One end of the third switch unit is connected to the output end of the amplifier and the first end of the second energy storage module, and the other end of the third switch unit is connected to the first end of the first energy storage module;
  • One end of the fourth switch unit is connected to the second end of the second energy storage module, and the other end of the fourth switch unit is connected to the second end of the first energy storage module.
  • the third switch unit is a third field effect transistor
  • the fourth switch unit is a fourth field effect transistor
  • the charge pump circuit further includes a voltage boost circuit, and the voltage boost circuit is connected between the clock control circuit and the gate of the fourth field effect transistor.
  • the third switch module is connected between the output terminal of the voltage replication module and the first terminal of the parasitic capacitor, the second terminal of the parasitic capacitor is grounded, and the first terminal of the parasitic capacitor is grounded.
  • the terminal is connected with the first terminal of the first energy storage module.
  • the third switch module is a fifth field effect transistor.
  • the first energy storage module is a first capacitor
  • the second energy storage module is a second capacitor
  • the parasitic capacitor is a third capacitor.
  • a plate of the first capacitor is connected to A third capacitor is formed between the ground points.
  • the output feedback circuit includes a sixth field effect transistor, a first resistor, a second resistor, and a fourth capacitor;
  • the output terminal of the charge pump circuit is connected with the gate of the sixth field effect transistor, the drain of the sixth field effect transistor is connected to the input voltage, and the source of the sixth field effect transistor outputs the output voltage of the low dropout linear voltage regulator circuit;
  • the first end of the first resistor is connected to the source of the sixth field effect transistor, the second end of the first resistor is connected to the second resistor, and the second end of the first resistor is connected to the inverting input end of the amplifier;
  • the second end of the second resistor is grounded, the first end of the fourth capacitor is connected to the source of the sixth field effect transistor, and the second end of the fourth capacitor is grounded.
  • the charge pump circuit provides a higher voltage, that is, the input voltage of the output feedback circuit is increased, so that the gate of the N-type MOS tube can also input a higher voltage in a low-voltage environment.
  • the voltage makes the N-type MOS tube suitable for low-voltage environments, and the clock control circuit included in the charge pump circuit can separately control the opening or closing of the first switch module, the third switch module and the second switch module.
  • the first energy storage module When the switch unit in the switch module is closed, the first energy storage module is charged, when the switch in the third switch module is closed, the parasitic capacitance is charged, and when the switch unit in the second switch module is closed, the first The energy storage module charges the second energy storage module to ensure voltage stability, and because the third switch module can be closed before the second switch module is closed, the parasitic capacitance can be charged separately to avoid when the second switch module is closed , Because the parasitic capacitance is charged and the voltage fluctuates greatly.
  • FIG. 1 is a block diagram of a low-dropout linear voltage stabilizing circuit provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of a low-dropout linear voltage stabilizing circuit provided by an embodiment of the application;
  • FIG. 3 is a schematic diagram of a timing control provided by an embodiment of the application.
  • FIG. 4 is an overall schematic diagram of a circuit structure of an output feedback circuit and a block diagram of an error amplifying circuit and a charge pump circuit in a low dropout linear voltage regulator circuit provided by an embodiment of the application;
  • FIG. 5 is a schematic structural diagram of an error amplifying circuit provided by an embodiment of the application.
  • FIG. 6 is a structural diagram of a voltage raising circuit provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of signal effects of a voltage boost circuit provided by an embodiment of the application.
  • FIG. 1 is a schematic block diagram of a low-dropout linear voltage stabilizer circuit provided by an embodiment of the application; an embodiment of the present application provides a low-dropout linear voltage stabilizer circuit 10, as shown in FIG. 1, the low-dropout linear voltage stabilizer
  • the circuit 10 includes: an error amplifier circuit 101, a charge pump circuit 102, and an output feedback circuit 103;
  • the output terminal of the error amplifying circuit 101 is connected to the input terminal of the charge pump circuit 102;
  • the charge pump circuit 102 includes a first switch module 1021, a first energy storage module 1022, a third switch module 1025, a parasitic capacitor 1026, a second switch module 1023, a second energy storage module 1024, and a clock control circuit 1027.
  • a parasitic capacitance 1026 is formed between the components in the first energy storage module 1022 and the ground point;
  • the first switch module 1021 is connected with the first energy storage module 1022 to form a first charging branch;
  • the third switch module 1025 is connected with one end of the first energy storage module 1022, and the third switch module 1025 and the parasitic capacitor 1026 form a first charging branch.
  • Three charging branches; the first energy storage module 1022 is connected with the second switch module 1023 and the second energy storage module 1024 to form a second charging branch;
  • the clock control circuit 1027 is respectively connected with the first switch module 1021, the third switch module 1025 and the second switch module 1023, and is used to control the first switch module 1021, the third switch module 1025 and the second switch module 1023 is it closed;
  • the output terminal of the charge pump circuit 102 is connected to the output feedback circuit 103, and the output feedback circuit 103 is connected to the error amplifier circuit 101.
  • the output feedback circuit 103 is used to stabilize the output voltage of the error amplifier circuit 101. Because the charge pump circuit 102 increases the input voltage, that is, the input voltage of the output feedback circuit 103, so that the output feedback circuit 103 provides a higher input voltage in a low-voltage environment, which can make the gate of the N-type MOS tube Extremely higher voltages can be obtained in low-voltage environments, making N-type MOS tubes suitable for low-voltage environments.
  • the output feedback circuit 103 includes an N-type MOS transistor.
  • the two input terminals of the error amplifier circuit 101 input the reference voltage and the output voltage of the output feedback circuit 103 respectively, and generate an error according to the error value between the reference voltage and the output voltage of the output feedback circuit 103.
  • the voltage and the error voltage are amplified and output through the output terminal of the error amplifying circuit 101.
  • the output voltage of the error amplifying circuit 101 is input to the charge pump circuit, and optionally, the output voltage of the error amplifying circuit 101 is input to the second charging branch and the third charging branch of the charge pump circuit 102.
  • each of the first switch module 1021, the third switch module 1025, and the second switch module 1023 includes at least one switch unit, and the opening or closing of the switch module can make the corresponding charging The branch is disconnected or connected. Specifically, when the first switch module 1021 is closed, the first charging branch is connected. At this time, the first energy storage module 1022 is charged by defining the bias voltage external to the energy storage module 1022; in the third switch module 1025 When closed, the third charging branch is connected, and the parasitic capacitor 1026 is charged through the error amplifier circuit 101; when the first switch module 1021 and the third switch module 1025 are disconnected, and the second switch module 1023 is turned on, the second switch module 1023 is turned on.
  • the charging branch is connected, the first energy storage module 1022 is discharged to charge the second energy storage module 1024, and when the first energy storage module 1022 is charging the second energy storage module 1024, the error amplifying circuit 101 is also charging the second energy storage module 1024.
  • the energy module 1024 is charged. Therefore, the voltage across the second energy storage module rises, and the voltage input to the output feedback circuit 103 is relatively high.
  • the end of the second energy storage module 1024 close to the output feedback circuit serves as the output terminal of the charge pump circuit 102 , A higher voltage can be provided to the output feedback circuit 103.
  • the first switch module 1021 and the second switch module 1023 are not opened or closed at the same time, or the states of the two switch modules are complementary.
  • the output feedback circuit 103 processes the voltage signal output by the charge pump circuit and feeds it back to the input terminal of the error amplifier circuit 101 to stabilize the output voltage of the error amplifier circuit 101.
  • the charge pump circuit 102 in this embodiment can provide a larger voltage, combined with the circuit shown in FIG. 1, because the first energy storage module 1022 can pre-store charges through charging, and transfer to the second energy storage module 1024 in the error amplifier circuit When charging, the pre-stored charge of the first energy storage module 1022 is also transferred to the second energy storage module 1024, which causes the voltage of the second energy storage module 1024 to increase, and the voltage input to the output feedback circuit 103 is relatively high.
  • the parasitic capacitance 1026 is formed between the elements in the first energy storage module 1022 and the ground point, it can also be said that the elements in the first energy storage module 1022 form a parasitic capacitance 1026 with respect to the ground.
  • the energy module 1022 When the energy module 1022 charges the second energy storage module 1024, it will charge the parasitic capacitance 1026 first, which will cause large ripples in the output of the circuit.
  • the third switch module 1025 before the first energy storage module 1022 charges the second energy storage module 1024, the third switch module 1025 is controlled to be closed, and the parasitic capacitor 1026 is first charged through the error amplifier circuit 101, and then the parasitic capacitor 1026 is charged in the first energy storage module 1024.
  • the module 1022 charges the second energy storage module 1024, because the parasitic capacitor 1026 has already been charged, the output ripple of the circuit is avoided, and the output voltage is not unstable.
  • FIG. 2 is a schematic structural diagram of a low-dropout linear regulator circuit provided by an embodiment of the application, and the low-dropout linear regulator circuit shown in FIG. 2 is a corresponding diagram A further limited description of the low-dropout linear voltage regulator circuit shown in Figure 1.
  • Figure 2 focuses on the internal structure of the charge pump circuit 102.
  • the structure of the error amplifier circuit 101 is further shown in detail.
  • the error amplifier circuit 101 includes an amplifier 1011 and a voltage replication module 1012, and the voltage replication module 1012 outputs the same output voltage as the amplifier 1011;
  • the inverting input terminal of the amplifier 1011 is connected to the output feedback circuit 103, the forward input terminal of the amplifier 1011 is input with a reference voltage, the output terminal of the amplifier 1011 is connected to the second charging branch; the output terminal of the voltage replication module 1012 is connected to the third charging circuit Branch connection.
  • the voltage output from the output terminal of the voltage replication module 1012 is the same as the voltage output from the output terminal of the amplifier 1011.
  • the switch module may include at least one switch unit, a switch unit may be a field effect tube or a triode, and the energy storage module may be a capacitor.
  • a switch unit may be a field effect tube or a triode
  • the energy storage module may be a capacitor
  • the first switch module 1021 includes a first switch unit 10211 and a second switch unit 10212; one end of the first switch unit 10211 is grounded, and the other end is connected to the first switch unit 1022 of the first energy storage module 1022. One end connected
  • the bias voltage is an external voltage and can be connected through an external circuit. enter.
  • the first switch unit 10211 is a first field effect transistor
  • the second switch unit 10212 is a second field effect transistor
  • the first energy storage module 1022 may be a first capacitor
  • the second switch module 1023 includes a third switch unit 10231 and a fourth switch unit 10232;
  • One end of the third switch unit 10231 is connected to the output end of the amplifier 1011 and the first end of the second energy storage module 1024, and the other end of the third switch unit 10231 is connected to the first end of the first energy storage module 1022;
  • One end of the fourth switch unit 10232 is connected to the second end of the second energy storage module 1024, and the other end of the fourth switch unit 10232 is connected to the second end of the first energy storage module 1022.
  • the third switch unit 10231 is a third field effect transistor
  • the fourth switch unit 10232 is a fourth field effect transistor
  • the second energy storage module 1024 may be a second capacitor.
  • the charge pump circuit 102 further includes a voltage boost circuit 1028, and the voltage boost circuit 1028 is connected between the clock control circuit 1027 and the gate of the fourth field effect transistor.
  • the third switch module 1025 is connected between the output terminal of the voltage replication module 1012 and the first terminal of the parasitic capacitor 1026, the second terminal of the parasitic capacitor 1026 is grounded, and the parasitic capacitor 1026 The first end of is connected to the first end of the first energy storage module 1022.
  • the third switch module 1025 may be a fifth switch unit, and the fifth switch unit may be a fifth field effect transistor.
  • the parasitic capacitance 1026 is a capacitance formed between a plate of the first capacitor and the ground point.
  • FIG. 3 is a schematic diagram of a timing control provided by an embodiment of the application.
  • the control of the first switch unit 10211, the second switch unit 10212, the third switch unit 10231, the fourth switch unit 10232, and the fifth switch unit is shown.
  • a high level indicates that the switch is closed and the branch is conductive.
  • On, low level means that the switch is off and the branch is off.
  • in one cycle of control it can be divided into three periods.
  • the first switch unit 10211 and the second switch unit 10212 are closed, and the third switch unit 10231, the fourth switch unit 10232 and The fifth switch unit is turned off, and the first energy storage module 1022 is charged to a regulated voltage; in the second period, the first switch unit 10211 and the second switch unit 10212 are disconnected, and the fifth switch unit is closed.
  • the voltage replication model The output voltage of the group 1012 charges the parasitic capacitance 1026; in the third period, the third switch unit 10231 and the fourth switch unit 10232 are closed, and the first switch unit 10211 and the second switch unit 10212 are disconnected, because in the second period, the The parasitic capacitor 1026 is charged.
  • the third switch unit 10231 and the fourth switch unit 10232 are closed, there is no need to charge the parasitic capacitor 1026 through the output voltage of the output terminal of the amplifier 1011, and the first energy storage module 1022 transfers to the second energy storage module 1024 Charge.
  • the bias voltage of the first switch unit 10211 may change from high to low before the bias voltage of the second switch unit 10212, that is, the first switch unit 10211 precedes the first switch unit 10211.
  • the second switch unit 10212 is disconnected.
  • the first switch unit 10211 and the second switch unit 10212 are closed, the first energy storage module 1022 is charged through the bias voltage (VA).
  • the second switch unit 10212 If the second switch unit 1022 is disconnected first The switch unit 10212, or disconnect the first switch unit 10211 and the second switch unit 10212 at the same time, the second switch unit 10212 will also have a part of the charge transferred to the first energy storage module 1022, that is, a channel injection effect will be generated, so that the first An error occurs between the charge stored on an energy storage module 1022 and the expected amount of charge. Therefore, when disconnecting the first switch unit 10211 and the second switch unit 10212, the first switch unit 10211 is disconnected first, so that the end of the first energy storage module 1022 close to the first switch unit 10211 is in a floating state, and then the second switch unit 10211 is disconnected.
  • the charge on the second switch unit 10212 will not be transferred to the first energy storage module 1022, which reduces the influence of the channel injection effect. Because the bias voltage of the first switch unit 10211 can be changed from a high level to a low level before the bias voltage of the second switch unit 10212, therefore, the bias voltage of the first switch unit 10211 also precedes the second switch unit The bias voltage of 10212 changes from low to high. Similarly, the third switch unit 10231 and the fourth switch unit 10232 are also controlled in this way to reduce the influence of the channel injection effect.
  • Such periodic cycle control can maintain the voltage of the second energy storage module 1024 near the regulated voltage.
  • the second end of the second energy storage module 1024 serves as the charge pump circuit 102.
  • the output terminal is connected to the input terminal of the output feedback circuit 103.
  • the output feedback circuit 103 transmits a feedback signal (VFB) to the error amplifier circuit 101 according to the voltage signal output by the second end of the second energy storage module 1024 to form the error amplifier circuit 101
  • Negative feedback plays a role in stabilizing the output voltage of the error amplifier circuit 101.
  • FIG. 4 is a circuit structure of an output feedback circuit and a block diagram of an error amplifier circuit and a charge pump circuit in the low-dropout linear regulator circuit provided by an embodiment of the application.
  • the overall schematic diagram of, focuses on the specific structure of the output feedback circuit 103 in the low dropout linear voltage regulator circuit.
  • the output feedback circuit 103 includes a sixth field effect transistor 1031, a first resistor 1032, a second resistor 1033, and a fourth capacitor 1034;
  • the output terminal of the charge pump circuit 102 is connected to the gate of the sixth field effect tube 1031, the drain of the sixth field effect tube 1031 is connected to the input voltage, and the source electrode of the sixth field effect tube 1031 outputs a low dropout linear voltage regulator circuit 10 The output voltage;
  • the first end of the first resistor 1032 is connected to the source of the sixth field effect transistor 1031, the second end of the first resistor 1032 is connected to the second resistor 1033, and the second end of the first resistor 1032 is connected to the inverting phase of the amplifier 1011. Input
  • the second end of the second resistor 1033 is grounded, the first end of the fourth capacitor 1034 is connected to the source of the sixth field effect transistor 1031, and the second end of the fourth capacitor 1034 is grounded.
  • the first The input to the gate of the six field effect transistor is the voltage output by the error amplifier circuit 101, and the drain of the sixth field effect transistor 1031 is connected to the power supply voltage, which causes the gate voltage of the sixth field effect transistor 1031 to be too small.
  • the sixth field effect transistor 1031 is turned on. After the charge pump circuit 102 is added, the voltage output by the error amplifier circuit 101 is boosted by the charge pump circuit 102 and then output to the gate of the sixth field effect transistor 1031.
  • the field effect transistor 1031 is turned on.
  • FIG. 5 is a schematic structural diagram of an error amplifying circuit provided by an embodiment of the application.
  • the error amplifier circuit 101 includes an amplifier 1011 and a voltage replication module 1012, and the signal output by the amplifier 1011 is the same as the signal voltage output by the voltage replication module 1012.
  • OUT represents the output terminal of the amplifier 1011
  • OUT_R represents the output terminal of the voltage replication module 1012.
  • the letter T is used to indicate a field effect tube.
  • the field effect tube T can also be a MOS tube. This application is not limited to this, and C is used to indicate a capacitor.
  • the amplifier 1011 includes 11 field effect tubes. T1-T11, and a capacitor C1;
  • the voltage replication module 1012 includes two field effect transistors T12 and T13, and a capacitor C2.
  • the sources of T1-T4 are all connected to the power supply voltage
  • the gates of T1-T3 are connected to the bias voltage VB1
  • the gate of T4 is connected to the drain of T3
  • the drain of T1 is connected to T5 and T6 respectively.
  • the gate of T5 serves as the inverting input terminal of the amplifier 1011
  • the gate of T5 can input the VFB signal (that is, the feedback signal output by the feedback circuit 103)
  • the gate of T6 serves as the non-inverting input terminal of the amplifier 1011.
  • the gate of T6 can input the VREF signal (that is, the external input reference voltage);
  • the drain of T7 is connected to the drain of T2, the drain of T8 is connected to the drain of T3, the gate of T7 is connected to the gate of T8, and the bias voltage VB2 is connected, and the drain of T5 is connected to the source of T7.
  • the drain of T6 is connected to the source of T8, and the drain of T8 and T4 are connected to both ends of C1;
  • the drain of T9 is connected to the source of T7, the drain of T10 is connected to the source of T8, the drain of T11 is connected to the drain of T4, the source of T9-T11 is grounded, and the gates of T9-T11 are connected biased.
  • the source of T12 is connected to the power supply voltage
  • the gate of T12 is connected to the bias voltage VB1
  • the drain of T12 is connected to the drain of T13
  • the source of T13 is grounded
  • the gate of T13 is connected.
  • Connected to the drain of T3, the drain of T12 and the source of T13 are respectively connected to both ends of C2, where the drain of T12 is the output terminal of the voltage replication module 1012.
  • bias voltages VB1, VB2, and VB3 shown in FIG. 5 are all input by an external circuit.
  • FIG. 5 only exemplarily illustrates the implementation of the amplifier 1011 and the voltage replication module 1012, and does not mean that the application is limited to this.
  • FIG. 6 is a structure diagram of a voltage boost circuit provided by an embodiment of the application, which describes the internal structure of the voltage boost circuit, as shown in FIG. 2
  • the input terminal of the voltage boost circuit 1028 is connected to the output terminal of the clock control circuit 1027, and the output terminal of the voltage boost circuit 1028 is connected to the gate of the fourth field effect transistor.
  • the letter T is used for field effect transistors
  • M is used for MOS transistors
  • C is used for capacitors.
  • the voltage boost circuit 1028 may include two field effect transistors T14 and T15, three MOS transistors M1, M2, and M3, one capacitor C3, and one inverter.
  • the input terminal of the inverter is connected to the output terminal of the clock control circuit 1027, the input terminal of the inverter inputs the clock input signal CLK IN , the output terminal of the inverter outputs the clock inverted signal CLK b , and the output terminal of the inverter is connected with
  • the drain of T14 is connected, the gate of T14 is connected to the gate of M1, and the power supply voltage is connected, and the source of T14 is connected to the drain of M1;
  • the source of M2 is connected to the source of M1, the gate of M2 is connected to the gate of T14, the drain of M2 is connected to the power supply voltage, and the source of M2 and the drain of T14 are respectively connected to both ends of C3;
  • the source of M2 is connected to the source of M3, the gate of M3 can be connected to the output of the inverter, the gate of M3 is connected to the clock inverted signal CLK b , the drain of M3 is connected to the drain of T15, T15
  • the gate of T15 can be connected to the output terminal of the inverter, the gate of T15 is connected to the clock inversion signal CLK b , the source of T15de is grounded, and the drain of M3 is the output terminal of the voltage boost circuit 1028, which outputs the clock output
  • the signal CLK OUT controls the fourth field effect transistor through the clock output signal CLK OUT.
  • FIG. 7 is a schematic diagram of a signal effect of a voltage raising circuit provided by an embodiment of the application.
  • the charge pump circuit provides a higher voltage, that is, the input voltage of the output feedback circuit is increased, so that the gate of the N-type MOS tube can also input a higher voltage in a low-voltage environment.
  • the voltage makes the N-type MOS tube suitable for low-voltage environments, and the clock control circuit included in the charge pump circuit can separately control the opening or closing of the first switch module, the third switch module and the second switch module.
  • the first energy storage module When the switch unit in the switch module is closed, the first energy storage module is charged, when the switch in the third switch module is closed, the parasitic capacitance is charged, and when the switch unit in the second switch module is closed, the first The energy storage module charges the second energy storage module to ensure voltage stability, and because the third switch module can be closed before the second switch module is closed, the parasitic capacitance can be charged separately to avoid when the second switch module is closed , Because the parasitic capacitance is charged and the voltage fluctuates greatly.
  • the improvement of a technology can be clearly distinguished between hardware improvements (for example, improvements in circuit structures such as diodes, transistors, switches, etc.) or software improvements (improvements in method flow).
  • hardware improvements for example, improvements in circuit structures such as diodes, transistors, switches, etc.
  • software improvements improvements in method flow.
  • the improvement of many methods and processes of today can be regarded as a direct improvement of the hardware circuit structure.
  • Designers almost always get the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that the improvement of a method flow cannot be realized by the hardware entity module.
  • a programmable logic device for example, a Field Programmable Gate Array (Field Programmable Gate Array, FPGA)
  • PLD Programmable Logic Device
  • FPGA Field Programmable Gate Array
  • HDL Hardware Description Language
  • ABEL Advanced Boolean Expression Language
  • AHDL Altera Hardware Description Language
  • HDCal JHDL
  • Lava Lava
  • Lola MyHDL
  • PALASM RHDL
  • VHDL Very-High-Speed Integrated Circuit Hardware Description Language
  • Verilog Verilog
  • the controller can be implemented in any suitable manner.
  • the controller can take the form of, for example, a microprocessor or a processor, and a computer-readable medium storing computer-readable program codes (such as software or firmware) executable by the (micro)processor. , Logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers and embedded microcontrollers. Examples of controllers include but are not limited to the following microcontrollers: ARC625D, Atmel AT91SAM, Microchip PIC18F26K20 and Silicon Labs C8051F320, the memory controller can also be implemented as part of the memory control logic.
  • controllers in addition to implementing the controller in a purely computer-readable program code manner, it is completely possible to program the method steps to make the controller use logic gates, switches, application specific integrated circuits, programmable logic controllers and embedded logic.
  • the same function can be realized in the form of a microcontroller or the like. Therefore, such a controller can be regarded as a hardware component, and the devices included in it for realizing various functions can also be regarded as a structure within the hardware component. Or even, the device for realizing various functions can be regarded as both a software module for realizing the method and a structure within a hardware component.

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Abstract

本申请实施例提供了一种低压差线性稳压电路，该电路包括：误差放大电路、电荷泵电路及输出反馈电路；误差放大电路的输出端与电荷泵电路的输入端连接；电荷泵电路包括第一开关模组、第一储能模块、第三开关模组、寄生电容、第二开关模组、第二储能模块及时钟控制电路；时钟控制电路分别与第一开关模组、第三开关模组及第二开关模组连接，用于控制第一开关模组、第三开关模组及第二开关模组是否闭合；电荷泵电路的输出端与输出反馈电路连接，输出反馈电路与误差放大电路连接。能够提供更高的电压，并且减少电压波动。

Description

低压差线性稳压电路 技术领域
本申请实施例涉及电子技术领域，尤其涉及低压差线性稳压电路。
背景技术
对于低压差线性稳压器(英文；Low Dropout Regulator，LDO)，为了实现更快的响应，通常使用N型金氧半场效晶体管(英文：Metal Oxide Semiconductor Field Effect Transistor，MOS)做输出功率管，因为N型MOS管具有更大的迁移率，使其在相同面积下能够提供更大的电流，并且源极负反馈也让N型MOS管瞬态响应能力更强。但是，N型MOS管需要消耗较多的电压裕度，在低电源电压下难以适用。
发明内容
有鉴于此，本申请实施例所解决的技术问题之一在于提供一种低压差线性稳压电路，用以克服现有技术中低压差线性稳压器中N型MOS管难以适用的缺陷。
本申请实施例提供了一种低压差线性稳压电路，包括：误差放大电路、电荷泵电路及输出反馈电路；
误差放大电路的输出端与电荷泵电路的输入端连接；
电荷泵电路包括第一开关模组、第一储能模块、第三开关模组、寄生电容、第二开关模组、第二储能模块及时钟控制电路，其中，第一储能模块中的元件与接地点之间形成寄生电容；
第一开关模组与第一储能模块连接形成第一充电支路；第三开关模组与第一储能模块的一端连接，第三开关模组与寄生电容形成第三充电支路；第一储能模块与第二开关模组及第二储能模块连接形成第二充电支路；
时钟控制电路分别与第一开关模组、第三开关模组及第二开关模组连接，用于控制第一开关模组、第三开关模组及第二开关模组是否闭合；
电荷泵电路的输出端与输出反馈电路连接，输出反馈电路与误差放大电路连接。
可选地，在本申请的一个实施例中，误差放大电路包括放大器和电压复 制模组，电压复制模组输出与放大器相同的输出电压；
放大器的反相输入端与输出反馈电路连接，放大器的正向输入端输入基准电压，放大器的输出端与第二充电支路连接；
电压复制模组的输出端与第三充电支路连接。
可选地，在本申请的一个实施例中，第一开关模组包括第一开关单元和第二开关单元；第一开关单元的一端接地，另一端与第一储能模块的第一端连接；
第二开关单元的一端与第一储能模块的第二端连接，第二开关单元的另一端接入稳压电压。
可选地，在本申请的一个实施例中，第一开关单元为第一场效应管，第二开关单元为第二场效应管。
可选地，在本申请的一个实施例中，第二开关模组包括第三开关单元和第四开关单元；
第三开关单元的一端与放大器的输出端及第二储能模块的第一端连接，第三开关单元的另一端与第一储能模块的第一端连接；
第四开关单元的一端与第二储能模块的第二端连接，第四开关单元的另一端与第一储能模块的第二端连接。
可选地，在本申请的一个实施例中，第三开关单元为第三场效应管，第四开关单元为第四场效应管。
可选地，在本申请的一个实施例中，电荷泵电路还包括电压抬升电路，电压抬升电路连接在时钟控制电路与第四场效应管的栅极之间。
可选地，在本申请的一个实施例中，第三开关模组连接在电压复制模组的输出端与寄生电容的第一端之间，寄生电容的第二端接地，寄生电容的第一端与第一储能模块的第一端连接。
可选地，在本申请的一个实施例中，第三开关模组为第五场效应管。
可选地，在本申请的一个实施例中，第一储能模块为第一电容，第二储能模块为第二电容，寄生电容为第三电容，其中，第一电容的一个极板与接地点之间形成第三电容。
可选地，在本申请的一个实施例中，输出反馈电路包括第六场效应管、第一电阻、第二电阻及第四电容；
电荷泵电路的输出端与第六场效应管的栅极连接，第六场效应管的漏极 接入输入电压，第六场效应管的源极输出低压差线性稳压电路的输出电压；
第一电阻的第一端与第六场效应管的源极连接，第一电阻的第二端与第二电阻连接，第一电阻的第二端连接至放大器的反相输入端；
第二电阻的第二端接地，第四电容的第一端与第六场效应管的源极连接，第四电容的第二端接地。
本申请实施例的低压差线性稳压电路，由于电荷泵电路提供了更高的电压，即输出反馈电路的输入电压增高，使得N型MOS管的栅极在低压环境下也可以输入更高的电压，使得N型MOS管适用于低压环境，而且电荷泵电路包含的时钟控制电路，可以分别控制第一开关模组、第三开关模组及第二开关模组断开或者闭合，在第一开关模组中的开关单元闭合时，对第一储能模块充电，在第三开关模组中的开关闭合时，对寄生电容充电，在第二开关模组中的开关单元闭合时，第一储能模块对第二储能模块充电，保证了电压稳定，而且因为在第二开关模组闭合前，可以闭合第三开关模组，对寄生电容单独充电，避免在第二开关模组闭合时，因为对寄生电容充电而导致电压波动较大。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比例绘制的。附图中：
图1为本申请实施例提供的一种低压差线性稳压电路的框图；
图2为本申请实施例提供的一种低压差线性稳压电路的结构示意图；
图3为本申请实施例提供的一种时序控制示意图；
图4为本申请实施例提供的一种输出反馈电路的电路结构与低压差线性稳压电路中的误差放大电路、电荷泵电路框图的整体示意图；
图5为本申请实施例提供的一种误差放大电路的结构示意图；
图6为本申请实施例提供的一种电压抬升电路的结构图；
图7为本申请实施例提供的一种电压抬升电路的信号效果示意图。
具体实施方式
实施本申请实施例的任一技术方案必不一定需要同时达到以上的所有优点。
为了使本领域的人员更好地理解本申请实施例中的技术方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请实施例一部分实施例，而不是全部的实施例。基于本申请实施例中的实施例，本领域普通技术人员所获得的所有其他实施例，都应当属于本申请实施例保护的范围。
下面结合本申请实施例附图进一步说明本申请实施例的具体实现。
图1为本申请实施例提供的一种低压差线性稳压电路的示意性框图；本申请实施例提供了一种低压差线性稳压电路10，如图1所示，该低压差线性稳压电路10包括：误差放大电路101、电荷泵电路102及输出反馈电路103；
误差放大电路101的输出端与电荷泵电路102的输入端连接；
电荷泵电路102包括第一开关模组1021、第一储能模块1022、第三开关模组1025、寄生电容1026、第二开关模组1023、第二储能模块1024及时钟控制电路1027，其中，第一储能模块1022中的元件与接地点之间形成寄生电容1026；
第一开关模组1021与第一储能模块1022连接形成第一充电支路；第三开关模组1025与第一储能模块1022的一端连接，第三开关模组1025与寄生电容1026形成第三充电支路；第一储能模块1022与第二开关模组1023及第二储能模块1024连接形成第二充电支路；
时钟控制电路1027分别与第一开关模组1021、第三开关模组1025及第二开关模组1023连接，用于控制第一开关模组1021、第三开关模组1025及第二开关模组1023是否闭合；
电荷泵电路102的输出端与输出反馈电路103连接，输出反馈电路103与误差放大电路101连接。输出反馈电路103用于对误差放大电路101的输出电压进行稳压。因为电荷泵电路102将输入的电压升高，也就是输出反馈电路103的输入电压升高，使得输出反馈电路103在低压环境下提供了更高的输入电压，就可以使得N型MOS管的栅极在低压环境下可以获得更高的电压，使得N型MOS管适用于低压环境。可选地，在本申请中，输出反馈电路103包括N型MOS管。
参照图1所示，可选地，误差放大电路101的两个输入端分别输入参考电压与输出反馈电路103的输出电压，根据参考电压与输出反馈电路103的输出电压之间的误差值产生误差电压并对误差电压进行放大，并通过误差放大电 路101的输出端输出。误差放大电路101的输出的电压输入到电荷泵电路，可选地，误差放大电路101的输出的电压输入到电荷泵电路102的第二充电支路路和第三充电支路。
需要说明的是，第一开关模组1021、第三开关模组1025和第二开关模组1023中每个开关模组都包含至少一个开关单元，开关模组断开或闭合可以使得对应的充电支路断开或连通。具体的，在第一开关模组1021闭合时，第一充电支路连通，此时，通过定义储能模块1022外接的偏置电压对第一储能模块1022充电；在第三开关模组1025闭合时，第三充电支路连通，通过误差放大电路101对寄生电容1026充电；在第一开关模组1021和第三开关模组1025断开，第二开关模组1023导通时，第二充电支路连通，第一储能模块1022放电以对第二储能模块1024充电，而在第一储能模块1022向第二储能模块1024充电时，误差放大电路101也在向第二储能模块1024充电，因此，第二储能模块两端电压升高，向输出反馈电路103输入的电压就比较高，第二储能模块1024靠近输出反馈电路的一端作为电荷泵电路102的输出端，可以向输出反馈电路103提供更高的电压。第一开关模组1021和第二开关模组1023不同时断开或闭合，或者说两个开关模组的状态互补。
输出反馈电路103因为输入的电压变高，使得N形MOS管可以适用于该电路。输出反馈电路103将电荷泵电路输出的电压信号进行处理并反馈至误差放大电路101的输入端，以对误差放大电路101的输出电压进行稳压。
本实施例中的电荷泵电路102可以提供更大的电压，结合图1所示的电路，因为第一储能模块1022可以通过充电预先存储电荷，在误差放大电路向第二储能模块1024转移电荷时，第一储能模块1022预先存储的电荷也向第二储能模块1024转移，这就导致第二储能模块1024的电压升高，向输出反馈电路103输入的电压就比较高。在此过程中，因为第一储能模块1022中的元件与接地点之间形成寄生电容1026，也可以说第一储能模块1022中的元件对地形成寄生电容1026，因此，在第一储能模块1022向第二储能模块1024充电时，会先向寄生电容1026充电，这会导致电路输出存在较大波纹。本申请中，在第一储能模块1022向第二储能模块1024充电之前，通过控制第三开关模组1025闭合，通过误差放大电路101先对寄生电容1026进行充电，进而在第一储能模块1022向第二储能模块1024充电时，因为寄生电容1026已经完成充电，避免了电路输出产生波纹，避免输出电压不稳定。
基于图1所示的低压差线性稳压电路的框图，图2为本申请实施例提供的一种低压差线性稳压电路的结构示意图，图2所示的低压差线性稳压电路是对图1所示的低压差线性稳压电路的进一步限定描述，图2中重点体现电荷泵电路102的内部结构，对误差放大电路101的结构作了进一步详细展示，参照图2所示，可选地，在本申请的一个实施例中，误差放大电路101包括放大器1011和电压复制模组1012，电压复制模组1012输出与放大器1011相同的输出电压；
放大器1011的反相输入端与输出反馈电路103连接，放大器1011的正向输入端输入基准电压，放大器1011的输出端与第二充电支路连接；电压复制模组1012的输出端与第三充电支路连接。
电压复制模组1012的输出端输出的电压与放大器1011的输出端输出的电压相同。
参照图2所示，本申请中，开关模组可以包括至少一个开关单元，一个开关单元可以是一个场效应管或三极管，储能模块可以是一个电容，当然，只是示例性说明，此处，列举三个示例分别对第一充电支路、第三充电支路和第二充电支路进行说明。
可选地，在第一个示例中，第一开关模组1021包括第一开关单元10211和第二开关单元10212；第一开关单元10211的一端接地，另一端与第一储能模块1022的第一端连接；
第二开关单元10212的一端与第一储能模块1022的第二端连接，第二开关单元10212的另一端接入偏置电压(VA)，偏置电压是外接的电压，可以通过外部电路接入。
可选地，在本申请的一个实施例中，第一开关单元10211为第一场效应管，第二开关单元10212为第二场效应管。第一储能模块1022可以是第一电容。
可选地，在第二个示例中，第二开关模组1023包括第三开关单元10231和第四开关单元10232；
第三开关单元10231的一端与放大器1011的输出端及第二储能模块1024的第一端连接，第三开关单元10231的另一端与第一储能模块1022的第一端连接；
第四开关单元10232的一端与第二储能模块1024的第二端连接，第四开关单元10232的另一端与第一储能模块1022的第二端连接。
可选地，在本申请的一个实施例中，第三开关单元10231为第三场效应管，第四开关单元10232为第四场效应管。第二储能模块1024可以是第二电容。
可选地，在本申请的一个实施例中，电荷泵电路102还包括电压抬升电路1028，电压抬升电路1028连接在时钟控制电路1027与第四场效应管的栅极之间。
可选地，在第三个示例中，第三开关模组1025连接在电压复制模组1012的输出端与寄生电容1026的第一端之间，寄生电容1026的第二端接地，寄生电容1026的第一端与第一储能模块1022的第一端连接。
可选地，在本申请的一个实施例中，第三开关模组1025可以是第五开关单元，第五开关单元可以是第五场效应管。寄生电容1026是第一电容的一个极板与接地点之间形成的电容。
基于上述图2所示的电路，图3为本申请实施例提供的一种时序控制示意图。图3中，示出了对第一开关单元10211、第二开关单元10212、第三开关单元10231、第四开关单元10232和第五开关单元的控制情况，高电平表示开关闭合，支路导通，低电平表示开关断开，支路断开。结合图3所示，在一个周期的控制中，可以分为三个时段，第一时段中，第一开关单元10211和第二开关单元10212闭合，第三开关单元10231、第四开关单元10232和第五开关单元断开，第一储能模块1022充电至稳压电压；第二时段中，第一开关单元10211和第二开关单元10212断开，第五开关单元闭合，此时，电压复制模组1012输出电压对寄生电容1026充电；第三时段中，第三开关单元10231和第四开关单元10232闭合，第一开关单元10211和第二开关单元10212断开，因为第二时段中，已经对寄生电容1026充电，在第三开关单元10231和第四开关单元10232闭合后，不需要通过放大器1011的输出端的输出电压向寄生电容1026进行充电，第一储能模块1022向第二储能模块1024充电。
需要说明的是，在一个周期中，第一开关单元10211的偏置电压可以先于第二开关单元10212的偏置电压由高电平变为低电平，即第一开关单元10211先于第二开关单元10212断开，第一结合图2，在第一开关单元10211和第二开关单元10212闭合时，通过偏置电压(VA)向第一储能模块1022充电，如果先断开第二开关单元10212，或者同时断开第一开关单元10211和第二开关单元10212，第二开关单元10212还会有一部分电荷转移至第一储能模块1022，也就是会产生沟道注入效应，使得第一储能模块1022上储存的电荷与预期的电 荷量产生误差。因此，在断开第一开关单元10211和第二开关单元10212时，先断开第一开关单元10211，使得第一储能模块1022靠近第一开关单元10211的一端处于悬空状态，再断开第二开关单元10212，第二开关单元10212上的电荷就不会转移到第一储能模块1022，减小了沟道注入效应的影响。因为第一开关单元10211的偏置电压可以先于第二开关单元10212的偏置电压由高电平变为低电平，因此，第一开关单元10211的偏置电压也先于第二开关单元10212的偏置电压由低电平变为高电平。同理，第三开关单元10231和第四开关单元10232也是这样控制，以减少沟道注入效应的影响。
以上描述了一个周期中的开关控制，如此周期性循环控制，就可以使得第二储能模块1024的电压维持在稳压电压附近，第二储能模块1024的第二端作为电荷泵电路102的输出端，与输出反馈电路103的输入端连接，输出反馈电路103根据第二储能模块1024的第二端输出的电压信号对误差放大电路101传输反馈信号(VFB)，对误差放大电路101形成负反馈，对误差放大电路101的输出电压起到稳压的作用。
基于上述图1所示的低压差线性稳压电路的框图，图4为本申请实施例提供的一种输出反馈电路的电路结构与低压差线性稳压电路中的误差放大电路、电荷泵电路框图的整体示意图，重点展示低压差线性稳压电路中输出反馈电路103的具体结构，可选地，在本申请的一个实施例中，如图4所示，输出反馈电路103包括第六场效应管1031、第一电阻1032、第二电阻1033及第四电容1034；
电荷泵电路102的输出端与第六场效应管1031的栅极连接，第六场效应管1031的漏极接入输入电压，第六场效应管1031的源极输出低压差线性稳压电路10的输出电压；
第一电阻1032的第一端与第六场效应管1031的源极连接，第一电阻1032的第二端与第二电阻1033连接，第一电阻1032的第二端连接至放大器1011的反相输入端；
第二电阻1033的第二端接地，第四电容1034的第一端与第六场效应管1031的源极连接，第四电容1034的第二端接地。
基于图4所示的输出反馈电路，因为第六场效应管1031的栅极和源极之间存在电压差，而栅极的电压又受限于电源电压，如果没有电荷泵电路102，则第六场效应管的栅极输入的是误差放大电路101输出的电压，第六场效应管 1031的漏极接入的是电源电压，这就导致第六场效应管1031栅极电压太小而无法使第六场效应管1031导通，在加入电荷泵电路102后，误差放大电路101输出的电压经过电荷泵电路102升压后输出到第六场效应管1031的栅极，就可以使第六场效应管1031导通。
基于上述图1所示的低压差线性稳压电路的框图，图5为本申请实施例提供的一种误差放大电路的结构示意图，对低压差线性稳压电路中误差放大电路101的内部结构进行说明，如图5所示，误差放大电路101包括放大器1011和电压复制模组1012，放大器1011输出的信号与电压复制模组1012输出的信号电压相同。其中，OUT表示放大器1011的输出端，OUT_R表示电压复制模组1012的输出端。
图5中，用字母T表示场效应管，图5所示的电路中，场效应管T也可以是MOS管，本申请对此不作限制，用C表示电容，放大器1011包括11个场效应管T1-T11，以及1个电容C1；
电压复制模组1012包括2个场效应管T12和T13，以及1个电容C2。
在放大器1011中，T1-T4的源极均接入电源电压，T1-T3的栅极接入偏置电压VB1，T4的栅极与T3的漏极相连，T1的漏极分别连接T5和T6的源极，T5的栅极作为放大器1011的反相输入端，T5的栅极可以输入VFB信号(即输出反馈电路103输出的反馈信号)，T6的栅极作为放大器1011的正相输入端，T6的栅极可以输入VREF信号(即外部输入的参考电压)；
T7的漏极与T2的漏极连接，T8的漏极与T3的漏极连接，T7的栅极与T8的栅极连接，并接入偏置电压VB2，T5的漏极与T7的源极连接，T6的漏极与T8的源极连接，T8的漏极与T4的漏极分别连接在C1的两端；
T9的漏极与T7的源极连接，T10的漏极与T8的源极连接，T11的漏极与T4的漏极连接，T9-T11的源极接地，T9-T11的栅极接入偏置电压VB3，其中，T4的漏极即为放大器1011的输出端。
在电压复制模组1012中，T12的源极均接入电源电压，T12的栅极接入偏置电压VB1，T12的漏极与T13的漏极连接，T13的源极接地，T13的栅极与T3的漏极相连，T12的漏极和T13的源极分别连接在C2的两端，其中T12的漏极即为电压复制模组1012的输出端。
需要说明的是，图5中所示的偏置电压VB1、VB2、VB3均由外部电路输入。当然，图5只是示例性说明放大器1011与电压复制模组1012的实现方 式，并不代表本申请局限于此。
基于上述图2所示的低压差线性稳压电路的结构图，图6为本申请实施例提供的一种电压抬升电路的结构图，对电压抬升电路的内部结构进行说明，结合图2所示的电路，电压抬升电路1028的输入端与时钟控制电路1027的输出端相连，电压抬升电路1028的输出端与第四场效应管的栅极相连。图6中，用字母T表示场效应管，用M表示MOS管，用C表示电容。
具体可选的，电压抬升电路1028可以包括两个场效应管T14和T15，3个MOS管M1、M2和M3、1个电容C3以及1个反相器。反相器的输入端与时钟控制电路1027的输出端相连，反相器的输入端输入时钟输入信号CLK IN，反相器的输出端输出时钟反相信号CLK b，反相器的输出端与T14的漏极相连，T14的栅极与M1的栅极相连，且接入电源电压，T14的源极与M1的漏极相连；
M2的源极与M1的源极连接，M2的栅极与T14的栅极相连，M2的漏极接入电源电压，M2的源极和T14的漏极分别连接在C3的两端；
M2的源极与M3的源极相连，M3的栅极可以与反相器的输出端相连，M3的栅极接入时钟反相信号CLK b，M3的漏极与T15的漏极连接，T15的栅极可以与反相器的输出端相连，T15的栅极接入时钟反相信号CLK b，T15de源极接地，其中，M3的漏极即为电压抬升电路1028的输出端，输出时钟输出信号CLK OUT，通过时钟输出信号CLK OUT对第四场效应管进行控制。
结合图2所示的电路结构，因为电荷泵电路102将输出电压抬高，也就是将输出反馈电路103的输入电压抬高了，此时，第四开关单元10232(可以是第四场效应管)的偏置电压也要相应抬高，否则无法令第四开关单元10232导通，因此，通过电压抬升电路1028将时钟偏置电压CLK IN的电压抬高输出钟偏置电压CLK OUT。如图7所示，图7为本申请实施例提供的一种电压抬升电路的信号效果示意图。
本申请实施例的低压差线性稳压电路，由于电荷泵电路提供了更高的电压，即输出反馈电路的输入电压增高，使得N型MOS管的栅极在低压环境下也可以输入更高的电压，使得N型MOS管适用于低压环境，而且电荷泵电路包含的时钟控制电路，可以分别控制第一开关模组、第三开关模组及第二开关模组断开或者闭合，在第一开关模组中的开关单元闭合时，对第一储能模块充电，在第三开关模组中的开关闭合时，对寄生电容充电，在第二开关模组中的开关单元闭合时，第一储能模块对第二储能模块充电，保证了电压稳定，而且 因为在第二开关模组闭合前，可以闭合第三开关模组，对寄生电容单独充电，避免在第二开关模组闭合时，因为对寄生电容充电而导致电压波动较大。
上述产品可执行本申请实施例所提供的方法，具备执行方法相应的功能模块和有益效果。未在本实施例中详尽描述的技术细节，可参见本申请实施例所提供的方法。
在20世纪90年代，对于一个技术的改进可以很明显地区分是硬件上的改进(例如，对二极管、晶体管、开关等电路结构的改进)还是软件上的改进(对于方法流程的改进)。然而，随着技术的发展，当今的很多方法流程的改进已经可以视为硬件电路结构的直接改进。设计人员几乎都通过将改进的方法流程编程到硬件电路中来得到相应的硬件电路结构。因此，不能说一个方法流程的改进就不能用硬件实体模块来实现。例如，可编程逻辑器件(Programmable Logic Device,PLD)(例如现场可编程门阵列(Field Programmable Gate Array，FPGA))就是这样一种集成电路，其逻辑功能由用户对器件编程来确定。由设计人员自行编程来把一个数字系统“集成”在一片PLD上，而不需要请芯片制造厂商来设计和制作专用的集成电路芯片。而且，如今，取代手工地制作集成电路芯片，这种编程也多半改用“逻辑编译器(logic compiler)”软件来实现，它与程序开发撰写时所用的软件编译器相类似，而要编译之前的原始代码也得用特定的编程语言来撰写，此称之为硬件描述语言(Hardware Description Language，HDL)，而HDL也并非仅有一种，而是有许多种，如ABEL(Advanced Boolean Expression Language)、AHDL(Altera Hardware Description Language)、Confluence、CUPL(Cornell University Programming Language)、HDCal、JHDL(Java Hardware Description Language)、Lava、Lola、MyHDL、PALASM、RHDL(Ruby Hardware Description Language)等，目前最普遍使用的是VHDL(Very-High-Speed Integrated Circuit Hardware Description Language)与Verilog。本领域技术人员也应该清楚，只需要将方法流程用上述几种硬件描述语言稍作逻辑编程并编程到集成电路中，就可以很容易得到实现该逻辑方法流程的硬件电路。
控制器可以按任何适当的方式实现，例如，控制器可以采取例如微处理器或处理器以及存储可由该(微)处理器执行的计算机可读程序代码(例如软件或固件)的计算机可读介质、逻辑门、开关、专用集成电路(Application Specific Integrated Circuit，ASIC)、可编程逻辑控制器和嵌入微控制器的形式，控制器 的例子包括但不限于以下微控制器：ARC 625D、Atmel AT91SAM、Microchip PIC18F26K20以及Silicone Labs C8051F320，存储器控制器还可以被实现为存储器的控制逻辑的一部分。本领域技术人员也知道，除了以纯计算机可读程序代码方式实现控制器以外，完全可以通过将方法步骤进行逻辑编程来使得控制器以逻辑门、开关、专用集成电路、可编程逻辑控制器和嵌入微控制器等的形式来实现相同功能。因此这种控制器可以被认为是一种硬件部件，而对其内包括的用于实现各种功能的装置也可以视为硬件部件内的结构。或者甚至，可以将用于实现各种功能的装置视为既可以是实现方法的软件模块又可以是硬件部件内的结构。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (11)

  1. 一种低压差线性稳压电路，其特征在于，包括：误差放大电路、电荷泵电路及输出反馈电路；
    所述误差放大电路的输出端与所述电荷泵电路的输入端连接；
    所述电荷泵电路包括第一开关模组、第一储能模块、第三开关模组、寄生电容、第二开关模组、第二储能模块及时钟控制电路，其中，所述第一储能模块中的元件与接地点之间形成所述寄生电容；
    所述第一开关模组与所述第一储能模块连接形成第一充电支路；所述第三开关模组与所述第一储能模块的一端连接，所述第一储能模与所述寄生电容形成第三充电支路；所述第一储能模块与所述第二开关模组及第二储能模块连接形成第二充电支路；
    所述时钟控制电路分别与所述第一开关模组、所述第三开关模组及所述第二开关模组连接，用于控制所述第一开关模组、所述第三开关模组及所述第二开关模组的导通与关断；
    所述电荷泵电路的输出端与所述输出反馈电路连接，所述输出反馈电路与所述误差放大电路连接。
  2. 根据权利要求1所述的低压差线性稳压电路，其特征在于，所述误差放大电路包括放大器和电压复制模组，所述电压复制模组输出与所述放大器相同的输出电压；
    所述放大器的反相输入端与所述输出反馈电路连接，所述放大器的正向输入端输入基准电压，所述放大器的输出端与所述第二充电支路连接；
    所述电压复制模组的输出端与所述第三充电支路连接。
  3. 根据权利要求1所述的低压差线性稳压电路，其特征在于，所述第一开关模组包括第一开关单元和第二开关单元；所述第一开关单元的一端接地，另一端与所述第一储能模块的第一端连接；
    所述第二开关单元的一端与所述第一储能模块的第二端连接，所述第二开关单元的另一端接入稳压电压。
  4. 根据权利要求3所述的低压差线性稳压电路，其特征在于，所述第一开关单元为第一场效应管，所述第二开关单元为第二场效应管。
  5. 根据权利要求2所述的低压差线性稳压电路，其特征在于，所述第二开关模组包括第三开关单元和第四开关单元；
    所述第三开关单元的一端与所述放大器的输出端及所述第二储能模块的第 一端连接，所述第三开关单元的另一端与所述第一储能模块的第一端连接；
    所述第四开关单元的一端与所述第二储能模块的第二端连接，所述第四开关单元的另一端与所述第一储能模块的第二端连接。
  6. 根据权利要求5所述的低压差线性稳压电路，其特征在于，所述第三开关单元为第三场效应管，所述第四开关单元为第四场效应管。
  7. 根据权利要求6所述的低压差线性稳压电路，其特征在于，所述电荷泵电路还包括电压抬升电路，所述电压抬升电路连接在所述时钟控制电路与所述第四场效应管的栅极之间。
  8. 根据权利要求2所述的低压差线性稳压电路，其特征在于，所述第三开关模组连接在所述电压复制模组的输出端与所述寄生电容的第一端之间，所述寄生电容的第二端接地，所述寄生电容的第一端与所述第一储能模块的第一端连接。
  9. 根据权利要求8所述的低压差线性稳压电路，其特征在于，所述第三开关模组为第五场效应管。
  10. 根据权利要求1-9任一项所述的低压差线性稳压电路，其特征在于，
    所述第一储能模块为第一电容，所述第二储能模块为第二电容，所述寄生电容为第三电容，其中，所述第一电容的一个极板与接地点之间形成第三电容。
  11. 根据权利要求2所述的低压差线性稳压电路，其特征在于，所述输出反馈电路包括第六场效应管、第一电阻、第二电阻及第四电容；
    所述电荷泵电路的输出端与所述第六场效应管的栅极连接，所述第六场效应管的漏极接入输入电压，所述第六场效应管的源极输出所述低压差线性稳压电路的输出电压；
    所述第一电阻的第一端与所述第六场效应管的源极连接，所述第一电阻的第二端与所述第二电阻连接，所述第一电阻的第二端连接至所述放大器的反相输入端；
    所述第二电阻的第二端接地，所述第四电容的第一端与所述第六场效应管的源极连接，所述第四电容的第二端接地。
PCT/CN2020/083370 2020-04-03 2020-04-03 低压差线性稳压电路 WO2021196233A1 (zh)

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EP20922475.7A EP3923111A4 (en) 2020-04-03 2020-04-03 LOW-LOSS LINEAR VOLTAGE STABILIZATION CIRCUIT
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CN115469703B (zh) * 2022-10-27 2024-05-03 北京智芯微电子科技有限公司 线性稳压电路、工作方法及电子设备

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