WO2023123545A1 - 显示装置及显示装置的制备方法 - Google Patents

显示装置及显示装置的制备方法 Download PDF

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Publication number
WO2023123545A1
WO2023123545A1 PCT/CN2022/070933 CN2022070933W WO2023123545A1 WO 2023123545 A1 WO2023123545 A1 WO 2023123545A1 CN 2022070933 W CN2022070933 W CN 2022070933W WO 2023123545 A1 WO2023123545 A1 WO 2023123545A1
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Prior art keywords
source
drain
substrate
layer
gate
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PCT/CN2022/070933
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English (en)
French (fr)
Inventor
罗传宝
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TCL China Star Optoelectronics Technology Co Ltd
Huizhou China Star Optoelectronics Display Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
Huizhou China Star Optoelectronics Display Co Ltd
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Priority to US17/597,941 priority Critical patent/US12527087B2/en
Publication of WO2023123545A1 publication Critical patent/WO2023123545A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate

Definitions

  • the present application relates to the field of display technology, in particular to a display device and a method for preparing the display device.
  • the switching thin film transistor (Thin Film Transistor, TFT) and the driving TFT in the pixel circuit are TFT devices of the same structure type, such as bottom-gate TFT or top-gate TFT.
  • the bottom-gate TFT and the top-gate TFT have their own advantages, specifically, from the perspective of reducing the size of the TFT to improve panel resolution, the size of the bottom-gate TFT is smaller than that of the top-gate TFT, and from the perspective of current From the viewpoint of device stability required for driving, the stability of the top-gate TFT is better than that of the bottom-gate TFT.
  • the stability requirements for the switching TFT and the driving TFT are not the same.
  • the driving TFT has high stability, so the switching TFT and driving TFT of the same structure type cannot meet the requirements for resolution and TFT device stability at the same time. Therefore, how to improve the stability of the TFT device while improving the resolution of the panel has become an urgent technical problem to be solved.
  • Embodiments of the present application provide a display device and a manufacturing method of the display device, which can improve the stability of a TFT device while improving the resolution of a panel.
  • An embodiment of the present application provides a display device, which includes:
  • a switch thin film transistor is arranged on one side of the substrate, the switch thin film transistor includes a first gate, a first active layer, a first source and a first drain, and the first gate is arranged on the On the substrate, the first active layer is located on the side of the first gate away from the substrate, and the first source and the first drain are arranged on the same layer of the first active layer. a side of the source layer away from the substrate; and
  • the driving thin film transistor is arranged on one side of the substrate, the driving thin film transistor is connected to the switching thin film transistor, and the driving thin film transistor includes a second source, a second drain, a second active layer, and a first Two gates, the second source and the second drain are arranged on the same layer on the substrate, and the second active layer is located away from the second source and the second drain from the substrate The second gate is located on the side of the second active layer away from the substrate.
  • the first gate, the second source and the second drain are arranged in the same layer.
  • the second active layer includes a channel
  • the orthographic projection of the second source or the second drain on the plane where the channel is located is at least partially Cover the trench.
  • the second active layer further includes a source contact portion and a drain contact portion located on opposite sides of the channel, the second source and the The source contact portion is connected and extends from the source contact portion toward the direction of the drain contact portion, and the orthographic projection of the channel on the plane where the substrate is located is located between the second source electrode and the substrate In the orthographic projection of the plane where the bottom is located, the second drain is connected to the drain contact portion.
  • the display device further includes a gate insulating layer, and the gate insulating layer is arranged between the channel and the second gate.
  • the two sources face to the direction of the second drain, and the width of the second gate is smaller than the width of the gate insulating layer.
  • the first source, the first drain and the second gate are located in the same metal layer.
  • the display device further includes a connection electrode, the connection electrode is located on a side of the second gate away from the substrate, and the second gate passes through the The connecting electrode is connected to the first drain.
  • the first active layer and the second active layer are arranged in the same layer, and the material of the first active layer and the material of the second active layer
  • the materials all include metal oxide semiconductors.
  • the orthographic projection of the second source on the plane of the substrate is located outside the orthographic projection of the channel on the plane of the substrate, and the display
  • the device further includes a light-shielding layer, the light-shielding layer is disposed on a side of the substrate close to the second active layer, and the orthographic projection of the light-shielding layer on the plane where the substrate is located covers the channel.
  • the embodiment of the present application also provides a display device, which includes:
  • a switch thin film transistor is arranged on one side of the substrate, the switch thin film transistor includes a first gate, a first active layer, a first source and a first drain, and the first gate is arranged on the On the substrate, the first active layer is located on the side of the first gate away from the substrate, and the first source and the first drain are arranged on the same layer of the first active layer. a side of the source layer away from the substrate; and
  • the driving thin film transistor is arranged on one side of the substrate, the driving thin film transistor is connected to the switching thin film transistor, and the driving thin film transistor includes a second source, a second drain, a second active layer, and a first Two gates, the second source and the second drain are arranged on the same layer on the substrate, and the second active layer is located away from the second source and the second drain from the substrate One side of the bottom, the second gate is located on the side of the second active layer away from the substrate;
  • first source, the first drain and the second gate are located in the same metal layer, and the first gate, the second source and the second drain are in the same layer set up.
  • the second active layer includes a channel
  • the orthographic projection of the second source or the second drain on the plane where the channel is located is at least partially Cover the trench.
  • the second active layer further includes a source contact portion and a drain contact portion located on opposite sides of the channel, the second source and the The source contact portion is connected and extends from the source contact portion toward the direction of the drain contact portion, and the orthographic projection of the channel on the plane where the substrate is located is located between the second source electrode and the substrate In the orthographic projection of the plane where the bottom is located, the second drain is connected to the drain contact portion.
  • the display device further includes a gate insulating layer, and the gate insulating layer is arranged between the channel and the second gate.
  • the two sources face to the direction of the second drain, and the width of the second gate is smaller than the width of the gate insulating layer.
  • the display device further includes a connection electrode, the connection electrode is located on a side of the second gate away from the substrate, and the second gate passes through the The connecting electrode is connected to the first drain.
  • the first active layer and the second active layer are arranged in the same layer, and the material of the first active layer and the material of the second active layer
  • the materials all include metal oxide semiconductors.
  • the orthographic projection of the second source on the plane of the substrate is located outside the orthographic projection of the channel on the plane of the substrate, and the display
  • the device further includes a light-shielding layer, the light-shielding layer is disposed on a side of the substrate close to the second active layer, and the orthographic projection of the light-shielding layer on the plane where the substrate is located covers the channel.
  • the embodiment of the present application also provides a method for preparing a display device as described in the foregoing embodiments, which includes the following steps:
  • first active layer on the first gate, and forming a second active layer on the second source and the second drain;
  • the first source and the first drain are formed on the first active layer, and the second gate is formed on the second active layer.
  • the step of forming a second active layer on the second source and the second drain further include:
  • a gate insulating layer is formed on the second active layer, the orthographic projection of the gate insulating layer on the plane where the substrate is located and the orthographic projection of the second source on the plane where the substrate is located are at least partly overlapping.
  • the first source and the first drain are formed on the first active layer, and the first drain is formed on the second active layer.
  • the step of the second grid includes:
  • the second metal layer is patterned to form the first source, the first drain and the second gate.
  • the region of the second active layer covered by the gate insulating layer is formed as a trench
  • the part of the second active layer not covered by the gate insulating layer is conductorized to form a source contact and a drain contact, the source contact is in contact with the second source, the A drain contact is in contact with the second drain.
  • the switching thin film transistor since the first gate of the switching thin film transistor is located below the first active layer, that is, the switching thin film transistor has a bottom gate structure; further, the second gate of the driving thin film transistor Located above the second active layer, the second source and the second drain are located below the second active layer, that is, the driving thin film transistor has a novel top-gate structure. Therefore, in this application, while setting the switching thin film transistor as a bottom-gate structure, the driving thin film transistor is set as a new top-gate structure, which can improve the stability of the TFT device while improving the resolution of the panel, so as to meet the high-resolution Rate and high stability show the design requirements of the product.
  • FIG. 1 is a schematic structural diagram of a display device provided by a first embodiment of the present application.
  • FIGS. 2A to 2H are schematic flow charts of the manufacturing method of the display device provided in the first embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a display device provided by a second embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a pixel driving circuit of a display device provided by an example of the present application.
  • the present application provides a display device and a manufacturing method of the display device. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • the present application provides a display device, which includes a substrate, a switching thin film transistor, and a driving thin film transistor.
  • the switch thin film transistor is arranged on one side of the substrate, the switch thin film transistor includes a first gate, a first active layer, a first source and a first drain, the first gate is arranged on the substrate, and the first active layer layer is located on the side of the first gate away from the substrate, the first source and the first drain are arranged in the same layer on the side of the first active layer away from the substrate;
  • the driving thin film transistor is arranged on the side of the substrate, and the driving The thin film transistor is connected to the switching thin film transistor, and the driving thin film transistor includes a second source, a second drain, a second active layer and a second gate, and the second source and the second drain are arranged on the same layer on the substrate,
  • the second active layer is located on a side of the second source and the second drain away from the substrate, and the second gate is located on a side of the second active layer away from the
  • the switching thin film transistor since the first gate of the switching thin film transistor is located below the first active layer, that is, the switching thin film transistor has a bottom gate structure; further, the first gate of the driving thin film transistor The two gates are located above the second active layer, and the second source and the second drain are located below the second active layer, that is, the driving thin film transistor has a novel top-gate structure. Therefore, in this application, while setting the switching thin film transistor as a bottom-gate structure, the driving thin film transistor is set as a new top-gate structure, which can improve the stability of the TFT device while improving the resolution of the panel, so as to meet the high-resolution Rate and high stability show the design requirements of the product.
  • the first embodiment of the present application provides a display device 100 .
  • the display device 100 includes a substrate 10 , a switching thin film transistor 20 and a driving thin film transistor 30 .
  • the substrate 10 may be a hard substrate, such as a glass substrate.
  • the substrate 10 can also be a flexible substrate, such as a polyimide substrate.
  • the switching thin film transistor 20 is disposed on one side of the substrate 10 .
  • the switching thin film transistor 20 has a bottom gate structure.
  • the switch TFT 20 includes a first gate 21 , a first active layer 22 , a first source 23 and a first drain 24 .
  • the first gate 21 is disposed on the substrate 10 .
  • the first gate 21 may be a single-layer structure, a double-layer structure or a multi-layer structure.
  • the material of the first gate 21 may include one or more of copper, aluminum, molybdenum and titanium.
  • the double-layer structure may include a bottom layer made of molybdenum as a conductive material and a top layer made of copper as a conductive material.
  • the first active layer 22 is located on a side of the first gate 21 away from the substrate 10 .
  • the material of the first active layer 22 includes a metal oxide semiconductor, such as one or more of IGZO, IGTO, IZTO, IGZTO, ITO and IZO.
  • the orthographic projection of the first active layer 22 on the plane of the substrate 10 is located within the orthographic projection of the first grid 21 on the plane of the substrate 10. The light below the bottom 10 prevents the first active layer 22 from being affected by the light and degrades the performance of the switching TFT.
  • the display device 100 further includes a buffer layer 40 disposed between the first gate 21 and the first active layer 22 .
  • the buffer layer 40 may be a single-layer structure, a double-layer structure or a multi-layer structure.
  • the material of the buffer layer 40 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • the double-layer structure may include a bottom layer made of silicon oxide as an insulating material and a top layer made of silicon nitride as an insulating material.
  • the first source 23 and the first drain 24 are arranged on the same layer on the side of the first active layer 22 away from the substrate 10 .
  • the first source electrode 23 and the first drain electrode 24 may have a single-layer structure, a double-layer structure or a multi-layer structure.
  • the material of the first source 23 is the same as that of the first drain 24 , and both may include one or more of copper, aluminum, molybdenum and titanium.
  • the double-layer structure may include a bottom layer made of molybdenum as a conductive material and a top layer made of copper as a conductive material.
  • the orthographic projection of the first gate 21 on the plane of the substrate 10 respectively overlaps with the orthographic projections of the first source 23 and the first drain 24 on the plane of the substrate 10 respectively.
  • a gate electric field is formed between the gate 21 and the first source 23 and the first drain 24 respectively, so as to control the movement of electrons in the region where the first source 23 and the first drain 24 are located.
  • the driving thin film transistor 30 is disposed on one side of the substrate 10 .
  • the driving thin film transistor 30 has a top-gate structure.
  • the driving thin film transistor 30 is connected with the switching thin film transistor 20 .
  • the driving thin film transistor 30 includes a second source 31 , a second drain 32 , a second active layer 33 and a second gate 34 .
  • the second source 31 and the second drain 32 are disposed on the substrate 10 in the same layer.
  • the second source electrode 31 and the second drain electrode 32 may have a single-layer structure, a double-layer structure or a multi-layer structure.
  • the material of the second source electrode 31 is the same as that of the second drain electrode 32 , and both may include one or more of copper, aluminum, molybdenum and titanium.
  • the double-layer structure may include a bottom layer made of molybdenum as a conductive material and a top layer made of copper as a conductive material.
  • the second active layer 33 is located on a side of the second source 31 and the second drain 32 away from the substrate 10 .
  • the material of the second active layer 33 includes a metal oxide semiconductor, such as one or more of IGZO, IGTO, IZTO, IGZTO, ITO and IZO.
  • the second active layer 33 is set in the same layer as the first active layer 22, and both materials are the same, which can improve the film formation of the first active layer 22 and the second active layer 33 Uniformity to meet the application requirements of large-size display products.
  • the second active layer 33 includes a channel 331 and a source contact portion 332 and a drain contact portion 333 located on opposite sides of the channel 331 .
  • the second source electrode 31 is connected to the source contact portion 332 through the first via hole 41 in the buffer layer 40 .
  • the second drain 32 is connected to the drain contact portion 333 through the second via hole 42 in the buffer layer 40 .
  • the material of the source contact portion 332 and the material of the drain contact portion 333 are conductors.
  • the orthographic projection of the second source 31 or the second drain 32 on the plane where the channel 331 is located at least partially covers the channel 331 .
  • the orthographic projection of the second source 31 on the plane where the channel 331 is located at least partially covers the channel 331 . Since the channel 331 is arranged opposite to the second gate 34, when the second source 31 and the channel 331 have an overlapping area, correspondingly, the second source 31 and the second gate 34 also have an overlapping area; because The second source 31 is usually at a low potential such as zero potential, and the second gate 34 is usually at a positive or negative potential. The above settings enable the electric field formed between the second source 31 and the second gate 34 to be shielded to the gate.
  • the polar insulating layer 35 can avoid affecting the driving performance of the driving thin film transistor 30 .
  • the second source 31 extends from the source contact portion 332 toward the direction of the drain contact portion 333, and the orthographic projection of the channel 331 on the plane of the substrate 10 is located at the front of the second source 31 on the plane of the substrate 10. inside the projection.
  • the above setting enables the second source 31 to shield the ambient light from under the substrate 10, avoiding the influence of light on the channel 331, thereby reducing the light-generated leakage current of the driving thin film transistor 30, so as to further improve the performance of the driving thin film transistor 30. stability.
  • the second source 31 and the second drain 32 in the driving thin film transistor 30 are arranged under the second active layer 33, and the second source 31 covers the area where the channel 331 is located, so that While improving the stability of the driving thin film transistor 30, the second source 31 can be used to shield the influence of ambient light on the channel 331, thereby eliminating the need for the setting of the light-shielding layer in the traditional structure, thereby helping to save the process of the display device 100 manufacturing cost.
  • the second gate 34 is located on a side of the second active layer 33 away from the substrate 10 .
  • the second gate 34 may be a single-layer structure, a double-layer structure or a multi-layer structure.
  • the material of the second gate 34 may include one or more of copper, aluminum, molybdenum and titanium.
  • the double-layer structure may include a bottom layer made of molybdenum as a conductive material and a top layer made of copper as a conductive material.
  • a gate insulating layer 35 is disposed between the channel 331 and the second gate 34 . From the second source 31 toward the second drain 32 , the width of the second gate 34 is smaller than the width of the gate insulating layer 35 .
  • the gate insulating layer 35 may be a single-layer structure, a double-layer structure or a multi-layer structure.
  • the material of the gate insulating layer 35 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • the double-layer structure may include a bottom layer made of silicon oxide as an insulating material and a top layer made of silicon nitride as an insulating material.
  • the actual width of the channel 331 will be smaller than the width of the gate insulating layer 35 due to the effect of thermal diffusion. Therefore, in this embodiment, by setting the width of the second gate 34 to be smaller than the width of the gate insulating layer 35 , it can ensure that the width of the second gate 34 in the driving thin film transistor 30 is consistent with the width of the channel 331 .
  • the present application sets the switching thin film transistor 20 as a bottom gate structure, and sets the driving thin film transistor 30 as a new top gate structure, which can improve the stability of the TFT device while improving the resolution of the panel, so as to satisfy High resolution and high stability display product design requirements.
  • the first gate 21 , the second source 31 and the second drain 32 are arranged in the same layer. That is, the first gate 21, the second source 31 and the second drain 32 are located in the same metal layer, in other words, the first gate 21, the second source 31 and the second drain 32 use the same light
  • the cover is prepared.
  • first source 23 , the first drain 24 and the second gate 34 are located in the same metal layer. That is, the first source 23 , the first drain 24 and the second gate 34 are prepared by using the same photomask.
  • the display device 100 further includes a passivation layer 50 and a connection electrode 60 .
  • the passivation layer 50 covers the switching thin film transistor 20 and the driving thin film transistor 30 .
  • the connecting electrode 60 is located on the side of the passivation layer 50 away from the substrate 10 , and is used to realize the electrical connection between the switching thin film transistor 20 and the driving thin film transistor 30 .
  • the passivation layer 50 is disposed on a side of the first source 23 , the first drain 24 and the second gate 34 away from the substrate 10 .
  • a first connection hole 51 and a second connection hole 52 are opened in the passivation layer 50 .
  • the first connection hole 51 exposes the first drain 24 .
  • the second connection hole 52 exposes the second gate 34 .
  • the connection electrode 60 covers the first connection hole 51 and the second connection hole 52 .
  • the second gate 34 is connected to the first drain 24 through the connection electrode 60 .
  • the passivation layer 50 may be a single-layer structure, a double-layer structure or a multi-layer structure.
  • the material of the passivation layer 50 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • the double-layer structure may include a bottom layer made of silicon oxide as an insulating material and a top layer made of silicon nitride as an insulating material.
  • the material of the connection electrode 60 may include ITO.
  • the display device 100 provided in this embodiment can improve the stability of the TFT device while improving the resolution of the panel by setting the switching thin film transistor 20 as a bottom gate structure and the driving thin film transistor 30 as a new top gate structure. To meet the design requirements of high-resolution and high-stability display products.
  • the first source 23 and the first drain 24 of the switching thin film transistor 20 are located in the same metal layer as the second gate 34 of the driving thin film transistor 30, the first gate of the switching thin film transistor 20 21 is located in the same metal layer as the second source 31 and the second drain 32 in the driving thin film transistor 30, and because there is an overlapping area between the second source 31 and the channel 331 in the driving thin film transistor 30, it can Acting as a light-shielding layer in the traditional structure to avoid the influence of light on the channel 331, since only two metal layers need to be provided in the display device 100 provided in this embodiment, the manufacturing process of the display device 100 is greatly simplified, thereby saving display Process manufacturing cost of the device 100 .
  • the present application also provides a method for manufacturing a display device 100, which includes the following steps:
  • a first metal layer (not shown in the figure) is formed on the substrate 10 by a physical vapor deposition process; then, patterning is performed on the first metal layer , to form the first gate 21 , the second source 31 and the second drain 32 .
  • the patterning process includes processes such as exposure, development, and etching, and the relevant technologies are all existing technologies, and will not be repeated here.
  • B3 Form a buffer layer 40 on the first gate 21 , the second source 31 and the second drain 32 , as shown in FIG. 2C .
  • the buffer layer 40 is formed by chemical vapor deposition, and annealed at a high temperature of 300°C-400°C for 2h-3h; then, the buffer layer 40 is patterning process to form the first via hole 41 exposing the second source electrode 31 and the second via hole 42 exposing the second drain electrode 32 .
  • At least one of IGZO, IGTO, IZTO, and IGZTO is used as a material to form an active base layer (not shown in the figure) by a deposition process; then, the active base layer is patterned to form a layer corresponding to the first The first active layer 22 of the gate 21 and the second active layer 33 corresponding to the second source 31 and the second drain 32 .
  • the gate insulating layer 35 is disposed above the second source electrode 31 .
  • the orthographic projection of the gate insulating layer 35 on the plane of the substrate 10 at least partially overlaps the orthographic projection of the second source 31 on the plane of the substrate 10 .
  • the orthographic projection of the gate insulating layer 35 on the plane of the substrate 10 is located within the orthographic projection of the second source 31 on the plane of the substrate 10 .
  • a second metal layer (not shown in the figure) is formed on the gate insulating layer 35 by a physical vapor deposition process, and the second metal layer covers the first active The portion of the layer 22 and the second active layer 33 not covered by the gate insulating layer 35 .
  • the area of the second active layer 33 covered by the gate insulating layer 35 is formed as a channel 331, and the area of the second active layer 33 not covered by the gate insulating layer 35 is conductorized.
  • the orthographic projection of the channel 331 on the plane of the substrate 10 is located within the orthographic projection of the second source 31 on the plane of the substrate 10 .
  • the conductorized portion of the second active layer 33 includes a source contact portion 332 in contact with the second source electrode 31 , and a drain contact portion 333 in contact with the second drain electrode 32 .
  • the second metal layer is patterned to form the first source 23 , the first drain 24 and the second gate 34 .
  • the first gate 21, the first active layer 22, the first source 23 and the first drain 24 constitute the switching thin film transistor 20; the second source 31, the second drain 32, the second The active layer 33 and the second gate 34 constitute the driving thin film transistor 30 .
  • the passivation layer 50 includes a first connection hole 51 and a second connection hole 52 , as shown in FIG. 2G .
  • the passivation layer 50 is patterned to form the exposed first drain 24 The first connection hole 51 and the second connection hole 52 exposing the second gate 34 .
  • connection electrode 60 on the passivation layer 50, as shown in FIG. 2H.
  • connection electrode 60 is formed by using a physical vapor deposition process and a photolithography process in sequence, and the connection electrode 60 covers the first connection hole 51 and the second connection hole 52 .
  • the second gate 34 is connected to the first drain 24 through the connection electrode 60 to implement signal transmission between the switching thin film transistor 20 and the driving thin film transistor 30 .
  • the second embodiment of the present application provides a display device 200 .
  • the display device 200 provided by the second embodiment of the present application is different from the first embodiment in that: the orthographic projection of the second source 31 on the plane of the substrate 10 is located at the position of the orthographic projection of the channel 331 on the plane of the substrate 10
  • the display device 200 further includes an inorganic insulating layer 70 and a light shielding layer 80, the light shielding layer 80 is disposed on the substrate 10, the inorganic insulating layer 70 is disposed on the side of the light shielding layer 80 close to the second source 31, the light shielding layer 80 is placed on the groove
  • the orthographic projection of the plane where the track 331 lies covers the channel 331 .
  • the light-shielding layer 80 is used to shield the ambient light from under the substrate 10 to avoid the influence of light on the channel 331, thereby reducing the photo-generated leakage current of the driving thin film transistor 30 to further improve the performance of the driving thin film transistor 30. stability.
  • the material of the inorganic insulating layer 70 may include one or more of silicon oxide, silicon nitride and silicon oxynitride; the material of the light shielding layer 80 may include one or more of copper, aluminum, molybdenum and titanium.
  • the present application does not specifically limit the material of the inorganic insulating layer 70 and the material of the light-shielding layer 80 .
  • the display device may be a current-driven display device such as an OLED display device, a Mini LED display device, or a Micro LED display device.
  • the display device can be used in a backlight module in a liquid crystal display device, and can also directly display.
  • the OLED display device includes a pixel driving circuit.
  • the pixel driving circuit can be 2T1C pixel driving circuit, 3T1C pixel driving circuit, 3T2C pixel driving circuit, 4T1C pixel driving circuit, 4T2C pixel driving circuit, 5T1C pixel driving circuit, 5T2C pixel driving circuit, 6T1C pixel driving circuit, 6T2C pixel driving circuit, A pixel driving circuit, a 7T1C pixel driving circuit or a 7T2C pixel driving circuit.
  • the pixel driving circuit is a 2T1C pixel driving circuit.
  • the 2T1C pixel driving circuit may include a first thin film transistor TFT1 , a second thin film transistor TFT2 and a capacitor C.
  • the first thin film transistor TFT1 may be an N-type transistor used as a switching thin film transistor
  • the second thin film transistor TFT2 may be a P-type transistor used as a driving thin film transistor
  • the capacitor C may be a storage capacitor.
  • the gate of the first thin film transistor TFT1 is connected to the scan signal Scan, the source is connected to the data signal Data, and the drain is electrically connected to the gate of the second thin film transistor TFT2 and one end of the capacitor C; the second thin film transistor TFT2
  • the source of the organic light-emitting diode LED is electrically connected to the positive voltage VDD, and the drain is electrically connected to the anode of the organic light-emitting diode LED; the cathode of the organic light-emitting diode LED is connected to the low-voltage power supply VSS.
  • the scan signal Scan controls the conduction of the first thin film transistor TFT1
  • the data signal Data enters the gate of the second thin film transistor TFT2 and the capacitor C through the first thin film transistor TFT1, and then the first thin film transistor TFT1 is turned off, Due to the storage function of the capacitor C, the gate voltage of the second thin film transistor TFT2 can continue to maintain the data signal voltage, so that the second thin film transistor TFT2 is in the conduction state, and the driving current passes through the second thin film transistor TFT2 to drive the organic light emitting diode LED to emit light. .
  • the first thin film transistor TFT1 is the switching thin film transistor 20 described in the foregoing embodiment
  • the second thin film transistor TFT2 is the driving thin film transistor 30 described in the foregoing embodiment
  • the specific components of the switching thin film transistor 20 and the driving thin film transistor 30 are For the structure, reference may be made to the descriptions of the foregoing embodiments, and details are not repeated here.

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Abstract

一种显示装置(100)及其制备方法。显示装置(100)包括衬底(10)；开关薄膜晶体管(20)，其包括设置在衬底(10)上的第一栅极(21)、第一有源层(22)、第一源极(23)以及第一漏极(24)，第一源极(23)和第一漏极(24)设置于第一有源层(22)远离衬底(10)的一侧；以及驱动薄膜晶体管(30)，其包括设置在衬底(10)上的第二源极(31)、第二漏极(32)、第二有源层(33)以及第二栅极(34)，第二有源层(33)位于第二源极(31)和第二漏极(32)远离衬底(10)的一侧。

Description

显示装置及显示装置的制备方法 技术领域
本申请涉及显示技术领域，具体涉及一种显示装置及显示装置的制备方法。
 背景技术
目前，对于大尺寸电流型显示装置如有机发光二极管（Organic Light-Emitting Diode, OLED）显示装置、迷你型发光二极管（Mini Light-Emitting Diode, Mini LED）显示装置或微型发光二极管（Micro Light-Emitting Diode, Micro LED）显示装置，其像素电路中的开关薄膜晶体管（Thin Film Transistor, TFT）和驱动TFT均为相同结构类型的TFT器件，如均为底栅型TFT或顶栅型TFT。
 技术问题
由于底栅型TFT和顶栅型TFT具有各自的优势，具体的，从减小TFT尺寸来提升面板分辨率的角度来看，底栅型TFT的尺寸小于顶栅型TFT的尺寸，而从电流驱动所需器件稳定性的角度来看，顶栅型TFT的稳定性优于底栅型TFT的稳定性。其中，在像素电路中，对开关TFT和驱动TFT的稳定性要求并不相同，比如，开关TFT负责写入电压，因而对开关TFT的稳定性要求较低，驱动TFT负责驱动LED发光，则要求驱动TFT具有较高的稳定性，故而相同结构类型的开关TFT和驱动TFT已无法同时满足对分辨率和TFT器件稳定性的要求。因此，如何在提升面板分辨率的同时提升TFT器件的稳定性，成为亟待解决的技术问题。
 技术解决方案
本申请实施例提供一种显示装置及显示装置的制备方法，在提高面板分辨率的同时，能够提升TFT器件的稳定性。
本申请实施例提供一种显示装置，其包括：
衬底；
开关薄膜晶体管，设置在所述衬底的一侧，所述开关薄膜晶体管包括第一栅极、第一有源层、第一源极以及第一漏极，所述第一栅极设置在所述衬底上，所述第一有源层位于所述第一栅极远离所述衬底的一侧，所述第一源极和所述第一漏极同层设置于所述第一有源层远离所述衬底的一侧；以及
驱动薄膜晶体管，设置在所述衬底的一侧，所述驱动薄膜晶体管与所述开关薄膜晶体管相连，所述驱动薄膜晶体管包括第二源极、第二漏极、第二有源层以及第二栅极，所述第二源极和所述第二漏极同层设置于所述衬底上，所述第二有源层位于所述第二源极和第二漏极远离所述衬底的一侧，所述第二栅极位于所述第二有源层远离所述衬底的一侧。
可选的，在本申请的一些实施例中，所述第一栅极、所述第二源极以及所述第二漏极同层设置。
可选的，在本申请的一些实施例中，所述第二有源层包括沟道，所述第二源极或所述第二漏极于所述沟道所在平面上的正投影至少部分覆盖所述沟道。
可选的，在本申请的一些实施例中，所述第二有源层还包括位于所述沟道相对两侧的源极接触部和漏极接触部，所述第二源极与所述源极接触部相连，并自所述源极接触部朝向所述漏极接触部的方向延伸，所述沟道于所述衬底所在平面的正投影位于所述第二源极于所述衬底所在平面的正投影内，所述第二漏极与所述漏极接触部相连。
可选的，在本申请的一些实施例中，所述显示装置还包括栅极绝缘层，所述栅极绝缘层设置在所述沟道和所述第二栅极之间，自所述第二源极朝向所述第二漏极的方向，所述第二栅极的宽度小于所述栅极绝缘层的宽度。
可选的，在本申请的一些实施例中，所述第一源极、所述第一漏极以及所述第二栅极位于同一金属层中。
可选的，在本申请的一些实施例中，所述显示装置还包括连接电极，所述连接电极位于所述第二栅极远离所述衬底的一侧，所述第二栅极通过所述连接电极与所述第一漏极相连。
可选的，在本申请的一些实施例中，所述第一有源层和所述第二有源层同层设置，所述第一有源层的材料和所述第二有源层的材料均包括金属氧化物半导体。
可选的，在本申请的一些实施例中，所述第二源极于所述衬底所在平面的正投影位于所述沟道于所述衬底所在平面的正投影的外侧，所述显示装置还包括遮光层，所述遮光层设置在所述衬底靠近所述第二有源层的一侧，所述遮光层于所述衬底所在平面的正投影覆盖所述沟道。
本申请实施例还提供一种显示装置，其包括：
衬底；
开关薄膜晶体管，设置在所述衬底的一侧，所述开关薄膜晶体管包括第一栅极、第一有源层、第一源极以及第一漏极，所述第一栅极设置在所述衬底上，所述第一有源层位于所述第一栅极远离所述衬底的一侧，所述第一源极和所述第一漏极同层设置于所述第一有源层远离所述衬底的一侧；以及
驱动薄膜晶体管，设置在所述衬底的一侧，所述驱动薄膜晶体管与所述开关薄膜晶体管相连，所述驱动薄膜晶体管包括第二源极、第二漏极、第二有源层以及第二栅极，所述第二源极和所述第二漏极同层设置于所述衬底上，所述第二有源层位于所述第二源极和第二漏极远离所述衬底的一侧，所述第二栅极位于所述第二有源层远离所述衬底的一侧；
其中，所述第一源极、所述第一漏极以及所述第二栅极位于同一金属层中，所述第一栅极、所述第二源极以及所述第二漏极同层设置。
可选的，在本申请的一些实施例中，所述第二有源层包括沟道，所述第二源极或所述第二漏极于所述沟道所在平面上的正投影至少部分覆盖所述沟道。
可选的，在本申请的一些实施例中，所述第二有源层还包括位于所述沟道相对两侧的源极接触部和漏极接触部，所述第二源极与所述源极接触部相连，并自所述源极接触部朝向所述漏极接触部的方向延伸，所述沟道于所述衬底所在平面的正投影位于所述第二源极于所述衬底所在平面的正投影内，所述第二漏极与所述漏极接触部相连。
可选的，在本申请的一些实施例中，所述显示装置还包括栅极绝缘层，所述栅极绝缘层设置在所述沟道和所述第二栅极之间，自所述第二源极朝向所述第二漏极的方向，所述第二栅极的宽度小于所述栅极绝缘层的宽度。
可选的，在本申请的一些实施例中，所述显示装置还包括连接电极，所述连接电极位于所述第二栅极远离所述衬底的一侧，所述第二栅极通过所述连接电极与所述第一漏极相连。
可选的，在本申请的一些实施例中，所述第一有源层和所述第二有源层同层设置，所述第一有源层的材料和所述第二有源层的材料均包括金属氧化物半导体。
可选的，在本申请的一些实施例中，所述第二源极于所述衬底所在平面的正投影位于所述沟道于所述衬底所在平面的正投影的外侧，所述显示装置还包括遮光层，所述遮光层设置在所述衬底靠近所述第二有源层的一侧，所述遮光层于所述衬底所在平面的正投影覆盖所述沟道。
本申请实施例还提供一种如前述实施例所述的显示装置的制备方法，其包括以下步骤：
提供所述衬底；
在所述衬底上形成第一金属层；
对所述第一金属层进行图案化处理，以形成所述第一栅极、所述第二源极以及所述第二漏极；
在所述第一栅极上形成所述第一有源层，以及在所述第二源极和所述第二漏极上形成第二有源层；
在所述第一有源层上形成所述第一源极和所述第一漏极，以及在所述第二有源层上形成所述第二栅极。
可选的，在本申请的一些实施例中，所述在所述第二源极和所述第二漏极上形成第二有源层的步骤之后，还包括：
在所述第二有源层上形成栅极绝缘层，所述栅极绝缘层于所述衬底所在平面的正投影与所述第二源极于所述衬底所在平面的正投影至少部分重叠。
可选的，在本申请的一些实施例中，所述在所述第一有源层上形成所述第一源极和所述第一漏极，以及在所述第二有源层上形成所述第二栅极的步骤，包括：
在所述栅极绝缘层上形成第二金属层，所述第二金属层覆盖所述第一有源层和所述第二有源层未被所述栅极绝缘层覆盖的部分；
对所述第二金属层进行图案化处理，以形成所述第一源极、所述第一漏极以及所述第二栅极。
可选的，在本申请的一些实施例中，在所述栅极绝缘层上形成第二金属层的步骤中，所述第二有源层被所述栅极绝缘层覆盖的区域形成为沟道，所述第二有源层未被所述栅极绝缘层覆盖的部分导体化形成源极接触部和漏极接触部，所述源极接触部与所述第二源极接触，所述漏极接触部与所述第二漏极接触。
 有益效果
在本申请提供的显示装置中，由于开关薄膜晶体管中的第一栅极位于第一有源层的下方，即开关薄膜晶体管为底栅型结构；进一步的，驱动薄膜晶体管中的第二栅极位于第二有源层的上方，第二源极和第二漏极位于第二有源层的下方，即驱动薄膜晶体管为新型的顶栅型结构。因此，本申请在将开关薄膜晶体管设置为底栅型结构的同时，将驱动薄膜晶体管设置为新型的顶栅型结构，能够在提高面板分辨率的同时提升TFT器件的稳定性，以满足高分辨率和高稳定性显示产品的设计需求。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请第一实施例提供的显示装置的结构示意图。
图2A至图2H是本申请第一实施例提供的显示装置的制备方法的流程结构示意图。
图3是本申请第二实施例提供的显示装置的结构示意图。
图4是本申请一示例提供的显示装置的像素驱动电路的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
本申请提供一种显示装置及显示装置的制备方法。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
本申请提供一种显示装置，其包括衬底、开关薄膜晶体管以及驱动薄膜晶体管。开关薄膜晶体管设置在衬底的一侧，开关薄膜晶体管包括第一栅极、第一有源层、第一源极以及第一漏极，第一栅极设置在衬底上，第一有源层位于第一栅极远离衬底的一侧，第一源极和第一漏极同层设置于第一有源层远离衬底的一侧；驱动薄膜晶体管设置在衬底的一侧，驱动薄膜晶体管与开关薄膜晶体管相连，驱动薄膜晶体管包括第二源极、第二漏极、第二有源层以及第二栅极，第二源极和第二漏极同层设置于衬底上，第二有源层位于第二源极和第二漏极远离衬底的一侧，第二栅极位于第二有源层远离衬底的一侧。
由此，在本申请提供的显示装置中，由于开关薄膜晶体管中的第一栅极位于第一有源层的下方，即开关薄膜晶体管为底栅型结构；进一步的，驱动薄膜晶体管中的第二栅极位于第二有源层的上方，第二源极和第二漏极位于第二有源层的下方，即驱动薄膜晶体管为新型的顶栅型结构。因此，本申请在将开关薄膜晶体管设置为底栅型结构的同时，将驱动薄膜晶体管设置为新型的顶栅型结构，能够在提高面板分辨率的同时提升TFT器件的稳定性，以满足高分辨率和高稳定性显示产品的设计需求。
下面通过具体实施例对本申请提供的显示装置进行详细的阐述。
请参照图1，本申请第一实施例提供一种显示装置100。显示装置100包括衬底10、开关薄膜晶体管20以及驱动薄膜晶体管30。
在本实施例中，衬底10可以为硬质基板，如玻璃基板。在一些实施例中，衬底10也可以为柔性基板，如聚酰亚胺基板。
开关薄膜晶体管20设置在衬底10的一侧。开关薄膜晶体管20为底栅型结构。开关薄膜晶体管20包括第一栅极21、第一有源层22、第一源极23以及第一漏极24。
第一栅极21设置在衬底10上。其中，第一栅极21可以为单层结构、双层结构或多层结构。第一栅极21的材料可以包括铜、铝、钼和钛中的一种或多种。示例性地，当第一栅极21为双层结构时，所述双层结构可以包括以钼为导电材料的底层和以铜为导电材料的顶层。
第一有源层22位于第一栅极21远离衬底10的一侧。其中，第一有源层22的材料包括金属氧化物半导体，如IGZO、IGTO、IZTO、IGZTO、ITO和IZO中的一种或多种。在本实施例中，第一有源层22于衬底10所在平面的正投影位于第一栅极21于衬底10所在平面的正投影内，该设置使得第一栅极21能够遮蔽来自衬底10下方的光线，避免第一有源层22受到光照影响而降低开关TFT的性能。
在本实施例中，显示装置100还包括缓冲层40，缓冲层40设置于第一栅极21和第一有源层22之间。其中，缓冲层40可以为单层结构、双层结构或多层结构。缓冲层40的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。示例性地，当缓冲层40为双层结构时，所述双层结构可以包括以氧化硅为绝缘材料的底层和以氮化硅为绝缘材料的顶层。
第一源极23和第一漏极24同层设置于第一有源层22远离衬底10的一侧。其中，第一源极23和第一漏极24可以为单层结构、双层结构或多层结构。第一源极23的材料和第一漏极24的材料相同，均可以包括铜、铝、钼和钛中的一种或多种。示例性地，当第一源极23和第一漏极24为双层结构时，所述双层结构可以包括以钼为导电材料的底层和以铜为导电材料的顶层。
在本实施例中，第一栅极21于衬底10所在平面的正投影分别与第一源极23和第一漏极24于衬底10所在平面的正投影部分重叠，该设置使得第一栅极21分别与第一源极23和第一漏极24之间形成栅极电场，以实现对第一源极23和第一漏极24所在区域电子运动的控制。
驱动薄膜晶体管30设置在衬底10的一侧。驱动薄膜晶体管30为顶栅型结构。驱动薄膜晶体管30与开关薄膜晶体管20相连。驱动薄膜晶体管30包括第二源极31、第二漏极32、第二有源层33以及第二栅极34。
第二源极31和第二漏极32同层设置于衬底10上。其中，第二源极31和第二漏极32可以为单层结构、双层结构或多层结构。第二源极31的材料和第二漏极32的材料相同，均可以包括铜、铝、钼和钛中的一种或多种。示例性地，当第二源极31和第二漏极32为双层结构时，所述双层结构可以包括以钼为导电材料的底层和以铜为导电材料的顶层。
第二有源层33位于第二源极31和第二漏极32远离衬底10的一侧。其中，第二有源层33的材料包括金属氧化物半导体，如IGZO、IGTO、IZTO、IGZTO、ITO和IZO中的一种或多种。在本实施例中，第二有源层33与第一有源层22同层设置，且两者的材料相同，该设置可以提高第一有源层22和第二有源层33的成膜均一性，以满足于大尺寸显示产品的应用需求。
具体的，第二有源层33包括沟道331和位于沟道331相对两侧的源极接触部332和漏极接触部333。第二源极31与源极接触部332通过缓冲层40中的第一过孔41相连。第二漏极32与漏极接触部333通过缓冲层40中的第二过孔42相连。在本实施例中，源极接触部332的材料和漏极接触部333的材料均为导体。
其中，第二源极31或第二漏极32于沟道331所在平面上的正投影至少部分覆盖沟道331。在本实施例中，第二源极31于沟道331所在平面上的正投影至少部分覆盖沟道331。由于沟道331与第二栅极34相对设置，当第二源极31与沟道331存在交叠区域时，相应的，第二源极31与第二栅极34也存在交叠区域；由于第二源极31通常为低电位如零电位，第二栅极34通常为正电位或负电位，上述设置使得第二源极31和第二栅极34之间形成的电场能够被屏蔽至栅极绝缘层35，从而能够避免影响到驱动薄膜晶体管30的驱动性能。
具体的，第二源极31自源极接触部332朝向漏极接触部333的方向延伸，沟道331于衬底10所在平面的正投影位于第二源极31于衬底10所在平面的正投影内。上述设置使得第二源极31能够遮蔽来着衬底10下方的环境光，避免了光照对沟道331的影响，从而能够降低驱动薄膜晶体管30的光生漏电流，以进一步提高驱动薄膜晶体管30的稳定性。
因此，本实施例通过将驱动薄膜晶体管30中的第二源极31和第二漏极32设置在第二有源层33的下方，并使第二源极31覆盖沟道331所在区域，使得在提高驱动薄膜晶体管30稳定性的同时，能够利用第二源极31来遮蔽环境光对沟道331的影响，进而能够省去传统结构中遮光层的设置，从而有利于节省显示装置100的工艺制造成本。
第二栅极34位于第二有源层33远离衬底10的一侧。其中，第二栅极34可以为单层结构、双层结构或多层结构。第二栅极34的材料可以包括铜、铝、钼和钛中的一种或多种。示例性地，当第二栅极34为双层结构时，所述双层结构可以包括以钼为导电材料的底层和以铜为导电材料的顶层。
沟道331和第二栅极34之间设置有栅极绝缘层35。自第二源极31朝向第二漏极32的方向，第二栅极34的宽度小于栅极绝缘层35的宽度。其中，栅极绝缘层35可以为单层结构、双层结构或多层结构。栅极绝缘层35的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。示例性地，当栅极绝缘层35为双层结构时，所述双层结构可以包括以氧化硅为绝缘材料的底层和以氮化硅为绝缘材料的顶层。可以理解的是，在源极接触部332和漏极接触部333所在区域的导体化过程中，受到热扩散作用的影响，实际的沟道331宽度会小于栅极绝缘层35的宽度，因此，本实施例通过将第二栅极34的宽度设置为小于栅极绝缘层35的宽度，能够确保驱动薄膜晶体管30中第二栅极34的宽度与沟道331的宽度一致。
综上，在本实施例提供的显示装置100中，由于开关薄膜晶体管20中的第一栅极21位于第一有源层22的下方，即开关薄膜晶体管20为底栅型结构；进一步的，驱动薄膜晶体管30中的第二栅极34位于第二有源层33的上方，第二源极31和第二漏极32位于第二有源层33的下方，即驱动薄膜晶体管30为新型的顶栅型结构。因此，本申请在将开关薄膜晶体管20设置为底栅型结构的同时，将驱动薄膜晶体管30设置为新型的顶栅型结构，能够在提高面板分辨率的同时提高TFT器件的稳定性，以满足高分辨率和高稳定性显示产品的设计需求。
在本实施例中，第一栅极21、第二源极31以及第二漏极32同层设置。也即，第一栅极21、第二源极31以及第二漏极32位于同一金属层中，换句话说，第一栅极21、第二源极31以及第二漏极32采用同一道光罩制备得到。
进一步的，第一源极23、第一漏极24以及第二栅极34位于同一金属层中。也即，第一源极23、第一漏极24以及第二栅极34采用同一道光罩制备得到。
在本实施例中，显示装置100还包括钝化层50和连接电极60。钝化层50覆盖开关薄膜晶体管20和驱动薄膜晶体管30。连接电极60位于钝化层50远离衬底10的一侧，用于实现开关薄膜晶体管20和驱动薄膜晶体管30的电连接。
具体的，钝化层50设置在第一源极23、第一漏极24以及第二栅极34远离衬底10的一侧。钝化层50中开设有第一连接孔51和第二连接孔52。第一连接孔51裸露出第一漏极24。第二连接孔52裸露出第二栅极34。连接电极60覆盖第一连接孔51和第二连接孔52。第二栅极34通过连接电极60与第一漏极24相连。其中，钝化层50可以为单层结构、双层结构或多层结构。钝化层50的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。示例性地，当钝化层50为双层结构时，所述双层结构可以包括以氧化硅为绝缘材料的底层和以氮化硅为绝缘材料的顶层。连接电极60的材料可以包括ITO。
由此，本实施例提供的显示装置100通过将开关薄膜晶体管20设置为底栅型结构、驱动薄膜晶体管30设置为新型的顶栅型结构，能够在提高面板分辨率的同时提高TFT器件的稳定性，以满足高分辨率和高稳定性显示产品的设计需求。进一步的，由于开关薄膜晶体管20中的第一源极23、第一漏极24与驱动薄膜晶体管30中的第二栅极34位于同一层金属层中，开关薄膜晶体管20中的第一栅极21与驱动薄膜晶体管30中的第二源极31、第二漏极32位于同一层金属层中，且因驱动薄膜晶体管30中的第二源极31与沟道331存在交叠区域，因而能够充当传统结构中遮光层的作用来避免光照对沟道331的影响，由于本实施例提供的显示装置100中仅需要设置两层金属层，进而大大简化了显示装置100的制程，从而能够节省显示装置100的工艺制造成本。
请一并参照图1、图2A至图2H，本申请还提供一种显示装置100的制备方法，其包括以下步骤：
B1：提供衬底10，如图2A所示。
B2：在衬底10上形成第一栅极21、第二源极31以及第二漏极32，如图2B所示。
首先，以钼、铜和钛中的至少一种为材料，采用物理气相沉积工艺在衬底10上形成第一金属层（图中未示出）；接着，对第一金属层进行图案化处理，以形成第一栅极21、第二源极31以及第二漏极32。其中，所述图案化处理包括曝光、显影以及蚀刻等工艺，相关技术均为现有技术，在此不再赘述。
B3：在第一栅极21、第二源极31以及第二漏极32上形成缓冲层40，如图2C所示。
首先，以氧化硅和氮化硅中的至少一种为材料，采用化学气相沉积工艺形成缓冲层40，并在300℃-400℃的高温下退火处理2h-3h；接着，对缓冲层40进行图案化处理，以形成裸露出第二源极31的第一过孔41和裸露出第二漏极32的第二过孔42。
B4：在缓冲层40上形成第一有源层22和第二有源层33，如图2D所示。
首先，以IGZO、IGTO、IZTO和IGZTO中的至少一种为材料，采用沉积工艺形成有源基层（图中未示出）；接着，对有源基层进行图案化处理，以形成对应于第一栅极21的第一有源层22、以及对应于第二源极31和第二漏极32的第二有源层33。
B5：在第二有源层33上形成栅极绝缘层35，如图2E所示。
具体的，以氧化硅和氮化硅中的至少一种为材料，依次采用化学气相沉积工艺和光刻工艺形成栅极绝缘层35，栅极绝缘层35设置在第二源极31上方。其中，栅极绝缘层35于衬底10所在平面的正投影与第二源极31于衬底10所在平面的正投影至少部分重叠。较佳地，栅极绝缘层35于衬底10所在平面的正投影位于第二源极31于衬底10所在平面的正投影内。
B6：在第一有源层22上形成第一源极23、第一漏极24，以及在栅极绝缘层35上形成第二栅极34，如图2F所示。
首先，以钼、铜和钛中的至少一种为材料，采用物理气相沉积工艺在栅极绝缘层35上形成第二金属层（图中未示出），第二金属层覆盖第一有源层22和第二有源层33未被栅极绝缘层35覆盖的部分。在沉积第二金属层的过程中，第二有源层33被栅极绝缘层35覆盖的区域形成为沟道331，第二有源层33未被栅极绝缘层35覆盖的区域实现导体化。其中，沟道331于衬底10所在平面的正投影位于第二源极31于衬底10所在平面的正投影内。第二有源层33中导体化的部分包括与第二源极31接触的源极接触部332，以及与第二漏极32接触的漏极接触部333。接着，对第二金属层进行图案化处理，以形成第一源极23、第一漏极24以及第二栅极34。
在本实施例中，第一栅极21、第一有源层22、第一源极23以及第一漏极24构成开关薄膜晶体管20；第二源极31、第二漏极32、第二有源层33以及第二栅极34构成驱动薄膜晶体管30。
B7：在第一源极23、第一漏极24以及第二栅极34上形成钝化层50，钝化层50包括第一连接孔51和第二连接孔52，如图2G所示。
具体的，以氧化硅和氮化硅中的至少一种为材料，采用化学气相沉积工艺形成钝化层50；接着，对钝化层50进行图案化处理，以形成裸露出第一漏极24的第一连接孔51，以及裸露出第二栅极34的第二连接孔52。
B8：在钝化层50上形成连接电极60，如图2H所示。
具体的，以ITO为材料，依次采用物理气相沉积工艺和光刻工艺形成连接电极60，连接电极60覆盖第一连接孔51和第二连接孔52。第二栅极34通过连接电极60与第一漏极24相连，以实现开关薄膜晶体管20和驱动薄膜晶体管30之间的信号传输。
由此，便完成了本申请所提供的显示装置100的制备方法。
请参照图3，本申请第二实施例提供一种显示装置200。本申请第二实施例提供的显示装置200与第一实施例的不同之处在于：第二源极31于衬底10所在平面的正投影位于沟道331于衬底10所在平面的正投影的外侧，显示装置200还包括无机绝缘层70和遮光层80，遮光层80设置在衬底10上，无机绝缘层70设置在遮光层80靠近第二源极31的一侧，遮光层80于沟道331所在平面的正投影覆盖沟道331。
在本实施例中，遮光层80用于遮蔽来着衬底10下方的环境光，避免光照对沟道331造成影响，从而能够降低驱动薄膜晶体管30的光生漏电流，以进一步提高驱动薄膜晶体管30的稳定性。
其中，无机绝缘层70的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种；遮光层80的材料可以包括铜、铝、钼和钛中的一种或多种。本申请对无机绝缘层70的材料和遮光层80的材料均不作具体限定。
在本申请中，所述显示装置可以为OLED显示装置、Mini LED显示装置或Micro LED显示装置等电流驱动型显示装置。其中，所述显示装置可以用于液晶显示装置中的背光模组，也可以直接进行显示。
以所述显示装置为OLED显示装置为例，OLED显示装置包括像素驱动电路。其中，所述像素驱动电路可以为2T1C像素驱动电路、3T1C像素驱动电路、3T2C像素驱动电路、4T1C像素驱动电路、4T2C像素驱动电路、5T1C像素驱动电路、5T2C像素驱动电路、6T1C像素驱动电路、6T2C像素驱动电路、7T1C像素驱动电路或7T2C像素驱动电路。
请参照图4，在一具体示例中，所述像素驱动电路为2T1C像素驱动电路。具体的，所述2T1C像素驱动电路可以包括第一薄膜晶体管TFT1、第二薄膜晶体管TFT2以及电容C。其中，第一薄膜晶体管TFT1可以为N型晶体管，以用作开关薄膜晶体管；第二薄膜晶体管TFT2可以为P型晶体管，以用作驱动薄膜晶体管；电容C可以为存储电容。
进一步的，第一薄膜晶体管TFT1的栅极接入扫描信号Scan，源极接入数据信号Data，漏极与第二薄膜晶体管TFT2的栅极以及电容C的一端电性连接；第二薄膜晶体管TFT2的源极电性连接至电源正电压VDD，漏极电性连接至有机发光二极管LED的阳极；有机发光二极管LED的阴极接低压电源VSS。
当OLED显示时，扫描信号Scan控制第一薄膜晶体管TFT1的导通，数据信号Data经过第一薄膜晶体管TFT1进入到第二薄膜晶体管TFT2的栅极和电容C，然后第一薄膜晶体管TFT1断开，由于电容C的存储作用，第二薄膜晶体管TFT2的栅极电压仍可继续保持数据信号电压，使得第二薄膜晶体管TFT2处于导通状态，驱动电流通过第二薄膜晶体管TFT2来驱动有机发光二极管LED发光。
在上述示例中，第一薄膜晶体管TFT1为前述实施例所述的开关薄膜晶体管20，第二薄膜晶体管TFT2为前述实施例所述的驱动薄膜晶体管30，开关薄膜晶体管20和驱动薄膜晶体管30的具体结构均可以参照前述实施例的描述，在此不再赘述。
以上对本申请实施例所提供的一种显示装置及显示装置的制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示装置，其包括：
    衬底；
    开关薄膜晶体管，设置在所述衬底的一侧，所述开关薄膜晶体管包括第一栅极、第一有源层、第一源极以及第一漏极，所述第一栅极设置在所述衬底上，所述第一有源层位于所述第一栅极远离所述衬底的一侧，所述第一源极和所述第一漏极同层设置于所述第一有源层远离所述衬底的一侧；以及
    驱动薄膜晶体管，设置在所述衬底的一侧，所述驱动薄膜晶体管与所述开关薄膜晶体管相连，所述驱动薄膜晶体管包括第二源极、第二漏极、第二有源层以及第二栅极，所述第二源极和所述第二漏极同层设置于所述衬底上，所述第二有源层位于所述第二源极和第二漏极远离所述衬底的一侧，所述第二栅极位于所述第二有源层远离所述衬底的一侧。
  2. 根据权利要求1所述的显示装置，其中，所述第一栅极、所述第二源极以及所述第二漏极同层设置。
  3. 根据权利要求2所述的显示装置，其中，所述第二有源层包括沟道，所述第二源极或所述第二漏极于所述沟道所在平面上的正投影至少部分覆盖所述沟道。
  4. 根据权利要求3所述的显示装置，其中，所述第二有源层还包括位于所述沟道相对两侧的源极接触部和漏极接触部，所述第二源极与所述源极接触部相连，并自所述源极接触部朝向所述漏极接触部的方向延伸，所述沟道于所述衬底所在平面的正投影位于所述第二源极于所述衬底所在平面的正投影内，所述第二漏极与所述漏极接触部相连。
  5. 根据权利要求4所述的显示装置，其中，所述显示装置还包括栅极绝缘层，所述栅极绝缘层设置在所述沟道和所述第二栅极之间，自所述第二源极朝向所述第二漏极的方向，所述第二栅极的宽度小于所述栅极绝缘层的宽度。
  6. 根据权利要求1所述的显示装置，其中，所述第一源极、所述第一漏极以及所述第二栅极位于同一金属层中。
  7. 根据权利要求6所述的显示装置，其中，所述显示装置还包括连接电极，所述连接电极位于所述第二栅极远离所述衬底的一侧，所述第二栅极通过所述连接电极与所述第一漏极相连。
  8. 根据权利要求1所述的显示装置，其中，所述第一有源层和所述第二有源层同层设置，所述第一有源层的材料和所述第二有源层的材料均包括金属氧化物半导体。
  9. 根据权利要求3所述的显示装置，其中，所述第二源极于所述衬底所在平面的正投影位于所述沟道于所述衬底所在平面的正投影的外侧，所述显示装置还包括遮光层，所述遮光层设置在所述衬底靠近所述第二有源层的一侧，所述遮光层于所述衬底所在平面的正投影覆盖所述沟道。
  10. 一种显示装置，其包括：
    衬底；
    开关薄膜晶体管，设置在所述衬底的一侧，所述开关薄膜晶体管包括第一栅极、第一有源层、第一源极以及第一漏极，所述第一栅极设置在所述衬底上，所述第一有源层位于所述第一栅极远离所述衬底的一侧，所述第一源极和所述第一漏极同层设置于所述第一有源层远离所述衬底的一侧；以及
    驱动薄膜晶体管，设置在所述衬底的一侧，所述驱动薄膜晶体管与所述开关薄膜晶体管相连，所述驱动薄膜晶体管包括第二源极、第二漏极、第二有源层以及第二栅极，所述第二源极和所述第二漏极同层设置于所述衬底上，所述第二有源层位于所述第二源极和第二漏极远离所述衬底的一侧，所述第二栅极位于所述第二有源层远离所述衬底的一侧；
    其中，所述第一源极、所述第一漏极以及所述第二栅极位于同一金属层中，所述第一栅极、所述第二源极以及所述第二漏极同层设置。
  11. 根据权利要求10所述的显示装置，其中，所述第二有源层包括沟道，所述第二源极或所述第二漏极于所述沟道所在平面上的正投影至少部分覆盖所述沟道。
  12. 根据权利要求11所述的显示装置，其中，所述第二有源层还包括位于所述沟道相对两侧的源极接触部和漏极接触部，所述第二源极与所述源极接触部相连，并自所述源极接触部朝向所述漏极接触部的方向延伸，所述沟道于所述衬底所在平面的正投影位于所述第二源极于所述衬底所在平面的正投影内，所述第二漏极与所述漏极接触部相连。
  13. 根据权利要求11所述的显示装置，其中，所述显示装置还包括栅极绝缘层，所述栅极绝缘层设置在所述沟道和所述第二栅极之间，自所述第二源极朝向所述第二漏极的方向，所述第二栅极的宽度小于所述栅极绝缘层的宽度。
  14. 根据权利要求10所述的显示装置，其中，所述显示装置还包括连接电极，所述连接电极位于所述第二栅极远离所述衬底的一侧，所述第二栅极通过所述连接电极与所述第一漏极相连。
  15. 根据权利要求10所述的显示装置，其中，所述第一有源层和所述第二有源层同层设置，所述第一有源层的材料和所述第二有源层的材料均包括金属氧化物半导体。
  16. 根据权利要求11所述的显示装置，其中，所述第二源极于所述衬底所在平面的正投影位于所述沟道于所述衬底所在平面的正投影的外侧，所述显示装置还包括遮光层，所述遮光层设置在所述衬底靠近所述第二有源层的一侧，所述遮光层于所述衬底所在平面的正投影覆盖所述沟道。
  17. 一种如权利要求1所述的显示装置的制备方法，其中，所述显示装置的制备方法包括以下步骤：
    提供所述衬底；
    在所述衬底上形成第一金属层；
    对所述第一金属层进行图案化处理，以形成所述第一栅极、所述第二源极以及所述第二漏极；
    在所述第一栅极上形成所述第一有源层，以及在所述第二源极和所述第二漏极上形成第二有源层；
    在所述第一有源层上形成所述第一源极和所述第一漏极，以及在所述第二有源层上形成所述第二栅极。
  18. 根据权利要求17所述的显示装置的制备方法，其中，所述在所述第二源极和所述第二漏极上形成第二有源层的步骤之后，还包括：
    在所述第二有源层上形成栅极绝缘层，所述栅极绝缘层于所述衬底所在平面的正投影与所述第二源极于所述衬底所在平面的正投影至少部分重叠。
  19. 根据权利要求18所述的显示装置的制备方法，其中，所述在所述第一有源层上形成所述第一源极和所述第一漏极，以及在所述第二有源层上形成所述第二栅极的步骤，包括：
    在所述栅极绝缘层上形成第二金属层，所述第二金属层覆盖所述第一有源层和所述第二有源层未被所述栅极绝缘层覆盖的部分；
    对所述第二金属层进行图案化处理，以形成所述第一源极、所述第一漏极以及所述第二栅极。
  20. 根据权利要求19所述的显示装置的制备方法，其中，在所述栅极绝缘层上形成第二金属层的步骤中，所述第二有源层被所述栅极绝缘层覆盖的区域形成为沟道，所述第二有源层未被所述栅极绝缘层覆盖的部分导体化形成源极接触部和漏极接触部，所述源极接触部与所述第二源极接触，所述漏极接触部与所述第二漏极接触。
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