WO2023122880A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2023122880A1
WO2023122880A1 PCT/CN2021/141623 CN2021141623W WO2023122880A1 WO 2023122880 A1 WO2023122880 A1 WO 2023122880A1 CN 2021141623 W CN2021141623 W CN 2021141623W WO 2023122880 A1 WO2023122880 A1 WO 2023122880A1
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WO
WIPO (PCT)
Prior art keywords
power bus
layer
driving power
area
display panel
Prior art date
Application number
PCT/CN2021/141623
Other languages
English (en)
French (fr)
Inventor
易宏
张跳梅
王梦奇
陈文波
青海刚
李正坤
李德
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180004211.0A priority Critical patent/CN116686417A/zh
Priority to PCT/CN2021/141623 priority patent/WO2023122880A1/zh
Publication of WO2023122880A1 publication Critical patent/WO2023122880A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.
  • the touch signal wiring needs to be shielded by the common electrode loaded with the reference power supply voltage and the reference power bus to reduce the noise in the display panel. Crosstalk from other signals to touch signal traces.
  • the purpose of the present disclosure is to overcome the shortcomings of the above-mentioned prior art, provide a display panel and a display device, and improve the flexibility of touch signal wiring when wiring.
  • a display panel including a display area and a peripheral area surrounding the display area;
  • the peripheral area includes a first peripheral area located on one side of the display area, the first The peripheral area has a lighting test area provided with a lighting test unit;
  • the display panel has a first edge, and the first edge is located on a side of the first peripheral area away from the display area;
  • the display panel is provided with a reference power bus and touch signal traces; in the first peripheral area, the reference power bus has a reference power bus protrusion; the reference power bus protrusion is on the first
  • the orthographic projection on the edge is located within the orthographic projection of the lighting test area on the first edge; at least part of the touch signal traces overlaps with the reference power bus protrusion.
  • the protruding portion of the reference power bus is located on a side of the lighting test unit close to the display area.
  • one end of the display area close to the lighting test unit has an arc-shaped top angle
  • the orthographic projection of the reference power bus protrusion on the first edge at least partially overlaps the orthographic projection of the arc-shaped vertex on the first edge.
  • the display panel includes a pixel layer, the pixel layer has a common electrode layer for loading a reference power supply voltage; the common electrode layer covers the display area;
  • the edge of the reference power bus protruding part away from the first edge is located between the edge of the common electrode layer close to the first edge and the display area.
  • the area where the protrusion of the reference power bus is located is the area of the protrusion, and at least part of the touch signal traces are bent in the area of the protrusion.
  • the display panel is provided with data wiring in the display area, and a first data transfer line is provided between the display area and the lighting test area;
  • the data wiring is electrically connected to the lighting test unit through the first data transfer line;
  • the protruding portion of the reference power bus overlaps at least part of the first data transfer line.
  • the display panel is further provided with a driving power bus located in the first peripheral area;
  • the driving power bus includes a first part of the driving power bus, a third part of the driving power bus and a plurality of second parts of the driving power bus; the first part of the driving power bus is located between the display area and the lighting test area;
  • the third part of the driving power bus is located on the side of the lighting test area away from the display area;
  • the lighting test area includes a plurality of lighting test sub-areas; the second part of the driving power bus is located between each of the lighting test sub-areas, and is electrically connected to the first part of the driving power bus and the third part of the driving power bus .
  • the display panel is provided with pads arranged along the first edge; the pads include driving power pads for applying a driving power voltage;
  • the driving power bus also includes a fourth part of the driving power bus; the third part of the driving power bus is electrically connected to the driving power pad through the fourth part of the driving power bus.
  • the number of the driving power pads is multiple and corresponds to each end of the third part of the driving power bus; the number of the fourth part of the driving power bus is more than one and corresponding to each end of the third part of the drive power bus;
  • Each end of the third part of the driving power bus is electrically connected to the corresponding pad of the driving power through the corresponding fourth part of the driving power bus.
  • the third part of the driving power bus is divided into two power sub-wirings; the end of each power sub-wiring passes through the fourth part of the driving power bus and the The above drive power pads are electrically connected.
  • the length of the first part of the driving power bus is shorter than the length of the third part of the driving power bus.
  • the orthographic projection of the first part of the driving power bus on the first edge does not coincide with the orthographic projection of the protrusion of the reference power bus on the first edge.
  • the display panel is further provided with a driving chip area for binding driving chips in the first peripheral area; the first part of the driving power bus is provided between the driving chip area and the Between lighting test areas.
  • the display panel includes a base substrate, a driving layer, a pixel layer, a thin film encapsulation layer, and a touch layer that are sequentially stacked;
  • the touch signal wiring is arranged on the touch layer
  • the driving layer includes a source-drain metal layer, and the driving power bus and the reference power bus are disposed on the source-drain metal layer.
  • a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of a display panel in an embodiment of the present disclosure.
  • Fig. 2 is a schematic structural diagram of an intermediate module in an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a source-drain metal layer of an intermediate module at a near end in an embodiment of the present disclosure.
  • FIG. 4 is an enlarged schematic diagram of a local structure of a source-drain metal layer of an intermediate module at a near end in an embodiment of the present disclosure.
  • Fig. 5 is a schematic diagram of a local structure of a part of the wires of the intermediate module at the proximal end in an embodiment of the present disclosure.
  • Fig. 6 is a structural schematic diagram of maintaining signal continuity through a lighting test jumper between lighting test units in an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a protruding portion of the reference power bus overlapping with a part of the first data transfer line in an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a film layer structure of a display panel in an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of the touch electrodes of the touch layer of the display panel in an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural view of the touch layer cut along the P1P2 direction in FIG. 9 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the present disclosure provides a display panel and a display device based on the display panel.
  • the display panel of the present disclosure includes a base substrate F100 , a driving layer F200 , a pixel layer F300 , a thin film encapsulation layer F400 and a touch layer F500 which are stacked in sequence.
  • the pixel layer F300 is provided with sub-pixels F300D for displaying pictures;
  • the driving layer is provided with a pixel driving circuit for driving the sub-pixels.
  • touch electrodes for sensing touch actions and touch signal traces TSL for transmitting touch sensing signals are arranged. In this way, the display panel of the present disclosure can realize display and touch functions.
  • structure A and structure B overlap each other, it means that structure A and structure B are located in different film layers, and the orthographic projection of structure A on the substrate is the same as that of structure B on the substrate. Orthographic projections have overlapping parts.
  • the structural layer C is located on the side of the structural layer D away from the base substrate. It can be understood that the structural layer C is formed on the side of the structural layer D away from the base substrate. When the structural layer D is a patterned structure, part of the structure of the structural layer C can also be located at the same physical height of the structural layer D or lower than the physical height of the structural layer D, wherein the base substrate is the height reference.
  • the base substrate F100 may be the base substrate F100 of inorganic materials, or may be the base substrate F100 of organic materials.
  • the material of the base substrate F100 may be glass materials such as soda-lime glass, quartz glass, sapphire glass, or may be stainless steel, aluminum, nickel, etc. metallic material.
  • the material of the substrate F100 may be polymethyl methacrylate (Polymethyl methacrylate, PMMA), polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl phenol (Polyvinyl phenol, PVP), polyethersulfone (Polyether sulfone, PES), polyimide, polyamide, polyacetal, polycarbonate (Polycarbonate, PC), polyethylene terephthalate (Polyethylene terephthalate, PET), Polyethylene naphthalate (PEN) or a combination thereof.
  • the base substrate F100 may also be a flexible base substrate F100, for example, the material of the base substrate F100 may be polyimide (PI).
  • the base substrate F100 can also be a composite of multi-layer materials.
  • the base substrate F100 can include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, A first polyimide layer and a second polyimide layer.
  • the driving layer F200 is provided with a pixel driving circuit for driving sub-pixels.
  • any pixel driving circuit may include a transistor F200M and a storage capacitor.
  • the transistor F200M can be a thin film transistor, and the thin film transistor can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor or a double-gate thin film transistor;
  • the material of the active layer of the thin film transistor can be an amorphous silicon semiconductor material, a low temperature Polysilicon semiconductor materials, metal oxide semiconductor materials, organic semiconductor materials or other types of semiconductor materials;
  • the thin film transistors can be N-type thin film transistors or P-type thin film transistors.
  • the types of any two transistors may be the same or different.
  • some transistors may be N-type transistors and some transistors may be P-type transistors.
  • the material of the active layer of some transistors may be low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be metal oxide semiconductor materials.
  • the thin film transistor is a low temperature polysilicon transistor. In some other embodiments of the present disclosure, some of the thin film transistors are low temperature polysilicon transistors, and some of the thin film transistors are metal oxide transistors.
  • the driving layer F200 may include a semiconductor layer F203, a gate insulating layer F204, a gate layer F205, an interlayer dielectric layer F206, and a source-drain metal layer F207 stacked between the base substrate F100 and the pixel layer F300.
  • Each thin film transistor and storage capacitor can be formed of film layers such as semiconductor layer F203 , gate insulating layer F204 , gate layer F205 , interlayer dielectric layer F206 , and source-drain metal layer F207 .
  • the positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor.
  • the semiconductor layer F203 can be used to form the channel region of the transistor; the gate layer can be used to form the gate layer wiring such as the scanning wiring, the reset control wiring, and the light emission control wiring, and can also be used to form the transistor’s
  • the gate can also be used to form part or all of the electrode plates of the storage capacitor.
  • the source-drain metal layer can be used to form source-drain metal layer wiring such as data wiring for loading driving data, driving power supply wiring for loading driving power supply voltage, and can also be used to form part of the electrode plate of the storage capacitor.
  • the driving layer F200 may include a semiconductor layer F203, a gate insulating layer F204, a gate layer F205, an interlayer dielectric layer F206, and a source-drain metal layer F207 that are sequentially stacked, so that The formed thin film transistor is a top-gate thin film transistor.
  • the driving layer F200 may include a gate layer F205, a gate insulating layer F204, a semiconductor layer F203, an interlayer dielectric layer F206, and a source-drain metal layer F207 that are sequentially stacked,
  • the thin film transistor thus formed is a bottom gate thin film transistor.
  • the gate layer may be two or three layers.
  • the gate layer F205 may include a first gate layer and a second gate layer
  • the gate insulating layer F204 may include a A first gate insulating layer, and a second gate insulating layer for isolating the first gate layer and the second gate layer.
  • the driving layer F200 may include a semiconductor layer F203, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, Interlayer dielectric layer F206 and source-drain metal layer F207.
  • the gate layer F205 may include a first gate layer and a second gate layer, and the semiconductor layer F203 may be interposed between the first gate layer and the second gate layer. between layers; the gate insulating layer F204 may include a first gate insulating layer for isolating the semiconductor layer F203 and the first gate layer, and a second gate for isolating the second gate layer and the semiconductor layer F203 Insulation.
  • the driving layer F200 may include a first gate layer, a first gate insulating layer, a semiconductor layer F203 , a second gate electrode insulating layer, second gate layer, interlayer dielectric layer F206 and source-drain metal layer F207.
  • the semiconductor layer F203 may include a low-temperature polysilicon semiconductor layer and a metal oxide semiconductor layer; the gate layer includes a first gate layer and a second gate layer, and the gate insulation The layers include first and second gate insulating layers.
  • the driving layer F200 may include a low-temperature polysilicon semiconductor layer, a first gate insulating layer, a first gate layer, a metal oxide semiconductor layer, a second gate insulating layer, and a second gate layer sequentially stacked on one side of the base substrate F100. Electrode layer, interlayer dielectric layer F206 and source-drain metal layer F207.
  • the semiconductor layer F203 may include a low-temperature polysilicon semiconductor layer and a metal oxide semiconductor layer; the gate layer includes first to third gate layers, and the gate insulating layer includes the first to third gate layers.
  • the driving layer F200 may include a low-temperature polysilicon semiconductor layer, a first gate insulating layer, a first gate layer, an insulating buffer layer, a second gate layer, and a second gate insulating layer stacked on one side of the substrate F100 in sequence. , a metal oxide semiconductor layer, a third gate insulating layer, a third gate layer, an interlayer dielectric layer F206 and a source-drain metal layer F207.
  • the source and drain metal layers may be two or three layers.
  • the source-drain metal layer may include a first source-drain metal layer and a second source-drain metal layer sequentially stacked on the side of the interlayer dielectric layer F206 away from the base substrate.
  • An insulating layer may be interposed between the first source-drain metal layer and the second source-drain metal layer, such as a passivation layer and/or a planarization layer.
  • the source-drain metal layer may include a first source-drain metal layer, a second source-drain metal layer, a second source-drain metal layer, The third source-drain metal layer; the first source-drain metal layer and the second source-drain metal layer may be sandwiched by an insulating layer, such as a passivation layer and/or a resin layer; the second source-drain metal layer and the second source-drain metal layer An insulating layer may be interposed between the three source-drain metal layers, for example, a passivation layer and/or a planarization layer may be interposed.
  • the driving layer F200 may further include a passivation layer, and the passivation layer may be disposed on the surface of the source-drain metal layer F207 away from the base substrate F100 so as to protect the source-drain metal layer F207.
  • the driving layer F200 may further include a buffer material layer F201 disposed between the base substrate F100 and the semiconductor layer F203, and the semiconductor layer F203, the gate layer F205, etc. are located on a side of the buffer material layer away from the base substrate F100. side.
  • the material of the buffer material layer may be inorganic insulating materials such as silicon oxide and silicon nitride.
  • the buffer material layer can be a layer of inorganic material, or a layer of inorganic material stacked in multiple layers.
  • the driving layer F200 may further include a planarization layer F208 located between the source-drain metal layer F207 and the pixel layer F300, and the planarization layer F208 may provide a planarized surface for the pixel electrode.
  • the material of the planarization layer F208 may be an organic material.
  • the pixel layer is provided with sub-pixels distributed in an array, and each sub-pixel emits light under the control of the pixel driving circuit.
  • the sub-pixels can be organic electroluminescent diodes (OLEDs), micro light-emitting diodes (Micro LEDs), quantum dot-organic electroluminescent diodes (QD-OLEDs), quantum dot light-emitting diodes (QLEDs) or other types of light-emitting elements.
  • OLEDs organic light emitting diodes
  • the display panel is an OLED display panel.
  • the pixel layer F300 may be disposed on the side of the driving layer F200 away from the base substrate F100, which may include a pixel electrode layer F301, a pixel definition layer F302, a support pillar layer F303, an organic light-emitting functional layer F304 and Common electrode layer F305.
  • the pixel electrode layer F301 has a plurality of pixel electrodes in the display area of the display panel;
  • the pixel definition layer F302 has a plurality of through pixel openings corresponding to the plurality of pixel electrodes in the display area, and any pixel opening exposes the corresponding At least a partial area of the pixel electrode.
  • the support column layer F303 includes a plurality of support columns in the display area, and the support columns are located on the surface of the pixel definition layer F302 away from the base substrate F100, so as to support a fine metal mask (Fine Metal Mask, FMM) during the evaporation process.
  • the organic light emitting functional layer F304 at least covers the pixel electrodes exposed by the pixel definition layer F302.
  • the organic light-emitting functional layer F304 may include an organic electroluminescent material layer, and may include one of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. or multiple.
  • Each film layer of the organic light-emitting functional layer F304 can be prepared by an evaporation process, and a fine metal mask or an open mask (Open Mask) can be used to define the pattern of each film layer during evaporation.
  • the common electrode layer F305 can cover the organic light-emitting functional layer F304 in the display area. In this way, the pixel electrode, the common electrode layer F305 and the organic light-emitting functional layer F304 between the pixel electrode and the common electrode layer F305 form an organic light-emitting diode F300D, and any organic light-emitting diode can be used as a sub-pixel of the display panel.
  • the source of the driving transistor can be loaded with a driving power supply voltage
  • the gate of the driving transistor can be loaded with a voltage related to the data voltage
  • its drain can be electrically connected with the pixel electrode of the sub-pixel
  • the common The electrodes can be loaded with a reference supply voltage as a common electrode voltage.
  • the drive transistor outputs a drive current under the control of the voltage on its gate, and the sub-pixel emits light under the drive of the drive current.
  • the pixel layer F300 may further include a light extraction layer located on the side of the common electrode layer F305 away from the base substrate F100, so as to enhance the light extraction efficiency of the organic light emitting diode.
  • the display panel may further include a thin film encapsulation layer F400.
  • the thin film encapsulation layer F400 is disposed on the surface of the pixel layer F300 away from the base substrate F100, and may include alternately stacked inorganic encapsulation layers and organic encapsulation layers.
  • the inorganic encapsulation layer can effectively block moisture and oxygen from the outside, preventing water and oxygen from invading the organic light-emitting functional layer F304 and causing material degradation.
  • the edge of the inorganic encapsulation layer may be located in the peripheral region.
  • the organic encapsulation layer is located between two adjacent inorganic encapsulation layers, so as to realize planarization and weaken the stress between the inorganic encapsulation layers.
  • the edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer.
  • the thin film encapsulation layer F400 includes a first inorganic encapsulation layer F401 , an organic encapsulation layer F402 and a second inorganic encapsulation layer F403 sequentially stacked on the side of the pixel layer F300 away from the base substrate F100 .
  • the touch layer F500 is disposed on the side of the thin film encapsulation layer F400 away from the base substrate F100 for realizing the touch operation of the display panel.
  • the touch layer F500 may include a first touch metal layer F501, a touch insulation layer F502 and a second touch metal layer F503 which are sequentially stacked; the second touch metal layer F503 is located on the first touch
  • the control metal layer F501 is away from the side of the base substrate F100.
  • One or both of the first touch metal layer F501 and the second touch metal layer F503 are used to form the touch electrode F510 .
  • the touch layer F500 is disposed on a side of the thin film encapsulation layer F400 away from the base substrate.
  • a touch buffer layer may also be included between the first touch metal layer F501 and the thin film encapsulation layer F400.
  • the material of the touch buffer layer may be an inorganic material, such as silicon nitride, silicon oxide, or silicon oxynitride. It can be understood that, in other embodiments of the present disclosure, the outermost inorganic encapsulation layer of the thin film encapsulation layer F400 can also be reused as a touch buffer layer.
  • a touch protection layer may also be included on the side of the second touch metal layer F503 away from the base substrate F100 .
  • the material of the touch protection layer may be an inorganic material, such as silicon nitride, silicon oxide, or silicon oxynitride. It can be understood that, in other embodiments of the present disclosure, the side of the second touch metal layer F503 away from the base substrate F100 may also be directly provided with an organic layer, such as an organic cover or an optical glue.
  • the first touch metal layer F501 and the second touch metal layer F503 can be transparent film layers, so that the formed touch electrode F510 is a transparent electrode.
  • the material of the first touch metal layer F501 and the second touch metal layer F503 may be a light-transmitting material, such as a transparent conductive metal oxide (such as indium tin oxide, etc.).
  • the shape and position of the touch electrode F510 can be set according to the needs of the touch display panel, so that the touch layer F500 can determine the touch position based on the self-capacitance or mutual-capacitance principle.
  • the touch layer F500 can also be used to form touch wires, so as to conduct signals generated by the touch electrodes F510 corresponding to touch actions.
  • the touch electrode F510 includes a plurality of row touch electrodes F512 extending along the row direction H1 and a plurality of column touch electrodes F511 extending along the column direction H2 .
  • Each row of touch electrodes F512 is arranged in sequence along the column direction H2, and each column of touch electrodes F511 is arranged in sequence along the row direction H1.
  • any one of the column touch electrodes F511 is disposed on the second touch metal layer F503, and includes a plurality of column touch sub-electrodes F5111 arranged in sequence along the column direction H2, and the ends of two adjacent column touch sub-electrodes F5111 interconnected.
  • any row touch electrode F512 includes a plurality of row touch sub-electrodes F5121 arranged in sequence along the row direction H1.
  • the row touch sub-electrodes F5121 are arranged on the second touch metal layer F503, and their edges are aligned with the column touch sub-electrodes F5111. The edges are adjacent to each other.
  • two adjacent row touch sub-electrodes F5121 are separated by a column touch electrode F511, and two adjacent row touch sub-electrodes F5121 are connected by the first touch metal
  • the bridging connection F5131 of the layer F501 is connected.
  • the touch electrodes include a plurality of row touch electrodes extending along the row direction and a plurality of column touch electrodes extending along the column direction.
  • the row touch electrodes are arranged sequentially along the column direction, and the row touch electrodes are arranged sequentially along the row direction.
  • any row touch electrode is disposed on the second touch metal layer, and includes a plurality of row touch sub-electrodes arranged in sequence along the row direction, and ends of two adjacent row touch sub-electrodes are connected to each other. In this way, the row touch electrodes are completely disposed on the second touch metal layer.
  • any one of the column touch electrodes includes a plurality of column touch sub-electrodes arranged in sequence along the column direction, and the column touch sub-electrodes are arranged on the second touch metal layer, and the edges of the column touch sub-electrodes are adjacent to the edges of the row touch sub-electrodes.
  • two adjacent column touch sub-electrodes are separated by a row touch electrode, and two adjacent column touch sub-electrodes are connected by a bridge located in the first touch metal layer department connection.
  • the touch electrodes include a plurality of row touch electrodes extending along a row square and a plurality of column touch electrodes extending along a column direction.
  • the row touch electrodes are arranged sequentially along the column direction, and the row touch electrodes are arranged sequentially along the row direction.
  • one of the row touch electrodes and the column touch electrodes is disposed on the first touch metal layer, and the other is disposed on the second touch metal layer.
  • the row touch electrodes and the column touch electrodes overlap each other and form a mutual capacitance.
  • the touch layer is pressed by a touch object such as a finger, the mutual capacitance between the row touch electrodes and the column touch electrodes changes.
  • the touch electrode array is distributed on the second touch metal layer, and the touch traces extend through the first touch metal layer to pass through the via holes with each touch electrode. connect.
  • the display panel may also include an anti-reflection layer F600, which may be disposed on the side of the thin-film encapsulation layer F400 away from the pixel layer F300 to reduce the reflection of the display panel on ambient light, thereby reducing the impact of ambient light on the display. The impact of the effect.
  • an anti-reflection layer F600 which may be disposed on the side of the thin-film encapsulation layer F400 away from the pixel layer F300 to reduce the reflection of the display panel on ambient light, thereby reducing the impact of ambient light on the display. The impact of the effect.
  • the anti-reflection layer F600 may include a color filter layer and a black matrix layer that are stacked, so that while reducing ambient light interference, the purity of light output can be improved to increase the color gamut of the display panel. Further, the antireflection layer F600 is disposed between the thin film encapsulation layer and the touch layer.
  • the anti-reflection layer F600 may be a polarizer, for example, a patterned coated circular polarizer. Further, the anti-reflection layer F600 may be disposed on a side of the touch layer F500 away from the base substrate F100.
  • FIG. 1 is a schematic top view structure diagram of a display panel in an embodiment of the present disclosure.
  • the display panel of the present disclosure includes a display area AA and a peripheral area BB surrounding the display area AA.
  • the display panel is provided with sub-pixels and a pixel driving circuit for driving the sub-pixels, as well as wiring for loading signals to the pixel driving circuit or receiving feedback signals from the pixel driving circuit.
  • These traces may include traces extending along the row direction DH, for example, scan traces for loading scan signals, light emission control traces for loading light emission control signals, reset control traces for loading reset control signals, One or more of the wirings such as initialization wirings for loading the initialization voltage, or other required wirings.
  • These wires may also be column wires extending along the column direction DV, for example, include data wires for loading driving data, driving power lines VDDL for loading driving power voltage, and the like.
  • the peripheral area BB may include a first peripheral area B1 , a second peripheral area B2 , a third peripheral area B3 , and a fourth peripheral area B4 sequentially connected.
  • the first peripheral area B1 and the third peripheral area B3 are respectively located on two opposite sides of the display area AA, and extend along the row direction DH. In other words, along the column direction, the first peripheral area B1, the display area AA, and the third peripheral area B3 are arranged in sequence.
  • the second peripheral area B2 and the fourth peripheral area B4 are respectively located on opposite sides of the display area AA, and extend along the column direction DV; in other words, along the row direction, the second peripheral area B2, the display area AA, and the fourth peripheral area B4 are sequentially arranged arrangement.
  • the outer edge of the first peripheral area B1 ie, the edge of the first peripheral area B1 away from the display area AA
  • the display panel has a first edge PL1
  • the first peripheral area B1 is located between the first edge PL1 and the display area AA.
  • the display panel may be provided with a pad area PADA extending along the first edge PL1, and a plurality of pads arranged along the first edge PL1 are arranged in the pad area PADA, so as to be bonded and connected to an external circuit, such as a flexible circuit board, Chip-on-film, printed circuit board, or other circuit structure bonding connection.
  • the display device of the present disclosure (for example, devices such as mobile phone screens, tablet computers, notebook computers, and interactive electronic billboards using the display panel of the present disclosure) has a controller, and the controller can be used as an external circuit of the display panel to communicate with the pad area PADA Pad bond connections in .
  • the end close to the first edge PL1 can be called the near end of the display panel
  • the end close to the third peripheral area B3 can be called the far end of the display panel
  • the end close to the second peripheral area B2 can be called the far end of the display panel.
  • the side of is defined as the left side
  • the side close to the fourth peripheral area B4 is defined as the right side.
  • the first peripheral area B1 has a lighting test area CTA provided with a lighting test unit CT, and has a first data transfer line D1L disposed between the lighting test area CTA and the display area AA.
  • the data wiring is electrically connected to the lighting test unit CT through the first data transfer line D1L.
  • the cell test unit CT can perform a cell test on the display panel, such as detecting whether there are defects such as bright spots, color spots, stains, and bright lines.
  • the display panel can be presented as an intermediate module during the manufacturing process, and FIG. 2 and FIG. 3 illustrate a schematic structural view of the intermediate module.
  • the middle module has one or more auxiliary regions, which can be removed during the cutting stage.
  • the intermediate module includes a first auxiliary area Dum1 located on the side of the first peripheral area B1 away from the display area AA, and a first auxiliary area Dum1 located on the side of the second peripheral area B2 away from the display area AA.
  • the second auxiliary area Dum2 and the third auxiliary area Dum3 are located on the side of the fourth peripheral area B4 away from the display area AA.
  • the edge on the proximal side of the middle module is the second edge PL2 , and the second edge PL2 is located on the side of the first auxiliary area Dum1 away from the display area AA.
  • contact pads PAD arranged along the second edge PL2 are arranged in the first auxiliary area Dum1; during the lighting test stage, the probes of the detection equipment can be pressed on the contact pads PAD, so as to provide the intermediate module Load heartbeat. During the cutting stage, these contact pads PAD can be cut off.
  • the intermediate module can have other auxiliary areas or have fewer auxiliary areas, for example, it only has the first auxiliary area Dum1 without the second auxiliary area Dum2 and the third auxiliary area. District Dum3.
  • the lighting test unit CT may include one or more rows of detection transistors, and the input terminals of the detection transistors are used for loading detection signals or driving data.
  • the gate of the detection transistor is electrically connected to the detection control line, and the output terminal of the detection transistor is electrically connected to the data wiring through the first data transfer line D1L.
  • the first data transfer line D1L is disposed on the gate layer, for example, one or both of the first gate layer and the second gate layer are disposed.
  • the display panel is provided with a reference power supply bus VSSB for loading a reference power supply voltage and a driving power supply bus VDDB for loading a driving power supply voltage in the peripheral area BB.
  • the reference power bus VSSB and the driving power bus VDDB can be disposed on the source-drain metal layer.
  • the reference power bus VSSB may include two left and right lines to provide the reference power supply voltage to the common electrode layer through the second peripheral area B2 and the fourth peripheral area B4 respectively.
  • the reference power bus VSSB includes a reference power distribution segment VSSB1 located in the first peripheral area B1 and a reference power supply segment VSSB2 located in the second peripheral area B2 or the fourth peripheral area B4.
  • the reference power distribution segment VSSB1 is located at the end of the first peripheral area B1, for example, at the left end or the right end of the first peripheral area B1.
  • the near end of the reference power distribution section VSSB1 is electrically connected to the reference power pad in the pad area PADA.
  • the remote end of the reference power distribution section VSSB1 is electrically connected to the reference power supply section VSSB2.
  • the common electrode layer covers the display area AA and extends to the second peripheral area B2 and the fourth peripheral area B4, and is electrically connected to the reference power supply segment VSSB2 through a via hole.
  • the driving power bus VDDB is disposed in the first peripheral area B1 and between two reference power busses VSSB, which can directly supply power to the driving power line VDDL of the display area AA from the first peripheral area B1 .
  • the driving power bus VDDB is at least partly disposed between the lighting test area CTA and the display area AA, and is directly electrically connected to at least part of the driving power line VDDL.
  • the touch signal traces TSL of the touch layer can be arranged in the peripheral area BB, for example, from the second peripheral area B2 and the fourth peripheral area B4 to the first peripheral area B1 respectively, so that in the A peripheral area B1 is electrically connected to the driver chip or external circuits.
  • the touch signal trace TSL can overlap with the reference power supply bus VSSB or the common electrode layer to realize signal shielding, ensure the stability of the touch sensing signal on the touch signal trace TSL, and reduce the The crosstalk of other signals to the touch signal trace TSL.
  • the driving power bus VDDB is completely disposed between the lighting test area CTA and the display area AA, and its orthographic projection on the first edge PL1 completely covers the orthographic projection of the lighting test unit CT on the first edge PL1.
  • the reference power distribution section VSSB1 needs to avoid the driving power bus VDDB during wiring, that is, the orthographic projection of the reference power distribution section VSSB1 on the first edge PL1 does not overlap with the orthographic projection of the lighting test unit CT on the first edge PL1.
  • this setting method results in a relatively small width of the reference power distribution section VSSB1 in the row direction, which leads to a small line width of the touch signal trace TSL to overlap with the reference power distribution section VSSB1 to realize signal Shielding, which is not conducive to increasing the number of touch signal traces TSL (and thus increasing the number of touch electrodes) to improve touch accuracy, nor is it conducive to increasing the width of touch signal traces TSL to reduce touch sensing signals pressure drop.
  • the reference power bus VSSB in the first peripheral area B1, has a reference power bus protrusion VSSBD; the reference power bus protrusion VSSBD is on the first edge
  • the orthographic projection on PL1 is located within the orthographic projection of the lighting test area CTA on the first edge PL1.
  • the reference power distribution section VSSB1 is provided with a reference power bus protrusion VSSBD that can extend toward the inner side of the first peripheral area B1 (the middle side of the first peripheral area B1 in the row direction). To increase the width of the reference power distribution section VSSB1.
  • the display panel of the present disclosure can increase the width of the touch signal traces TSL so that part of the touch signal traces TSL overlap with the reference power bus protrusion VSSBD, and can also increase the number of touch signal traces TSL to Part of the touch signal trace TSL overlaps with the reference power supply bus protrusion VSSBD.
  • the reference power bus protrusion VSSBD is located on a side of the lighting test area CTA close to the display area AA.
  • the reference power supply bus protrusion VSSBD and the common electrode layer can be closely adjacent to or even overlapped in the first peripheral region B1, reducing or eliminating the gap between the reference power supply bus protrusion VSSBD and the common electrode layer, thereby making The reference power bus bump VSSBD has better signal shielding capability.
  • the reference power bus protrusion VSSBD is located between the edge of the common electrode layer close to the first edge PL1 and the display area AA, which is far from the edge of the first edge PL1. In other words, there may be no gap between the reference power bus bump VSSBD and the common electrode layer. In this way, the touch signal trace TSL extends along the column direction to a path overlapping with the reference power bus bump VSSBD, which can sequentially overlap the common electrode layer and the reference power bus bump VSSBD to obtain a better signal shield.
  • the reference power bus protrusion VSSBD overlaps at least part of the first data transfer line D1L.
  • the protruding portion VSSBD of the reference power bus can shield at least part of the first data transfer line D1L, reducing or eliminating crosstalk from the first data transfer line D1L to the touch signal trace TSL.
  • the end of the display area AA close to the lighting test unit CT has an arc-shaped top angle.
  • the orthographic projection of the reference power bus protrusion VSSBD on the first edge PL1 at least partially overlaps with the orthographic projection of the arc vertex on the first edge PL1 .
  • the part of the first peripheral region B1 close to the top corner of the arc can neither be provided with a common electrode layer nor have a reference power supply bus VSSB trace; this makes the touch signal trace TSL near the top corner of the arc. Signal shielding cannot be obtained on the terminal side and there is a greater risk of crosstalk.
  • the protruding part VSSBD of the reference power bus is inserted between the apex of the arc and the lighting test unit CT, which overcomes the defect of lack of shielding of the touch signal trace TSL in this area, and can ensure that the touch signal trace stabilization of the sense signal on line TSL.
  • the region where the reference power bus bump VSSBD is disposed may be referred to as a bump region.
  • Part of the touch signal traces TSL can be bent in the protrusion area, for example, from extending along the row direction to extending along the column direction. In this way, the wiring of the touch signal wiring TSL can be more flexible, which is conducive to selecting a better wiring method according to the needs of the display panel.
  • the contact pads PAD are distributed into three contact pad groups, that is, the middle contact pad group MPADS located near the middle of the second edge PL2 and the middle contact pad group MPADS located at the first edge PL1
  • Two side contact pad sets EPADS are provided at the left and right ends.
  • the reference power supply contact pads for loading the reference power supply voltage to the reference power supply bus VSSB may be located in the side contact pad group EPADS.
  • the reference power distribution section VSSB1 may include a first wiring section VSSBA of a reference power bus, a second wiring section VSSBB of a reference power bus, a third wiring section VSSBC of a reference power bus, and a reference Power bus bump VSSBD.
  • the first trace section VSSBA of the reference power bus is connected to the reference power pad and extends to the far end to electrically connect with the second trace section VSSBB of the reference power bus; the width of the second trace section VSSBB of the reference power bus is larger than that of the first trace of the reference power bus.
  • the line segment VSSBA extends along the column direction; the third line segment VSSBC of the reference power supply bus is connected to the far end of the second line segment VSSBB of the reference power supply bus and extends toward the inner side of the first peripheral area B1 along the row direction until it is connected to the reference power supply section VSSB2 electrical connection.
  • the reference power bus protrusion VSSBD is connected to an inner end of the third reference power bus line segment VSSBC, and extends toward the inner side of the first peripheral area B1.
  • the third routing section VSSBC of the reference power bus has an inner section and an outer section, and a notch is provided on the side of the inner section near the first edge PL1 to avoid the lighting test unit CT.
  • the width (dimension along the column direction) of the reference power supply bus bump VSSBD is the same as the width (dimension along the column direction) of the inner section of the third trace section VSSBC of the reference power supply bus.
  • the touch signal traces TSL are divided into two groups corresponding to two reference power supply buses VSSB, and each group of touch signal traces TSL uses a corresponding reference power supply bus VSSB for signal shielding.
  • the touch signal pads connected to each group of touch signal traces TSL are adjacent to the reference power pads connected to the corresponding reference power bus VSSB.
  • each set of touch signal traces TSL overlaps with the second trace segment VSSBB of the corresponding reference power supply bus VSSB, and is connected to the corresponding touch signal pad; in the pad area PADA, The touch signal pad is located on the inner side of the reference power pad.
  • gate driving circuits are provided in the second peripheral area B2 and the fourth peripheral area B4 to load signals to at least some of the running lines.
  • the gate driving circuit can load scan signals to the scan lines.
  • the display panel may be provided with a gate drive signal line GOAL for loading control signals to the gate drive circuit in the first peripheral area B1, such as a clock line for loading timing signals to the gate drive circuit, a line for loading a high-level signal High-level traces, low-level traces loaded with low-level signals, etc.
  • pads for electrical connection with the gate driving signal line GOAL are provided so as to load signals to the gate driving circuit.
  • the pads electrically connected to the gate driving signal line GOAL are located outside the reference power pads.
  • the gate driving circuit is located at a side of the reference power supply segment VSSB2 close to the display area AA.
  • the driving power bus VDDB includes a first part UVDDB of a driving power bus, a third part DVDDB of a driving power bus, and a plurality of second parts MVDDB of a plurality of driving power buses; the driving power bus The first part UVDDB is located between the display area AA and the lighting test area CTA.
  • the third part of the drive power bus DVDDB is located on the side of the lighting test area CTA away from the display area AA; the lighting test area CTA includes a plurality of lighting test sub-areas SCTA; the second part of the driving power bus MVDDB It is located between each of the lighting test sub-areas SCTA, and is electrically connected to the first part UVDDB of the driving power bus and the third part DVDDB of the driving power bus.
  • the driving power bus VDDB includes a first part UVDDB of the driving power bus and a third part DVDDB of the driving power bus, both of which are extended along the row direction.
  • the pad includes a driving power pad for loading the driving power voltage;
  • the driving power bus VDDB also includes the fourth part of the driving power bus TVDDB between the first edge PL1 and the third part of the driving power bus DVDDB ;
  • One end of TVDDB, the fourth part of the driving power bus, is electrically connected to the driving power pad, and the other end is electrically connected to the third part of the driving power bus, DVDDB.
  • the third part DVDDB of the driving power bus is electrically connected to the driving power pad through the fourth part TVDDB of the driving power bus.
  • the contact pad PAD includes a driving power contact pad for loading the driving power voltage; the fourth part of the driving power bus TVDDB also extends outwards to be electrically connected with the driving power contact pad; the driving power bus No. The portion of the four-part TVDDB beyond the cutting line CL can be cut off in the cutting stage.
  • the driving power supply pads include side driving power supply pads respectively located at two ends of the pad area, and two middle driving power supply pads located in the middle of the pad area. There are four TVDDBs in the fourth part of the driving power bus, and they are respectively electrically connected to the four driving power pads.
  • the driving power contact pads include side driving power contact pads respectively located in the two side contact pad groups EPADS, and include two middle driving power contact pads located in the middle contact pad group MPADS .
  • the side drive power supply pad can be located inside the touch signal pad, so that the two sides of the touch signal pad are respectively provided with a reference power pad and a driving power pad to improve the control of the touch signal pad. shielding effect.
  • two middle driving power contact pads may be respectively located at two ends of the middle contact pad set MPADS, so as to provide a certain signal shielding effect to other contact pads PAD of the middle contact pad set MPADS.
  • the fourth drive power bus part TVDDB electrically connected to the side drive power pads may be electrically connected to the outer end (the outer end along the row direction) of the third drive power bus part DVDDB.
  • the third part DVDDB of the driving power bus is divided into two power sub-wires, and both ends of the power sub-wires pass through the fourth part TVDDB of the driving power bus and the driving power The pads are electrically connected.
  • the third part DVDDB of the driving power bus is divided into a left power sub-wiring and a right power sub-wiring.
  • the middle drive power pad on the left is electrically connected to the inner end (ie, the right end) of the left power sub-wire through the fourth part of the drive power bus TVDDB, and the middle drive power pad on the right is connected through the fourth part of the drive power bus TVDDB It is electrically connected with the inner end (ie, the left end) of the right power sub-trace. In this way, it can be ensured that the third part DVDDB of the driving power bus is evenly loaded with the driving power voltage and has a relatively uniform current.
  • the lighting test area CTA is divided into four lighting test sub-areas SCTA, that is, two side lighting test sub-areas SCTA located on both sides and a middle one located in the middle. Two midpoint lamp test sub-areas SCTA.
  • a lighting test jumper CTL extending along the row direction is arranged between two adjacent lighting test sub-areas SCTA, and control signals in two adjacent lighting test sub-areas SCTA are transmitted through the lighting test jumper CTL to ensure signal continuity.
  • the second part of the driving power bus MVDDB is arranged in the gap between the lighting test sub-areas SCTA.
  • the signal wiring of the lighting test unit CT is bridged through the lighting test jumper CTL located in the gate layer, for example, the first gate layer and the second gate layer are used at the same time.
  • the polarity is crossed to avoid driving the second part of the power bus, MVDDB.
  • the signal wiring of the lighting test unit CT can be bridged to dissipate the charge accumulated on the lighting test unit CT more effectively, and avoid electrostatic breakdown caused by the accumulation of static electricity on the lighting test unit CT.
  • the gap width (dimension along the row direction) between the mid-light test sub-area SCTA is greater than the gap width between the side light test sub-area SCTA and the mid-light test sub-area SCTA.
  • the near ends of the second part of the two driving power buses MVDDB are respectively electrically connected to the inner ends of the third part of the driving power bus DVDDB, and the far ends of the two second parts of the driving power buses MVDDB are respectively electrically connected to the first part of the driving power bus UVDDB.
  • the length of the first part UVDDB of the driving power bus is smaller than the length of the third part DVDDB of the driving power bus.
  • the first peripheral area B1 further includes a driver chip area ICA for binding driver chip ICs, and the driver chip area ICA is located between the third part DVDDB of the driver power bus and the first edge PL1 .
  • Connection lines are provided between the driver chip area ICA and the pads, the lighting test unit CT and the gate drive circuit, so that the driver chip IC interacts with the external circuit through the pad PAD, and loads signals to the lighting test unit CT and the gate drive circuit .
  • a second data transfer line D2L is provided between the lighting test area CTA and the driver chip area ICA, and the connection between the lighting test unit CT and the driver chip IC is through the second The data transfer cable D2L is electrically connected.
  • the second data transfer line D2L is arranged on the gate layer so as to avoid driving the third part DVDDB of the power bus.
  • the driver chip area ICA is divided into at least two sections along the row direction, so as to bind multiple driver chips.

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Abstract

一种显示面板和显示装置，属于显示技术领域。显示面板包括显示区(AA)和围绕显示区(AA)的外围区(BB)；外围区(BB)的第一外围区(B1)具有设置点灯测试单元(CT)的点灯测试区(CTA)。显示面板具有位于第一外围区(B1)远离显示区(AA)的一侧的第一边缘(PL1)。显示面板设置有参考电源总线(VSSB)和触控信号走线(TSL)；在第一外围区(B1)，参考电源总线(VSSB)具有参考电源总线凸出部(VSSBD)；参考电源总线凸出部(VSSBD)在第一边缘(PL1)上的正投影，位于点灯测试区(CTA)在第一边缘(PL1)上的正投影内；至少部分触控信号走线(TSL)与参考电源总线凸出部(VSSBD)交叠。该显示面板可以提高触控信号走线(TSL)布线时的灵活性。

Description

显示面板和显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板和显示装置。
背景技术
在柔性AMOLED(有源驱动式有机电致发光装置)触控一体化显示面板中，触控信号走线需要借助加载有参考电源电压的公共电极和参考电源总线进行屏蔽，以减少显示面板中的其他信号对触控信号走线的串扰。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板和显示装置，提高触控信号走线在布线时的灵活性。
根据本公开的第一个方面，提供一种显示面板，包括显示区和围绕所述显示区的外围区；所述外围区包括位于所述显示区一侧的第一外围区，所述第一外围区具有设置点灯测试单元的点灯测试区；所述显示面板具有第一边缘，所述第一边缘位于所述第一外围区远离所述显示区的一侧；
所述显示面板设置有参考电源总线和触控信号走线；在所述第一外围区，所述参考电源总线具有参考电源总线凸出部；所述参考电源总线凸出部在所述第一边缘上的正投影，位于所述点灯测试区在所述第一边缘上的正投影内；至少部分所述触控信号走线与所述参考电源总线凸出部交叠。
根据本公开的一种实施方式，所述参考电源总线凸出部位于所述点灯测试单元靠近所述显示区的一侧。
根据本公开的一种实施方式，所述显示区靠近所述点灯测试单元的一端具有弧形顶角；
所述参考电源总线凸出部在所述第一边缘上的正投影，与所述弧形顶角在所述第一边缘上的正投影至少部分重叠。
根据本公开的一种实施方式，所述显示面板包括像素层，所述像素层具有用于加载参考电源电压的公共电极层；所述公共电极层覆盖所述显示区；
所述参考电源总线凸出部远离所述第一边缘的边缘，位于所述公共电极层靠近所述第一边缘的边缘和所述显示区之间。
根据本公开的一种实施方式，所述参考电源总线凸出部所处的区域为凸出部区域，至少部分所述触控信号走线在所述凸出部区域弯折。
根据本公开的一种实施方式，所述显示面板在所述显示区设置有数据走线，在所述显示区和所述点灯测试区之间设置有第一数据转接线；
所述数据走线与所述点灯测试单元通过所述第一数据转接线电连接；
所述参考电源总线凸出部与至少部分所述第一数据转接线交叠。
根据本公开的一种实施方式，所述显示面板还设置有位于所述第一外围区的驱动电源总线；
所述驱动电源总线包括驱动电源总线第一部分、驱动电源总线第三部分和多个驱动电源总线第二部分；所述驱动电源总线第一部分位于所述显示区和所述点灯测试区之间；
所述驱动电源总线第三部分位于所述点灯测试区远离所述显示区的一侧；
所述点灯测试区包括多个点灯测试子区；所述驱动电源总线第二部分位于各个所述点灯测试子区之间，且与所述驱动电源总线第一部分、驱动电源总线第三部分电连接。
根据本公开的一种实施方式，所述显示面板设置有沿第一边缘排列的焊盘；所述焊盘包括用于加载驱动电源电压的驱动电源焊盘；
所述驱动电源总线还包括驱动电源总线第四部分；所述驱动电源总线第三部分通过所述驱动电源总线第四部分与所述驱动电源焊盘电连接。
根据本公开的一种实施方式，所述驱动电源焊盘的数量为多个且与所述驱动电源总线第三部分的各个端部一一对应；所述驱动电源总线第四部分的数量为多个且与所述驱动电源总线第三部分的各个端部一一对应；
所述驱动电源总线第三部分的各个端部均通过对应的所述驱动电源总线第四部分电连接至对应的所述驱动电源焊盘。
根据本公开的一种实施方式，所述驱动电源总线第三部分被分割为两个电源子走线；每个所述电源子走线的端部均通过所述驱动电源总线第四部分与所述驱动电源焊盘电连接。
根据本公开的一种实施方式，所述驱动电源总线第一部分的长度小于所述驱动电源总线第三部分的长度。
根据本公开的一种实施方式，所述驱动电源总线第一部分在所述第一边缘上的正投影，与所述参考电源总线凸出部在所述第一边缘上的正投影不重合。
根据本公开的一种实施方式，所述显示面板在所述第一外围区还设置有用于绑定驱动芯片的驱动芯片区；所述驱动电源总线第一部分设置于所述驱动芯片区和所述点灯测试区之间。
根据本公开的一种实施方式，所述显示面板包括依次层叠设置的衬底基板、驱动层、像素层、薄膜封装层和触控层；
所述触控信号走线设置于所述触控层；
所述驱动层包括源漏金属层，所述驱动电源总线和所述参考电源总线设置于所述源漏金属层。
根据本公开的第二个方面，提供一种显示装置，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种实施方式中，显示面板的结构示意图。
图2为本公开一种实施方式中，中间模组的结构示意图。
图3为本公开一种实施方式中，中间模组的源漏金属层在近端的结构示意图。
图4为本公开一种实施方式中，中间模组的源漏金属层在近端的局部结构放大示意图。
图5为本公开一种实施方式中，中间模组的部分走线在近端的局部结构示意图。
图6为本公开一种实施方式中，点灯测试单元之间通过点灯测试跨接线保持信号连续的结构示意图。
图7为本公开一种实施方式中，参考电源总线凸出部与部分第一数据转接线交叠的结构示意图。
图8为本公开一种实施方式中，显示面板的膜层结构示意图。
图9为本公开一种实施方式中，显示面板的触控层的触控电极的结构示意图。
图10为触控层沿图9中的P1P2方向进行剖切的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个 或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开提供一种显示面板以及基于该显示面板的显示装置。参见图8，本公开的显示面板包括依次层叠设置的衬底基板F100、驱动层F200、像素层F300、薄膜封装层F400和触控层F500。所述像素层F300设置有用于显示画面的子像素F300D；驱动层中设置有用于驱动子像素的像素驱动电路。在触控层F500，设置有用于感测触控动作的触控电极和传输触控感测信号的触控信号走线TSL。如此，本公开的显示面板可以实现显示和触控功能。
在本公开中，描述A结构与B结构相互交叠时，指的是A结构与B结构位于不同的膜层，且A结构在衬底基板上的正投影与B结构在衬底基板上的正投影存在相互重合的部分。
结构层C位于结构层D背离衬底基板的一侧，可以理解为，结构层C在结构层D背离衬底基板的一侧形成。当结构层D为图案化结构时，结构层C的部分结构也可以位于结构层D的同一物理高度或低于结构层D的物理高度，其中，衬底基板为高度基准。
本公开的实施方式中，衬底基板F100可以为无机材料的衬底基板F100，也可以为有机材料的衬底基板F100。举例而言，在本公开的一种实施方式中，衬底基板F100的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板F100的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。在本公开的另一种实施方式中，衬底基板F100也可以为柔性衬底基板F100，例如衬底基板F100的材料可以为聚酰亚胺(polyimide，PI)。衬底基板F100还可以为多层材料的复合， 举例而言，在本公开的一种实施方式中，衬底基板F100可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
驱动层F200设置有用于驱动子像素的像素驱动电路。在驱动层F200中，任意一个像素驱动电路可以包括有晶体管F200M和存储电容。进一步地，晶体管F200M可以为薄膜晶体管，薄膜晶体管可以选自顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管；薄膜晶体管的有源层的材料可以为非晶硅半导体材料、低温多晶硅半导体材料、金属氧化物半导体材料、有机半导体材料或者其他类型的半导体材料；薄膜晶体管可以为N型薄膜晶体管或者P型薄膜晶体管。
可以理解的是，像素驱动电路中的各个晶体管中，任意两个晶体管之间的类型可以相同或者不相同。示例性地，在一种实施方式中，在一个像素驱动电路中，部分晶体管可以为N型晶体管且部分晶体管可以为P型晶体管。再示例性地，在本公开的另一种实施方式中，在一个像素驱动电路中，部分晶体管的有源层的材料可以为低温多晶硅半导体材料，且部分晶体管的有源层的材料可以为金属氧化物半导体材料。在本公开的一些实施方式中，薄膜晶体管为低温多晶硅晶体管。在本公开的另外一些实施方式中，部分薄膜晶体管为低温多晶硅晶体管，部分薄膜晶体管为金属氧化物晶体管。
可选地，驱动层F200可以包括层叠于衬底基板F100和像素层F300之间的半导体层F203、栅极绝缘层F204、栅极层F205、层间电介质层F206和源漏金属层F207等。各个薄膜晶体管和存储电容可以由半导体层F203、栅极绝缘层F204、栅极层F205、层间电介质层F206、源漏金属层F207等膜层形成。其中，各个膜层的位置关系可以根据薄膜晶体管的膜层结构确定。进一步地，半导体层F203可以用于形成晶体管的沟道区；栅极层可以用于形成扫描走线、复位控制走线、发光控制走线等栅极层走线，也可以用于形成晶体管的栅极，还可以用于形成存储电容的部分或者全部电极板。源漏金属层可以用于形成用于加载驱动数据的数据走线、用于加载驱动电源电压的驱动电源走线等源漏金属层走线，也可以用于形成存储电容的部分电极板。
举例而言，在本公开的一些实施方式中，驱动层F200可以包括依次层叠设置的半导体层F203、栅极绝缘层F204、栅极层F205、层间电介质层F206和源漏金属层F207，如此所形成的薄膜晶体管为顶栅型薄膜晶体管。
再举例而言，在本公开的一些实施方式中，驱动层F200可以包括依次层叠设置的栅极层F205、栅极绝缘层F204、半导体层F203、层间电介质层F206和源漏金属层F207，如此所形成的薄膜晶体管为底栅型薄膜晶体管。
在一些实施方式中，栅极层可以为两层或者三层。举例而言，在本公开的一种实施方式中，栅极层F205可以包括第一栅极层和第二栅极层，栅极绝缘层F204可以包括用于隔离半导体层F203和第一栅极层的第一栅极绝缘层，以及包括用于隔离第一栅极层和第二栅极层的第二栅极绝缘层。示例性地，驱动层F200可以包括依次层叠设置于衬底基板F100一侧的半导体层F203、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层、层间电介质层F206和源漏金属层F207。再举例而言，在本公开的一种实施方式中，栅极层F205可以包括第一栅极层和第二栅极层，半导体层F203可以夹设于第一栅极层和第二栅极层之间；栅极绝缘层F204可以包括用于隔离半导体层F203和第一栅极层的第一栅极绝缘层，以及包括用于隔离第二栅极层和半导体层F203的第二栅极绝缘层。示例性地，在本公开的一种实施方式中，驱动层F200可以包括依次层叠设置于衬底基板F100一侧的第一栅极层、第一栅极绝缘层、半导体层F203、第二栅极绝缘层、第二栅极层、层间电介质层F206和源漏金属层F207。这样，可以形成具有双栅结构的晶体管。再举例而言，在本公开的一种实施方式中，半导体层F203可以包括低温多晶硅半导体层和金属氧化物半导体层；栅极层包括第一栅极层和第二栅极层，栅极绝缘层包括第一和第二栅极绝缘层。驱动层F200可以包括依次层叠设置于衬底基板F100一侧的低温多晶硅半导体层、第一栅极绝缘层、第一栅极层、金属氧化物半导体层、第二栅极绝缘层、第二栅极层、层间电介质层F206和源漏金属层F207。再举例而言，在本公开的一种实施方式中，半导体层F203可以包括低温多晶硅半导体层和金属氧化物半导体层；栅极层包括第一至第三栅极层，栅 极绝缘层包括第一至第三栅极绝缘层。驱动层F200可以包括依次层叠设置于衬底基板F100一侧的低温多晶硅半导体层、第一栅极绝缘层、第一栅极层、绝缘缓冲层、第二栅极层、第二栅极绝缘层、金属氧化物半导体层、第三栅极绝缘层、第三栅极层、层间电介质层F206和源漏金属层F207。
在一些实施方式中，源漏金属层可以为两层或者三层。举例而言，在本公开的一种实施方式中，源漏金属层可以包括依次层叠于层间电介质层F206远离衬底基板一侧的第一源漏金属层和第二源漏金属层，第一源漏金属层和第二源漏金属层之间可以夹设于绝缘层，例如夹设有钝化层和/或平坦化层。再举例而言，在本公开的一种实施方式中，源漏金属层可以包括依次层叠于层间电介质层F206远离衬底基板一侧的第一源漏金属层、第二源漏金属层、第三源漏金属层；第一源漏金属层和第二源漏金属层之间可以夹设于绝缘层，例如夹设有钝化层和/或树脂层；第二源漏金属层和第三源漏金属层之间可以夹设于绝缘层，例如夹设有钝化层和/或平坦化层。
可选地，驱动层F200还可以包括有钝化层，钝化层可以设于源漏金属层F207远离衬底基板F100的表面，以便保护源漏金属层F207。
可选地，驱动层F200还可以包括设于衬底基板F100与半导体层F203之间的缓冲材料层F201，且半导体层F203、栅极层F205等均位于缓冲材料层远离衬底基板F100的一侧。缓冲材料层的材料可以为氧化硅、氮化硅等无机绝缘材料。缓冲材料层可以为一层无机材料层，也可以为多层层叠的无机材料层。
可选地，驱动层F200还可以包括位于源漏金属层F207和像素层F300之间的平坦化层F208，平坦化层F208可以为像素电极提供平坦化表面。可选地，平坦化层F208的材料可以为有机材料。
像素层设置有阵列分布的子像素，且各个子像素在像素驱动电路的控制下发光。在本公开中，子像素可以为有机电致发光二极管(OLED)、微发光二极管(Micro LED)、量子点-有机电致发光二极管(QD-OLED)、量子点发光二极管(QLED)或者其他类型的发光元件。示例性地，在本公开的一种实施方式中，子像素为有机电致发光二极管(OLED)，则该显示面板为OLED显示面板。如下，以子像素为有机电致发光二极管为例，对像素层的一种可行结构进行示例性的介绍。
可选地，像素层F300可以设置于驱动层F200远离衬底基板F100的一侧，其可以包括依次层叠设置的像素电极层F301、像素定义层F302、支撑柱层F303、有机发光功能层F304和公共电极层F305。其中，像素电极层F301在显示面板的显示区具有多个像素电极；像素定义层F302在显示区具有与多个像素电极一一对应设置的多个贯通的像素开口，任意一个像素开口暴露对应的像素电极的至少部分区域。支撑柱层F303在显示区包括多个支撑柱，且支撑柱位于像素定义层F302远离衬底基板F100的表面，以便在蒸镀制程中支撑精细金属掩模版(Fine Metal Mask，FMM)。有机发光功能层F304至少覆盖被像素定义层F302所暴露的像素电极。其中，有机发光功能层F304可以包括有机电致发光材料层，以及可以包括有空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一种或者多种。可以通过蒸镀工艺制备有机发光功能层F304的各个膜层，且在蒸镀时可以采用精细金属掩模版或者开放式掩膜板(Open Mask)定义各个膜层的图案。公共电极层F305在显示区可以覆盖有机发光功能层F304。如此，像素电极、公共电极层F305和位于像素电极和公共电极层F305之间的有机发光功能层F304形成有机发电致光二极管F300D，任意一个有机电致发光二极管可以作为显示面板的一个子像素。像素驱动电路在工作时，其驱动晶体管的源极可以加载驱动电源电压，驱动晶体管的栅极可以加载与数据电压相关的电压，其漏极可以与子像素的像素电极电连通；子像素的公共电极可以加载参考电源电压以作为公共电极电压。驱动晶体管在其栅极上的电压的控制下输出驱动电流，子像素在驱动电流的驱动下发光。
在一些实施方式中，像素层F300还可以包括位于公共电极层F305远离衬底基板F100一侧的光取出层，以增强有机发光二极管的出光效率。
可选地，显示面板还可以包括薄膜封装层F400。薄膜封装层F400设于像素层F300远离衬底基板F100的表面，可以包括交替层叠设置的无机封装层和有机封装层。其中，无机封装层可以有效的阻隔外界的水分和氧气，避免水氧入侵有机发光功能层F304而导致材料降解。可选地，无机封装层的边缘可以位于外围区。有机封装层位于相邻的两层无机封装层之间，以便实现平坦化和减弱无机封装层之间的应力。其中，有机封装层的 边缘，可以位于显示区的边缘和无机封装层的边缘之间。示例性地，薄膜封装层F400包括依次层叠于像素层F300远离衬底基板F100一侧的第一无机封装层F401、有机封装层F402和第二无机封装层F403。
触控层F500设于薄膜封装层F400远离衬底基板F100的一侧，用于实现显示面板的触控操作。参见图9和图10，触控层F500可以包括依次层叠设置的第一触控金属层F501、触控绝缘层F502和第二触控金属层F503；第二触控金属层F503位于第一触控金属层F501远离衬底基板F100的一侧。第一触控金属层F501和第二触控金属层F503中的一层或者两层用于形成触控电极F510。在本公开的一种实施方式中，触控层F500设置于薄膜封装层F400远离衬底基板的一侧。
可选地，在第一触控金属层F501与薄膜封装层F400之间还可以包括触控缓冲层。触控缓冲层的材料可以为无机材料，例如可以为氮化硅、氧化硅或者氮氧化硅等。可以理解的是，在本公开的其他实施方式中，薄膜封装层F400最外侧的无机封装层，也可以复用为触控缓冲层。
可选地，在第二触控金属层F503远离衬底基板F100的一侧还可以包括触控保护层。触控保护层的材料可以为无机材料，例如可以为氮化硅、氧化硅或者氮氧化硅等。可以理解的是，在本公开的其他实施方式中，第二触控金属层F503远离衬底基板F100的一侧也可以直接设置有机层，例如设置有机盖板或者设置光学胶等。
可选地，第一触控金属层F501和第二触控金属层F503可以为透光膜层，以使得所形成的触控电极F510为透明电极为准。在本公开的一种实施方式中，第一触控金属层F501和第二触控金属层F503的材料可以为透光材料，例如可以采为透明导电金属氧化物(如氧化铟锡等)。
触控电极F510的形状和位置，可以根据触控显示面板的需要进行设置，以使得触控层F500能够基于自容或者互容原理确定触控位置为准。触控层F500还可以用于形成触控走线，以便将触控电极F510相应触控动作而产生的信号传导出来。
举例而言，在本公开的一种实施方式中，参见图10，触控电极F510包括多个沿行方向H1延伸的行触控电极F512和多个沿列方向H2延伸的列触控电极F511。各个行触控电极F512沿列方向H2依次排列，各个列 触控电极F511沿行方向H1依次排列。其中，任意一个列触控电极F511设置于第二触控金属层F503，且包括沿列方向H2依次排列的多个列触控子电极F5111，相邻两个列触控子电极F5111的端部相互连接。如此，列触控电极F511完全设置于第二触控金属层F503。任意一个行触控电极F512包括沿行方向H1依次排列的多个行触控子电极F5121，行触控子电极F5121设置于第二触控金属层F503，且其边缘与列触控子电极F5111的边缘相邻设置。在任意一个行触控电极F512中，相邻两个行触控子电极F5121之间被列触控电极F511隔离，且相邻两个行触控子电极F5121之间通过位于第一触控金属层F501的桥接连接部F5131连接。
再举例而言，在本公开的另一种实施方式中，触控电极包括多个沿行方向延伸的行触控电极和多个沿列方向延伸的列触控电极。各个行触控电极沿列方向依次排列，各个列触控电极沿行方向依次排列。其中，任意一个行触控电极设置于第二触控金属层，且包括沿行方向依次排列的多个行触控子电极，相邻两个行触控子电极的端部相互连接。如此，行触控电极完全设置于第二触控金属层。任意一个列触控电极包括沿列方向依次排列的多个列触控子电极，列触控子电极设置于第二触控金属层，且其边缘与行触控子电极的边缘相邻设置。在任意一个列触控电极中，相邻两个列触控子电极之间被行触控电极隔离，且相邻两个列触控子电极之间通过位于第一触控金属层的桥接连接部连接。
再举例而言，在本公开的另一种实施方式中，触控电极包括多个沿行方形延伸的行触控电极和多个沿列方向延伸的列触控电极。各个行触控电极沿列方向依次排列，且各个列触控电极沿行方向依次排列。其中，行触控电极和列触控电极中的一个，设置于第一触控金属层，且另一个设置于第二触控金属层。如此，行触控电极和列触控电极之间相互交叠且形成互容电容。当触控层被手指等触控物按压时，行触控电极和列触控电极之间的互容电容发生改变。
再举例而言，在本公开的另一种实施方式中，触控电极阵列分布于第二触控金属层，触控走线通过第一触控金属层延伸至与各个触控电极通过过孔连接。
可选地，显示面板还可以包括降反层F600，降反层F600可以设置于 薄膜封装层F400远离像素层F300的一侧，用于降低显示面板对环境光线的反射，进而降低环境光线对显示效果的影响。
示例性地，降反层F600可以包括层叠设置的彩膜层和黑矩阵层，如此可以在实现降低环境光线干扰的同时，提高出光纯度以提高显示面板的色域。进一步地，降反层F600设置于薄膜封装层和触控层之间。
再示例性地，降反层F600可以为偏光片，例如可以为图案化的涂布型圆偏光片。进一步地，降反层F600可以设置于触控层F500远离衬底基板F100的一侧。
图1为本公开一种实施方式中，显示面板的俯视结构示意图。参见图1，本公开的显示面板包括显示区AA和围绕显示区AA的外围区BB。在显示区AA，显示面板设置有子像素和驱动子像素的像素驱动电路，以及设置有用于向像素驱动电路加载信号或者接收像素驱动电路的反馈信号的走线。这些走线可以包括沿行方向DH延伸的行走线，例如包括用于加载扫描信号的扫描走线、用于加载发光控制信号的发光控制走线、用于加载复位控制信号的复位控制走线、用于加载初始化电压的初始化走线等走线中的一种或者多种，亦或包括其他所需的走线。这些走线还可以沿列方向DV延伸的列走线，例如包括用于加载驱动数据的数据走线、用于加载驱动电源电压的驱动电源线VDDL等。
参见图1，外围区BB可以包括依次连接的第一外围区B1、第二外围区B2、第三外围区B3和第四外围区B4。其中，第一外围区B1和第三外围区B3分别位于显示区AA相对的两侧，且沿行方向DH延伸。换言之，沿列方向，第一外围区B1、显示区AA和第三外围区B3依次排列。第二外围区B2和第四外围区B4分别位于显示区AA相对的两侧，且沿列方向DV延伸；换言之，沿行方向，第二外围区B2、显示区AA和第四外围区B4依次排列。第一外围区B1的外侧边缘(即第一外围区B1远离显示区AA的边缘)可以定义为第一边缘PL1。换言之，所述显示面板具有第一边缘PL1，所述第一外围区B1位于所述第一边缘PL1与所述显示区AA之间。显示面板可以设置有沿第一边缘PL1延伸的焊盘区PADA，焊盘区PADA中设置有沿第一边缘PL1排列的多个焊盘，以便与外部电路绑定连接，例如与柔性电路板、覆晶薄膜、印刷电路板或者其他电路结构绑定连 接。本公开的显示装置(例如采用本公开的显示面板的手机屏幕、平板电脑、笔记本电脑、可交互电子广告牌等装置)具有控制器，控制器可以作为显示面板的外部电路而与焊盘区PADA中的焊盘绑定连接。
在本公开中，为了表述方便，可以将靠近第一边缘PL1的一端称为显示面板的近端，将靠近第三外围区B3的一端称为显示面板的远端，将靠近第二外围区B2的一侧定义为左侧，将靠近第四外围区B4的一侧定义为右侧。可以理解的是，本公开中的“远端”、“近端”、“右侧”、“左侧”均为相对的概念而非其通常的含义，其用于表述各个结构之间的相对位置关系而非绝对位置关系。
参见图3～图6，第一外围区B1具有设置点灯测试单元CT的点灯测试区CTA，以及具有设置在点灯测试区CTA和显示区AA之间的第一数据转接线D1L。数据走线通过第一数据转接线D1L与点灯测试单元CT之间电连接。这样，在显示面板在制备过程的点灯测试(cell test)阶段，点灯测试单元CT可以实现对显示面板进行点灯测试，例如检测是否有亮点、色斑、污点、亮线等不良。
显示面板在制备过程中可以呈现为中间模组，图2和图3示例了中间模组的一种结构示意图。相较于显示面板，中间模组具有一个或者多个辅助区，辅助区可以在切割阶段被切除。在一种示例中，参见图2和图3，中间模组包括位于第一外围区B1远离显示区AA一侧的第一辅助区Dum1、位于第二外围区B2离显示区AA一侧的第二辅助区Dum2、位于第四外围区B4离显示区AA一侧第三辅助区Dum3。在切除这些辅助区时，可以沿着切割线CL进行切割。参见图2和图3，在切割之前，中间模组的近端一侧的边缘为第二边缘PL2，第二边缘PL2位于第一辅助区Dum1远离显示区AA的一侧。参见图2和图3，第一辅助区Dum1中设置有沿第二边缘PL2排列的接触垫PAD；在点灯测试阶段，检测设备的探针可以压覆在接触垫PAD上，以便向中间模组加载检测信号。在切割阶段，这些接触垫PAD可以被切除。可以理解的是，在本公开的其他实施方式中，中间模组可以具有其他的辅助区或者具有更少的辅助区，例如只具有第一辅助区Dum1而没有第二辅助区Dum2和第三辅助区Dum3。
在本公开的一种实施方式中，点灯测试单元CT可以包括一行或者多 行检测晶体管，检测晶体管的输入端用于加载检测信号或者驱动数据。检测晶体管的栅极与检测控制线电连接，检测晶体管的输出端通过第一数据转接线D1L与数据走线电连接。
在本公开的一种实施方式中，第一数据转接线D1L设置于栅极层，例如设置有第一栅极层、第二栅极层中的一层或者两层。
参见图1，显示面板在外围区BB设置有用于加载参考电源电压的参考电源总线VSSB和用于加载驱动电源电压的驱动电源总线VDDB。在一些实施方式中，参考电源总线VSSB和驱动电源总线VDDB可以设置于源漏金属层。
参见图1，参考电源总线VSSB可以包括左右两条，以分别通过第二外围区B2和第四外围区B4向公共电极层提供参考电源电压。具体的，参考电源总线VSSB包括位于第一外围区B1的参考电源布电段VSSB1和位于第二外围区B2或者第四外围区B4的参考电源供电段VSSB2。参考电源布电段VSSB1位于第一外围区B1的端部，例如设置于第一外围区B1的左端或者右端。参考电源布电段VSSB1的近端与焊盘区PADA中的参考电源焊盘电连接。参考电源布电段VSSB1的远端与参考电源供电段VSSB2电连接。公共电极层覆盖显示区AA并延伸至第二外围区B2和第四外围区B4中，且通过过孔与参考电源供电段VSSB2电连接。
参见图1，驱动电源总线VDDB设置于第一外围区B1且位于两个参考电源总线VSSB之间，其可以从第一外围区B1直接向显示区AA的驱动电源线VDDL供电。换言之，驱动电源总线VDDB至少部分设置于点灯测试区CTA和显示区AA之间，且与至少部分驱动电源线VDDL直接电连接。
参见图1，触控层的至少部分触控信号走线TSL可以布设于外围区BB中，例如分别从第二外围区B2和第四外围区B4向第一外围区B1走线，以便在第一外围区B1与驱动芯片或者外部电路电连接。触控信号走线TSL在走线时，可以与参考电源总线VSSB或者公共电极层交叠以实现信号屏蔽，保证触控信号走线TSL上的触控感测信号的稳定性，减少显示面板中其他信号对触控信号走线TSL的串扰。
在相关技术中，驱动电源总线VDDB完全设置于点灯测试区CTA与 显示区AA之间，其在第一边缘PL1上的正投影完全覆盖点灯测试单元CT在第一边缘PL1上的正投影。参考电源布电段VSSB1在布线时需要避让驱动电源总线VDDB，即参考电源布电段VSSB1在第一边缘PL1上的正投影与点灯测试单元CT在第一边缘PL1上的正投影不交叠。然而，这种设置方式导致参考电源布电段VSSB1在行方向上的宽度比较小，这导致触控信号走线TSL需要保持较小的线宽才能够与参考电源布电段VSSB1交叠以实现信号屏蔽，这既不利于提高触控信号走线TSL的数量(进而提高触控电极的数量)以提高触控精度，也不利于增大触控信号走线TSL的宽度以降低触控感测信号的压降。
参见图1，在本公开提供的显示面板中，在第一外围区B1，所述参考电源总线VSSB具有参考电源总线凸出部VSSBD；所述参考电源总线凸出部VSSBD在所述第一边缘PL1上的正投影，位于所述点灯测试区CTA在所述第一边缘PL1上的正投影内。换言之，参考电源布电段VSSB1设置有参考电源总线凸出部VSSBD，该参考电源总线凸出部VSSBD可以向第一外围区B1的内侧(第一外围区B1在行方向上的中间一侧)延伸以增大参考电源布电段VSSB1的宽度。至少部分触控信号走线TSL与参考电源总线凸出部VSSBD交叠，以通过参考电源总线凸出部VSSBD进行信号屏蔽。这样，本公开的显示面板可以增大触控信号走线TSL的宽度以使得部分触控信号走线TSL与参考电源总线凸出部VSSBD交叠，也可以增加触控信号走线TSL的数量以使得部分触控信号走线TSL与参考电源总线凸出部VSSBD交叠，这些方式均克服了参考电源布电段VSSB1的宽度小而对触控信号走线TSL布线的制约，可以提高触控的准确性或者触控精度，并提高触控触控信号走线TSL布线的灵活性。
参见图1，在本公开的一种实施方式中，所述参考电源总线凸出部VSSBD位于所述点灯测试区CTA靠近所述显示区AA的一侧。这样，可以使得参考电源总线凸出部VSSBD与公共电极层在第一外围区B1尽可能紧邻甚至交叠，减小或者消除参考电源总线凸出部VSSBD与公共电极层之间的间隙，进而使得参考电源总线凸出部VSSBD具有较好的信号屏蔽能力。
在一种示例中，所述参考电源总线凸出部VSSBD远离所述第一边缘 PL1的边缘，位于所述公共电极层靠近所述第一边缘PL1的边缘和所述显示区AA之间。换言之，参考电源总线凸出部VSSBD与公共电极层之间可以没有间隙。这样，触控信号走线TSL沿列方向延伸至与参考电源总线凸出部VSSBD交叠的路径中，其可以依次与公共电极层、参考电源总线凸出部VSSBD交叠，获得较好的信号屏蔽。
在一种示例中，所述参考电源总线凸出部VSSBD与至少部分所述第一数据转接线D1L交叠。这样，参考电源总线凸出部VSSBD可以屏蔽至少部分第一数据转接线D1L，降低或者消除第一数据转接线D1L对触控信号走线TSL的串扰。
在本公开的一种实施方式中，参见图3，所述显示区AA靠近点灯测试单元CT的一端具有弧形顶角。所述参考电源总线凸出部VSSBD在所述第一边缘PL1上的正投影，与所述弧形顶角在所述第一边缘PL1上的正投影至少部分重叠。在相关技术中，第一外围区B1靠近弧形顶角的部分既不能设置有公共电极层，也没有参考电源总线VSSB走线；这使得，触控信号走线TSL在弧形顶角的近端一侧无法获得信号屏蔽而存在较大的串扰风险。而在本实施方式中，参考电源总线凸出部VSSBD插入弧形顶角与点灯测试单元CT之间，克服了该区域缺失对触控信号走线TSL的屏蔽的缺陷，可以保证触控信号走线TSL上的感测信号的稳定。
在本公开的一种实施方式中，可以将设置参考电源总线凸出部VSSBD的区域称为凸出部区域。部分触控信号走线TSL在凸出部区域可以弯折，例如从沿行方向延伸弯折至沿列方向延伸。这样，触控信号走线TSL的布线可以更为灵活，利于根据显示面板的需要而选择更佳的布线方式。
在本公开的一些实施方式中，参见图2，在中间模组中，接触垫PAD分布成三个接触垫组，即靠近第二边缘PL2中间设置的中接触垫组MPADS和位于第一边缘PL1左右两端设置的两个侧接触垫组EPADS。其中，在点灯测试阶段，用于向参考电源总线VSSB加载参考电源电压的参考电源接触垫可以位于侧接触垫组EPADS。
在本公开的一种实施方式中，参见图1，参考电源布电段VSSB1可以包括参考电源总线第一走线段VSSBA、参考电源总线第二走线段VSSBB、 参考电源总线第三走线段VSSBC和参考电源总线凸出部VSSBD。其中，参考电源总线第一走线段VSSBA连接参考电源焊盘并向远端延伸至与参考电源总线第二走线段VSSBB电连接；参考电源总线第二走线段VSSBB的宽度大于参考电源总线第一走线段VSSBA且沿列方向延伸；参考电源总线第三走线段VSSBC连接于参考电源总线第二走线段VSSBB的远端并沿行方向向第一外围区B1的内侧延伸，直至与参考电源供电段VSSB2电连接。参考电源总线凸出部VSSBD连接于参考电源总线第三走线段VSSBC的内侧一端，并向第一外围区B1的内侧延伸。
在一种示例中，参见图4，参考电源总线第三走线段VSSBC具有内侧段和外侧段，内侧段靠近第一边缘PL1的一侧设置有缺口以避让点灯测试单元CT。参考电源总线凸出部VSSBD的宽度(沿列方向上的尺寸)与参考电源总线第三走线段VSSBC的内侧段的宽度(沿列方向的尺寸)相同。
在一种示例中，参见图1和图4，参考电源总线第二走线段VSSBB的外侧边缘(在行方向上的外侧边缘)与参考电源总线第一走线段VSSBA的外侧边缘(在行方向上的外侧边缘)齐平。
在一种示例中，触控信号走线TSL分为与两个参考电源总线VSSB对应的两组，每组触控信号走线TSL采用对应的参考电源总线VSSB进行信号屏蔽。其中，每组触控信号走线TSL所连接的触控信号焊盘与对应的参考电源总线VSSB所连接的参考电源焊盘相邻。举例而言，每组触控信号走线TSL与对应的参考电源总线VSSB的参考电源总线第二走线段VSSBB交叠设置，并连接至对应的触控信号焊盘；在焊盘区PADA中，触控信号焊盘位于参考电源焊盘的内侧。
在本公开的一种实施方式中，在第二外围区B2和第四外围区B4中设置有栅极驱动电路，以便向至少部分行走线加载信号。举例而言，栅极驱动电路可以向扫描走线加载扫描信号。显示面板在第一外围区B1可以设置有用于向栅极驱动电路加载控制信号的栅极驱动信号线GOAL，例如用于向栅极驱动电路加载时序信号的时钟走线、加载高电平信号的高电平走线、加载低电平信号的低电平走线等。在焊盘区中，设置有用于与栅极驱动信号线GOAL电连接的焊盘，以便向栅极驱动电路加载信号。
在一种示例中，沿行方向，在焊盘区，与栅极驱动信号线GOAL电连接的焊盘位于参考电源焊盘的外侧。
在一种示例中，栅极驱动电路位于参考电源供电段VSSB2靠近显示区AA的一侧。
在本公开的一些实施方式中，参见图1，所述驱动电源总线VDDB包括驱动电源总线第一部分UVDDB、驱动电源总线第三部分DVDDB和多个驱动电源总线第二部分MVDDB；所述驱动电源总线第一部分UVDDB位于所述显示区AA和所述点灯测试区CTA之间。所述驱动电源总线第三部分DVDDB位于所述点灯测试区CTA远离所述显示区AA的一侧；所述点灯测试区CTA包括多个点灯测试子区SCTA；所述驱动电源总线第二部分MVDDB位于各个所述点灯测试子区SCTA之间，且与所述驱动电源总线第一部分UVDDB、驱动电源总线第三部分DVDDB电连接。这样，尽管驱动电源总线第一部分UVDDB向内侧收缩而导致驱动电源总线第一部分UVDDB的总长度减小，但是通过设置驱动电源总线第三部分DVDDB和多个驱动电源总线第二部分MVDDB，可以使得驱动电源总线VDDB呈网格化且布线面积增大。一方面这使得驱动电源总线VDDB整体上阻抗降低，减小了驱动电源总线VDDB的压降；另一方面，这使得驱动电源总线VDDB上的电流获得更好的均一性。进一步地，驱动电源总线VDDB包括驱动电源总线第一部分UVDDB、驱动电源总线第三部分DVDDB均沿行方向延伸设置。
在焊盘区，焊盘中包括用于加载驱动电源电压的驱动电源焊盘；驱动电源总线VDDB还包括位于第一边缘PL1和驱动电源总线第三部分DVDDB之间的驱动电源总线第四部分TVDDB；驱动电源总线第四部分TVDDB一端与驱动电源焊盘电连接，另一端与驱动电源总线第三部分DVDDB电连接。这样，驱动电源总线第三部分DVDDB通过驱动电源总线第四部分TVDDB与驱动电源焊盘电连接。这避免了驱动电源总线第四部分TVDDB直接连接至驱动电源总线第一部分UVDDB时挤压参考电源总线凸出部VSSBD的空间，既可以保证参考电源总线凸出部VSSBD具有较大的尺寸，又可以保证驱动电源电压VDD有效地加载至驱动电源总线第一部分UVDDB。
相应的，在中间模组中，接触垫PAD中包括用于加载驱动电源电压的驱动电源接触垫；驱动电源总线第四部分TVDDB还向外延伸以与驱动电源接触垫电连接；驱动电源总线第四部分TVDDB超出切割线CL的部分可以在切割阶段被切除。
在本公开的一种实施方式中，驱动电源焊盘包括分别位于焊盘区两端的侧驱动电源焊盘，以及包括位于焊盘区中间的两个中驱动电源焊盘。驱动电源总线第四部分TVDDB的数量为四个且分别与四个驱动电源焊盘电连接。
相应的，参见图2，在中间模组中，驱动电源接触垫包括分别位于两个侧接触垫组EPADS的侧驱动电源接触垫，以及包括位于中接触垫组MPADS的两个中驱动电源接触垫。
在一种示例中，侧驱动电源焊盘可以位于触控信号焊盘的内侧，以使得触控信号焊盘的两侧分别设置参考电源焊盘和驱动电源焊盘，提高对触控信号焊盘的屏蔽效果。
在一种示例中，在中间模组中，两个中驱动电源接触垫可以分别位于中接触垫组MPADS的两端，以对中接触垫组MPADS的其他接触垫PAD提供一定的信号屏蔽作用。
在一种示例中，与侧驱动电源焊盘电连接的驱动电源总线第四部分TVDDB，可以与驱动电源总线第三部分DVDDB的外侧端(沿行方向的外侧端)电连接。
在本公开的一种实施方式中，沿行方向，驱动电源总线第三部分DVDDB被分割为两个电源子走线，电源子走线的两端均通过驱动电源总线第四部分TVDDB与驱动电源焊盘电连接。示例性地，驱动电源总线第三部分DVDDB分为左电源子走线和右电源子走线。其中，左侧的中驱动电源焊盘通过驱动电源总线第四部分TVDDB与左电源子走线的内侧端(即右端)电连接，右侧的中驱动电源焊盘通过驱动电源总线第四部分TVDDB与右电源子走线的内侧端(即左端)电连接。这样，可以保证驱动电源总线第三部分DVDDB上较为均匀的加载驱动电源电压且具有较为均匀的电流。
在本公开的一种实施方式中，参见图1，沿行方向DH，点灯测试区 CTA分为四个点灯测试子区SCTA，即位于两侧的两个侧点灯测试子区SCTA和位于中间的两个中点灯测试子区SCTA。在相邻两个点灯测试子区SCTA之间设置有沿行方向延伸的点灯测试跨接线CTL，相邻两个点灯测试子区SCTA中的控制信号通过点灯测试跨接线CTL传递以保证信号连续。点灯测试子区SCTA之间的间隙中设置有驱动电源总线第二部分MVDDB。
参见图6，在相邻点灯测试子区SCTA之间，点灯测试单元CT的信号走线通过位于栅极层的点灯测试跨接线CTL进行跨接，例如同时采用第一栅极层和第二栅极层跨接，以避让驱动电源总线第二部分MVDDB。不仅如此，点灯测试单元CT的信号走线通过跨接，可以使得点灯测试单元CT上累积的电荷更有效的消散，避免点灯测试单元CT上静电累积而产生静电击穿。
在一种示例中，中点灯测试子区SCTA之间的间隙宽度(沿行方向的尺寸)，大于侧点灯测试子区SCTA和中点灯测试子区SCTA之间的间隙宽度。在中点灯测试子区SCTA之间，可以设置有两个驱动电源总线第二部分MVDDB。两个驱动电源总线第二部分MVDDB的近端分别与驱动电源总线第三部分DVDDB的内侧端电连接，两个驱动电源总线第二部分MVDDB的远端分别与驱动电源总线第一部分UVDDB电连接。这样，可以进一步提高驱动电源总线VDDB的网格化程度，提高驱动电源总线VDDB上的电流的均一性。
在本公开的一种实施方式中，所述驱动电源总线第一部分UVDDB的长度小于所述驱动电源总线第三部分DVDDB的长度。
在本公开的一种实施方式中，第一外围区B1还包括用于绑定驱动芯片IC的驱动芯片区ICA，驱动芯片区ICA位于驱动电源总线第三部分DVDDB与第一边缘PL1之间。驱动芯片区ICA与焊盘、点灯测试单元CT和栅极驱动电路之间设置有连接线，以便驱动芯片IC通过焊盘PAD与外部电路交互，以及向点灯测试单元CT和栅极驱动电路加载信号。
在本公开的一种实施方式中，参见图5和图7，点灯测试区CTA和驱动芯片区ICA之间设置有第二数据转接线D2L，点灯测试单元CT与驱动芯片IC之间通过第二数据转接线D2L电连接。可选地，第二数据转接线 D2L设置于栅极层，以便避让驱动电源总线第三部分DVDDB。
在本公开的一种实施方式中，参见图3，沿行方向驱动芯片区ICA分为至少两段，以便绑定多个驱动芯片。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (15)

  1. 一种显示面板，包括显示区和围绕所述显示区的外围区；所述外围区包括位于所述显示区一侧的第一外围区，所述第一外围区具有设置点灯测试单元的点灯测试区；所述显示面板具有第一边缘，所述第一边缘位于所述第一外围区远离所述显示区的一侧；
    所述显示面板设置有参考电源总线和触控信号走线；在所述第一外围区，所述参考电源总线具有参考电源总线凸出部；所述参考电源总线凸出部在所述第一边缘上的正投影，位于所述点灯测试区在所述第一边缘上的正投影内；至少部分所述触控信号走线与所述参考电源总线凸出部交叠。
  2. 根据权利要求1所述的显示面板，其中，所述参考电源总线凸出部位于所述点灯测试单元靠近所述显示区的一侧。
  3. 根据权利要求2所述的显示面板，其中，所述显示区靠近所述点灯测试单元的一端具有弧形顶角；
    所述参考电源总线凸出部在所述第一边缘上的正投影，与所述弧形顶角在所述第一边缘上的正投影至少部分重叠。
  4. 根据权利要求1所述的显示面板，其中，所述显示面板包括像素层，所述像素层具有用于加载参考电源电压的公共电极层；所述公共电极层覆盖所述显示区；
    所述参考电源总线凸出部远离所述第一边缘的边缘，位于所述公共电极层靠近所述第一边缘的边缘和所述显示区之间。
  5. 根据权利要求1所述的显示面板，其中，所述参考电源总线凸出部所处的区域为凸出部区域，至少部分所述触控信号走线在所述凸出部区域弯折。
  6. 根据权利要求1所述的显示面板，其中，所述显示面板在所述显示区设置有数据走线，在所述显示区和所述点灯测试区之间设置有第一数据转接线；
    所述数据走线与所述点灯测试单元通过所述第一数据转接线电连接；
    所述参考电源总线凸出部与至少部分所述第一数据转接线交叠。
  7. 根据权利要求1所述的显示面板，其中，所述显示面板还设置有位于所述第一外围区的驱动电源总线；
    所述驱动电源总线包括驱动电源总线第一部分、驱动电源总线第三部分和多个驱动电源总线第二部分；所述驱动电源总线第一部分位于所述显示区和所述点灯测试区之间；
    所述驱动电源总线第三部分位于所述点灯测试区远离所述显示区的一侧；
    所述点灯测试区包括多个点灯测试子区；所述驱动电源总线第二部分位于各个所述点灯测试子区之间，且与所述驱动电源总线第一部分、驱动电源总线第三部分电连接。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板设置有沿第一边缘排列的焊盘；所述焊盘包括用于加载驱动电源电压的驱动电源焊盘；
    所述驱动电源总线还包括驱动电源总线第四部分；所述驱动电源总线第三部分通过所述驱动电源总线第四部分与所述驱动电源焊盘电连接。
  9. 根据权利要求8所述的显示面板，其中，所述驱动电源焊盘的数量为多个且与所述驱动电源总线第三部分的各个端部一一对应；所述驱动电源总线第四部分的数量为多个且与所述驱动电源总线第三部分的各个端部一一对应；
    所述驱动电源总线第三部分的各个端部均通过对应的所述驱动电源总线第四部分电连接至对应的所述驱动电源焊盘。
  10. 根据权利要求9所述的显示面板，其中，所述驱动电源总线第三部分被分割为两个电源子走线；每个所述电源子走线的端部均通过所述驱动电源总线第四部分与所述驱动电源焊盘电连接。
  11. 根据权利要求7所述的显示面板，其中，所述驱动电源总线第一部分的长度小于所述驱动电源总线第三部分的长度。
  12. 根据权利要求7所述的显示面板，其中，所述驱动电源总线第一部分在所述第一边缘上的正投影，与所述参考电源总线凸出部在所述第一边缘上的正投影不重合。
  13. 根据权利要求7所述的显示面板，其中，所述显示面板在所述第一外围区还设置有用于绑定驱动芯片的驱动芯片区；所述驱动电源总线第一部分设置于所述驱动芯片区和所述点灯测试区之间。
  14. 根据权利要求7所述的显示面板，其中，所述显示面板包括依次层叠设置的衬底基板、驱动层、像素层、薄膜封装层和触控层；
    所述触控信号走线设置于所述触控层；
    所述驱动层包括源漏金属层，所述驱动电源总线和所述参考电源总线设置于所述源漏金属层。
  15. 一种显示装置，包括权利要求1～14任意一项所述的显示面板。
PCT/CN2021/141623 2021-12-27 2021-12-27 显示面板和显示装置 WO2023122880A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108831910A (zh) * 2018-06-07 2018-11-16 武汉华星光电半导体显示技术有限公司 显示面板
CN110190103A (zh) * 2019-05-31 2019-08-30 武汉天马微电子有限公司 一种显示面板和显示装置
CN110690365A (zh) * 2019-11-08 2020-01-14 京东方科技集团股份有限公司 显示基板及其显示装置
CN112905055A (zh) * 2021-03-11 2021-06-04 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN113345933A (zh) * 2020-03-03 2021-09-03 三星显示有限公司 显示设备

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CN108831910A (zh) * 2018-06-07 2018-11-16 武汉华星光电半导体显示技术有限公司 显示面板
CN110190103A (zh) * 2019-05-31 2019-08-30 武汉天马微电子有限公司 一种显示面板和显示装置
CN110690365A (zh) * 2019-11-08 2020-01-14 京东方科技集团股份有限公司 显示基板及其显示装置
CN113345933A (zh) * 2020-03-03 2021-09-03 三星显示有限公司 显示设备
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