WO2022199084A1 - 像素驱动电路、显示面板和显示装置 - Google Patents

像素驱动电路、显示面板和显示装置 Download PDF

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Publication number
WO2022199084A1
WO2022199084A1 PCT/CN2021/132462 CN2021132462W WO2022199084A1 WO 2022199084 A1 WO2022199084 A1 WO 2022199084A1 CN 2021132462 W CN2021132462 W CN 2021132462W WO 2022199084 A1 WO2022199084 A1 WO 2022199084A1
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WIPO (PCT)
Prior art keywords
node
transistor
light
display panel
power supply
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PCT/CN2021/132462
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English (en)
French (fr)
Inventor
刘庭良
杨慧娟
韩林宏
舒晓青
廖茂颖
董向丹
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/282,242 priority Critical patent/US20240161699A1/en
Publication of WO2022199084A1 publication Critical patent/WO2022199084A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel driving circuit, a display panel and a display device.
  • initialization leads may be set to initialize the pixel electrodes of the OLED, and an initialization voltage may be loaded on the initialization leads.
  • an initialization voltage may be loaded on the initialization leads.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a pixel driving circuit, a display panel and a display device to improve the brightness uniformity of the display panel.
  • a pixel driving circuit comprising:
  • a driving transistor connected to the first node, the second node and the third node, for outputting a driving current to the third node under the control of the first node;
  • a data writing unit connected to the second node, for loading a data voltage to the second node in response to a scan signal
  • a threshold compensation unit connected to the first node and the third node, and configured to make conduction between the first node and the third node in response to the scan signal
  • a first lighting control unit connected to the second node, for loading a first power supply voltage to the second node in response to a lighting control signal
  • a second lighting control unit connected to the third node and the fourth node, and configured to make the connection between the third node and the fourth node conductive in response to the lighting control signal;
  • a first reset unit connected to the fourth node, for loading a second power supply voltage to the fourth node in response to the scan signal
  • One end of the light-emitting element is connected to the fourth node, and the other end is used for loading the second power supply voltage.
  • the data writing unit includes a data writing transistor, the data writing transistor has a first end, a second end and a control end, and the first end of the data writing transistor is for loading the data voltage, the second terminal of the data writing transistor is connected to the second node, and the control terminal of the data writing transistor is used for loading the scan signal;
  • the threshold compensation unit includes a threshold compensation transistor, the threshold compensation transistor has a first end, a second end and a control end, the first end of the threshold compensation transistor is connected to the first node, and the first end of the threshold compensation transistor is connected to the first node. Two terminals are connected to the third node, and the control terminal of the threshold compensation transistor is used to load the scan signal;
  • the first light-emitting control unit includes a first light-emitting control transistor, the first light-emitting control transistor has a first end, a second end and a control end, and the first end of the first light-emitting control transistor is used to load the first light-emitting control transistor. a power supply voltage, the second end of the first light-emitting control transistor is connected to the second node, and the control end of the first light-emitting control transistor is used to load the light-emitting control signal;
  • the second light-emitting control unit includes a second light-emitting control transistor, the second light-emitting control transistor has a first end, a second end and a control end, and the first end of the second light-emitting control transistor is connected to the third node , the second end of the second light-emitting control transistor is connected to the fourth node, and the control end of the second light-emitting control transistor is used to load the light-emitting control signal;
  • the first reset unit includes a first reset transistor, the first reset transistor has a first terminal, a second terminal and a control terminal, and the first terminal of the first reset transistor is used for loading the second power supply voltage, The second terminal of the first reset transistor is connected to the fourth node, and the control terminal of the first reset transistor is used for loading the scan signal.
  • the pixel driving circuit further includes a second reset unit connected to the first node for loading an initialization voltage to the first node in response to a reset signal.
  • a display panel including the above-mentioned pixel driving circuit.
  • the display panel has a display area and a peripheral area surrounding the display area;
  • the display panel is provided with a second power supply lead for loading the second power supply voltage in the display area, and the second power supply lead is electrically connected to the fourth node of the pixel driving circuit.
  • the number of the second power leads is plural, and extends in the row direction or in the column direction.
  • the second power supply lead includes a plurality of second power supply row sub-leads extending in a row direction and a plurality of second power supply column sub-leads extending in a column direction; the second power supply row sub-leads
  • the leads and the sub-leads of the second power supply columns are connected to each other, so that each of the second power supply leads is in a grid shape.
  • the peripheral area is provided with a second power bus, and the second power bus is connected to at least part of the second power lead.
  • the peripheral area has a binding area;
  • the second power bus has interconnected wiring segments and connection segments;
  • the number of the second power bus is two, and the two said The wiring segments of the second power bus extend along the column direction and are respectively located on both sides of the display area;
  • the connection segments of the second power bus extend to the binding area.
  • the wiring segment of the second power bus is located at an end of the display panel close to the binding area.
  • the pixel driving circuit includes a second reset unit, and the peripheral area of the display panel includes a binding area; the display panel is further provided with:
  • an initialization bus used to load the initialization voltage
  • the number of the initialization bus is two and located in the peripheral area, and includes interconnected wiring segments and connection segments; the wiring segments of the two initialization buses are along the The column direction extends and is respectively located on both sides of the display area; the connection section of the initialization bus extends to the binding area;
  • an initialization lead which runs through the display area along the row direction and is connected to the wiring segment of the initialization bus
  • a first power bus used for loading a first power voltage
  • the number of the first power bus is two and is arranged in the peripheral area, and one end of the first power bus extends to the binding area
  • a first power lead arranged in the display area and distributed in a grid, and connected to the first power bus;
  • the first power bus partially overlaps the initialization bus.
  • a display device including a display panel thereon.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by the present disclosure.
  • FIG. 2 is a schematic structural diagram of a pixel driving circuit provided by the present disclosure.
  • FIG. 3 is a schematic structural diagram of a display panel provided by the present disclosure.
  • FIG. 4 is a schematic structural diagram of a display panel provided by the present disclosure.
  • FIG. 5 is a schematic structural diagram of a display panel provided by the present disclosure.
  • FIG. 6 is a schematic diagram of a partial structure of a display panel provided in the present disclosure in a pixel driving circuit region, in which only part of the leads are shown.
  • FIG. 7 is a schematic partial structure diagram of a display panel provided in the present disclosure in a pixel driving circuit region, in which only part of the leads are shown.
  • FIG. 8 is a schematic partial structure diagram of a display panel provided by the present disclosure in a pixel driving circuit area, in which only part of the leads are shown.
  • FIG. 9 is a schematic structural diagram of a display panel provided by the present disclosure, in which only part of the leads are shown.
  • FIG. 10 is a schematic structural diagram of a display panel provided by the present disclosure, in which only part of the leads are shown.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • a transistor refers to an element including at least three terminals of a gate, a drain, and a source.
  • a transistor has a channel region between the drain (drain terminal, drain region or drain electrode) and source (source terminal, source region or source electrode) and current can flow through the drain, channel region and source .
  • the channel region refers to the region through which current mainly flows.
  • the transistor can have a first terminal, a second terminal and a control terminal, wherein the gate of the transistor can be used as the control terminal of the transistor; one of the source and drain of the transistor can be used as the first terminal of the transistor, and the other One can act as the second terminal of the transistor.
  • the "on" state of a transistor refers to a state in which the source and drain of the transistor are electrically connected.
  • the “off” state of a transistor refers to a state in which the source and drain of the transistor are electrically disconnected; it can be understood that when the transistor is turned off, leakage current may still exist.
  • initialization leads are provided to initialize the pixel electrodes of the OLED, and an initialization voltage can be loaded on the initialization leads.
  • an initialization voltage can be loaded on the initialization leads.
  • the initialization voltage along the direction away from the source driver of the display panel, there are voltage drops in the initialization voltage, driving voltage and common voltage, and the voltage of the pixel electrode of the OLED is directly related to the driving current flowing through the OLED. This results in a difference in brightness between an end of the OLED display panel close to the source driver and an end far from the source driver.
  • the OLED display panel has relatively obvious color spots (mura) in the row area where the through-holes are located, and the color spots are more obvious in the low gray scale state, which is not suitable for low gray scales. screen has a greater impact.
  • the present disclosure provides a pixel driving circuit and a display panel using the pixel driving circuit, so as to improve the brightness uniformity of the display panel.
  • the pixel driving circuit includes:
  • a driving transistor T3 connected to the first node N1, the second node N2 and the third node N3, for outputting a driving current to the third node N3 under the control of the first node N1;
  • a data writing unit 110 connected to the second node N2, for loading a data voltage Vdata to the second node N2 in response to the scan signal Vgate;
  • a threshold compensation unit 120 connected to the first node N1 and the third node N3, and configured to conduct conduction between the first node N1 and the third node N3 in response to the scan signal Vgate;
  • a first lighting control unit 130 connected to the second node N2, for loading a first power supply voltage VDD to the second node N2 in response to the lighting control signal EM;
  • the second lighting control unit 140 is connected to the third node N3 and the fourth node N4, and is configured to make the connection between the third node N3 and the fourth node N4 in response to the lighting control signal EM;
  • a first reset unit 150 connected to the fourth node N4, for loading a second power supply voltage VSS to the fourth node N4 in response to the scan signal Vgate;
  • One end of the light-emitting element 170 is connected to the fourth node N4, and the other end is used to load the second power supply voltage VSS.
  • one end of the light-emitting element 170 is used to load the second power supply voltage VSS, and the other end is reset by the second power supply voltage VSS.
  • the pixel driving circuit avoids the situation of using the initialization voltage to reset the light-emitting element 170, reduces the difference in the source-drain voltage difference between the driving crystal points at different positions, and improves the driving performance.
  • the uniformity of the working environment of the transistor T3 further improves the uniformity of the brightness of the display panel.
  • the pixel driving circuit provided by the present disclosure may be applied to a display panel, and the display panel may include a display area D and a peripheral area C surrounding the display area D.
  • the pixel driving circuit can be arranged in the display area D, especially the array is arranged in the display area D; the light emitting element 170 of the pixel driving circuit can be used as a sub-pixel of the display panel.
  • a binding area E may be provided in the peripheral area C, and the binding area E is used for binding a circuit board or a driver chip.
  • the display panel can bind a driver chip through a COP (chip on panel) technology.
  • the binding area E may include a chip binding area and a circuit board binding area.
  • the chip binding area is provided with a chip binding pad for binding with the driver chip
  • the circuit board binding area is provided with a chip binding pad for binding with the circuit board. specified circuit board bonding pads.
  • the display panel can also bind a driver chip through COF (chip on film) technology.
  • the binding area E includes a circuit board binding area.
  • the circuit board binding area is provided with a circuit board binding pad for binding with a chip on film, and a driving chip can be bound on the chip on film.
  • the display panel can also bind the driving chip by other methods, for example, the display panel is bound to the flexible circuit board and the driving chip is bound to the flexible circuit board, which is not limited in the present disclosure.
  • the light emitting element 170 of the present disclosure may be an OLED (organic electroluminescent diode).
  • the display panel may include a base substrate F100 , a circuit layer F200 and a pixel layer F300 that are stacked in sequence.
  • the base substrate F100 may be the base substrate F100 of an inorganic material or the base substrate F100 of an organic material.
  • the material of the base substrate F100 may be glass materials such as soda-lime glass, quartz glass, sapphire glass, etc., or may be stainless steel, aluminum, nickel, etc. metallic material.
  • the material of the base substrate F100 may be polymethyl methacrylate (Polymethyl methacrylate, PMMA), polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl phenol (Polyvinyl phenol, PVP), Polyethersulfone (PES), Polyimide, Polyamide, Polyacetal, Polycarbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN) or a combination thereof.
  • the base substrate F100 may also be a flexible base substrate F100, for example, the material of the base substrate F100 may be polyimide (PI).
  • the base substrate F100 may also be a composite of multi-layer materials.
  • the base substrate F100 may include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, A first polyimide layer and a second polyimide layer.
  • each unit of the pixel driving circuit of the present disclosure the driving transistor and the storage capacitor are provided in the circuit layer F200.
  • each power supply in the pixel driving circuit may include a transistor F200M and a storage capacitor.
  • the transistor F200M can be a thin film transistor, and the thin film transistor can be a top gate thin film transistor, a bottom gate thin film transistor or a double gate thin film transistor;
  • the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low temperature polysilicon Semiconductor materials, metal oxide semiconductor materials, organic semiconductor materials or other types of semiconductor materials;
  • the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.
  • the thin film transistor is a low temperature polysilicon transistor.
  • the types of any two transistors may be the same or different.
  • some transistors may be N-type transistors and some of the transistors may be P-type transistors.
  • the material of the active layer of some transistors may be low temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be metal. Oxide semiconductor material.
  • the transistor may have a first terminal, a second terminal and a control terminal, one of the first terminal and the second terminal may be the source of the transistor and the other may be the drain of the transistor, and the control terminal may be the gate of the transistor.
  • the source and drain of a transistor are two opposite concepts that can be converted to each other; when the working state of the transistor changes, for example, when the current direction changes, the source and drain of the transistor can be interchanged.
  • the circuit layer F200 may include a semiconductor layer F203, a gate insulating layer F204, a gate layer F205, an interlayer dielectric layer F206, a source-drain metal layer F207, etc., which are stacked between the base substrate F100 and the pixel layer F300.
  • Each thin film transistor and storage capacitor can be formed by a semiconductor layer F203, a gate insulating layer F204, a gate layer F205, an interlayer dielectric layer F206, a source-drain metal layer F207 and other film layers.
  • the positional relationship of each film layer may be determined according to the film layer structure of the thin film transistor.
  • the circuit layer F200 may include a semiconductor layer F203, a gate insulating layer F204, a gate layer F205, an interlayer dielectric layer F206, and a source-drain metal layer F207 that are stacked in sequence
  • the thin film transistor thus formed is a top-gate thin film transistor.
  • the circuit layer F200 may include a gate layer F205 , a gate insulating layer F204 , a semiconductor layer F203 , an interlayer dielectric layer F206 and a source-drain metal layer that are stacked in sequence.
  • F207, the thin film transistor thus formed is a bottom gate thin film transistor.
  • the circuit layer F200 may also adopt a double gate layer F205 structure, that is, the gate layer F205 may include a first gate layer and a second gate layer, and the gate insulating layer F204 may include a semiconductor layer for isolation F203 and the first gate insulating layer of the first gate layer, and including a second gate insulating layer for isolating the first gate layer and the second gate layer.
  • the circuit layer F200 may include a semiconductor layer F203, a first gate insulating layer, a first gate layer, and a second gate layer that are sequentially stacked on one side of the base substrate F100 A polar insulating layer, a second gate layer, an interlayer dielectric layer F206 and a source-drain metal layer F207.
  • the circuit layer F200 may also adopt a structure of a dual source-drain metal layer F207, that is, the source-drain metal layer F207 may include a first source-drain metal layer and a second source-drain metal layer, and the interlayer dielectric layer F206 may include A first interlayer dielectric layer located on the side of the first source-drain metal layer close to the base substrate F100 and a second interlayer dielectric layer located between the first source-drain metal layer and the second source-drain metal layer.
  • the source-drain metal layer F207 may include a first source-drain metal layer and a second source-drain metal layer
  • the interlayer dielectric layer F206 may include A first interlayer dielectric layer located on the side of the first source-drain metal layer close to the base substrate F100 and a second interlayer dielectric layer located between the first source-drain metal layer and the second source-drain metal layer.
  • the circuit layer F200 may further include a passivation layer, and the passivation layer may be provided on the surface of the source/drain metal layer F207 away from the base substrate F100 so as to protect the source/drain metal layer F207.
  • the circuit layer F200 may further include a buffer material layer disposed between the base substrate F100 and the semiconductor layer F203, and the semiconductor layer F203, the gate layer F205, etc. are all located on the side of the buffer material layer away from the base substrate F100.
  • the material of the buffer material layer may be inorganic insulating materials such as silicon oxide and silicon nitride.
  • the buffer material layer may be one inorganic material layer, or may be a multilayered inorganic material layer.
  • the buffer material layer may include a barrier layer F201 on the side close to the base substrate F100 and a buffer layer F202 on the side of the barrier layer F201 away from the base substrate F100 .
  • the barrier layer F201 is used to block the penetration of ions and other components in the base substrate F100 into the circuit layer F200, so that the circuit layer F200 maintains stable performance.
  • the buffer layer F202 can improve the bonding force between the circuit layer F200 and the base substrate F100, and provide a stable environment for the circuit layer F200.
  • the circuit layer F200 may further include a planarization layer F208 located between the source-drain metal layer F207 and the pixel layer F300, and the planarization layer F208 may provide a planarized surface for the pixel electrode.
  • the material of the planarization layer F208 may be an organic material.
  • the pixel layer F300 may be disposed on the side of the circuit layer F200 away from the base substrate F100, and the light-emitting element of the pixel driving circuit of the present disclosure may be disposed in the pixel layer F300.
  • the pixel layer F300 may include a pixel electrode layer F301, a pixel definition layer F302, a support column layer F303, an organic light-emitting functional layer F304, and a common electrode layer F305 that are stacked in sequence.
  • the pixel electrode layer F301 has a plurality of pixel electrodes in the display area of the display panel; the pixel definition layer F302 has a plurality of through pixel openings in the display area corresponding to the plurality of pixel electrodes, and any pixel opening exposes the corresponding at least part of the pixel electrode.
  • the support column layer F303 includes a plurality of support columns in the display area, and the support columns are located on the surface of the pixel definition layer F302 away from the base substrate F100, so as to support a fine metal mask (FMM) during the evaporation process.
  • the organic light emitting functional layer F304 covers at least the pixel electrodes exposed by the pixel definition layer F302.
  • the organic light-emitting functional layer F304 may include an organic electroluminescent material layer, and may include one of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer or more.
  • Each film layer of the organic light-emitting functional layer F304 can be prepared by an evaporation process, and a fine metal mask or an open mask can be used to define the pattern of each film layer during evaporation.
  • the common electrode layer F305 may cover the organic light-emitting functional layer F304 in the display area.
  • the pixel electrode, the common electrode layer F305 and the organic light-emitting functional layer F304 between the pixel electrode and the common electrode layer F305 form an organic light-emitting diode, and any organic light-emitting diode can be used as a sub-pixel of the display panel.
  • the pixel layer F300 may further include a light extraction layer on the side of the common electrode layer F305 away from the base substrate F100 to enhance the light extraction efficiency of the organic light emitting diode.
  • the display panel may further include a thin film encapsulation layer F400.
  • the thin film encapsulation layer F400 is disposed on the surface of the pixel layer F300 away from the base substrate F100, and may include an inorganic encapsulation layer and an organic encapsulation layer that are alternately stacked.
  • the inorganic encapsulation layer can effectively block the moisture and oxygen from the outside, and prevent the water and oxygen from invading the organic light-emitting functional layer F304 and causing the material to degrade.
  • the edge of the inorganic encapsulation layer may be located in the peripheral region.
  • the organic encapsulation layer is located between two adjacent inorganic encapsulation layers in order to achieve planarization and reduce stress between the inorganic encapsulation layers.
  • the edge of the organic encapsulation layer may be located between the display area and the edge of the inorganic encapsulation layer.
  • the thin film encapsulation layer F400 includes a first inorganic encapsulation layer F401 , an organic encapsulation layer F402 and a second inorganic encapsulation layer F403 sequentially stacked on the side of the pixel layer F300 away from the base substrate F100 .
  • the display panel may further include an anti-reflection layer F500, and the anti-reflection layer F500 may be disposed on the side of the thin film encapsulation layer F400 away from the pixel layer F300 to reduce the reflection of the display panel to ambient light, thereby reducing the effect of ambient light on the display. effect.
  • the anti-reflection layer F500 may include a color filter layer and a black matrix layer stacked in layers, so that the reduction of the light transmittance of the display panel can be avoided while reducing the interference of ambient light.
  • the antireflection layer F500 may be a polarizer, for example, a patterned coated circular polarizer.
  • the display panel may further include a touch function layer F600, and the touch function layer F600 is disposed on the side of the thin film encapsulation layer F400 away from the base substrate F100, and is used to realize the touch operation of the display panel.
  • the touch function layer F600 may be disposed between the thin film encapsulation layer F400 and the anti-reflection layer F500.
  • the display panel is formed with data leads 220 on the source-drain metal layer.
  • the data leads 220 may extend along the column direction B and be electrically connected to the data writing unit 110 for writing to the data writing unit. 110 loads the data voltage Vdata.
  • the display panel is provided with scan wires 210 on the gate layer, and the scan wires 210 extend along the row direction A and are used to load the scan signal Vgate.
  • the scan wire 210 may be electrically connected with the data writing unit 110 , the threshold compensation unit 120 and the first reset unit 150 .
  • the display panel is provided with a light-emitting control lead 240 on the gate layer, and the light-emitting control lead 240 extends along the row direction A and is used for loading the light-emitting control signal EM.
  • the lighting control lead 240 can be electrically connected to the first lighting control unit 130 and the second lighting control unit 140 .
  • the display panel is provided with a first power supply lead 231 on the circuit layer, and the first power supply lead 231 is used to load the first power supply voltage VDD.
  • the first power supply lead 231 may be connected with the first light emission control unit 130 to load the first power supply voltage VDD to the first light emission control unit 130 .
  • the first power supply leads 231 are disposed in the display area D and are distributed in a grid, so that the uniformity of the first power supply voltage VDD on the first power supply leads 231 can be improved.
  • the first power lead 231 is disposed on the source-drain metal layer. In another embodiment of the present disclosure, the first power lead 231 may be partially disposed on the source-drain metal layer and partially disposed on the gate layer. Exemplarily, the first power supply leads 231 are distributed in a grid shape, the part extending in the column direction may be disposed on the source-drain metal layer, and the part extending in the row direction may be disposed in the gate layer.
  • the display panel may also be provided with a first power bus 232 .
  • the first power bus 232 is disposed in the peripheral area C, and one end of the first power bus 232 extends to the binding area E.
  • the first power bus 232 can be connected to the pads in the binding area E, and the circuit board can be connected to the display panel in the binding area E through the binding connection, so that its circuit extends into the circuit board, so as to receive the first power supply from the circuit board.
  • a power supply voltage VDD The first power bus 232 is connected to the first power leads 231 for loading the first power voltage VDD and distributing the first power voltage VDD to each of the first power leads 231 .
  • the number of the first power busses 232 may be two, and the two first power busses 232 may be symmetrically distributed.
  • the first power bus 232 is disposed on the source-drain metal layer.
  • the display panel may further be provided with a second power supply lead 251 for loading the second power supply voltage VSS, and the second power supply lead 251 is electrically connected to the fourth node N4 of the pixel driving circuit.
  • the number of the second power leads 251 is multiple.
  • any one of the second power leads 251 extends along the row direction A or along the column direction B. Further optionally, any one of the pixel driving circuit regions passes through the second power lead 251 .
  • the second power supply lead 251 includes a plurality of second power supply row sub-leads 2511 extending along the row direction A and a plurality of first power supply row sub-leads 2511 extending along the column direction B
  • Two power supply column sub-leads 2512; the second power supply row sub-leads 2511 and the second power supply column sub-leads 2512 are connected to each other, so that each of the second power supply leads 251 is in a grid shape.
  • the second power supply leads 251 are designed in a grid shape, which can improve the uniformity of the second power supply voltage VSS in the display panel, reduce the voltage drop of the second power supply voltage VSS, and further improve the brightness uniformity of the display panel.
  • the second power lead 251 may be disposed on the source-drain metal layer, for example, may bridge and extend between the first source-drain metal layer and the second source-drain metal layer.
  • the second power lead 251 may also be partially disposed on other film layers, for example, may be partially disposed on film layers such as a semiconductor layer, a gate layer, and a pixel electrode layer.
  • the peripheral area C is provided with a second power bus 252 , and the second power bus 252 is connected to at least part of the second power leads 251 .
  • the second power bus 252 is electrically connected to the bonding area E, and can load the second power voltage VSS, thereby distributing the second power voltage VSS to the second power lead 251 . It can be understood that if some of the second power leads 251 are not directly connected to the second power bus 252 , other conductive structures, such as other second power leads 251 , can be electrically connected to the second power bus 252 .
  • the number of the second power busses 252 is two, and they are arranged symmetrically.
  • the second power bus 252 has interconnected wiring sections 2521 and connection sections 2522; the number of the second power bus 252 is two, and two of the second power bus
  • the wiring segments 2521 of the 252 extend along the column direction B and are located on both sides of the display area D respectively; the connecting segments 2522 of the second power bus 252 extend to the binding area E.
  • the common electrode of the display panel may cover the display area and extend to the peripheral area, and partially overlap with the wiring segment 2521 of the second power bus 252, so that the second power bus 252 can Two power supply voltages VSS are applied to the common electrode.
  • the pixel electrode layer can be provided with a transfer electrode, the transfer electrode can be connected with the second power bus 252 through a via hole, and the common electrode can be connected with the transfer electrode, thereby realizing the connection between the common electrode and the second power bus 252. electrical connection.
  • the wiring segments 2521 of the second power bus 252 extend along the column direction B; The wiring segment 2521 of the second power bus 252 is connected.
  • the second power supply voltage VSS can be applied to the second power supply lead 251 by means of the second power supply bus 252 with low impedance, so as to further improve the uniformity of the second power supply voltage VSS.
  • the part of the second power supply lead 251 extending along the row direction A such as each second power supply row sub-lead 2511 , has two ends connected to the wiring segments 2521 of the two second power supply buses 252 respectively.
  • the wiring segment 2521 of the second power bus 252 is located at one end of the display panel close to the binding area E.
  • the length of the wiring segment 2521 of the second power bus 252 is shorter than the length of the display area D in the column direction B, and the wiring segment 2521 of the second power bus 252 is only provided on the side close to the binding area E.
  • This arrangement can reduce the extension length of the wiring segment 2521 of the second power bus 252, thereby reducing the frame space occupied by the wiring segment 2521 of the second power bus 252, thereby reducing the frame of the display panel.
  • the wiring segments 2521 of the second power bus 252 may be located only at the top corners of the display panel close to the binding area E, that is, outside the two top corners of the display area D close to the binding area E. In this way, the wiring segments 2521 of the second power bus 252 do not extend further along the column direction B, thereby significantly reducing the frame width of the display panel.
  • the second power leads 251 may be distributed in a grid shape and are electrically connected to the wiring segments 2521 of the second power bus 252 to ensure that the second power voltage VSS can be applied to the fourth node N4 of each pixel driving circuit.
  • a node refers to a conductive structure with equal potential and electrically connected to each other.
  • the conductive structure can be the same conductive structure located in the same film layer, different conductive structures located in the same film layer, or different conductive structures located in different layers. Different conductive structures of film layers.
  • the data writing unit 110 includes a data writing transistor T4 having a first terminal, a second terminal and a control terminal, and the data writing transistor T4 has a first terminal, a second terminal and a control terminal.
  • the first terminal of the writing transistor T4 is used to load the data voltage Vdata
  • the second terminal of the data writing transistor T4 is connected to the second node N2
  • the control terminal of the data writing transistor T4 is used to load the data voltage Vdata.
  • the scanning signal Vgate the scanning signal Vgate.
  • the first end of the data writing transistor T4 may be electrically connected to the data lead 220 , and the control end of the data writing transistor T4 may be electrically connected to the scan lead 210 .
  • control terminal of the transistor is electrically connected to the scan lead 210, which may mean that the gate of the transistor is multiplexed as a part of the scan lead 210 (that is, the scan lead 210 overlaps with the active layer of the transistor), or it may refer to The gates of the transistors are directly or indirectly connected to the scan wires 210 .
  • the threshold compensation unit 120 includes a threshold compensation transistor T2, the threshold compensation transistor T2 has a first end, a second end and a control end, and the first end of the threshold compensation transistor T2 The first node N1 is connected, the second end of the threshold compensation transistor T2 is connected to the third node N3, and the control end of the threshold compensation transistor T2 is used for loading the scan signal Vgate.
  • control terminal of the threshold compensation transistor T2 is electrically connected to the scan lead 210 .
  • the first light emission control unit 130 includes a first light emission control transistor T5, the first light emission control transistor T5 has a first end, a second end and a control end, the first light emission control transistor T5 The first end of the light-emitting control transistor T5 is used to load the first power supply voltage VDD, the second end of the first light-emitting control transistor T5 is connected to the second node N2, and the control end of the first light-emitting control transistor T5 Used to load the luminescence control signal EM.
  • the first end of the first light emission control transistor T5 is electrically connected to the first power supply lead 231 , and the control end of the first light emission control transistor T5 is electrically connected to the light emission control lead 240 .
  • the transistor control terminal is electrically connected to the light-emitting control lead 240, which may mean that the gate of the transistor is multiplexed as a part of the light-emitting control lead 240 (that is, the light-emitting control lead 240 overlaps with the active layer of the transistor), or It may refer to the direct or indirect connection between the gate of the transistor and the light emitting control lead 240 .
  • the second light-emitting control unit 140 includes a second light-emitting control transistor T6, the second light-emitting control transistor T6 has a first end, a second end and a control end, the second light-emitting control transistor T6 The first end of the light-emitting control transistor T6 is connected to the third node N3, the second end of the second light-emitting control transistor T6 is connected to the fourth node N4, and the control end of the second light-emitting control transistor T6 is used for loading the light-emitting control signal EM;
  • the second end of the second light-emitting control transistor T6 is connected to a pixel electrode, which may serve as a part of the fourth node N4 of the present disclosure; the control end of the second light-emitting control transistor T6 is electrically connected to the light-emitting control lead 240 .
  • the first reset unit 150 includes a first reset transistor T7, the first reset transistor T7 has a first terminal, a second terminal and a control terminal, the first reset transistor T7 The first terminal of the first reset transistor T7 is used to load the second power supply voltage VSS, the second terminal of the first reset transistor T7 is connected to the fourth node N4, and the control terminal of the first reset transistor T7 is used to load the scan signal Vgate.
  • the first end of the first reset transistor T7 is electrically connected to the second power supply lead 251
  • the second end of the first reset transistor T7 is electrically connected to the pixel electrode
  • the control end of the first reset transistor T7 is electrically connected to the scan lead 210 . connect.
  • one end of the storage capacitor Cst is electrically connected to the first node N1, and the other end can be used to load the first power supply voltage VDD, and can also be used to load the second power supply voltage VSS.
  • the pixel driving circuit further includes a second reset unit 160, the second reset unit 160 is connected to the first node N1, and is configured to load the initialization voltage Vinit to all the nodes in response to the reset control signal Vreset. Describe the first node N1. In this way, the pixel driving circuit can also reset the first node N1 to improve the stability and uniformity of the operation of each display driving circuit.
  • the second reset unit 160 may include a second reset transistor T1 having a first terminal, a second terminal and a control terminal, wherein the second reset transistor T1 The first terminal of T1 is used to load the initialization voltage Vinit, the second terminal of the second reset transistor T1 is electrically connected to the first node N1, and the control terminal of the second reset transistor T1 is used to load the reset control signal Vreset.
  • the display panel may be provided with a reset control lead 270 , and the reset control lead 270 is used to load the reset control signal Vreset.
  • the reset control lead 270 may extend along the row direction A and be electrically connected to the gate of the second reset transistor T1.
  • the reset control lead 270 may be disposed on the gate layer.
  • the display panel may be provided with an initialization lead 261, and the initialization lead 261 is used to load the initialization voltage Vinit.
  • the initialization lead 261 may extend along the row direction A and be electrically connected to the first terminal of the second reset transistor T1.
  • the initialization lead 261 may run through the display area D along the row direction A. As shown in FIG.
  • the initialization lead 261 may be disposed on the source-drain metal layer.
  • the display panel may also be provided with an initialization bus 262, which is used to load the initialization voltage Vinit; the number of the initialization buses 262 is two and is located in the peripheral area C, and includes interconnected wiring segments 2621 and connection segments 2622; the wiring segments 2621 of the two initialization buses 262 both extend along the column direction B and are located on both sides of the display area D respectively; Connecting segment 2622 extends to the binding region E.
  • the initialization lead 261 runs through the display area D along the row direction A and is connected to the wiring segment 2621 of the initialization bus 262 .
  • the initialization bus 262 can distribute the initialization voltage Vinit to the initialization leads 261 and improve the uniformity of the initialization voltage Vinit.
  • the initialization bus 262 is located between the second power bus 252 and the display area D.
  • connection sections 2622 of the two initialization buses 262 are located inside the two first power busses 232.
  • the connection sections 2622 of the two initialization buses 262 are bent to both sides of the row direction A of the display panel, which makes the connection sections 2622 of the two initialization buses 262 partially overlap the first power bus 232 .
  • the scan lead 210 along the column direction, the scan lead 210 , the first power lead 231 , the light emission control lead 240 , the initialization lead 261 and the reset lead
  • the control leads 270 are arranged in sequence.
  • the display panel is provided with a through hole F in the display area D.
  • abnormal light emission will not occur around the through hole F of the display panel and each pixel arranged in the same row with the through hole F, thereby avoiding the problem of hole mura around the through hole F.
  • the pixel driving circuit of the present disclosure uses the second power supply voltage VSS to initialize the fourth node N4 of the pixel driving circuit; compared with the conventional initialization voltage Vinit, the distribution of the second power supply voltage VSS is more uniform and the voltage drop is smaller, which The magnitude of the load received (the number of light-emitting elements 170) has less influence.
  • this overcomes the problem that the initialization voltage Vinit around the through hole F in the related art exhibits a significant voltage difference due to the difference in the number of light-emitting elements 170 distributed (the voltage difference can reach 0.2V), and improves the brightness uniformity of the apertured screen .
  • Embodiments of the present disclosure further provide a display device, where the display device includes any one of the display panels described in the above-mentioned display panel embodiments.
  • the display device may be a smart watch screen, a smart phone screen, or other types of display devices. Since the display device has any one of the display panels described in the above-mentioned display panel embodiments, it has the same beneficial effects, and details are not described here in the present disclosure.

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Abstract

一种像素驱动电路、显示面板和显示装置，该像素驱动电路包括驱动晶体管（T3）、存储电容（Cst）、数据写入单元（110）、阈值补偿单元（120）、第一发光控制单元（130）、第二发光控制单元（140）、第一复位单元（150）和发光元件（170）；驱动晶体管（T3）连接第一节点（N1）、第二节点（N2）和第三节点（N3），用于在第一节点（N1）的控制下输出驱动电流至第三节点（N3）；存储电容（Cst）一端连接第一节点（N1）；数据写入单元（110）连接第二节点（N2）；阈值补偿单元（120）连接第一节点（N1）和第三节点（N3）；第一发光控制单元（130）连接第二节点（N2）；第二发光控制单元（140）连接第三节点（N3）和第四节点（N4）；第一复位单元（150）连接第四节点（N4），用于响应扫描信号（Vgate）而加载第二电源电压（VSS）至第四节点（N4）；发光元件（170）一端连接第四节点（N4），另一端用于加载第二电源电压（VSS）。该像素驱动电路能够改善显示面板的亮度均一性。

Description

像素驱动电路、显示面板和显示装置
交叉引用
本公开要求于2021年3月25日提交的申请号为202110322033.8、名称为“像素驱动电路、显示面板和显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种像素驱动电路、显示面板和显示装置。
背景技术
在一些OLED(有机电致发光二极管)显示面板中，可以设置初始化引线对OLED的像素电极进行初始化，初始化引线上可以加载初始化电压。然而，显示面板沿远离源极驱动器的方向，初始化电压、驱动电压和公共电压均存在压降，且OLED的像素电极的电压对流经OLED的驱动电流直接相关。这导致OLED显示面板靠近源极驱动器的一端和远离源极驱动器的一端存在亮度差异。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种像素驱动电路、显示面板和显示装置，改善显示面板的亮度均一性。
根据本公开的一个方面，提供一种像素驱动电路，包括：
驱动晶体管，连接第一节点、第二节点和第三节点，用于在所述第一节点的控制下输出驱动电流至所述第三节点；
存储电容，一端连接所述第一节点；
数据写入单元，连接所述第二节点，用于响应扫描信号而加载数据电 压至所述第二节点；
阈值补偿单元，连接所述第一节点和所述第三节点，用于响应所述扫描信号而使得所述第一节点和所述第三节点之间导通；
第一发光控制单元，连接所述第二节点，用于响应发光控制信号而加载第一电源电压至所述第二节点；
第二发光控制单元，连接所述第三节点和第四节点，用于响应所述发光控制信号而使得所述第三节点与所述第四节点之间导通；
第一复位单元，连接所述第四节点，用于响应所述扫描信号而加载第二电源电压至所述第四节点；
发光元件，一端连接所述第四节点，另一端用于加载所述第二电源电压。
根据本公开的一种实施方式，所述数据写入单元包括数据写入晶体管，所述数据写入晶体管具有第一端、第二端和控制端，所述数据写入晶体管的第一端用于加载所述数据电压，所述数据写入晶体管的第二端连接所述第二节点，所述数据写入晶体管的控制端用于加载所述扫描信号；
所述阈值补偿单元包括阈值补偿晶体管，所述阈值补偿晶体管具有第一端、第二端和控制端，所述阈值补偿晶体管的第一端连接所述第一节点，所述阈值补偿晶体管的第二端连接所述第三节点，所述阈值补偿晶体管的控制端用于加载所述扫描信号；
所述第一发光控制单元包括第一发光控制晶体管，所述第一发光控制晶体管具有第一端、第二端和控制端，所述第一发光控制晶体管的第一端用于加载所述第一电源电压，所述第一发光控制晶体管的第二端连接所述第二节点，所述第一发光控制晶体管的控制端用于加载所述发光控制信号；
所述第二发光控制单元包括第二发光控制晶体管，所述第二发光控制晶体管具有第一端、第二端和控制端，所述第二发光控制晶体管的第一端连接所述第三节点，所述第二发光控制晶体管的第二端连接所述第四节点，所述第二发光控制晶体管的控制端用于加载所述发光控制信号；
所述第一复位单元包括第一复位晶体管，所述第一复位晶体管具有第一端、第二端和控制端，所述第一复位晶体管的第一端用于加载所述第二电源电压，所述第一复位晶体管的第二端连接所述第四节点，所述第一复 位晶体管的控制端用于加载所述扫描信号。
根据本公开的一种实施方式，所述像素驱动电路还包括第二复位单元，所述第二复位单元连接所述第一节点，用于响应复位信号而加载初始化电压至所述第一节点。
根据本公开的另一个方面，提供一种显示面板，所述显示面板包括上述的像素驱动电路。
根据本公开的一种实施方式，所述显示面板具有显示区和围绕所述显示区的外围区；
所述显示面板在所述显示区设置有用于加载所述第二电源电压的第二电源引线，所述第二电源引线与所述像素驱动电路的第四节点电连接。
根据本公开的一种实施方式，所述第二电源引线的数量为多个，且沿行方向延伸或者沿列方向延伸。
根据本公开的一种实施方式，所述第二电源引线包括沿行方向延伸的多个第二电源行子引线和沿列方向延伸的多个第二电源列子引线；所述第二电源行子引线和所述第二电源列子引线相互连接，使得各个所述第二电源引线呈网格状。
根据本公开的一种实施方式，所述外围区设置有第二电源总线，所述第二电源总线与至少部分所述第二电源引线连接。
根据本公开的一种实施方式，所述外围区具有绑定区；所述第二电源总线具有相互连接的布线段和连接段；所述第二电源总线的数量为两个，两个所述第二电源总线的布线段均沿列方向延伸且分别位于所述显示区的两侧；所述第二电源总线的连接段延伸至所述绑定区。
根据本公开的一种实施方式，所述第二电源总线的布线段位于所述显示面板靠近所述绑定区的一端。
根据本公开的一种实施方式，所述像素驱动电路包括第二复位单元，所述显示面板的外围区包括绑定区；所述显示面板还设置有：
初始化总线，用于加载所述初始化电压；所述初始化总线的数量为两个且设于所述外围区，且包括相互连接的布线段和连接段；两个所述初始化总线的布线段均沿列方向延伸且分别位于所述显示区的两侧；所述初始化总线的连接段延伸至所述绑定区；
初始化引线，沿行方向贯穿所述显示区并与所述初始化总线的布线段连接；
第一电源总线，用于加载第一电源电压；所述第一电源总线的数量为两个且设于所述外围区，其一端延伸至所述绑定区；
第一电源引线，设于所述显示区且呈网格分布，且与所述第一电源总线连接；
所述第一电源总线与所述初始化总线部分交叠。
根据本公开的另一个方面，提供一种显示装置，包括上的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开提供的一种像素驱动电路的结构示意图。
图2为本公开提供的一种像素驱动电路的结构示意图。
图3为本公开提供的一种显示面板的结构示意图。
图4为本公开提供的一种显示面板的结构示意图。
图5为本公开提供的一种显示面板的结构示意图。
图6为本公开提供的一种显示面板的在一个像素驱动电路区域的局部结构示意图，其中仅示出了部分引线。
图7为本公开提供的一种显示面板的在一个像素驱动电路区域的局部结构示意图，其中仅示出了部分引线。
图8为本公开提供的一种显示面板的在一个像素驱动电路区域的局部结构示意图，其中仅示出了部分引线。
图9为本公开提供的一种显示面板的结构示意图，其中仅示出了部分引线。
图10为本公开提供的一种显示面板的结构示意图，其中仅示出了部分引线。
附图标记说明：
110、数据写入单元；120、阈值补偿单元；130、第一发光控制单元；140、第二发光控制单元；150、第一复位单元；160、第二复位单元；170、发光元件；210、扫描引线；220、数据引线；231、第一电源引线；232、第一电源总线；240、发光控制引线；251、第二电源引线；2511、第二电源行子引线；2512、第二电源列子引线；252、第二电源总线；2521、第二电源总线的布线段；2522、第二电源总线的连接段；261、初始化引线；262、初始化总线；2621、初始化总线的布线段；2622、初始化总线的连接段；270、复位控制引线；310、电路板；320、驱动芯片；T1、第二复位晶体管；T2、阈值补偿晶体管；T3、驱动晶体管；T4、数据写入晶体管；T5、第一发光控制晶体管；T6、第二发光控制晶体管；T7、第一复位晶体管；Cst、存储电容；Vgate、扫描信号；Vdata、数据电压；EM、发光控制信号；VDD、第一电源电压；VSS、第二电源电压；Vinit、初始化电压；Vreset、复位控制信号；N1、第一节点；N2、第二节点；N3、第三节点；N4、第四节点；A、行方向；B、列方向；C、外围区；D、显示区；E、绑定区；F、通孔。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。 当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
在本公开中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏极端子、漏区域或漏电极)与源极(源极端子、源区域或源电极)之间具有沟道区，并且电流可以流过漏极、沟道区以及源极。沟道区是指电流主要流过的区域。在使用类型相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本公开中，“源极”和“漏极”可以互相调换。从结构上，晶体管可以具有第一端、第二端和控制端，其中，晶体管的栅极可以作为晶体管的控制端；晶体管的源极和漏极中的一个可以作为晶体管的第一端，另一个可以作为晶体管的第二端。
在本公开中，晶体管的“导通”状态，指的是晶体管的源极和漏极之间处于电性连接的状态。晶体管的“截止”状态，指的是晶体管的源极和漏极之间处于电性断路的状态；可以理解的是，当晶体管截止时，其依然可以存在漏电流。
在一些OLED(有机电致发光二极管)显示面板中，设置有初始化引线对OLED的像素电极进行初始化，初始化引线上可以加载初始化电压。然而，显示面板沿远离源极驱动器的方向，初始化电压、驱动电压和公共电压均存在压降，且OLED的像素电极的电压与流经OLED的驱动电流直接相关。这导致OLED显示面板靠近源极驱动器的一端和远离源极驱动器的一端存在亮度差异。
进一步地，当显示面板设置有通孔时，OLED显示面板在通孔所在的行区域出现较为明显的色斑(mura)，该色斑在低灰阶状态下更为明显，这对低灰阶画面产生较大的影响。
本公开提供一种像素驱动电路以及应用该像素驱动电路的显示面板，以提高显示面板的亮度均一性。
参见图1，该像素驱动电路包括：
驱动晶体管T3，连接第一节点N1、第二节点N2和第三节点N3，用于在所述第一节点N1的控制下输出驱动电流至所述第三节点N3；
存储电容Cst，一端连接所述第一节点N1；
数据写入单元110，连接所述第二节点N2，用于响应扫描信号Vgate而加载数据电压Vdata至所述第二节点N2；
阈值补偿单元120，连接所述第一节点N1和所述第三节点N3，用于响应所述扫描信号Vgate而使得所述第一节点N1和所述第三节点N3之间导通；
第一发光控制单元130，连接所述第二节点N2，用于响应发光控制信号EM而加载第一电源电压VDD至所述第二节点N2；
第二发光控制单元140，连接所述第三节点N3和第四节点N4，用于响应所述发光控制信号EM而使得所述第三节点N3与所述第四节点N4之间导通；
第一复位单元150，连接所述第四节点N4，用于响应所述扫描信号Vgate而加载第二电源电压VSS至所述第四节点N4；
发光元件170，一端连接所述第四节点N4，另一端用于加载所述第二电源电压VSS。
根据本公开提供的像素驱动电路，发光元件170的一端用于加载第二电源电压VSS，另一端通过第二电源电压VSS进行复位。如此，当该像素驱动电路应用于显示面板上时，该像素驱动电路避免了采用初始化电压对发光元件170进行复位的情况，减少了不同位置的驱动晶体点的源漏电压差的差异，提高驱动晶体管T3工作环境的均一性，进而提高显示面板的亮度均一性。
下面，结合附图对本公开提供的像素驱动电路的结构、原理和效果做进一步地解释和说明。
参见图3和图4，本公开提供的像素驱动电路可以应用于一显示面板，该显示面板可以包括显示区D和围绕显示区D的外围区C。其中，像素 驱动电路可以设置于显示区D内，尤其是阵列设置于显示区D内；像素驱动电路的发光元件170可以作为显示面板的子像素。在外围区C可以设置有绑定区E，绑定区E用于绑定电路板或者驱动芯片。
在本公开的一种实施方式中，显示面板可以通过COP(chip on panel)技术绑定驱动芯片。绑定区E可以包括芯片绑定区和电路板绑定区，芯片绑定区内设置有用于与驱动芯片绑定的芯片绑定焊盘，电路板绑定区内设置有用于与电路板绑定的电路板绑定焊盘。
在本公开的另一种实施方式中，显示面板也可以通过COF(chip on film)技术绑定驱动芯片。其中，绑定区E包括电路板绑定区，电路板绑定区内设置有用于与覆晶薄膜绑定的电路板绑定焊盘，在覆晶薄膜上可以绑定有驱动芯片。
可以理解的是，显示面板也可以通过其他方法绑定驱动芯片，例如显示面板绑定柔性电路板且在柔性电路板上绑定驱动芯片，本公开对此不做限定。
可选地，本公开的发光元件170可以为OLED(有机电致发光二极管)。
可选地，参见图3，显示面板可以包括依次层叠设置的衬底基板F100、电路层F200和像素层F300。
衬底基板F100可以为无机材料的衬底基板F100，也可以为有机材料的衬底基板F100。举例而言，在本公开的一种实施方式中，衬底基板F100的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板F100的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。在本公开的另一种实施方式中，衬底基板F100也可以为柔性衬底基板F100，例如衬底基板F100的材料可以为聚酰亚胺(polyimide，PI)。衬底基板F100还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板F100可以包括依次层叠设置的底膜 层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
可选地，在电路层F200中设置有本公开的像素驱动电路的各个单元、驱动晶体管和存储电容。进一步地，像素驱动电路中的各个电源可以包括有晶体管F200M和存储电容。进一步地，晶体管F200M可以为薄膜晶体管，薄膜晶体管可以为顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管；薄膜晶体管的有源层的材料可以为非晶硅半导体材料、低温多晶硅半导体材料、金属氧化物半导体材料、有机半导体材料或者其他类型的半导体材料；薄膜晶体管可以为N型薄膜晶体管或者P型薄膜晶体管。在本公开的一种实施方式中，薄膜晶体管为低温多晶硅晶体管。
可以理解的是，电路层F200的各个晶体管中，任意两个晶体管之间的类型可以相同或者不相同。示例性地，在一种实施方式中，在一个像素驱动电路中，部分晶体管可以为N型晶体管且部分晶体管可以为P型晶体管。再示例性地，在本公开的另一种实施方式中，在一个像素驱动电路中，部分晶体管的有源层的材料可以为低温多晶硅半导体材料，且部分晶体管的有源层的材料可以为金属氧化物半导体材料。
晶体管可以具有第一端、第二端和控制端，第一端和第二端中的一个可以为晶体管的源极且另一个可以为晶体管的漏极，控制端可以为晶体管的栅极。可以理解的是，晶体管的源极和漏极为两个相对且可以相互转换的概念；当晶体管的工作状态改变时，例如电流方向改变时，晶体管的源极和漏极可以互换。
可选地，电路层F200可以包括层叠于衬底基板F100和像素层F300之间的半导体层F203、栅极绝缘层F204、栅极层F205、层间电介质层F206和源漏金属层F207等。各个薄膜晶体管和存储电容可以由半导体层F203、栅极绝缘层F204、栅极层F205、层间电介质层F206、源漏金属层F207等膜层形成。其中，各个膜层的位置关系可以根据薄膜晶体管的膜层结构确定。举例而言，在本公开的一种实施方式中，电路层F200可以包括依次层叠设置的半导体层F203、栅极绝缘层F204、栅极层F205、层间电介质层F206和源漏金属层F207，如此所形成的薄膜晶体管为顶栅型薄膜晶体管。再举例而言，在本公开的另一种实施方式中，电路层F200可以包括依次层叠设置的栅极层F205、栅极绝缘层F204、半导体层F203、层间 电介质层F206和源漏金属层F207，如此所形成的薄膜晶体管为底栅型薄膜晶体管。
在一些实施方式中，电路层F200还可以采用双栅极层F205结构，即栅极层F205可以包括第一栅极层和第二栅极层，栅极绝缘层F204可以包括用于隔离半导体层F203和第一栅极层的第一栅极绝缘层，以及包括用于隔离第一栅极层和第二栅极层的第二栅极绝缘层。举例而言，在本公开的一种实施方式中，电路层F200可以包括依次层叠设置于衬底基板F100一侧的半导体层F203、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层、层间电介质层F206和源漏金属层F207。
在一些实施方式中，电路层F200还可以采用双源漏金属层F207的结构，即源漏金属层F207可以包括第一源漏金属层和第二源漏金属层，层间电介质层F206可以包括位于第一源漏金属层靠近衬底基板F100一侧的第一层间电介质层和位于第一源漏金属层和第二源漏金属层之间的第二层间电介质层。
可选地，电路层F200还可以包括有钝化层，钝化层可以设于源漏金属层F207远离衬底基板F100的表面，以便保护源漏金属层F207。
可选地，电路层F200还可以包括设于衬底基板F100与半导体层F203之间的缓冲材料层，且半导体层F203、栅极层F205等均位于缓冲材料层远离衬底基板F100的一侧。缓冲材料层的材料可以为氧化硅、氮化硅等无机绝缘材料。缓冲材料层可以为一层无机材料层，也可以为多层层叠的无机材料层。示例性地，在本公开的一种实施方式中，参见图3，缓冲材料层可以包括靠近衬底基板F100一侧的阻隔层F201和位于阻隔层F201远离衬底基板F100一侧的缓冲层F202。阻隔层F201用于阻挡衬底基板F100中的离子等组分向电路层F200渗透，使得电路层F200保持性能稳定。缓冲层F202可以提高电路层F200与衬底基板F100之间的结合力，并为电路层F200提供稳定环境。
可选地，电路层F200还可以包括位于源漏金属层F207和像素层F300之间的平坦化层F208，平坦化层F208可以为像素电极提供平坦化表面。可选地，平坦化层F208的材料可以为有机材料。
可选地，像素层F300可以设置于电路层F200远离衬底基板F100的 一侧，本公开的像素驱动电路的发光元件可以设置于该像素层F300。可选地，像素层F300可以包括依次层叠设置的像素电极层F301、像素定义层F302、支撑柱层F303、有机发光功能层F304和公共电极层F305。其中，像素电极层F301在显示面板的显示区具有多个像素电极；像素定义层F302在显示区具有与多个像素电极一一对应设置的多个贯通的像素开口，任意一个像素开口暴露对应的像素电极的至少部分区域。支撑柱层F303在显示区包括多个支撑柱，且支撑柱位于像素定义层F302远离衬底基板F100的表面，以便在蒸镀制程中支撑精细金属掩模版(Fine Metal Mask，FMM)。有机发光功能层F304至少覆盖被像素定义层F302所暴露的像素电极。其中，有机发光功能层F304可以包括有机电致发光材料层，以及可以包括有空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一种或者多种。可以通过蒸镀工艺制备有机发光功能层F304的各个膜层，且在蒸镀时可以采用精细金属掩模版或者开放式掩膜板(Open Mask)定义各个膜层的图案。公共电极层F305在显示区可以覆盖有机发光功能层F304。如此，像素电极、公共电极层F305和位于像素电极和公共电极层F305之间的有机发光功能层F304形成有机发电致光二极管，任意一个有机电致发光二极管可以作为显示面板的一个子像素。
在一些实施方式中，像素层F300还可以包括位于公共电极层F305远离衬底基板F100一侧的光取出层，以增强有机发光二极管的出光效率。
可选地，显示面板还可以包括薄膜封装层F400。薄膜封装层F400设于像素层F300远离衬底基板F100的表面，可以包括交替层叠设置的无机封装层和有机封装层。其中，无机封装层可以有效的阻隔外界的水分和氧气，避免水氧入侵有机发光功能层F304而导致材料降解。可选地，无机封装层的边缘可以位于外围区。有机封装层位于相邻的两层无机封装层之间，以便实现平坦化和减弱无机封装层之间的应力。其中，有机封装层的边缘，可以位于显示区和无机封装层的边缘之间。示例性地，薄膜封装层F400包括依次层叠于像素层F300远离衬底基板F100一侧的第一无机封装层F401、有机封装层F402和第二无机封装层F403。
可选地，显示面板还可以包括降反层F500，降反层F500可以设置于 薄膜封装层F400远离像素层F300的一侧，用于降低显示面板对环境光线的反射，进而降低环境光线对显示效果的影响。在本公开的一种实施方式中，降反层F500可以包括层叠设置的彩膜层和黑矩阵层，如此可以在实现降低环境光线干扰的同时，可以避免降低显示面板的透光率。在本公开的另一种实施方式中，降反层F500可以为偏光片，例如可以为图案化的涂布型圆偏光片。
可选地，显示面板还可以包括触控功能层F600，触控功能层F600设于薄膜封装层F400远离衬底基板F100的一侧，用于实现显示面板的触控操作。在本公开的一种实施方式中，触控功能层F600可以设于薄膜封装层F400和降反层F500之间。
可选地，参见图6～图8，显示面板在源漏金属层形成有数据引线220，数据引线220可以沿列方向B延伸并与数据写入单元110电连接，用于向数据写入单元110加载数据电压Vdata。
可选地，参见图6～图8，显示面板在栅极层设置有扫描引线210，扫描引线210沿行方向A延伸并用于加载扫描信号Vgate。该扫描引线210可以与数据写入单元110、阈值补偿单元120和第一复位单元150电连接。
可选地，参见图6～图8，显示面板在栅极层设置有发光控制引线240，发光控制引线240沿行方向A延伸并用于加载发光控制信号EM。该发光控制引线240可以与第一发光控制单元130、第二发光控制单元140电连接。
可选地，参见图6～图8，显示面板在电路层设置有第一电源引线231，第一电源引线231用于加载第一电源电压VDD。第一电源引线231可以与第一发光控制单元130连接，以便向第一发光控制单元130加载第一电源电压VDD。进一步地，第一电源引线231设于所述显示区D且呈网格分布，如此可以提高第一电源引线231上的第一电源电压VDD的均一性。
在本公开的一种实施方式中，第一电源引线231设置于源漏金属层。在本公开的另一种实施方式中，第一电源引线231可以部分设置于源漏金属层且部分设置于栅极层。示例性地，第一电源引线231网格状分布，其沿列方向延伸的部分可以设置于源漏金属层，其沿行方向延伸的部分可以设置于栅极层。
在本公开的一种实施方式中，参见图9和图10，显示面板还可以设置有第一电源总线232。第一电源总线232设置于外围区C，其一端延伸至绑定区E。第一电源总线232可以与绑定区E中的焊盘连接，并借助电路板与显示面板在绑定区E的绑定连接，使得其电路延伸至电路板中，以便于从电路板接收第一电源电压VDD。第一电源总线232与第一电源引线231连接，用于加载第一电源电压VDD并将第一电源电压VDD分布至各个第一电源引线231上。
在本公开的一种实施方式中，参见图9和图10，第一电源总线232的数量可以为两个，两个第一电源总线232可以对称分布。
在本公开的一种实施方式中，第一电源总线232设置于源漏金属层。
参见图6～图8，显示面板还可以设置有用于加载所述第二电源电压VSS的第二电源引线251，所述第二电源引线251与所述像素驱动电路的第四节点N4电连接。
可选地，参见图9和图10，所述第二电源引线251的数量为多个。参见图6～图8，任意一个第二电源引线251沿行方向A延伸或者沿列方向B延伸。进一步可选地，任意一个像素驱动电路区域，均通过有第二电源引线251。
在本公开的一种实施方式中，参见图9和图10，所述第二电源引线251包括沿行方向A延伸的多个第二电源行子引线2511和沿列方向B延伸的多个第二电源列子引线2512；所述第二电源行子引线2511和所述第二电源列子引线2512相互连接，使得各个所述第二电源引线251呈网格状。如此，第二电源引线251呈网格状设计，可以提高显示面板中第二电源电压VSS的均一性，降低第二电源电压VSS的压降，进而提高显示面板的亮度均一性。
第二电源引线251可以设置于源漏金属层，例如可以在第一源漏金属层和第二源漏金属层之间相互跨接并延伸。当然的，可以理解的是，第二电源引线251也可以部分设置于其他膜层，例如可以部分设置于半导体层、栅极层、像素电极层等膜层。
可选地，参见图9和图10，所述外围区C设置有第二电源总线252，所述第二电源总线252与至少部分所述第二电源引线251连接。参见图9 和图10，第二电源总线252与绑定区E电连接，并能够加载第二电源电压VSS，进而将第二电源电压VSS分布至第二电源引线251。可以理解的是，如果部分第二电源引线251不与第二电源总线252直接连接，则可以借助其他导电结构，例如借助其他第二电源引线251与第二电源总线252电连接。
可选地，第二电源总线252的数量为两个，且呈对称设置。
在本公开的一种实施方式中，所述第二电源总线252具有相互连接的布线段2521和连接段2522；所述第二电源总线252的数量为两个，两个所述第二电源总线252的布线段2521均沿列方向B延伸且分别位于所述显示区D的两侧；所述第二电源总线252的连接段2522延伸至所述绑定区E。
在该实施方式中，可选地，显示面板的公共电极可以覆盖显示区并延伸至外围区，且与该第二电源总线252的布线段2521部分交叠，以便第二电源总线252能够将第二电源电压VSS加载至公共电极上。进一步地，像素电极层可以设置有转接电极，转接电极可以与第二电源总线252通过过孔连接，公共电极可以与转接电极连接，进而实现公共电极与第二电源总线252之间的电连接。
在本公开的一种实施方式中，参见图9和图10，第二电源总线252的布线段2521沿列方向B延伸；第二电源引线251中的至少部分沿行方向A延伸以与两根第二电源总线252的布线段2521连接。如此，可以借助低阻抗的第二电源总线252向第二电源引线251加载第二电源电压VSS，进一步提高第二电源电压VSS的均一性。
示例性地，参见图9，第二电源引线251中沿行方向A延伸的部分，例如各个第二电源行子引线2511，其两端分别与两个第二电源总线252的布线段2521连接。
在本公开的另一种实施方式中，参见图10，所述第二电源总线252的布线段2521位于所述显示面板靠近所述绑定区E的一端。换言之，第二电源总线252的布线段2521的长度短于显示区D在列方向B上的长度，第二电源总线252的布线段2521仅在靠近绑定区E的一侧设置。这种设置方式，可以减少第二电源总线252的布线段2521的延伸长度，进而降 低第二电源总线252的布线段2521所占用的边框空间，进而降低显示面板的边框。
示例性地，第二电源总线252的布线段2521可以仅位于显示面板靠近绑定区E的顶角处，即位于显示区D的靠近绑定区E的两个顶角的外侧。如此，第二电源总线252的布线段2521不沿列方向B进一步延伸，进而显著的减小显示面板的边框宽度。第二电源引线251可以呈网格状分布，并与第二电源总线252的布线段2521电连接，保证第二电源电压VSS能够加载至各个像素驱动电路的第四节点N4。
在本公开中，节点是指具有等电位且相互电连接的导电结构，该导电结构既可以为位于同一膜层的同一导电结构，可以为位于同一膜层的不同导电结构，还可以为位于不同膜层的不同导电结构。
在本公开的一种实施方式中，参见图2，所述数据写入单元110包括数据写入晶体管T4，所述数据写入晶体管T4具有第一端、第二端和控制端，所述数据写入晶体管T4的第一端用于加载所述数据电压Vdata，所述数据写入晶体管T4的第二端连接所述第二节点N2，所述数据写入晶体管T4的控制端用于加载所述扫描信号Vgate。
可选地，数据写入晶体管T4的第一端可以与数据引线220电连接，数据写入晶体管T4的控制端可以与扫描引线210电连接。
在本公开中，晶体管控制端与扫描引线210电连接，既可以是指晶体管的栅极复用为扫描引线210的一部分(即扫描引线210与晶体管的有源层交叠)，又可以是指晶体管的栅极与扫描引线210之间直接或者间接连接。
在本公开的一种实施方式中，所述阈值补偿单元120包括阈值补偿晶体管T2，所述阈值补偿晶体管T2具有第一端、第二端和控制端，所述阈值补偿晶体管T2的第一端连接所述第一节点N1，所述阈值补偿晶体管T2的第二端连接所述第三节点N3，所述阈值补偿晶体管T2的控制端用于加载所述扫描信号Vgate。
可选地，阈值补偿晶体管T2的控制端与扫描引线210电连接。
在本公开的一种实施方式中，所述第一发光控制单元130包括第一发光控制晶体管T5，所述第一发光控制晶体管T5具有第一端、第二端和控 制端，所述第一发光控制晶体管T5的第一端用于加载所述第一电源电压VDD，所述第一发光控制晶体管T5的第二端连接所述第二节点N2，所述第一发光控制晶体管T5的控制端用于加载所述发光控制信号EM。
可选地，第一发光控制晶体管T5的第一端与第一电源引线231电连接，第一发光控制晶体管T5的控制端与发光控制引线240电连接。
在本公开中，晶体管控制端与发光控制引线240电连接，既可以是指晶体管的栅极复用为发光控制引线240的一部分(即发光控制引线240与晶体管的有源层交叠)，又可以是指晶体管的栅极与发光控制引线240之间直接或者间接连接。
在本公开的一种实施方式中，所述第二发光控制单元140包括第二发光控制晶体管T6，所述第二发光控制晶体管T6具有第一端、第二端和控制端，所述第二发光控制晶体管T6的第一端连接所述第三节点N3，所述第二发光控制晶体管T6的第二端连接所述第四节点N4，所述第二发光控制晶体管T6的控制端用于加载所述发光控制信号EM；
可选地，第二发光控制晶体管T6的第二端与像素电极连接，像素电极可以作为本公开的第四节点N4的一部分；第二发光控制晶体管T6的控制端与发光控制引线240电连接。
在本公开的一种实施方式中，所述第一复位单元150包括第一复位晶体管T7，所述第一复位晶体管T7具有第一端、第二端和控制端，所述第一复位晶体管T7的第一端用于加载所述第二电源电压VSS，所述第一复位晶体管T7的第二端连接所述第四节点N4，所述第一复位晶体管T7的控制端用于加载所述扫描信号Vgate。
可选地，第一复位晶体管T7的第一端与第二电源引线251电连接，第一复位晶体管T7的第二端与像素电极电连接，第一复位晶体管T7的控制端与扫描引线210电连接。
在本公开提供的显示面板中，存储电容Cst的一端与第一节点N1电连接，另一端可以用于加载第一电源电压VDD，也可以用于加载第二电源电压VSS。
可选地，参见图1，所述像素驱动电路还包括第二复位单元160，所述第二复位单元160连接所述第一节点N1，用于响应复位控制信号Vreset 而加载初始化电压Vinit至所述第一节点N1。如此，该像素驱动电路还可以对第一节点N1进行复位，提高各个显示驱动电路工作的稳定性和均一性。
在本公开的一种实施方式中，参见图2，第二复位单元160可以包括第二复位晶体管T1，第二复位晶体管T1具有第一端、第二端和控制端，其中，第二复位晶体管T1的第一端用于加载初始化电压Vinit，第二复位晶体管T1的第二端与第一节点N1电连接，第二复位晶体管T1的控制端用于加载复位控制信号Vreset。
在本公开的一种实施方式中，参见图6～图10，显示面板可以设置有复位控制引线270，复位控制引线270用于加载复位控制信号Vreset。可选地，复位控制引线270可以沿行方向A延伸，且与第二复位晶体管T1的栅极电连接。
进一步可选地，复位控制引线270可以设置于栅极层。
在本公开的一种实施方式中，显示面板可以设置有初始化引线261，初始化引线261用于加载初始化电压Vinit。可选地，初始化引线261可以沿行方向A延伸，且与第二复位晶体管T1的第一端电连接。示例性地，初始化引线261可以沿行方向A贯穿所述显示区D。
进一步可选地，初始化引线261可以设置于源漏金属层。
可选地，参见图9和图10，显示面板还可以设置有初始化总线262，初始化总线262用于加载所述初始化电压Vinit；所述初始化总线262的数量为两个且设于所述外围区C，且包括相互连接的布线段2621和连接段2622；两个所述初始化总线262的布线段2621均沿列方向B延伸且分别位于所述显示区D的两侧；所述初始化总线262的连接段2622延伸至所述绑定区E。初始化引线261沿行方向A贯穿所述显示区D并与所述初始化总线262的布线段2621连接。
如此，初始化总线262可以将初始化电压Vinit分布至各个初始化引线261，并提高初始化电压Vinit的均一性。
可选地，参见图9和图10，初始化总线262的位于第二电源总线252与显示区D之间。
可选地，参见图9和图10，在靠近绑定区E的位置，两个初始化总 线262的连接段2622位于两个第一电源总线232的内侧。在靠近显示区D的位置，两个初始化总线262的连接段2622向显示面板的行方向A的两侧弯折，这使得两个初始化总线262的连接段2622与第一电源总线232部分交叠。
在本公开的一种实施方式中，参见图6～图8，在一个像素驱动电路的范围内，沿列方向，扫描引线210、第一电源引线231、发光控制引线240、初始化引线261和复位控制引线270依次排列。
在本公开的一种实施方式中，参见图4和图5，所述显示面板在显示区D设置有通孔F。在该实施方式中，显示面板的通孔F周围以及与通孔F同行设置的各个像素不会出现发光异常，进而可以避免通孔F周边的光斑(Hole Mura)问题。本公开的像素驱动电路采用第二电源电压VSS对像素驱动电路的第四节点N4进行初始化；相较于常规的初始化电压Vinit，第二电源电压VSS的分布更为均一且压降更小，其所收到的负载大小(发光元件170数量的多少)的影响更小。如此，这克服了相关技术中通孔F周边的初始化电压Vinit因发光元件170分布数量差异而呈现出明显的压差的问题(压差可以达到0.2V)，提高了开孔屏的亮度均一性。
本公开实施方式还提供一种显示装置，该显示装置包括上述显示面板实施方式所描述的任意一种显示面板。该显示装置可以为智能手表屏幕、智能手机屏幕或者其他类型的显示装置。由于该显示装置具有上述显示面板实施方式所描述的任意一种显示面板，因此具有相同的有益效果，本公开在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (12)

  1. 一种像素驱动电路，包括：
    驱动晶体管，连接第一节点、第二节点和第三节点，用于在所述第一节点的控制下输出驱动电流至所述第三节点；
    存储电容，一端连接所述第一节点；
    数据写入单元，连接所述第二节点，用于响应扫描信号而加载数据电压至所述第二节点；
    阈值补偿单元，连接所述第一节点和所述第三节点，用于响应所述扫描信号而使得所述第一节点和所述第三节点之间导通；
    第一发光控制单元，连接所述第二节点，用于响应发光控制信号而加载第一电源电压至所述第二节点；
    第二发光控制单元，连接所述第三节点和第四节点，用于响应所述发光控制信号而使得所述第三节点与所述第四节点之间导通；
    第一复位单元，连接所述第四节点，用于响应所述扫描信号而加载第二电源电压至所述第四节点；
    发光元件，一端连接所述第四节点，另一端用于加载所述第二电源电压。
  2. 根据权利要求1所述的像素驱动电路，其中，
    所述数据写入单元包括数据写入晶体管，所述数据写入晶体管具有第一端、第二端和控制端，所述数据写入晶体管的第一端用于加载所述数据电压，所述数据写入晶体管的第二端连接所述第二节点，所述数据写入晶体管的控制端用于加载所述扫描信号；
    所述阈值补偿单元包括阈值补偿晶体管，所述阈值补偿晶体管具有第一端、第二端和控制端，所述阈值补偿晶体管的第一端连接所述第一节点，所述阈值补偿晶体管的第二端连接所述第三节点，所述阈值补偿晶体管的控制端用于加载所述扫描信号；
    所述第一发光控制单元包括第一发光控制晶体管，所述第一发光控制晶体管具有第一端、第二端和控制端，所述第一发光控制晶体管的第一端用于加载所述第一电源电压，所述第一发光控制晶体管的第二端连接所述第二节点，所述第一发光控制晶体管的控制端用于加载所述发光控制信号；
    所述第二发光控制单元包括第二发光控制晶体管，所述第二发光控制晶体管具有第一端、第二端和控制端，所述第二发光控制晶体管的第一端连接所述第三节点，所述第二发光控制晶体管的第二端连接所述第四节点，所述第二发光控制晶体管的控制端用于加载所述发光控制信号；
    所述第一复位单元包括第一复位晶体管，所述第一复位晶体管具有第一端、第二端和控制端，所述第一复位晶体管的第一端用于加载所述第二电源电压，所述第一复位晶体管的第二端连接所述第四节点，所述第一复位晶体管的控制端用于加载所述扫描信号。
  3. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括第二复位单元，所述第二复位单元连接所述第一节点，用于响应复位信号而加载初始化电压至所述第一节点。
  4. 一种显示面板，包括权利要求1～3任意一项所述的像素驱动电路。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板具有显示区和围绕所述显示区的外围区；
    所述显示面板在所述显示区设置有用于加载所述第二电源电压的第二电源引线，所述第二电源引线与所述像素驱动电路的第四节点电连接。
  6. 根据权利要求5所述的显示面板，其中，所述第二电源引线的数量为多个，且沿行方向延伸或者沿列方向延伸。
  7. 根据权利要求5所述的显示面板，其中，所述第二电源引线包括沿行方向延伸的多个第二电源行子引线和沿列方向延伸的多个第二电源列子引线；所述第二电源行子引线和所述第二电源列子引线相互连接，使得各个所述第二电源引线呈网格状。
  8. 根据权利要求5所述的显示面板，其中，所述外围区设置有第二电源总线，所述第二电源总线与至少部分所述第二电源引线连接。
  9. 根据权利要求8所述的显示面板，其中，所述外围区具有绑定区；所述第二电源总线具有相互连接的布线段和连接段；所述第二电源总线的数量为两个，两个所述第二电源总线的布线段均沿列方向延伸且分别位于所述显示区的两侧；所述第二电源总线的连接段延伸至所述绑定区。
  10. 根据权利要求9所述的显示面板，其中，所述第二电源总线的布线段位于所述显示面板靠近所述绑定区的一端。
  11. 根据权利要求5所述的显示面板，其中，所述像素驱动电路包括第二复位单元，所述显示面板的外围区包括绑定区；所述显示面板还设置有：
    初始化总线，用于加载所述初始化电压；所述初始化总线的数量为两个且设于所述外围区，且包括相互连接的布线段和连接段；两个所述初始化总线的布线段均沿列方向延伸且分别位于所述显示区的两侧；所述初始化总线的连接段延伸至所述绑定区；
    初始化引线，沿行方向贯穿所述显示区并与所述初始化总线的布线段连接；
    第一电源总线，用于加载第一电源电压；所述第一电源总线的数量为两个且设于所述外围区，其一端延伸至所述绑定区；
    第一电源引线，设于所述显示区且呈网格分布，且与所述第一电源总线连接；
    所述第一电源总线与所述初始化总线部分交叠。
  12. 一种显示装置，包括权利要求4～11任意一项所述的显示面板。
PCT/CN2021/132462 2021-03-25 2021-11-23 像素驱动电路、显示面板和显示装置 WO2022199084A1 (zh)

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