WO2023103060A1 - 柔性显示面板和柔性阵列基板 - Google Patents

柔性显示面板和柔性阵列基板 Download PDF

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Publication number
WO2023103060A1
WO2023103060A1 PCT/CN2021/139360 CN2021139360W WO2023103060A1 WO 2023103060 A1 WO2023103060 A1 WO 2023103060A1 CN 2021139360 W CN2021139360 W CN 2021139360W WO 2023103060 A1 WO2023103060 A1 WO 2023103060A1
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WO
WIPO (PCT)
Prior art keywords
drain
source
opening
connection part
active layer
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Application number
PCT/CN2021/139360
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English (en)
French (fr)
Inventor
曹蔚然
林高波
徐源竣
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/623,604 priority Critical patent/US20240040834A1/en
Publication of WO2023103060A1 publication Critical patent/WO2023103060A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present application relates to the field of flexible display technology, in particular to a flexible display panel and a flexible array substrate.
  • the flexible display panel includes a flexible array substrate, and the flexible array substrate includes an array composed of a plurality of thin film transistors.
  • the requirements for the bending performance of flexible display panels are getting higher and higher, it is difficult for conventional thin film transistors to meet the requirements of flexible display panels.
  • the present application provides a flexible display panel and a flexible array substrate capable of improving bending performance.
  • the application provides a flexible display panel, which includes:
  • a thin film transistor the thin film transistor includes an active layer disposed on the flexible substrate, an opening is opened in the active layer, and the opening penetrates at least a part of the active layer.
  • the active layer includes a channel region, a source connection part, and a drain connection part, and the source connection part and the drain connection part are located on opposite sides of the channel region;
  • the thin film transistor also includes a source and a drain, the source and the drain are arranged on the side of the active layer away from the flexible substrate, and the source is connected to the source connection part , the drain is connected to the drain connection part, and the opening is located in at least one of the source connection part and the drain connection part.
  • At least one of the source and the drain extends into the opening to connect with the active layer.
  • the opening is located in the source connection part and the drain connection part, and the opening in the source connection part is connected to the drain connection part.
  • the openings are arranged symmetrically with respect to the channel region.
  • the thin film transistor further includes an ohmic contact layer, and the ohmic contact layer includes a first ohmic contact portion and a second ohmic contact portion, and the first ohmic contact portion is located between the source connection portion and the second ohmic contact portion. Between the sources, the second ohmic contact is located between the drain connection and the drain, at least one of the first ohmic contact and the second ohmic contact extends into the connected to the active layer in the opening.
  • the thin film transistor further includes a gate and a gate insulating layer, the gate is located between the active layer and the source and the drain, and the gate insulating layer Located between the gate and the active layer, the opening has an area of 0.1 square micrometers to 20 square micrometers.
  • the active layer includes a channel region, and the opening is located in the channel region.
  • the openings in the channel region are arranged symmetrically.
  • the active layer includes a channel region, a source connection part, and a drain connection part, and the source connection part and the drain connection part are located on opposite sides of the channel region, so The openings are located in the channel region, the source connection part and the drain connection part, the openings in the channel region are arranged symmetrically, and the openings in the source connection part and the drain
  • the opening in the connecting portion is arranged symmetrically with respect to the channel region, the source and the drain extend into the opening to connect with the active layer
  • the thin film transistor also includes a gate an insulating layer, the gate insulating layer covers the channel region, and the gate insulating layer fills the opening.
  • the flexible display panel further includes a first electrode, a pixel definition layer, a light-emitting layer, and a second electrode, the first electrode is disposed on the thin film transistor, and the pixel definition layer is disposed on the second electrode.
  • the present application provides a flexible array substrate, including:
  • a thin film transistor the thin film transistor includes an active layer disposed on the flexible substrate, an opening is opened in the active layer, and the opening penetrates at least a part of the active layer.
  • the active layer includes a channel region, a source connection part, and a drain connection part, and the source connection part and the drain connection part are located opposite to the channel region. both sides;
  • the thin film transistor also includes a source and a drain, the source and the drain are arranged on the side of the active layer away from the flexible substrate, and the source is connected to the source connection part , the drain is connected to the drain connection part, and the opening is located in at least one of the source connection part and the drain connection part.
  • At least one of the source electrode and the drain electrode extends into the opening to connect with the active layer.
  • the opening is located in the source connecting portion and the drain connecting portion, and the opening in the source connecting portion is connected to the drain connecting portion
  • the openings are arranged symmetrically with respect to the channel region.
  • the thin film transistor further includes an ohmic contact layer, the ohmic contact layer includes a first ohmic contact portion and a second ohmic contact portion, the first ohmic contact portion is located at the source Between the electrode connection part and the source electrode, the second ohmic contact part is located between the drain connection part and the drain electrode, at least the first ohmic contact part and the second ohmic contact part One extends into the opening and connects with the active layer.
  • the thin film transistor further includes a gate and a gate insulating layer, the gate is located between the active layer and the source and the drain, the The gate insulating layer is located between the gate and the active layer, and the area of the opening is 0.1 square micrometers to 20 square micrometers.
  • the active layer includes a channel region, and the opening is located in the channel region.
  • the openings in the channel region are arranged symmetrically.
  • the active layer includes a channel region, a source connection part, and a drain connection part, and the source connection part and the drain connection part are located opposite to the channel region.
  • the openings are located in the channel region, the source connection part and the drain connection part, the openings in the channel region are arranged symmetrically, and the openings in the source connection part and the The opening in the drain connection part is arranged symmetrically with respect to the channel region, the source and the drain extend into the opening to connect with the active layer, and the thin film transistor
  • a gate insulating layer is also included, the gate insulating layer covers the channel region, and the gate insulating layer fills the opening.
  • the opening holes in the active layer when a bending force is applied to the flexible display panel, the stress on the thin film transistors is concentrated in the openings, which can effectively reduce the damage to the thin film transistors caused by bending. Even if cracks are generated in the active layer due to excessive bending force, the openings in the active layer can effectively prevent the crack from spreading and protect the thin film transistor.
  • FIG. 1 is a schematic cross-sectional view of a flexible display panel according to a first embodiment of the present application.
  • FIG. 2 is a schematic top view of an active layer of the flexible display panel in FIG. 1 .
  • FIG. 3 is a schematic cross-sectional view of a flexible display panel according to a second embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional view of a flexible display panel according to a third embodiment of the present application.
  • FIG. 5 is a schematic top view of an active layer of the flexible display panel of FIG. 4 .
  • FIG. 6 is a schematic cross-sectional view of a flexible display panel according to a fourth embodiment of the present application.
  • FIG. 7(a) to 7(h) are schematic diagrams of the steps of the method for manufacturing the flexible display panel of the present application, wherein FIG. 7(c) is a schematic top view of the semiconductor layer in FIG. 7(b), and FIG. 7(e ) is a schematic top view of the active layer in Figure 7(d).
  • a first feature being “on” or “below” a second feature may include the first and second features directly, or may include that the first and second features are not directly connected but through another characteristic contact between them.
  • “above”, “above” and “above” the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature.
  • "Below”, “beneath” and “under” the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • features defined as “first” and “second” may explicitly or implicitly include one or more features.
  • the present application provides a flexible display panel and a flexible array substrate.
  • the display panel in the embodiment of the present application can be used in mobile phones, tablet computers, e-readers, electronic display screens, notebook computers, mobile phones, augmented reality (augmented reality, AR) ⁇ virtual reality (virtual reality, VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.
  • augmented reality augmented reality, AR
  • virtual reality virtual reality
  • the display panel may be an organic light-emitting diode (Organic Light-emitting Diode, OLED) display panel, a quantum dot light-emitting diode (Quantum Dot Light-emitting Diode, QLED) display panel, Micro Light-emitting Diode (Micro-LED) display panel, submillimeter light-emitting diode (Mini Light-emitting Diode, Mini-LED) display panel or Liquid Crystal (Liquid Crystal) display panel.
  • OLED Organic Light-emitting Diode
  • QLED Quantum Dot Light-emitting Diode
  • Micro-emitting Diode Micro Light-emitting Diode
  • submillimeter light-emitting diode Mini Light-emitting Diode, Mini-LED
  • Liquid Crystal Liquid Crystal
  • the flexible display panel 1 includes a flexible array substrate 100 .
  • the flexible array substrate 100 includes a flexible substrate 10 and a thin film transistor 20 disposed on the flexible substrate 10 .
  • the flexible array substrate 100 may further include a buffer layer BL disposed between the flexible substrate 10 and the thin film transistor 20 .
  • the material of the flexible substrate 10 is selected from polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate (PAR), polycarbonate One of ester (PC), polyetherimide (PEI) and polyethersulfone (PES).
  • PI polyimide
  • PEN polyethylene naphthalate
  • PET polyethylene terephthalate
  • PAR polyarylate
  • PC polycarbonate One of ester
  • PEI polyetherimide
  • PES polyethersulfone
  • the thin film transistor 20 includes an active layer AL, a gate GE, a gate insulating layer GI, a source SE, a drain DE, an interlayer insulating layer IL, and a passivation layer PV.
  • the active layer AL is disposed on the flexible substrate 10
  • the gate GE is disposed on the side of the active layer AL away from the flexible substrate 10
  • the gate insulating layer GI is disposed between the gate GE and the active layer AL
  • the SE and the drain DE are arranged on the side of the gate GE and the active layer AL away from the flexible substrate 10
  • the interlayer insulating layer IL is arranged between the source SE, the drain DE and the active layer AL, and the passivation layer PV Covering the side of the source SE and the drain DE away from the flexible substrate 10 .
  • the source SE and the drain DE are respectively connected to two ends of the active layer AL through contact holes opened in the interlayer insulating layer IL.
  • An opening OP is opened in the active layer, and the opening OP penetrates at least a part of the active layer AL.
  • the opening OP can be a through hole or a blind hole, that is, the opening OP can completely penetrate the active layer AL, or partially penetrate the active layer AL.
  • the active layer AL includes a channel region AL1 , a source connection portion AL2 and a drain connection portion AL3 , and the source connection portion AL2 and the drain connection portion AL3 are located on opposite sides of the channel region AL1 .
  • the source SE is connected to the source connection part AL2, and the drain DE is connected to the drain connection part AL3.
  • the opening OP may be located in at least one of the channel area AL1 , the source connection part AL2 and the drain connection part AL3 . When the opening OP is located in at least one of the source connection portion AL2 and the drain connection portion AL3 , at least one of the source SE and the drain DE extends into the opening OP to connect with the active layer AL.
  • the opening OP is located in the source connection portion AL2 and the drain connection portion AL3 .
  • the source SE extends into the opening OP of the source connection portion AL2 to connect to the source connection portion AL2
  • the drain DE extends into the opening OP of the drain connection portion AL3 to connect to the drain connection portion AL3 .
  • the film covering the side of the channel region AL1 away from the flexible substrate 10 can extend into the opening OP to fill the opening OP.
  • the film layer covering the side of the channel region AL1 away from the flexible substrate 10 is, for example, a gate insulating layer in a top-gate transistor, and a source-drain layer, an ohmic contact layer, or a channel protection layer in a bottom-gate transistor.
  • the setting of the opening OP can increase the overlapping area of the active layer AL, the source SE and the drain DE, reduce the contact resistance, and improve the device performance of the thin film transistor 20 .
  • the number and arrangement of the openings OP are not limited in this application.
  • 16 openings OP may be respectively opened in the source connecting portion AL2 and the drain connecting portion AL3 .
  • the 16 openings OP located in the source connecting portion AL2 are arranged in a matrix, and the 16 openings OP located in the drain connecting portion AL3 are also arranged in a matrix.
  • the opening OP in the source connecting portion AL2 and the opening OP in the drain connecting portion AL3 can be arranged symmetrically with respect to the channel region AL1 , so as to avoid damage to the active layer due to stress release dislocation.
  • the symmetrical arrangement with respect to the channel region AL1 means that when the channel region AL1 is a symmetrical pattern, the opening OP in the source connecting portion AL2 and the opening OP in the drain connecting portion AL3 are relatively opposite to the channel region AL1.
  • the symmetry axis O of AL1 is symmetrical.
  • the opening OP in the source connecting portion AL2 and the opening OP in the drain connecting portion AL3 may be symmetrically arranged with the center line of the channel region AL1 as a symmetrical axis.
  • the shape of the opening OP can be circular or square.
  • the area of the opening OP may be 0.1 square micrometers to 20 square micrometers.
  • the area of the opening OP may be 20 square micrometers, for example, a rectangular hole of 4 micrometers ⁇ 5 micrometers.
  • the thin film transistor may also be a bottom gate thin film transistor.
  • the flexible array substrate 100 may include multiple thin film transistors 20 .
  • the driving circuit of the OLED display panel can be 2T1C, 3T1C, 5T1C or 7T1C, etc.
  • the type and number of the thin film transistors 20 included in the flexible array substrate 100 can be different.
  • the opening OP can be opened in the active layer AL of some thin film transistors 20, or the opening OP can be opened in the active layer AL of all the thin film transistors 20, and can also be selectively opened in the display area and/or non- An opening OP is opened in the thin film transistor 20 in the display area.
  • the flexible display panel 1 further includes a passivation layer PLN, a first electrode 200, a pixel definition layer 300, a light emitting layer 400 and a second electrode 500, the passivation layer PLN covers the flexible array substrate 100, and the first electrode 200 is disposed on the passivation layer PLN
  • the pixel definition layer 300 is disposed on the side of the first electrode 200 away from the flexible array substrate 100, an opening 300a is opened in the pixel definition layer 300, the light emitting layer 400 is disposed in the opening 300a, and the second The electrode 500 covers the pixel definition layer 300 and the light emitting layer 400 .
  • the first electrode 200 may be an anode, and the second electrode 500 may be a cathode; or the first electrode 200 may be a cathode, and the second electrode 500 may be an anode.
  • a first via hole VIA1 is formed in the passivation layer PV, and a second via hole VIA2 is formed in the organic planar layer 30 , wherein the second via hole VIA2 communicates with the first via hole VIA1 .
  • the first electrode 200 overlaps with the TFT 20 through the second via hole VIA2 and the first via hole VIA1 .
  • the difference between the flexible display panel of the second embodiment of the present application and the flexible display panel of the first embodiment is:
  • the thin film transistor 20 further includes an ohmic contact layer OL including a first ohmic contact portion OL1 and a second ohmic contact portion OL2 .
  • the first ohmic contact OL1 is located between the source connection AL2 and the source SE
  • the second ohmic contact OL2 is located between the drain connection AL3 and the drain DE
  • the first ohmic contact OL1 and the second ohmic contact OL2 extends into the opening OP to connect with the active layer AL.
  • opening OP is opened in both the source connecting portion AL2 and the drain connecting portion AL3 in this embodiment, and in other embodiments, an opening OP may also be opened in one of the source connecting portion AL2 and the drain connecting portion AL3 Open OP.
  • the difference between the flexible display panel of the third embodiment of the present application and the flexible display panel of the first embodiment is:
  • the opening OP is located not only in the source connection AL2 and the drain connection AL3 , but also in the channel region AL1 .
  • the gate insulating layer GI covers the channel region AL1, and the gate insulating layer GI fills the opening OP.
  • the openings OP in the channel region AL1 are arranged symmetrically, which can avoid damage to the active layer due to stress release dislocation. Specifically, being symmetrical with respect to the channel region AL1 means that when the channel region AL1 is a symmetrical pattern, the opening OP in the channel region AL1 is symmetrical with respect to the symmetry axis O of the channel region AL1 .
  • the openings OP in the channel area AL1 may be arranged substantially symmetrically with the center line of the channel area AL1 as the axis of symmetry.
  • the opening OP is opened in the channel region AL1, the source connection part AL2 and the drain connection part AL3, however, in other embodiments of the present application, only the channel region The opening OP is provided in AL1, and the opening OP is not provided in the source connection portion AL2 and the drain connection portion AL3.
  • the difference between the flexible display panel of the fourth embodiment of the present application and the flexible display panel of the first embodiment is:
  • the thin film transistor 20 may also be a bottom gate thin film transistor.
  • the thin film transistor 20 includes a gate GE, a gate insulating layer GI, an active layer AL, a source SE, a drain DE and a passivation layer PV.
  • the gate GE is disposed on the flexible substrate 10
  • the active layer AL is disposed on the side of the gate GE away from the flexible substrate 10
  • the gate insulating layer GI is disposed between the gate GE and the active layer AL and covers the gate GE and the flexible substrate 10
  • the source SE and the drain DE are arranged on the side of the active layer AL away from the gate GE and connected to both ends of the active layer AL respectively
  • the passivation layer PV covers the source SE and the drain
  • the pole DE is away from the side of the active layer AL.
  • the opening OP may be located at the source connecting portion AL2 and the drain connecting portion AL3 .
  • the source SE extends into the opening OP of the source connection portion AL2 to connect to the source connection portion AL2
  • the drain DE extends into the opening OP of the drain connection portion AL3 to connect to the drain connection portion AL3 .
  • the present application also provides a method for manufacturing a flexible display panel, which is used for manufacturing the above-mentioned flexible display panel.
  • the manufacturing method of the flexible display panel includes the following steps:
  • Step 101 Please refer to FIG. 7( a ), providing a flexible substrate 10 .
  • the material of the flexible substrate 10 is selected from polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate (PAR), polycarbonate One or more of ester (PC), polyetherimide (PEI) and polyethersulfone (PES).
  • PI polyimide
  • PEN polyethylene naphthalate
  • PET polyethylene terephthalate
  • PAR polyarylate
  • PC polycarbonate
  • PC polyetherimide
  • PES polyethersulfone
  • Step 102 depositing a buffer layer BL, the material of the buffer layer can be a single layer of silicon nitride, a single layer of silicon oxide or a single layer of silicon oxide, or a double layer of silicon oxide, silicon nitride and silicon oxide or a double layer or more , the buffer layer has a thickness of 1000 angstroms to 5000 angstroms.
  • Step 103 deposit a semiconductor material layer CL, and the material of the semiconductor material layer CL can be IGZO, ITZO or IGZTO.
  • the thickness of the semiconductor material layer CL is 100 angstroms to 1000 angstroms, and the semiconductor material layer CL is divided into a channel region CL1, a source bonding region CL2 and a drain bonding region CL3, and the source bonding region CL2 and the drain region
  • the overlapping areas CL3 respectively form openings OP.
  • the opening OP in the source connection portion AL2 and the opening OP in the drain connection portion AL3 are arranged symmetrically with respect to the channel region AL1 .
  • the shape of the opening OP can be circular or square.
  • the area of the opening OP may be 0.1 square micrometers to 20 square micrometers.
  • the area of the opening OP may be 20 square micrometers, for example, a rectangular hole of 4 micrometers ⁇ 5 micrometers.
  • Step 104 Please refer to FIG. 7(d) and FIG. 7(e), deposit a gate insulating material layer (not shown) on the active layer AL, the material of the gate insulating material layer is silicon oxide, and the thickness is 1000 angstroms to 3000 Angstroms.
  • Step 105 Deposit a gate metal layer (not shown) on the gate insulating material layer.
  • the material of the gate metal layer can be a single layer of Mo, Al, Cu, Ti, etc., or Mo/Al/Mo, Al /Mo, Mo/Cu, MoTi/Cu and other multi-layer metals, with a thickness of 500 angstroms to 10000 angstroms.
  • Step 106 using a photomask to define the gate GE and the gate insulating layer GI, using wet etching to first etch the gate metal layer, and then using the gate pattern for self-alignment, dry etching to form the gate insulating layer GI.
  • Step 107 Perform conductorization treatment on the semiconductor material layer without the protection of the gate insulating layer GI by using plasma (Plasma) treatment to form an N-doped conductor region as the source connection part AL2 and Drain connection AL3.
  • the semiconductor material layer under the gate insulating layer GI is left untreated, and serves as the channel region AL1 of the thin film transistor 20 .
  • Step 108 Please refer to FIG. 7(f), deposit a silicon oxide film as the interlayer insulating layer IL with a thickness of 3000 angstroms to 10000 angstroms, and etch the source, drain and active layer AL in the interlayer insulating layer IL The contact hole CH.
  • Step 109 Please refer to FIG. 7(g), deposit a source-drain metal layer, which has a single-layer or multi-layer junction, such as Cu, Al, MoTi/Cu, Ti/Al/Ti, Mo/Al/Mo, MoTi/Cu /MoTi, Mo/Cu/Mo, i/Cu/Ti, etc., the thickness of the source and drain metal layer is 2000-10000A, patterned to form the source SE and the drain DE, and the source SE and the drain DE respectively pass through the contact hole CH
  • the conductorized source connection AL2 and drain connection AL3 are connected.
  • Step 110 depositing a passivation layer PV, which can be a silicon oxide film with a thickness of 1000 angstroms to 5000 angstroms.
  • Step 111 Please refer to FIG. 7( h ), forming a first via hole VIA1 in the passivation layer PV.
  • Step 112 Deposit an organic photoresist material as the organic planar layer PLN, and open a second via hole VIA2 in the organic planar layer PLN, wherein the second via hole VIA2 communicates with the first via hole VIA1 .
  • It can be a photoresist layer with different components, the thickness of the organic planar layer PLN is 10000 angstroms to 50000 angstroms, and the organic planar layer PLN fills the via hole VIA.
  • Step 113 Deposit the first electrode 200, the first electrode 200 is an anode, and the first electrode 200 includes metal materials with high reflectivity, including but not limited to ITO/Ag/ITO, IZO/Ag/IZO, ITO/Al/ ITO or IZO/Al/IZO, etc., the first electrode 200 overlaps with the thin film transistor 20 through the second via hole VIA2 and the first via hole VIA1;
  • Step 115 Form the light emitting layer 400 in the opening 300a.
  • Step 116 Form a second electrode 500 on the light emitting layer 400 and the pixel definition layer 300, the second electrode 500 is a cathode, and obtain a completed display panel.
  • the method for manufacturing the flexible display panel in the first embodiment of the present application has been described above in specific steps.
  • the manufacturing methods for the flexible display panel in the second embodiment to the fourth embodiment of the present application can be obtained by adjusting the above-mentioned manufacturing method. The description thereof is omitted here.

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Abstract

本申请提供一种柔性显示面板和柔性阵列基板。柔性显示面板包括柔性衬底和薄膜晶体管。薄膜晶体管包括有源层，有源层设置于柔性衬底上，有源层中开设有开孔，开孔贯穿有源层的至少一部分。

Description

柔性显示面板和柔性阵列基板 技术领域
本申请涉及柔性显示技术领域，尤其涉及柔性显示面板和柔性阵列基板。
 背景技术
近年来，柔性显示面板由于能够被弯曲或者卷曲，能够适应各种显示需求，应用越来越广泛。柔性显示面板包括柔性阵列基板，柔性阵列基板包括多个薄膜晶体管构成的阵列。随着对柔性显示面板弯折性能的要求越来越高，常规的薄膜晶体管已经难以满足柔性显示面板的要求。
 技术问题
有鉴于此，本申请提供一种能够提升弯折性能的柔性显示面板和柔性阵列基板。
 技术解决方案
本申请提供一种柔性显示面板，其包括：
柔性衬底；
薄膜晶体管，所述薄膜晶体管包括有源层，设置于所述柔性衬底上，所述有源层中开设有开孔，所述开孔贯穿所述有源层的至少一部分。
在一种实施方式中，所述有源层包括沟道区、源极连接部以及漏极连接部，所述源极连接部与所述漏极连接部位于沟道区的相对两侧；
所述薄膜晶体管还包括源极和漏极，所述源极和所述漏极设置于所述有源层远离所述柔性衬底的一侧，所述源极与所述源极连接部连接，所述漏极与所述漏极连接部连接，所述开孔位于所述源极连接部和所述漏极连接部的至少一个中。
在一种实施方式中，所述源极和所述漏极的至少一个延伸入所述开孔中与所述有源层连接。
在一种实施方式中，所述开孔位于所述源极连接部和所述漏极连接部中，所述源极连接部中的所述开孔与所述漏极连接部中的所述开孔相对于所述沟道区对称设置。
在一种实施方式中，所述薄膜晶体管还包括欧姆接触层，所述欧姆接触层包括第一欧姆接触部和第二欧姆接触部，所述第一欧姆接触部位于所述源极连接部与所述源极之间，所述第二欧姆接触部位于所述漏极连接部与所述漏极之间，所述第一欧姆接触部和所述第二欧姆接触部的至少一个延伸入所述开孔中与所述有源层连接。
在一种实施方式中，所述薄膜晶体管还包括栅极和栅极绝缘层，所述栅极位于所述有源层与所述源极和所述漏极之间，所述栅极绝缘层位于所述栅极与所述有源层之间，所述开孔的面积为0.1平方微米至20平方微米。
在一种实施方式中，所述有源层包括沟道区，所述开孔位于所述沟道区中。
在一种实施方式中，所述沟道区中的开孔对称设置。
在一种实施方式中，所述有源层包括沟道区、源极连接部以及漏极连接部，所述源极连接部与所述漏极连接部位于沟道区的相对两侧，所述开孔位于所述沟道区、源极连接部以及漏极连接部中，所述沟道区中的开孔对称设置，所述源极连接部中的所述开孔与所述漏极连接部中的所述开孔相对于所述沟道区对称设置，所述源极和所述漏极延伸入所述开孔中与所述有源层连接，所述薄膜晶体管还包括栅极绝缘层，所述栅极绝缘层覆盖所述沟道区，所述栅极绝缘层填充所述开孔。
在一种实施方式中，所述柔性显示面板还包括第一电极、像素定义层、发光层和第二电极，第一电极设置于所述薄膜晶体管上，所述像素定义层设置于所述第一电极远离所述薄膜晶体管的一侧，所述像素定义层中开设有开口，所述发光层设置于所述开口中，所述第二电极覆盖于所述像素定义层和所述发光层上。
本申请提供一种柔性阵列基板，其中，包括：
柔性衬底；
薄膜晶体管，所述薄膜晶体管包括有源层，设置于所述柔性衬底上，所述有源层中开设有开孔，所述开孔贯穿所述有源层的至少一部分。
在一种实施方式的柔性阵列基板中，所述有源层包括沟道区、源极连接部以及漏极连接部，所述源极连接部与所述漏极连接部位于沟道区的相对两侧；
所述薄膜晶体管还包括源极和漏极，所述源极和所述漏极设置于所述有源层远离所述柔性衬底的一侧，所述源极与所述源极连接部连接，所述漏极与所述漏极连接部连接，所述开孔位于所述源极连接部和所述漏极连接部的至少一个中。
在一种实施方式的柔性阵列基板中，所述源极和所述漏极的至少一个延伸入所述开孔中与所述有源层连接。
在一种实施方式的柔性阵列基板中，所述开孔位于所述源极连接部和所述漏极连接部中，所述源极连接部中的所述开孔与所述漏极连接部中的所述开孔相对于所述沟道区对称设置。
在一种实施方式的柔性阵列基板中，所述薄膜晶体管还包括欧姆接触层，所述欧姆接触层包括第一欧姆接触部和第二欧姆接触部，所述第一欧姆接触部位于所述源极连接部与所述源极之间，所述第二欧姆接触部位于所述漏极连接部与所述漏极之间，所述第一欧姆接触部和所述第二欧姆接触部的至少一个延伸入所述开孔中与所述有源层连接。
在一种实施方式的柔性阵列基板中，所述薄膜晶体管还包括栅极和栅极绝缘层，所述栅极位于所述有源层与所述源极和所述漏极之间，所述栅极绝缘层位于所述栅极与所述有源层之间，所述开孔的面积为0.1平方微米至20平方微米。
在一种实施方式的柔性阵列基板中，所述有源层包括沟道区，所述开孔位于所述沟道区中。
在一种实施方式的柔性阵列基板中，所述沟道区中的开孔对称设置。
在一种实施方式的柔性阵列基板中，所述有源层包括沟道区、源极连接部以及漏极连接部，所述源极连接部与所述漏极连接部位于沟道区的相对两侧，所述开孔位于所述沟道区、源极连接部以及漏极连接部中，所述沟道区中的开孔对称设置，所述源极连接部中的所述开孔与所述漏极连接部中的所述开孔相对于所述沟道区对称设置，所述源极和所述漏极延伸入所述开孔中与所述有源层连接，所述薄膜晶体管还包括栅极绝缘层，所述栅极绝缘层覆盖所述沟道区，所述栅极绝缘层填充所述开孔。
 有益效果
本申请通过在有源层中开设开孔，当对柔性显示面板施加弯折力时，薄膜晶体管受到的应力集中在开孔中，能够有效减少弯折对薄膜晶体管的损伤。即使由于弯折力过大，有源层中产生裂纹，有源层中的开孔也能够有效阻止裂纹扩散，保护薄膜晶体管。
 附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施方式描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请第一实施方式的柔性显示面板的剖面示意图。
图2为图1的柔性显示面板的有源层的俯视示意图。
图3为本申请第二实施方式的柔性显示面板的剖面示意图。
图4为本申请第三实施方式的柔性显示面板的剖面示意图。
图5为图4的柔性显示面板的有源层的俯视示意图。
图6为本申请第四实施方式的柔性显示面板的剖面示意图。
图7（a）至图7（h）为本申请的柔性显示面板的制造方法的步骤示意图，其中，图7（c）为图7（b）中的半导体层的俯视示意图，图7（e）为图7（d）中的有源层的俯视示意图。
 本发明的实施方式
下面将结合本申请实施方式中的附图，对本申请中的技术方案进行清楚、完整地描述。显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接，也可以包括第一和第二特征不是直接连接而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征。
本申请提供一种柔性显示面板和柔性阵列基板。本申请实施例中的显示面板可以用于手机、平板电脑、电子阅读器、电子展示屏、笔记本电脑、手机、增强现实(augmented reality，AR)\虚拟现实(virtual reality，VR)设备、媒体播放器、可穿戴设备、数码相机、车载导航仪等。
显示面板可以为有机发光二极管（Organic Light-emitting Diode，OLED）显示面板、量子点发光二极管（Quantum Dot Light-emitting Diode，QLED）显示面板、微发光二极管（Micro Light-emitting Diode，Micro-LED）显示面板、次毫米发光二极管（Mini Light-emitting Diode，Mini-LED）显示面板或者液晶（Liquid Crystal）显示面板。
请参考图1和图2，柔性显示面板1包括柔性阵列基板100。柔性阵列基板100包括柔性衬底10和设置于柔性衬底10上的薄膜晶体管20。柔性阵列基板100还可以包括设置于柔性衬底10与薄膜晶体管20之间的缓冲层BL。
柔性衬底10的材料选自聚酰亚胺(PI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)、聚芳酯(PAR)、聚碳酸酯(PC)、聚醚酰亚胺(PEI)和聚醚砜(PES)中的一种。
薄膜晶体管20包括有源层AL、栅极GE、栅极绝缘层GI、源极SE、漏极DE、层间绝缘层IL以及钝化层PV。有源层AL设置于柔性衬底10上，栅极GE设置于有源层AL远离柔性衬底10的一侧，栅极绝缘层GI设置于栅极GE与有源层AL之间，源极SE和漏极DE设置于栅极GE和有源层AL远离柔性衬底10的一侧，层间绝缘层IL设置于源极SE、漏极DE与有源层AL之间，钝化层PV覆盖于源极SE和漏极DE远离柔性衬底10的一侧。源极SE和漏极DE通过开设于层间绝缘层IL中的接触孔分别与有源层AL的两端连接。
有源层中开设有开孔OP，开孔OP贯穿有源层AL的至少一部分。开孔OP可以为通孔也可以为盲孔，即开孔OP可以完全贯穿有源层AL，也可以贯穿部分有源层AL。通过在有源层AL中开设开孔OP，当对柔性显示面板1施加弯折力时，薄膜晶体管20受到的应力集中在开孔OP中，能够有效减少弯折对薄膜晶体管20的损伤。即使由于弯折力过大，有源层AL中产生裂纹，有源层AL中的开孔OP也能够有效阻止裂纹扩散，保护薄膜晶体管20。
有源层AL包括沟道区AL1、源极连接部AL2以及漏极连接部AL3，源极连接部AL2与漏极连接部AL3位于沟道区AL1的相对两侧。源极SE与源极连接部AL2连接，漏极DE与漏极连接部AL3连接。开孔OP可以位于沟道区AL1、源极连接部AL2和漏极连接部AL3的至少一个中。当开孔OP位于源极连接部AL2和漏极连接部AL3的至少一个中时，源极SE和漏极DE的至少一个延伸入开孔OP中与有源层AL连接。在本实施方式中，开孔OP位于源极连接部AL2和漏极连接部AL3中。源极SE延伸入源极连接部AL2的开孔OP中与源极连接部AL2连接，漏极DE延伸入漏极连接部AL3的开孔OP中与漏极连接部AL3连接。当开孔OP位于沟道区AL1时，覆盖在沟道区AL1远离柔性衬底10的一侧的膜层，可以延伸入开孔OP中，填充开孔OP。覆盖在沟道区AL1远离柔性衬底10的一侧的膜层在顶栅型晶体管中例如是栅极绝缘层，在底栅型晶体管中例如是源漏极、欧姆接触层或者沟道保护层。开口OP的设置能够增大有源层AL与源极SE和漏极DE的搭接面积，降低接触电阻，提高薄膜晶体管20的器件性能。
本申请中不限定开孔OP的个数和排列方式。可选的，本实施方式中，可以在源极连接部AL2和漏极连接部AL3中分别开设16个开孔OP。位于源极连接部AL2中的16个开孔OP呈矩阵排布，位于漏极连接部AL3中的16个开孔OP也呈矩阵排布。进一步，源极连接部AL2中的开孔OP与漏极连接部AL3中的开孔OP可以相对于沟道区AL1对称设置，可避免因应力释放错位造成有源层损伤。具体地，相对于沟道区AL1对称设置是指：当沟道区AL1为对称图形时，源极连接部AL2中的开孔OP与漏极连接部AL3中的开孔OP相对于沟道区AL1的对称轴O对称。当沟道区AL1不是标准的对称图形时，源极连接部AL2中的开孔OP与漏极连接部AL3中的开孔OP以沟道区AL1的中线为对称轴对称排列即可。开孔OP的形状可以是圆形，也可以是方形。为了防止开孔OP过大，影响有源层AL的功能，开孔OP的面积可以为0.1平方微米至20平方微米。可选的，当开孔OP的数量为一个时，开孔OP的面积可以为20平方微米，例如4微米×5微米的矩形孔。
在本实施方式中，以自对准（self-alignment）型的顶栅型薄膜晶体管进行说明。可以理解的是，本申请的其他实施方式中，薄膜晶体管也可以是底栅型薄膜晶体管。
需要说明的是，虽然图中只示出一个薄膜晶体管20，但柔性阵列基板100可以包括多个薄膜晶体管20。OLED显示面板的驱动电路可以为2T1C、3T1C、5T1C或者7T1C等，根据像素驱动电路的架构不同，柔性阵列基板100包括的薄膜晶体管20的类型和个数可以不同。在本申请可以在部分薄膜晶体管20的有源层AL中开设开孔OP，也可以在全部薄膜晶体管20的有源层AL中开设开孔OP，还可以选择性地在显示区和/或非显示区的薄膜晶体管20中开孔OP。
柔性显示面板1还包括钝化层PLN、第一电极200、像素定义层300、发光层400和第二电极500，钝化层PLN覆盖柔性阵列基板100、第一电极200设置于钝化层PLN远离柔性阵列基板100的一侧上，像素定义层300设置于第一电极200远离柔性阵列基板100的一侧，像素定义层300中开设有开口300a，发光层400设置于开口300a中，第二电极500覆盖于像素定义层300和发光层400上。第一电极200可以是阳极，第二电极500可以是阴极；或者第一电极200是阴极，第二电极500是阳极。钝化层PV中形成第一过孔VIA1，有机平坦层30中形成有第二过孔VIA2，其中，第二过孔VIA2与第一过孔VIA1连通。第一电极200通过第二过孔VIA2和第一过孔VIA1与薄膜晶体管20搭接。
请参考图3，本申请第二实施方式的柔性显示面板与第一实施方式的柔性显示面板的不同之处在于：
薄膜晶体管20还包括欧姆接触层OL，欧姆接触层OL包括第一欧姆接触部OL1和第二欧姆接触部OL2。第一欧姆接触部OL1位于源极连接部AL2与源极SE之间，第二欧姆接触部OL2位于漏极连接部AL3与漏极DE之间，第一欧姆接触部OL1和第二欧姆接触部OL2延伸入开孔OP中与有源层AL连接。
可以理解，本实施方式的源极连接部AL2和漏极连接部AL3中均开设有开口OP，在其他实施方式中，也可以在源极连接部AL2和漏极连接部AL3的其中一个中开设开口OP。
请参考图4和图5，本申请第三实施方式的柔性显示面板与第一实施方式的柔性显示面板的不同之处在于：
开孔OP不仅位于源极连接部AL2和漏极连接部AL3，还位于沟道区AL1中。栅极绝缘层GI覆盖沟道区AL1，栅极绝缘层GI填充开孔OP。进一步，沟道区AL1中的开孔OP对称设置，可避免因应力释放错位造成有源层损伤。具体地，相对于沟道区AL1对称设置是指：当沟道区AL1为对称图形时，沟道区AL1中的开孔OP相对于沟道区AL1的对称轴O对称。当沟道区AL1不是标准的对称图形时，沟道区AL1中的开孔OP以沟道区AL1的中线为对称轴大致对称排列即可。
可以理解，虽然第三实施方式公开了在沟道区AL1、源极连接部AL2和漏极连接部AL3均开设开孔OP，然而，在本申请的其他实施方式中，可以仅在沟道区AL1设置开孔OP，而在源极连接部AL2和漏极连接部AL3不设置开孔OP。
请参考图6，本申请第四实施方式的柔性显示面板与第一实施方式的柔性显示面板的不同之处在于：
薄膜晶体管20也可以为底栅型薄膜晶体管。薄膜晶体管20包括栅极GE、栅极绝缘层GI、有源层AL、源极SE、漏极DE以及钝化层PV。栅极GE设置于柔性衬底10上，有源层AL设置于栅极GE远离柔性衬底10的一侧，栅极绝缘层GI设置于栅极GE与有源层AL之间并覆盖栅极GE和柔性衬底10，源极SE和漏极DE设置于有源层AL远离栅极GE的一侧并分别与有源层AL的两端连接，钝化层PV覆盖于源极SE和漏极DE远离有源层AL的一侧。
与第一实施方式相同的，开孔OP可以位于源极连接部AL2和漏极连接部AL3。源极SE延伸入源极连接部AL2的开孔OP中与源极连接部AL2连接，漏极DE延伸入漏极连接部AL3的开孔OP中与漏极连接部AL3连接。
本申请还提供一种柔性显示面板的制造方法，其用于制造上述柔性显示面板。如图7（a）至图7（h）所示，柔性显示面板的制造方法包括以下步骤：
步骤101：请参考图7（a），提供柔性衬底10。
柔性衬底10的材料选自聚酰亚胺(PI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)、聚芳酯(PAR)、聚碳酸酯(PC)、聚醚酰亚胺(PEI)和聚醚砜(PES)中的一种或多种。
步骤102：沉积缓冲层BL，缓冲层的材料可以是单层氮化硅，单层氧化硅或者单层氧化硅，或者是氧化硅、氮化硅和氧化硅双层膜或者双层以上膜层，缓冲层的厚度为1000埃至5000埃。
步骤103：请参考图7（b）和图7（c），沉积半导体材料层CL，半导体材料层CL的材料可以为IGZO、ITZO或IGZTO。半导体材料层CL的厚度为100埃至1000埃，将半导体材料层CL划分为沟道区CL1、源极搭接区CL2和漏极搭接区CL3，并在源极搭接区CL2和漏极搭接区CL3分别形成开孔OP。源极连接部AL2中的开孔OP与漏极连接部AL3中的开孔OP相对于沟道区AL1对称设置。开孔OP的形状可以是圆形，也可以是方形。为了防止开孔OP过大，影响有源层的功能，开孔OP的面积可以为0.1平方微米至20平方微米。可选的，当开孔OP的数量为一个时，开孔OP的面积可以为20平方微米，例如4微米×5微米的矩形孔。
步骤104：请参考图7（d）和图7（e），在有源层AL上沉积栅极绝缘材料层（未图示），栅极绝缘材料层的材料为氧化硅，厚度1000埃至3000埃。
步骤105：在栅极绝缘材料层上沉积栅极金属层（未图示），栅极金属层的材料可以是单层Mo，Al，Cu，Ti等，也可以是Mo/Al/Mo、Al/Mo、Mo/Cu、MoTi/Cu等多层金属，厚度为500埃至10000埃。
步骤106：利用一道光罩，定义出栅极GE和栅极绝缘层GI，采用湿蚀刻先栅蚀刻极金属层，再利用栅极图形为自对准，干法蚀刻形成栅极绝缘层GI。
步骤107：采用等离子（Plasma）处理对上方没有栅极绝缘层GI保护的半导体材料层进行导体化处理，形成N掺杂的导体区域，作为与源极和漏极接触的源极连接部AL2和漏极连接部AL3。栅极绝缘层GI下方的半导体材料层不做处理，作为薄膜晶体管20沟道区AL1。
步骤108：请参考图7（f），沉积氧化硅膜作为层间绝缘层IL，厚度在3000埃至10000埃，并且在层间绝缘层IL中蚀刻出源极、漏极与有源层AL的接触孔CH。
步骤109：请参考图7（g），沉积源漏金属层，其具有单层或者多层结，例如Cu，Al，MoTi/Cu，Ti/Al/Ti，Mo/Al/Mo，MoTi/Cu/MoTi，Mo/Cu/Mo，i/Cu/Ti等，源漏金属层的厚度为2000-10000A，图案化形成源极SE和漏极DE，源极SE和漏极DE分别通过接触孔CH连接导体化的源极连接部AL2和漏极连接部AL3。
步骤110：沉积钝化层PV，钝化层PV可以为氧化硅薄膜，厚度为1000埃至5000埃。
步骤111：请参考图7（h），在钝化层PV中形成第一过孔VIA1。
步骤112：沉积有机光阻材料作为有机平坦层PLN，在有机平坦层PLN中开设第二过孔VIA2，其中，第二过孔VIA2与第一过孔VIA1连通。可以是不同成分的光阻层，有机平坦层PLN的厚度为10000埃至50000埃，有机平坦层PLN填充过孔VIA。
步骤113：沉积第一电极200，第一电极200为阳极，第一电极200包括具有高反射率的金属材料，包括但不局限于ITO/Ag/ITO，IZO/Ag/IZO，ITO/Al/ITO或者IZO/Al/IZO等，第一电极200通过第二过孔VIA2和第一过孔VIA1与薄膜晶体管20搭接；步骤114：形成像素定义层300，像素定义层300的厚度在10000埃至20000埃，通过黄光制程定义出开口300a。
步骤115：在开口300a中形成发光层400。
步骤116：在发光层400和像素定义层300上形成第二电极500，第二电极500为阴极，得到完成显示面板。
以上以具体步骤描述了本申请第一实施方式的柔性显示面板的制造方法，本申请的第二实施方式至第四实施方式的柔性显示面板的制造方法可以在上述制造方法中进行调整得到，在此省略其说明。
以上对本申请实施方式提供了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施方式的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (19)

  1. 一种柔性显示面板，其特征在于，包括：
    柔性衬底；
    薄膜晶体管，所述薄膜晶体管包括有源层，设置于所述柔性衬底上，所述有源层中开设有开孔，所述开孔贯穿所述有源层的至少一部分。
  2. 如权利要求1所述的柔性显示面板，其特征在于，所述有源层包括沟道区、源极连接部以及漏极连接部，所述源极连接部与所述漏极连接部位于沟道区的相对两侧；
    所述薄膜晶体管还包括源极和漏极，所述源极和所述漏极设置于所述有源层远离所述柔性衬底的一侧，所述源极与所述源极连接部连接，所述漏极与所述漏极连接部连接，所述开孔位于所述源极连接部和所述漏极连接部的至少一个中。
  3. 如权利要求2所述的柔性显示面板，其特征在于，所述源极和所述漏极的至少一个延伸入所述开孔中与所述有源层连接。
  4. 如权利要求2所述的柔性显示面板，其特征在于，所述开孔位于所述源极连接部和所述漏极连接部中，所述源极连接部中的所述开孔与所述漏极连接部中的所述开孔相对于所述沟道区对称设置。
  5. 如权利要求2所述的柔性显示面板，其特征在于，所述薄膜晶体管还包括欧姆接触层，所述欧姆接触层包括第一欧姆接触部和第二欧姆接触部，所述第一欧姆接触部位于所述源极连接部与所述源极之间，所述第二欧姆接触部位于所述漏极连接部与所述漏极之间，所述第一欧姆接触部和所述第二欧姆接触部的至少一个延伸入所述开孔中与所述有源层连接。
  6. 如权利要求2所述的柔性显示面板，其特征在于，所述薄膜晶体管还包括栅极和栅极绝缘层，所述栅极位于所述有源层与所述源极和所述漏极之间，所述栅极绝缘层位于所述栅极与所述有源层之间，所述开孔的面积为0.1平方微米至20平方微米。
  7. 如权利要求1所述的柔性显示面板，其特征在于，所述有源层包括沟道区，所述开孔位于所述沟道区中。
  8. 如权利要求7所述的柔性显示面板，其特征在于，所述沟道区中的开孔对称设置。
  9. 如权利要求1所述的柔性显示面板，其特征在于，所述有源层包括沟道区、源极连接部以及漏极连接部，所述源极连接部与所述漏极连接部位于沟道区的相对两侧，所述开孔位于所述沟道区、源极连接部以及漏极连接部中，所述沟道区中的开孔对称设置，所述源极连接部中的所述开孔与所述漏极连接部中的所述开孔相对于所述沟道区对称设置，所述源极和所述漏极延伸入所述开孔中与所述有源层连接，所述薄膜晶体管还包括栅极绝缘层，所述栅极绝缘层覆盖所述沟道区，所述栅极绝缘层填充所述开孔。
  10. 如权利要求9所述的柔性显示面板，其特征在于，所述柔性显示面板还包括第一电极、像素定义层、发光层和第二电极，第一电极设置于所述薄膜晶体管上，所述像素定义层设置于所述第一电极远离所述薄膜晶体管的一侧，所述像素定义层中开设有开口，所述发光层设置于所述开口中，所述第二电极覆盖于所述像素定义层和所述发光层上。
  11. 一种柔性阵列基板，其中，包括：
    柔性衬底；
    薄膜晶体管，所述薄膜晶体管包括有源层，设置于所述柔性衬底上，所述有源层中开设有开孔，所述开孔贯穿所述有源层的至少一部分。
  12. 如权利要求1所述的柔性阵列基板，其中，所述有源层包括沟道区、源极连接部以及漏极连接部，所述源极连接部与所述漏极连接部位于沟道区的相对两侧；
    所述薄膜晶体管还包括源极和漏极，所述源极和所述漏极设置于所述有源层远离所述柔性衬底的一侧，所述源极与所述源极连接部连接，所述漏极与所述漏极连接部连接，所述开孔位于所述源极连接部和所述漏极连接部的至少一个中。
  13. 如权利要求2所述的柔性阵列基板，其中，所述源极和所述漏极的至少一个延伸入所述开孔中与所述有源层连接。
  14. 如权利要求2所述的柔性阵列基板，其中，所述开孔位于所述源极连接部和所述漏极连接部中，所述源极连接部中的所述开孔与所述漏极连接部中的所述开孔相对于所述沟道区对称设置。
  15. 如权利要求2所述的柔性阵列基板，其中，所述薄膜晶体管还包括欧姆接触层，所述欧姆接触层包括第一欧姆接触部和第二欧姆接触部，所述第一欧姆接触部位于所述源极连接部与所述源极之间，所述第二欧姆接触部位于所述漏极连接部与所述漏极之间，所述第一欧姆接触部和所述第二欧姆接触部的至少一个延伸入所述开孔中与所述有源层连接。
  16. 如权利要求2所述的柔性阵列基板，其中，所述薄膜晶体管还包括栅极和栅极绝缘层，所述栅极位于所述有源层与所述源极和所述漏极之间，所述栅极绝缘层位于所述栅极与所述有源层之间，所述开孔的面积为0.1平方微米至20平方微米。
  17. 如权利要求1所述的柔性阵列基板，其中，所述有源层包括沟道区，所述开孔位于所述沟道区中。
  18. 如权利要求7所述的柔性阵列基板，其中，所述沟道区中的开孔对称设置。
  19. 如权利要求1所述的柔性阵列基板，其中，所述有源层包括沟道区、源极连接部以及漏极连接部，所述源极连接部与所述漏极连接部位于沟道区的相对两侧，所述开孔位于所述沟道区、源极连接部以及漏极连接部中，所述沟道区中的开孔对称设置，所述源极连接部中的所述开孔与所述漏极连接部中的所述开孔相对于所述沟道区对称设置，所述源极和所述漏极延伸入所述开孔中与所述有源层连接，所述薄膜晶体管还包括栅极绝缘层，所述栅极绝缘层覆盖所述沟道区，所述栅极绝缘层填充所述开孔。
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