WO2023103015A1 - 发光器件驱动电路、背光模组及显示面板 - Google Patents

发光器件驱动电路、背光模组及显示面板 Download PDF

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Publication number
WO2023103015A1
WO2023103015A1 PCT/CN2021/138876 CN2021138876W WO2023103015A1 WO 2023103015 A1 WO2023103015 A1 WO 2023103015A1 CN 2021138876 W CN2021138876 W CN 2021138876W WO 2023103015 A1 WO2023103015 A1 WO 2023103015A1
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Prior art keywords
emitting device
light emitting
signal
transistor
electrically connected
Prior art date
Application number
PCT/CN2021/138876
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English (en)
French (fr)
Inventor
孙博
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/623,119 priority Critical patent/US20240046863A1/en
Publication of WO2023103015A1 publication Critical patent/WO2023103015A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G09G2310/0256—Control of polarity reversal in general, other than for liquid crystal displays with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2330/10—Dealing with defective pixels
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    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present application relates to the field of display technology, in particular to a light emitting device driving circuit, a backlight module and a display panel.
  • MLED Mini LED (Mini Light-Emitting Diode, Mini Light-Emitting Diode), Micro LED (Micro Light-Emitting Diode, micron light-emitting diode) is collectively referred to as MLED.
  • MLED Micro Light-Emitting Diode, micron light-emitting diode
  • the driving of MLED is current driving.
  • the input data signal is different, and the gate-source voltage Vgs of the driving transistor is different, so that the source-drain current Ids and the brightness of MLED are different, thereby realizing gray scale segmentation.
  • the driving transistor is in an on state during the entire display time, and the current needs to be precisely controlled in order to achieve the purpose of gray scale segmentation. Therefore, the threshold voltage and mobility drift of the driving transistor will directly act on the driving current, causing abnormal display.
  • the current direction of the driving transistor is consistent at all times. Under the effects of long turn-on time and fixed current direction, the current bias (stress) effect is very obvious, which will easily lead to the performance drift of the driving transistor, thereby reducing the performance of the driving transistor. stability.
  • the present application provides a light-emitting device driving circuit, a backlight module and a display panel to solve the technical problem in the prior art that the driving transistor in the light-emitting device driving circuit is subjected to a significant current bias effect and its stability is easily affected.
  • the present application provides a light emitting device driving circuit, which includes:
  • one of the source and the drain of the driving transistor is electrically connected to the first node, and the other of the source and the drain of the driving transistor is electrically connected to the first power supply signal;
  • a data writing module accesses the scan signal and the data signal, and is electrically connected to the gate of the drive transistor, and the data writing module is used to write the Writing the data signal into the gate of the drive transistor;
  • a light emitting module includes at least one first light emitting device and at least one second light emitting device, the first pole of the first light emitting device and the second pole of the second light emitting device are both electrically connected to the first light emitting device A node, the second pole of the first light emitting device and the first pole of the second light emitting device are both electrically connected to the second power supply signal;
  • the first power supply signal and the second power supply signal are configured to perform potential conversion according to a preset period, so that the direction of the current flowing through the driving transistor changes according to the preset period.
  • the preset period is at least one frame.
  • the potential of the first power signal and the second power signal is switched during a vertical blank period between adjacent frames.
  • the first power signal has a first high level and a first low level, and the first power signal switches between the first high level and the first low level according to the preset period. switching between the first low levels;
  • the second power signal has a second high level and a second low level, and the second power signal is switched between the second high level and the second low level according to the preset cycle.
  • the first high level is the same as the second high level
  • the first low level is the same as the second low level
  • the first power signal and the second power supply signal are kept in opposite phase.
  • the data writing module includes a switching transistor and a storage capacitor
  • the gate of the switching transistor is connected to the scanning signal, one of the source and the drain of the switching transistor is connected to the data signal, and the other of the source and the drain of the switching transistor is 1.
  • One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end of the storage capacitor is electrically connected to one of the source and the drain of the driving transistor.
  • the light emitting device driving circuit further includes a sensing module, the sensing module is connected to a sensing signal and a reset signal, and is electrically connected to the source of the driving transistor and one of the drains, the sensing module is used to detect the threshold voltage of the driving transistor under the control of the sensing signal and the reset signal.
  • the sensing module includes a sensing transistor and a first switch unit, the gate of the sensing transistor is connected to the sensing signal, and the source of the sensing transistor One of the electrode and the drain is electrically connected to one end of the first switch unit, the other of the source and the drain of the sensing transistor is connected to one of the source and the drain of the driving transistor or electrically connected, and the other end of the first switch unit is connected to the reset signal.
  • a backlight module which includes:
  • the data line is used to provide a data signal
  • Scanning lines the scanning lines are used to provide scanning signals
  • the first power line is used to provide a first power signal
  • the second power line is used to provide a second power signal
  • a light emitting device driving circuit is electrically connected to the data line, the scanning line, the first power line and the second power line, and the light emitting device driving circuit includes:
  • one of the source and the drain of the driving transistor is electrically connected to the first node, and the other of the source and the drain of the driving transistor is electrically connected to the first power supply signal;
  • a data writing module accesses the scan signal and the data signal, and is electrically connected to the gate of the drive transistor, and the data writing module is used to write the Writing the data signal into the gate of the driving transistor;
  • a light emitting module includes at least one first light emitting device and at least one second light emitting device, the first pole of the first light emitting device and the second pole of the second light emitting device are both electrically connected to the first light emitting device A node, the second pole of the first light emitting device and the first pole of the second light emitting device are both electrically connected to the second power supply signal;
  • the first power supply signal and the second power supply signal are configured to perform potential conversion according to a preset period, so that the direction of the current flowing through the driving transistor changes according to the preset period.
  • the preset period is at least one frame.
  • the potential of the first power signal and the second power signal is switched during a vertical blank period between adjacent frames.
  • the first power signal has a first high level and a first low level, and the first power signal switches between the first high level and the first low level according to the preset period. switching between the first low levels;
  • the second power signal has a second high level and a second low level, and the second power signal is switched between the second high level and the second low level according to the preset cycle.
  • the first high level is the same as the second high level
  • the first low level is the same as the second low level
  • the first power signal and the second power supply signal are kept in opposite phase.
  • the data writing module includes a switching transistor and a storage capacitor
  • the gate of the switching transistor is connected to the scanning signal, one of the source and the drain of the switching transistor is connected to the data signal, and the other of the source and the drain of the switching transistor is 1.
  • One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end of the storage capacitor is electrically connected to one of the source and the drain of the driving transistor.
  • the present application also provides a display panel, the display panel includes a plurality of pixel units arranged in an array, each of the pixel units includes a light emitting device driving circuit, and the light emitting device driving circuit includes:
  • one of the source and the drain of the driving transistor is electrically connected to the first node, and the other of the source and the drain of the driving transistor is electrically connected to the first power supply signal;
  • a data writing module accesses the scan signal and the data signal, and is electrically connected to the gate of the drive transistor, and the data writing module is used to write the Writing the data signal into the gate of the driving transistor;
  • a light emitting module includes at least one first light emitting device and at least one second light emitting device, the first pole of the first light emitting device and the second pole of the second light emitting device are both electrically connected to the first light emitting device A node, the second pole of the first light emitting device and the first pole of the second light emitting device are both electrically connected to the second power supply signal;
  • the first power supply signal and the second power supply signal are configured to perform potential conversion according to a preset period, so that the direction of the current flowing through the driving transistor changes according to the preset period.
  • the preset period is at least one frame.
  • the potential of the first power signal and the second power signal is switched during a vertical blank period between adjacent frames.
  • the first power signal has a first high level and a first low level, and the first power signal switches between the first high level and the first low level according to the preset period. switching between the first low levels;
  • the second power signal has a second high level and a second low level, and the second power signal is switched between the second high level and the second low level according to the preset cycle.
  • the first high level is the same as the second high level
  • the first low level is the same as the second low level
  • the first power signal and the second power supply signal are kept in opposite phase.
  • the data writing module includes a switching transistor and a storage capacitor
  • the gate of the switching transistor is connected to the scanning signal, one of the source and the drain of the switching transistor is connected to the data signal, and the other of the source and the drain of the switching transistor is 1.
  • One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end of the storage capacitor is electrically connected to one of the source and the drain of the driving transistor.
  • the application provides a light emitting device driving circuit, a backlight module and a display panel.
  • the light emitting device driving circuit includes a driving transistor, a data writing module and a light emitting module. Wherein, the source and the drain of the driving transistor are respectively electrically connected to the first power supply signal and the first node.
  • the light emitting module includes at least one first light emitting device and at least one second light emitting device. Both the first pole of the first light emitting device and the second pole of the second light emitting device are electrically connected to the first node. Both the second pole of the first light emitting device and the first pole of the second light emitting device are electrically connected to the second power supply signal.
  • the present application configures the first power signal and the second power signal to perform potential conversion according to a preset period, so that the direction of the current flowing through the drive transistor changes according to the preset period, thereby effectively improving the current bias of the drive transistor, Threshold voltage and mobility shifts of the driving transistor are avoided, thereby improving the stability of the driving transistor.
  • the first light-emitting device and the second light-emitting device are arranged in opposite directions, they can alternately emit light under the action of the driving current, thereby achieving the purpose of reducing light efficiency and reducing dead pixels.
  • Fig. 1 is a first structural schematic diagram of a light emitting device driving circuit provided by the present application
  • Fig. 2 is a timing diagram of the first power supply signal and the second power supply signal in the light emitting device driving circuit provided by the present application;
  • Fig. 3 is a first schematic circuit diagram of a light emitting device driving circuit provided by the present application.
  • Fig. 4 is a second structural schematic diagram of the light emitting device driving circuit provided by the present application.
  • Fig. 5 is a third structural schematic diagram of the light emitting device driving circuit provided by the present application.
  • Fig. 6 is a second schematic circuit diagram of the light emitting device driving circuit provided by the present application.
  • FIG. 7 is a schematic structural view of the backlight module provided by the present application.
  • FIG. 8 is a schematic structural diagram of a display panel provided by the present application.
  • the present application provides a light emitting device driving circuit, a backlight module and a display panel, which will be described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.
  • FIG. 1 is a schematic diagram of the first structure of the light emitting device driving circuit provided in the present application.
  • the light emitting device driving circuit 100 includes a driving transistor DT, a data writing module 101 and a light emitting module 102 .
  • one of the source and the drain of the driving transistor DT is electrically connected to the first node A. As shown in FIG. The other of the source and the drain of the driving transistor DT is electrically connected to the first power signal VDD.
  • the data writing module 101 receives the scan signal Vsc and the data signal Vda, and is electrically connected to the gate of the driving transistor DT. The data writing module 101 is used for writing the data signal Vda into the gate of the driving transistor DT under the control of the scanning signal Vsc.
  • the light emitting module 102 includes at least one first light emitting device D1 and at least one second light emitting device D2.
  • Both the first pole of the first light emitting device D1 and the second pole of the second light emitting device D2 are electrically connected to the first node A. Both the second electrode of the first light emitting device D1 and the first electrode of the second light emitting device D2 are electrically connected to the second power signal VSS.
  • the first power signal VDD and the second power signal VSS are configured to perform potential conversion according to a preset period, so that the direction of the current flowing through the driving transistor DT changes according to a preset period.
  • the first pole of the first light-emitting device D1 and the second pole of the second light-emitting device D2 are both electrically connected to the first node A, the second pole of the first light-emitting device D1 and Both first electrodes of the second light emitting device D2 are electrically connected to the second power signal VSS. That is, the first light emitting device D1 and the second light emitting device D2 are arranged in opposite directions. Therefore, the first light emitting device D1 and the second light emitting device D2 do not emit light at the same time.
  • the direction of the current flowing through the driving transistor DT can be changed according to the preset period, thereby effectively improving the current received by the driving transistor DT.
  • the bias voltage avoids the threshold voltage and mobility shift of the driving transistor DT, thereby improving the stability of the driving transistor DT.
  • the first light emitting device D1 and the second light emitting device D2 can emit light alternately, so as to avoid abnormal light emission caused by changing the direction of the driving current.
  • each light emitting module 102 has a first light emitting device D1 and a second light emitting device D2. Therefore, when one of them is damaged, the other one can still continue to provide brightness, thereby reducing the influence of dead pixels.
  • the first light emitting device D1 and the second light emitting device D2 may be mini light emitting diodes, micro light emitting diodes or organic light emitting diodes.
  • the first electrode of the first light emitting device D1 may be one of an anode or a cathode of a light emitting diode.
  • the second pole of the first light emitting device D1 may be the other pole of the anode or the cathode of the light emitting diode. The same is true for the second light emitting device D2 , which will not be repeated here.
  • the preset period is at least one frame.
  • One frame represents the time for the display panel to display one frame of picture.
  • the preset period can be 1 frame, 2 frames, 5 frames, 10 frames, etc., which can be set according to specific parameters of the light emitting device driving circuit 100, which is not limited in this application.
  • the first power supply signal VDD and the second power supply signal VSS may be provided by an external power supply chip (not shown in the figure), which will not be repeated here.
  • the vertical blank period between the current frame and the adjacent next frame (vertical During the blanking time), the potentials of the first power signal VDD and the second power signal VSS are converted, so as to avoid affecting the display screen of the display panel.
  • the voltage value of the first power signal VDD and the voltage value of the second power signal VSS can be set according to practical applications. It only needs to be satisfied that the first light emitting device D1 and the second light emitting device D2 can emit light alternately under the action of the voltage value of the first power signal VDD and the second power signal VSS. For example, when the voltage value of the first power signal VDD is greater than the second power signal VSS, the first light emitting device D1 emits light, and the driving current flows from the first power signal VDD to the second power signal VSS. When the voltage value of the first power signal VDD is lower than the second power signal VSS, the second light emitting device D2 emits light, and the driving current flows from the second power signal VSS to the first power signal VDD.
  • FIG. 2 is a timing diagram of the first power signal and the second power signal in the light emitting device driving circuit provided by the present application.
  • the first power signal VDD has a first high level V1 and a first low level V2.
  • the first power signal VDD is switched between a first high level V1 and a first low level V2 according to a preset cycle.
  • the second power signal VSS has a second high level V3 and a second low level V4.
  • the second power signal VSS is switched between a second high level V3 and a second low level V4 according to a preset cycle.
  • the first high level V1 and the second high level V3 can be any high potential that can drive the first light emitting device D1 and the second light emitting device D2 to emit light stably.
  • the potentials of the first low level V2 and the second low level V4 may be the potential of the ground terminal.
  • the potentials of the first low level V2 and the second low level V4 can also be other low potentials that drive the first light emitting device D1 and the second light emitting device D2 to emit light stably.
  • the first high level V1 and the second high level V3 are the same.
  • the first low level V2 is the same as the second low level V4. That is, the first power signal VDD and the second power signal VSS keep inverting at all times. Wherein, maintaining inversion refers to that the absolute value of the voltage of the first power signal VDD is equal to the absolute value of the voltage of the second power signal VSS, but the phases are opposite. Therefore, the sequence in the light-emitting device driving circuit 100 can be simplified, and the power consumption of the power chip that provides the first power signal VDD and the second power signal VSS can be reduced.
  • FIG. 3 is a first schematic circuit diagram of the light emitting device driving circuit provided in the present application.
  • the data writing module 101 includes a switch transistor T1 and a storage capacitor Cst.
  • the gate of the switching transistor T1 is connected to the scanning signal Vsc.
  • One of the source and the drain of the switching transistor T1 is connected to the data signal Vda.
  • the other of the source and the drain of the switching transistor T1, one end of the storage capacitor Cst, and the gate of the driving transistor DT are electrically connected.
  • the other end of the storage capacitor Cst is electrically connected to one of the source and the drain of the driving transistor DT.
  • the data writing module 101 can also be formed by connecting a plurality of transistors and a capacitor in series.
  • the transistors used in all embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain can be interchanged. of. In the embodiment of the present application, in order to distinguish the two poles of the transistor except the gate, one pole is called the source, and the other pole is called the drain. According to the form in the accompanying drawings, it is stipulated that the middle terminal of the switching transistor is the gate, the signal input terminal is the source terminal, and the output terminal is the drain terminal.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors, wherein, the P-type transistors are turned on when the gate is at a low level, and are turned off when the gate is at a high level, and the N-type transistors are turned on when the gate is at a high level. It turns on when the gate is high and turns off when the gate is low.
  • the transistors in the light-emitting device driving circuit 100 provided in the present application can be set to be of the same type, so as to avoid the influence of differences between different types of transistors on the light-emitting device driving circuit 100 .
  • the following embodiments of the present application are all described by taking each transistor as an N-type transistor as an example, but it should not be construed as a limitation of the present application.
  • the scan signal Vsc changes from a low potential to a high potential, and the switch transistor T1 is turned on.
  • the data signal Vda is transmitted to the gate of the driving transistor TD through the switching transistor T1 and stored in the storage capacitor Cst. Since the gate potential of the driving transistor TD is pulled up to the potential of the data signal Vda, the driving transistor DT is turned on.
  • the first power signal VDD when the potential of the first power signal VDD is higher than the potential of the second power signal VSS, the first power signal VDD, the driving transistor DT, the first light-emitting device D1 and the second power signal VSS form a light-emitting loop, and the current flows from The first power signal VDD flows to the second power signal VSS, and the first light emitting device D1 normally emits light.
  • the first power signal VDD is lower than the potential of the second power signal VSS
  • the first power signal VDD, the driving transistor DT, the second light emitting device D2 and the second power signal VSS form a light-emitting circuit
  • the current is from the second power signal VSS flows to the first power signal VDD
  • the second light emitting device D2 normally emits light.
  • FIG. 4 is a second structural schematic diagram of the light emitting device driving circuit provided in the present application.
  • the light emitting module 102 includes a plurality of first light emitting devices D1 and a plurality of light emitting devices D2.
  • the arrangement directions of the first poles and the second poles of the plurality of first light emitting devices D1 are the same.
  • Multiple first light emitting devices D1 can be arranged in series or in parallel.
  • the arrangement directions of the first poles and the second poles of the plurality of second light emitting devices D2 are the same.
  • Multiple second light emitting devices D2 can be arranged in series or in parallel.
  • FIG. 4 is only an example, and should not be construed as a limitation to the present application.
  • multiple first light-emitting devices D1 and multiple light-emitting devices D2 are arranged in the light-emitting module 102, and multiple first light-emitting devices D1 can be arranged in series or in parallel, and multiple second light-emitting devices D2 can be arranged in series Or set up in parallel, so that the luminous brightness can be improved. And when one of the light-emitting devices fails, other light-emitting devices can also provide sufficient brightness, further reducing the influence of dead pixels, and improving the service life of the light-emitting device driving circuit 100 .
  • FIG. 5 is a schematic diagram of a third structure of the light emitting device driving circuit provided in the present application.
  • the difference from the light emitting device driving circuit 100 shown in FIG. 1 is that in this embodiment, the light emitting device driving circuit 100 further includes a sensing module 103 .
  • the sensing module 103 receives the sensing signal Vse and the reset signal Vref, and is electrically connected to one of the source and the drain of the driving transistor DT.
  • the sensing module 103 is used for detecting the threshold voltage of the driving transistor DT under the control of the sensing signal Vse and the reset signal Vref.
  • the sensing module 103 includes a sensing transistor T2 and a first switch unit Spre.
  • the gate of the sensing transistor T2 is connected to the sensing signal Vse.
  • One of the source and the drain of the sensing transistor T2 is electrically connected to one end of the first switching unit Spre.
  • the other of the source and the drain of the sensing transistor T2 is electrically connected to one of the source and the drain of the driving transistor DT.
  • the other terminal of the first switch unit Spre is connected to the reset signal Vref.
  • the driving sequence of the light emitting device driving circuit 100 in this embodiment includes a sensing phase and a light emitting phase.
  • the scan signal Vsc changes from a low potential to a high potential, and the switch transistor T1 is turned on.
  • the data signal Vda is transmitted to the gate of the driving transistor TD through the switching transistor T1 and stored in the storage capacitor Cst.
  • the sensing signal Sen is at a high potential, and the sensing transistor T2 is turned on.
  • the first switch unit Spre is closed.
  • the reset signal Vref is transmitted to one of the source or the drain of the driving transistor TD so that the voltage of one of the source or the drain of the driving transistor TD is equal to the reset signal Vref.
  • the scan signal Vsc changes from a high potential to a low potential, and the switching transistor T1 is turned off, so that the gate of the driving transistor TD is in a floating state.
  • the sensing transistor keeps T2 turned on, and the first switching element Spre is turned off.
  • the voltage of one of the source or the drain of the drive transistor TD is raised.
  • an external detection source ADC Analog To Digital Converter, analog-to-digital converter
  • the scan signal Vsc changes from a low potential to a high potential, and the switch transistor T1 is turned on.
  • the data signal Vda is transmitted to the gate of the driving transistor TD through the switching transistor T1 and stored in the storage capacitor Cst.
  • the sensing signal is at a low potential, and the sensing transistor T2 is turned off. Since the gate potential of the driving transistor TD is pulled up to the potential of the data signal Vda, the driving transistor DT is turned on. At this time, the first light emitting device D1 or the second light emitting device D2 emits light, which will not be repeated here.
  • the data signal Vda is a threshold voltage compensated signal.
  • the light emitting device driving circuit 100 provided in the present application is only an example, and those skilled in the art can configure the light emitting device driving circuit 100 according to specific needs. That is, the light emitting device driving circuit 100 provided in the embodiment of the present application not only includes the devices described above.
  • the light emitting device driving circuit 100 provided in the embodiment of the present application may also include other devices. For example: in order to further improve the control of the lighting time of the light emitting module 102, a transistor can be provided between the first power supply signal VDD and the driving transistor DT, and/or a transistor can be provided between the light emitting module 102 and the second power supply signal VSS The transistor is used to control the light-emitting duration of the light-emitting module 102 .
  • the light-emitting driving circuit 100 may further include an internal compensation circuit to internally compensate the threshold voltage of the driving transistor DT. Compared with the external detection of the sensing module 103 , the internal detection is more convenient.
  • a new type of light-emitting device drive circuit 100 is designed, by configuring the first power signal and the second power signal to perform potential conversion according to a preset cycle, so that the first light-emitting device and the second The light emitting devices emit light alternately. That is, the direction of the current flowing through the driving transistor is changed according to a preset period. Therefore, the current bias voltage received by the driving transistor can be effectively improved, and the stability of the driving transistor can be improved, so that the backlight module 200 can provide a stable light source.
  • FIG. 8 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the embodiment of the present application provides a display panel 300 .
  • the display panel 300 includes a plurality of pixel units 301 arranged in an array.
  • Each pixel unit 301 includes the above-mentioned light-emitting device driving circuit 100 , for details, reference may be made to the above-mentioned description of the light-emitting device driving circuit 100 , which will not be repeated here.
  • the display panel 300 may be a Mini LED display panel, a Micro LED display panel or an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display panel.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • a new type of light-emitting device driving circuit 100 is designed for the pixel unit 301, by configuring the first power signal and the second power signal to perform potential conversion according to a preset cycle, so that the current flowing through the driving The current direction of the transistor changes according to a preset period. Therefore, the current bias voltage received by the driving transistor can be effectively improved, and the stability of the driving transistor can be improved. Furthermore, the display of the display panel 300 is uniform, and the quality of the display panel 300 is improved. In addition, the first light emitting device and the second light emitting device emit light alternately, which can reduce the influence of dead pixels and improve the quality of the display panel 300 .

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Abstract

一种发光器件驱动电路（100）、背光模组（200）及显示面板（300）。发光器件驱动电路（100）包括驱动晶体管（DT）、数据写入模块（101）以及发光模块（102）。在发光模块（102）中，第一发光器件（D1）和第二发光器件（D2）的第一极以及第二极反向设置。第一电源信号（VDD）和第二电源信号（VSS）被配置为根据预设周期进行电位转换，使得流经驱动晶体管（DT）的电流方向根据预设周期发生改变。

Description

发光器件驱动电路、背光模组及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种发光器件驱动电路、背光模组及显示面板。
 背景技术
Mini LED（Mini Light-Emitting Diode，迷你发光二极管）、Micro LED（Micro Light-Emitting Diode，微米发光二极管）统称为MLED，其作为新一代显示技术，展示出较好的显示特性，如高对比度、高色域、高响应速度、广视角等。因此，MLED被广泛地应用于高性能显示领域中。
 技术问题
MLED的驱动属于电流驱动，一方面，输入的数据信号不同，驱动晶体管的栅源电压Vgs就不同，使得源漏极电流Ids以及MLED的亮度不同，从而实现灰阶切分。另一方面，驱动晶体管在整个显示时间内都是处于开态，而且需要对电流进行精确地控制，才能达到灰阶切分的目的。因此，驱动晶体管的阈值电压和迁移率漂移会直接作用于驱动电流上，造成显示异常。但是，在MLED中，驱动晶体管的电流方向时刻一致，在开启时间长、电流方向固定的两者作用下，电流偏压（stress）效应非常明显，易导致驱动晶体管的性能漂移，从而降低驱动晶体管的稳定性。
 技术解决方案
本申请提供一种发光器件驱动电路、背光模组及显示面板，以解决现有技术中，发光器件驱动电路中的驱动晶体管受到的电流偏压效应明显，稳定性易受影响的技术问题。
本申请提供一种发光器件驱动电路，其包括：
驱动晶体管，所述驱动晶体管的源极和漏极中的一者电连接于第一节点，所述驱动晶体管的源极和漏极中的另一者电连接于第一电源信号；
数据写入模块，所述数据写入模块接入扫描信号和数据信号，并与所述驱动晶体管的栅极电连接，所述数据写入模块用于在所述扫描信号的控制下，将所述数据信号写入所述驱动晶体管的栅极；
发光模块，所述发光模块包括至少一第一发光器件和至少一第二发光器件，所述第一发光器件的第一极与所述第二发光器件的第二极均电连接于所述第一节点，所述第一发光器件的第二极与所述第二发光器件的第一极均电连接于第二电源信号；
其中，所述第一电源信号和所述第二电源信号被配置为根据预设周期进行电位转换，使得流经所述驱动晶体管的电流方向根据所述预设周期发生改变。可选的，在本申请一些实施例中，所述预设周期至少为一帧。
可选的，在本申请一些实施例中，所述第一电源信号和所述第二电源信号在相邻帧之间的垂直空白周期内进行电位转换。
可选的，在本申请一些实施例中，所述第一电源信号具有第一高电平和第一低电平，所述第一电源信号根据所述预设周期在所述第一高电平和所述第一低电平之间进行转换；
所述第二电源信号具有第二高电平和第二低电平，所述第二电源信号根据所述预设周期在所述第二高电平和所述第二低电平之间进行转换。
可选的，在本申请一些实施例中，所述第一高电平和所述第二高电平相同，所述第一低电平和所述第二低电平相同，所述第一电源信号和所述第二电源信号保持反相。
可选的，在本申请一些实施例中，所述数据写入模块包括开关晶体管和存储电容；
所述开关晶体管的栅极接入所述扫描信号，所述开关晶体管的源极和漏极中的一者接入所述数据信号，所述开关晶体管的源极和漏极中的另一者、所述存储电容的一端以及所述驱动晶体管的栅极电连接，所述存储电容的另一端与所述驱动晶体管的源极和漏极中的一者电连接。
可选的，在本申请一些实施例中，所述发光器件驱动电路还包括感测模块，所述感测模块接入感测信号和重置信号，并电连接于所述驱动晶体管的源极和漏极中的一者，所述感测模块用于在所述感测信号和所述重置信号的控制下侦测所述驱动晶体管的阈值电压。
可选的，在本申请一些实施例中，所述感测模块包括感测晶体管和第一开关单元，所述感测晶体管的栅极接入所述感测信号，所述感测晶体管的源极和漏极中的一者与所述第一开关单元的一端电连接，所述感测晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电连接，所述第一开关单元的另一端接入所述重置信号。
相应的，本申请还提供一种背光模组，其包括：
数据线，所述数据线用于提供数据信号；
扫描线，所述扫描线用于提供扫描信号；
第一电源线，所述第一电源线用于提供第一电源信号；
第二电源线，所述第二电源线用于提供第二电源信号；
发光器件驱动电路，所述发光器件驱动电路与所述数据线、所述扫描线、所述第一电源线以及所述第二电源线电连接，所述发光器件驱动电路包括：
驱动晶体管，所述驱动晶体管的源极和漏极中的一者电连接于第一节点，所述驱动晶体管的源极和漏极中的另一者电连接于第一电源信号；
数据写入模块，所述数据写入模块接入扫描信号和数据信号，并与所述驱动晶体管的栅极电连接，所述数据写入模块用于在所述扫描信号的控制下，将所述数据信号写入所述驱动晶体管的栅极；
发光模块，所述发光模块包括至少一第一发光器件和至少一第二发光器件，所述第一发光器件的第一极与所述第二发光器件的第二极均电连接于所述第一节点，所述第一发光器件的第二极与所述第二发光器件的第一极均电连接于第二电源信号；
其中，所述第一电源信号和所述第二电源信号被配置为根据预设周期进行电位转换，使得流经所述驱动晶体管的电流方向根据所述预设周期发生改变。
可选的，在本申请一些实施例中，所述预设周期至少为一帧。
可选的，在本申请一些实施例中，所述第一电源信号和所述第二电源信号在相邻帧之间的垂直空白周期内进行电位转换。
可选的，在本申请一些实施例中，所述第一电源信号具有第一高电平和第一低电平，所述第一电源信号根据所述预设周期在所述第一高电平和所述第一低电平之间进行转换；
所述第二电源信号具有第二高电平和第二低电平，所述第二电源信号根据所述预设周期在所述第二高电平和所述第二低电平之间进行转换。
可选的，在本申请一些实施例中，所述第一高电平和所述第二高电平相同，所述第一低电平和所述第二低电平相同，所述第一电源信号和所述第二电源信号保持反相。
可选的，在本申请一些实施例中，所述数据写入模块包括开关晶体管和存储电容；
所述开关晶体管的栅极接入所述扫描信号，所述开关晶体管的源极和漏极中的一者接入所述数据信号，所述开关晶体管的源极和漏极中的另一者、所述存储电容的一端以及所述驱动晶体管的栅极电连接，所述存储电容的另一端与所述驱动晶体管的源极和漏极中的一者电连接。
相应的，本申请还提供一种显示面板，所述显示面板包括多个呈阵列排布的像素单元，每一所述像素单元均包括发光器件驱动电路，所述发光器件驱动电路包括：
驱动晶体管，所述驱动晶体管的源极和漏极中的一者电连接于第一节点，所述驱动晶体管的源极和漏极中的另一者电连接于第一电源信号；
数据写入模块，所述数据写入模块接入扫描信号和数据信号，并与所述驱动晶体管的栅极电连接，所述数据写入模块用于在所述扫描信号的控制下，将所述数据信号写入所述驱动晶体管的栅极；
发光模块，所述发光模块包括至少一第一发光器件和至少一第二发光器件，所述第一发光器件的第一极与所述第二发光器件的第二极均电连接于所述第一节点，所述第一发光器件的第二极与所述第二发光器件的第一极均电连接于第二电源信号；
其中，所述第一电源信号和所述第二电源信号被配置为根据预设周期进行电位转换，使得流经所述驱动晶体管的电流方向根据所述预设周期发生改变。
可选的，在本申请一些实施例中，所述预设周期至少为一帧。
可选的，在本申请一些实施例中，所述第一电源信号和所述第二电源信号在相邻帧之间的垂直空白周期内进行电位转换。
可选的，在本申请一些实施例中，所述第一电源信号具有第一高电平和第一低电平，所述第一电源信号根据所述预设周期在所述第一高电平和所述第一低电平之间进行转换；
所述第二电源信号具有第二高电平和第二低电平，所述第二电源信号根据所述预设周期在所述第二高电平和所述第二低电平之间进行转换。
可选的，在本申请一些实施例中，所述第一高电平和所述第二高电平相同，所述第一低电平和所述第二低电平相同，所述第一电源信号和所述第二电源信号保持反相。
可选的，在本申请一些实施例中，所述数据写入模块包括开关晶体管和存储电容；
所述开关晶体管的栅极接入所述扫描信号，所述开关晶体管的源极和漏极中的一者接入所述数据信号，所述开关晶体管的源极和漏极中的另一者、所述存储电容的一端以及所述驱动晶体管的栅极电连接，所述存储电容的另一端与所述驱动晶体管的源极和漏极中的一者电连接。
 有益效果
本申请提供一种发光器件驱动电路、背光模组及显示面板。所述发光器件驱动电路包括驱动晶体管、数据写入模块以及发光模块。其中，驱动晶体管的源极和漏极分别电连接于第一电源信号与第一节点。发光模块包括至少一第一发光器件和至少一第二发光器件。第一发光器件的第一极与第二发光器件的第二极均电连接于第一节点。第一发光器件的第二极与第二发光器件的第一极均电连接于第二电源信号。本申请通过将第一电源信号和第二电源信号配置为根据预设周期进行电位转换，使得流经驱动晶体管的电流方向根据预设周期发生改变，从而能够有效改善驱动晶体管受到的电流偏压，避免驱动晶体管的阈值电压和迁移率偏移，进而提高驱动晶体管的稳定性。此外，由于第一发光器件和第二发光器件反向排列，因此可以在驱动电流的作用下交替发光，从而达到降低光效以及降低坏点的目的。
 附图说明
图1是本申请提供的发光器件驱动电路的第一结构示意图；
图2是本申请提供的发光器件驱动电路中第一电源信号和第二电源信号的时序图；
图3是本申请提供的发光器件驱动电路的第一电路示意图；
图4是本申请提供的发光器件驱动电路的第二结构示意图；
图5是本申请提供的发光器件驱动电路的第三结构示意图；
图6是本申请提供的发光器件驱动电路的第二电路示意图；
图7是本申请提供的背光模组的一种结构示意图；
图8是本申请提供的显示面板的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
此外，本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。
本申请提供一种发光器件驱动电路、背光模组及显示面板以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1，图1是本申请提供的发光器件驱动电路的第一结构示意图。在本申请中，发光器件驱动电路100包括驱动晶体管DT、数据写入模块101以及发光模块102。
其中，驱动晶体管DT的源极和漏极中的一者电连接于第一节点A。驱动晶体管DT的源极和漏极中的另一者电连接于第一电源信号VDD。数据写入模块101接入扫描信号Vsc和数据信号Vda，并与驱动晶体管DT的栅极电连接。数据写入模块101用于在扫描信号Vsc的控制下，将数据信号Vda写入驱动晶体管DT的栅极。发光模块102包括至少一第一发光器件D1和至少一第二发光器件D2。第一发光器件D1的第一极与第二发光器件D2的第二极均电连接于第一节点A。第一发光器件D1的第二极与第二发光器件D2的第一极均电连接于第二电源信号VSS。第一电源信号VDD和第二电源信号VSS被配置为根据预设周期进行电位转换，以使得流经驱动晶体管DT的电流方向根据预设周期发生改变。
在本申请的发光器件驱动电路100中，由于第一发光器件D1的第一极与第二发光器件D2的第二极均电连接于第一节点A，第一发光器件D1的第二极与第二发光器件D2的第一极均电连接于第二电源信号VSS。也即第一发光器件D1和第二发光器件D2反向排布。因此，第一发光器件D1和第二发光器件D2不会同时发光。然后，通过根据预设周期将第一电源信号VDD和第二电源信号VSS进行电位转换，可以使得流经驱动晶体管DT的电流方向根据预设周期发生改变，从而能够有效改善驱动晶体管DT受到的电流偏压，避免驱动晶体管DT的阈值电压和迁移率偏移，从而提高驱动晶体管DT的稳定性。同时，在驱动电流方向改变时，第一发光器件D1和第二发光器件D2可以交替发光，避免出现驱动电流方向改变导致的发光异常。
此外，由于第一发光器件D1和第二发光器件D2交替发光，因此第一发光器件D1和第二发光器件D2的温度不会过高，从而降低光效。且第一发光器件D1和第二发光器件D2受到的电流偏压效应也会得到抑制。再则，由于每个发光模块102具有第一发光器件D1和第二发光器件D2。因此，当其中之一被损坏时，另外一颗仍可以继续提供亮度，从而降低坏点的影响。
在本申请中，第一发光器件D1和第二发光器件D2可以是迷你发光二极管、微型发光二极管或有机发光二极管。当第一发光器件D1和第二发光器件D2为上述发光二极管时。第一发光器件D1的第一极可以是发光二极管的阳极或阴极中的一极。第一发光器件D1的第二极可以是发光二极管的阳极或阴极中的另一极。第二发光器件D2亦然，在此不再赘述。
在本申请中，预设周期至少为一帧。一帧表示显示面板显示一帧画面的时间。比如，其中，该预设周期可以是1帧、2帧、5帧、10帧等，具体可根据发光器件驱动电路100的具体参数进行设置，本申请对此不作限定。其中，第一电源信号VDD和第二电源信号VSS可由外部电源芯片（图中未示出）提供，在此不再赘述。进一步的，可在当前帧以及相邻下一帧中间的垂直空白周期（vertical blanking time）内对第一电源信号VDD和第二电源信号VSS进行电位转换，从而避免对显示面板的显示画面产生影响。
在本申请中，第一电源信号VDD的电压值和第二电源信号VSS的电压值可以根据实际应用进行设定。只需满足第一发光器件D1和第二发光器件D2能够在第一电源信号VDD的电压值和第二电源信号VSS的作用下交替发光即可。比如，当第一电源信号VDD的电压值大于第二电源信号VSS时，第一发光器件D1发光，驱动电流自第一电源信号VDD流向第二电源信号VSS。当第一电源信号VDD的电压值小于第二电源信号VSS时，第二发光器件D2发光，驱动电流自第二电源信号VSS流向第一电源信号VDD。
具体的，请参阅图2，图2是本申请提供的发光器件驱动电路中第一电源信号和第二电源信号的时序图。在本申请一些实施例中，第一电源信号VDD具有第一高电平V1和第一低电平V2。第一电源信号VDD根据预设周期在第一高电平V1和第一低电平V2之间进行转换。第二电源信号VSS具有第二高电平V3和第二低电平V4。第二电源信号VSS根据预设周期在第二高电平V3和第二低电平V4之间进行转换。
其中，第一高电平V1和第二高电平V3可以是任一可以驱动第一发光器件D1和第二发光器件D2稳定发光的高电位。第一低电平V2和第二低电平V4的电位可以为接地端的电位。当然，可以理解地，第一低电平V2和第二低电平V4的电位还可以为其它驱动第一发光器件D1和第二发光器件D2稳定发光的低电位。
在本申请一些实施例中，第一高电平V1和第二高电平V3相同。第一低电平V2和第二低电平V4相同。也即，第一电源信号VDD和第二电源信号VSS时刻保持反相。其中，保持反相指的是第一电源信号VDD的电压绝对值和第二电源信号VSS的电压绝对值相等，但是相位相反。从而可以简化发光器件驱动电路100中的时序，降低提供第一电源信号VDD和第二电源信号VSS的电源芯片的功耗。
请参阅图3，图3是本申请提供的发光器件驱动电路的第一电路示意图。在本申请一些实施例中，数据写入模块101包括开关晶体管T1和存储电容Cst。开关晶体管T1的栅极接入扫描信号Vsc。开关晶体管T1的源极和漏极中的一者接入数据信号Vda。开关晶体管T1的源极和漏极中的另一者、存储电容Cst的一端以及驱动晶体管DT的栅极电连接。存储电容Cst的另一端与驱动晶体管DT的源极和漏极中的一者电连接。当然，可以理解地，数据写入模块101还可以采用多个晶体管和一个电容串联形成。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P型晶体管和/或N型晶体管两种，其中，P型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
进一步的，可以设置本申请提供的发光器件驱动电路100中的晶体管为同一种类型的晶体管，从而避免不同类型的晶体管之间的差异性对发光器件驱动电路100造成的影响。本申请以下实施例均以各晶体管为N型晶体管为例进行说明，但不能理解为对本申请的限定。
具体的，扫描信号Vsc由低电位转变为高电位，开关晶体管T1导通。数据信号Vda经开关晶体管T1传输至驱动晶体管TD的栅极，并储存在存储电容Cst中。由于驱动晶体管TD的栅极电位被拉高至数据信号Vda的电位，驱动晶体管DT打开。此时，当第一电源信号VDD的电位高于第二电源信号VSS的电位时，第一电源信号VDD、驱动晶体管DT、第一发光器件D1以及第二电源信号VSS形成一发光回路，电流自第一电源信号VDD流向第二电源信号VSS，第一发光器件D1正常发光。反之，当第一电源信号VDD的电位小于第二电源信号VSS时，第一电源信号VDD、驱动晶体管DT、第二发光器件D2以及第二电源信号VSS形成一发光回路，电流自第二电源信号VSS流向第一电源信号VDD，第二发光器件D2正常发光。
请参阅图4，图4是本申请提供的发光器件驱动电路的第二结构示意图。与图1所示的发光器件驱动电路100的不同之处在于，在本实施例中，发光模块102包括多个第一发光器件D1和多个发光器件D2。其中，多个第一发光器件D1的第一极和第二极的排列方向相同。多个第一发光器件D1可以串联设置，也可以并联设置。同理，多个第二发光器件D2的第一极和第二极的排列方向相同。多个第二发光器件D2可以串联设置，也可以并联设置。图4仅为示例，不能理解为对本申请的限定。
本实施例通过在发光模块102中设置多个第一发光器件D1和多个发光器件D2，且多个第一发光器件D1可以串联设置或并联设置，以及多个第二发光器件D2可以串联设置或并联设置，从而可以提高发光亮度。且当其中一个发光器件出现故障时，其它发光器件也可以提供足够的亮度，进一步降低坏点的影响，提高发光器件驱动电路100的使用寿命。
请参阅图5，图5是本申请提供的发光器件驱动电路的第三结构示意图。与图1所示的发光器件驱动电路100的不同之处在于，在本实施例中，发光器件驱动电路100还包括感测模块103。感测模块103接入感测信号Vse和重置信号Vref，并电连接于驱动晶体管DT的源极和漏极中的一者。感测模块103用于在感测信号Vse和重置信号Vref的控制下侦测驱动晶体管DT的阈值电压。
具体的，请参阅图6，图6是本申请提供的发光器件驱动电路的第二电路示意图。在本申请一些实施例中，感测模块103包括感测晶体管T2和第一开关单元Spre。感测晶体管T2的栅极接入感测信号Vse。感测晶体管T2的源极和漏极中的一者与第一开关单元Spre的一端电连接。感测晶体管T2的源极和漏极中的另一者与驱动晶体管DT的源极和漏极中的一者电连接。第一开关单元Spre的另一端接入重置信号Vref。
其中，本实施例中的发光器件驱动电路100的驱动时序包括感测阶段和发光阶段。
在感测阶段，扫描信号Vsc由低电位转变为高电位，开关晶体管T1导通。数据信号Vda经开关晶体管T1传输至驱动晶体管TD的栅极，并储存在存储电容Cst中。此时，感测信号Sen为高电位，感测晶体管T2打开。第一开关单元Spre闭合。重置信号Vref传输至驱动晶体管TD的源极或漏极中的一者，使得驱动晶体管TD的源极或漏极中的一者的电压等于重置信号Vref。然后，扫描信号Vsc由高电位转变为低电位，开关晶体管T1截止，从而使得驱动晶体管TD的栅极处于浮空状态。感测晶体管保持T2导通，第一开关元件Spre截止。驱动晶体管TD的源极或漏极中的一者的电压抬升。当驱动晶体管TD的源极或漏极中的一者的电压抬升至驱动晶体管TD关闭时，可利用外部的侦测源ADC（Analog To Digital Converter，模拟数字转换器）对驱动晶体管TD的源极或漏极中的一者的电位进行侦测，从而获得驱动晶体管DT的初始阈值电压。
在发光阶段，扫描信号Vsc由低电位转变为高电位，开关晶体管T1导通。数据信号Vda经开关晶体管T1传输至驱动晶体管TD的栅极，并储存在存储电容Cst中。此时，感测信号为低电位，感测晶体管T2关闭。由于驱动晶体管TD的栅极电位被拉高至数据信号Vda的电位，驱动晶体管DT打开。此时，第一发光器件D1或第二发光器件D2发光，在此不再赘述。其中，数据信号Vda为经过阈值电压补偿的信号。
本实施例通过在发光器件驱动电路100中增设感测模块103，可以对驱动晶体管DT的阈值电压进行侦测，从而实现对驱动晶体管DT的阈值电压偏移的补偿，进一步提高驱动晶体管DT的稳定性。
需要说明的是，本申请提供的发光器件驱动电路100仅仅只是一种示例，本领域技术人员可以根据具体需要对发光器件驱动电路100进行设置。也即，本申请实施例提供的发光器件驱动电路100不仅仅包括以上描述的器件。本申请实施例提供的发光器件驱动电路100还可以包括其他器件。比如：为了进一步提升对发光模块102发光时间的控制，可以在第一电源信号VDD和驱动晶体管DT之间设置一晶体管，和/或，在发光模块102和第二电源信号VSS之间可以设置一晶体管，以控制发光模块102的发光时长。又比如，发光驱动电路100还可以包括内部补偿电路，以对驱动晶体管DT的阈值电压进行内部补偿，相较于设置感测模块103的外部侦测，内部侦测更加方便。
请参阅图7，图7为本申请实施例提供的背光模组的结构示意图。本申请实施例还提供一种背光模组200，其包括扫描线21、数据线22、第一电源线23、第二电源线24以及以上任一实施例所述的发光器件驱动电路100。其中，扫描线21用于提供扫描信号。数据线22用于提供数据信号。第一电源线23用于提供第一电源信号。第二电源线24用于提供第二电源信号。发光器件驱动电路100分别与扫描线21、数据线22、第一电源线23以及第二电源线24电连接。发光器件驱动电路100具体可参照以上对该发光器件驱动电路的描述，在此不做赘述。
在本申请的背光模组200中，设计一种新型的发光器件驱动电路100，通过将第一电源信号和第二电源信号配置为根据预设周期进行电位转换，使得第一发光器件和第二发光器件交替发光。也即，使得流经驱动晶体管的电流方向根据预设周期发生改变。从而能够有效改善驱动晶体管受到的电流偏压，提高驱动晶体管的稳定性，进而使得背光模组200能够提供稳定的光源。
请参阅图8，图8为本申请实施例提供的显示面板的结构示意图。本申请实施例提供一种显示面板300。显示面板300包括多个呈阵列排布的像素单元301。每一像素单元301均包括以上所述的发光器件驱动电路100，具体可参照以上对该发光器件驱动电路100的描述，在此不做赘述。
其中，显示面板300可以是Mini LED显示面板、Micro LED显示面板或者OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板。
在本申请的显示面板300中，针对像素单元301设计了一种新型的发光器件驱动电路100，通过将第一电源信号和第二电源信号配置为根据预设周期进行电位转换，使得流经驱动晶体管的电流方向根据预设周期发生改变。从而能够有效改善驱动晶体管受到的电流偏压，提高驱动晶体管的稳定性。进而使得显示面板300显示均匀，提高显示面板300的品质。此外，第一发光器件和第二发光器件交替发光，可以降低坏点的影响，提高显示面板300的品质。
以上对本申请实施例进行了详细介绍。本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想，并非因此限制本申请的专利范围。凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种发光器件驱动电路，其包括：
    驱动晶体管，所述驱动晶体管的源极和漏极中的一者电连接于第一节点，所述驱动晶体管的源极和漏极中的另一者电连接于第一电源信号；
    数据写入模块，所述数据写入模块接入扫描信号和数据信号，并与所述驱动晶体管的栅极电连接，所述数据写入模块用于在所述扫描信号的控制下，将所述数据信号写入所述驱动晶体管的栅极；
    发光模块，所述发光模块包括至少一第一发光器件和至少一第二发光器件，所述第一发光器件的第一极与所述第二发光器件的第二极均电连接于所述第一节点，所述第一发光器件的第二极与所述第二发光器件的第一极均电连接于第二电源信号；
    其中，所述第一电源信号和所述第二电源信号被配置为根据预设周期进行电位转换，使得流经所述驱动晶体管的电流方向根据所述预设周期发生改变。
  2. 根据权利要求1所述的发光器件驱动电路，其中，所述预设周期至少为一帧。
  3. 根据权利要求2所述的发光器件驱动电路，其中，所述第一电源信号和所述第二电源信号在相邻帧之间的垂直空白周期内进行电位转换。
  4. 根据权利要求1所述的发光器件驱动电路，其中，所述第一电源信号具有第一高电平和第一低电平，所述第一电源信号根据所述预设周期在所述第一高电平和所述第一低电平之间进行转换；
    所述第二电源信号具有第二高电平和第二低电平，所述第二电源信号根据所述预设周期在所述第二高电平和所述第二低电平之间进行转换。
  5. 根据权利要求4所述的发光器件驱动电路，其中，所述第一高电平和所述第二高电平相同，所述第一低电平和所述第二低电平相同，所述第一电源信号和所述第二电源信号保持反相。
  6. 根据权利要求1所述的发光器件驱动电路，其中，所述数据写入模块包括开关晶体管和存储电容；
    所述开关晶体管的栅极接入所述扫描信号，所述开关晶体管的源极和漏极中的一者接入所述数据信号，所述开关晶体管的源极和漏极中的另一者、所述存储电容的一端以及所述驱动晶体管的栅极电连接，所述存储电容的另一端与所述驱动晶体管的源极和漏极中的一者电连接。
  7. 根据权利要求1所述的发光器件驱动电路，其中，所述发光器件驱动电路还包括感测模块，所述感测模块接入感测信号和重置信号，并电连接于所述驱动晶体管的源极和漏极中的一者，所述感测模块用于在所述感测信号和所述重置信号的控制下侦测所述驱动晶体管的阈值电压。
  8. 根据权利要求7所述的发光器件驱动电路，其中，所述感测模块包括感测晶体管和第一开关单元，所述感测晶体管的栅极接入所述感测信号，所述感测晶体管的源极和漏极中的一者与所述第一开关单元的一端电连接，所述感测晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电连接，所述第一开关单元的另一端接入所述重置信号。
  9. 一种背光模组，其包括：
    数据线，所述数据线用于提供数据信号；
    扫描线，所述扫描线用于提供扫描信号；
    第一电源线，所述第一电源线用于提供第一电源信号；
    第二电源线，所述第二电源线用于提供第二电源信号；以及
    发光器件驱动电路，所述发光器件驱动电路与所述数据线、所述扫描线、所述第一电源线以及所述第二电源线电连接，所述发光器件驱动电路包括：
    驱动晶体管，所述驱动晶体管的源极和漏极中的一者电连接于第一节点，所述驱动晶体管的源极和漏极中的另一者电连接于第一电源信号；
    数据写入模块，所述数据写入模块接入扫描信号和数据信号，并与所述驱动晶体管的栅极电连接，所述数据写入模块用于在所述扫描信号的控制下，将所述数据信号写入所述驱动晶体管的栅极；
    发光模块，所述发光模块包括至少一第一发光器件和至少一第二发光器件，所述第一发光器件的第一极与所述第二发光器件的第二极均电连接于所述第一节点，所述第一发光器件的第二极与所述第二发光器件的第一极均电连接于第二电源信号；
    其中，所述第一电源信号和所述第二电源信号被配置为根据预设周期进行电位转换，使得流经所述驱动晶体管的电流方向根据所述预设周期发生改变。
  10. 根据权利要求9所述的背光模组，其中，所述预设周期至少为一帧。
  11. 根据权利要求10所述的背光模组，其中，所述第一电源信号和所述第二电源信号在相邻帧之间的垂直空白周期内进行电位转换。
  12. 根据权利要求9所述的背光模组，其中，所述第一电源信号具有第一高电平和第一低电平，所述第一电源信号根据所述预设周期在所述第一高电平和所述第一低电平之间进行转换；
    所述第二电源信号具有第二高电平和第二低电平，所述第二电源信号根据所述预设周期在所述第二高电平和所述第二低电平之间进行转换。
  13. 根据权利要求12所述的背光模组，其中，所述第一高电平和所述第二高电平相同，所述第一低电平和所述第二低电平相同，所述第一电源信号和所述第二电源信号保持反相。
  14. 根据权利要求9所述的背光模组，其中，所述数据写入模块包括开关晶体管和存储电容；
    所述开关晶体管的栅极接入所述扫描信号，所述开关晶体管的源极和漏极中的一者接入所述数据信号，所述开关晶体管的源极和漏极中的另一者、所述存储电容的一端以及所述驱动晶体管的栅极电连接，所述存储电容的另一端与所述驱动晶体管的源极和漏极中的一者电连接。
  15. 一种显示面板，其包括多个呈阵列排布的像素单元，每一所述像素单元均包括发光器件驱动电路，所述发光器件驱动电路包括：
    驱动晶体管，所述驱动晶体管的源极和漏极中的一者电连接于第一节点，所述驱动晶体管的源极和漏极中的另一者电连接于第一电源信号；
    数据写入模块，所述数据写入模块接入扫描信号和数据信号，并与所述驱动晶体管的栅极电连接，所述数据写入模块用于在所述扫描信号的控制下，将所述数据信号写入所述驱动晶体管的栅极；
    发光模块，所述发光模块包括至少一第一发光器件和至少一第二发光器件，所述第一发光器件的第一极与所述第二发光器件的第二极均电连接于所述第一节点，所述第一发光器件的第二极与所述第二发光器件的第一极均电连接于第二电源信号；
    其中，所述第一电源信号和所述第二电源信号被配置为根据预设周期进行电位转换，使得流经所述驱动晶体管的电流方向根据所述预设周期发生改变。
  16. 根据权利要求15所述的显示面板，其中，所述预设周期至少为一帧。
  17. 根据权利要求16所述的显示面板，其中，所述第一电源信号和所述第二电源信号在相邻帧之间的垂直空白周期内进行电位转换。
  18. 根据权利要求15所述的显示面板，其中，所述第一电源信号具有第一高电平和第一低电平，所述第一电源信号根据所述预设周期在所述第一高电平和所述第一低电平之间进行转换；
    所述第二电源信号具有第二高电平和第二低电平，所述第二电源信号根据所述预设周期在所述第二高电平和所述第二低电平之间进行转换。
  19. 根据权利要求18所述的显示面板，其中，所述第一高电平和所述第二高电平相同，所述第一低电平和所述第二低电平相同，所述第一电源信号和所述第二电源信号保持反相。
  20. 根据权利要求15所述的背光模组，其中，所述数据写入模块包括开关晶体管和存储电容；
    所述开关晶体管的栅极接入所述扫描信号，所述开关晶体管的源极和漏极中的一者接入所述数据信号，所述开关晶体管的源极和漏极中的另一者、所述存储电容的一端以及所述驱动晶体管的栅极电连接，所述存储电容的另一端与所述驱动晶体管的源极和漏极中的一者电连接。
    。
PCT/CN2021/138876 2021-12-09 2021-12-16 发光器件驱动电路、背光模组及显示面板 WO2023103015A1 (zh)

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