WO2023102964A1 - 存储器件及其制备方法 - Google Patents

存储器件及其制备方法 Download PDF

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Publication number
WO2023102964A1
WO2023102964A1 PCT/CN2021/137861 CN2021137861W WO2023102964A1 WO 2023102964 A1 WO2023102964 A1 WO 2023102964A1 CN 2021137861 W CN2021137861 W CN 2021137861W WO 2023102964 A1 WO2023102964 A1 WO 2023102964A1
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Prior art keywords
layer
source
drain
nmos
metal
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PCT/CN2021/137861
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English (en)
French (fr)
Inventor
刘子易
朱慧珑
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北京超弦存储器研究院
中国科学院微电子研究所
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Application filed by 北京超弦存储器研究院, 中国科学院微电子研究所 filed Critical 北京超弦存储器研究院
Priority to US18/256,669 priority Critical patent/US20240114672A1/en
Publication of WO2023102964A1 publication Critical patent/WO2023102964A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Definitions

  • the present disclosure relates to the field of semiconductors, in particular to a storage device and a manufacturing method thereof.
  • an object of the present disclosure is at least in part to provide a memory device capable of reducing standby leakage without increasing the threshold voltage of the device and a method of manufacturing the same.
  • a memory device including: a substrate; a memory cell array on the substrate, including a plurality of memory cells, wherein each memory cell includes: left stacked layers arranged at intervals in the horizontal direction and the right stacking layer, the left stacking layer and the right stacking layer both include a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer stacked on the substrate in sequence, the PMOS layer, the first NMOS layer and the second NMOS layer both include a first source/drain layer, a channel layer and a second source/drain layer stacked vertically, and the channel layer is laterally recessed relative to the first source/drain layer and the second source/drain layer into; the gate stack is vertically interposed between the first source/drain layer and the second source/drain layer, and is arranged on opposite sides of the channel layer to embed the lateral recess of the channel layer.
  • a method for fabricating a memory device including: forming left stacked layers and right stacked layers arranged at intervals in the horizontal direction on a substrate, the left stacked layers and the right stacked layers each including sequentially stacked
  • the lower isolation layer, the PMOS layer, the first NMOS layer, the upper isolation layer and the second NMOS layer, the PMOS layer, the first NMOS layer and the second NMOS layer all include vertically stacked first source/drain layers, trench
  • the channel layer and the second source/drain layer, the channel layer is laterally recessed relative to the first source/drain layer and the second source/drain layer;
  • a gate dielectric layer and a p-type gate are sequentially deposited on the lateral recess of the channel layer Conductor layer; deposit SiO 2 at the bottom of the left stack and the right stack, and then etch the SiO 2 and stop at a first preset height to form a first spacer; etch the first NMOS layer and the second NMOS
  • an electronic device including the above storage device.
  • the storage device and the preparation method provided by the present disclosure have at least the following beneficial effects: the storage device uses a 6T SRAM unit as the smallest storage unit, has fewer transistors, and simplifies the storage and calculation of the computer. structure, which saves computing resources and improves computing progress and computing efficiency.
  • laterally adjacent sidewall interconnect structures may be provided.
  • one mask layer can be utilized, thus reducing photolithography steps in the manufacturing process and lowering manufacturing costs.
  • the three-dimensional configuration allows more space for interconnections between devices, and thus can have low resistance and high bandwidth. Due to the presence of the sidewall interconnect structure, the semiconductor device can have lead-out terminals, so that the fabrication of the semiconductor device can be separated from the fabrication of the metallization stack.
  • Fig. 1 schematically shows the circuit principle diagram of 6T SRAM unit
  • Figure 2 schematically shows a cross-sectional view of forming a stack on a substrate
  • Fig. 3 (a) schematically shows the top view of photoresist patterning area
  • Fig. 3 (b) is the sectional view along AA ' line formed according to Fig. 3 (a);
  • Fig. 4 (a) schematically shows the top view of photoresist patterning area
  • Fig. 4 (b) is the sectional view along AA ' line formed according to Fig. 4 (a);
  • Fig. 5 (a) schematically shows a top view of the photoresist patterning region
  • Fig. 5 (b) is a cross-sectional view along line 11' formed according to Fig. 5 (a);
  • Figure 6 (a) schematically shows a top view of the photoresist patterning region
  • Figure 6 (b) is a cross-sectional view along line 11' formed according to Figure 6 (a)
  • Figure 6 (c) is a cross-sectional view according to Figure 6 ( a) The formed cross-sectional view along the line AA';
  • Fig. 7 schematically shows a sectional view along AA' line
  • Fig. 8 schematically shows a sectional view along AA' line
  • Fig. 9 schematically shows a cross-sectional view along line AA'
  • Fig. 10 schematically shows a sectional view along AA' line
  • Fig. 11 schematically shows a cross-sectional view along line AA'
  • Fig. 12 schematically shows a cross-sectional view along line AA'
  • Fig. 13 schematically shows a cross-sectional view along line AA'
  • Figure 14 schematically shows a cross-sectional view along AA' line
  • Fig. 15 schematically shows a cross-sectional view along line AA'
  • Figure 16 schematically shows a cross-sectional view along AA' line
  • Figure 17(a) schematically shows a top view of the photoresist patterning region
  • Figure 17(b) is a cross-sectional view along AA' line formed according to Figure 17(a)
  • Figure 17(c) is a cross-sectional view according to Figure 17( a) The formed cross-sectional view along the BB' line;
  • Figure 18(a) schematically shows a top view of the photoresist patterning region
  • Figure 18(b) is a cross-sectional view along AA' line formed according to Figure 18(a)
  • Figure 18(c) is a cross-sectional view according to Figure 18( a) The sectional view formed along the BB' line
  • Figure 18(d) is a sectional view along the CC' line formed according to Figure 18(a);
  • Figure 19(a) schematically shows a top view of the photoresist patterning region
  • Figure 19(b) is a cross-sectional view along the AA' line formed according to Figure 19(a);
  • Figure 19(c) is a cross-sectional view according to Figure 19( a) The sectional view formed along the BB' line;
  • Figure 19(d) is a sectional view along the CC' line formed according to Figure 19(a);
  • Figure 20 schematically shows a cross-sectional view along line AA'
  • Figure 21 (a) schematically shows a top view of the photoresist patterning area
  • Figure 21 (b) is a cross-sectional view along the line AA' formed according to Figure 21 (a);
  • Figure 22 schematically shows a cross-sectional view along line AA'
  • Figure 23 (a) schematically shows a top view of the photoresist patterning region
  • Figure 23 (b) is a cross-sectional view along the BB' line formed according to Figure 23 (a);
  • Figure 24 schematically shows a cross-sectional view along line BB'
  • Figure 25 schematically shows a sectional view along line BB'
  • Figure 26 schematically shows a cross-sectional view along line BB'
  • Figure 27(a) schematically shows a top view of the photoresist patterning region
  • Figure 27(b) is a cross-sectional view along the BB' line formed according to Figure 27(a);
  • Figure 28 (a) schematically shows a top view of the photoresist patterning region
  • Figure 28 (b) is a cross-sectional view along the BB' line formed according to Figure 28 (a);
  • Fig. 29 schematically shows a cross-sectional view along line BB'.
  • 2004-fourth SiC layer 2011-first SiO 2 layer; 2012-second SiO 2 layer;
  • 2013-third SiO 2 layer 2014-fourth SiO 2 layer; 2015-fifth SiO 2 layer;
  • 3001-first epitaxial layer 3002-second epitaxial layer; 4001-gate dielectric layer;
  • 5005 the fifth metal layer
  • 6001 the first contact portion
  • 6002 the second contact portion.
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on” another layer/element in one orientation, the layer/element can be located “below” the other layer/element when the orientation is reversed.
  • the disclosure can be presented in various forms, some examples of which are described below.
  • the selection of various materials is involved.
  • the selection of materials also considers etching selectivity.
  • the desired etch selectivity may or may not be indicated. It should be clear to those skilled in the art that when it is mentioned below that a certain material layer is etched, if it is not mentioned that other layers are also etched or it is not shown in the figure that other layers are also etched, then such etching It may be selective, and the layer of material may be etch-selective relative to other layers exposed to the same etch formulation.
  • Figure 1 schematically shows the circuit schematic of a 6T SRAM cell.
  • the 6T SRAM unit includes transistors M1-M6, G in the figure represents the gate of the transistor, S represents the source of the transistor, and D represents the drain of the transistor.
  • the source of the transistor M2 and the source of the transistor M4 are both connected to the power supply Vdd
  • the source of the transistor M1 and the source of the transistor M3 are both grounded to GND
  • the drain of the transistor M1 is connected to the drain of the transistor M2, and the drain of the transistor M3
  • the drain is connected to the drain of the transistor M4; the gate of the transistor M1, the gate of the transistor M2 are connected to the drain of the transistor M3, the gate of the transistor M3, the gate of the transistor M4 are connected to the drain of the transistor M1.
  • Both the gate of the transistor M5 and the gate of the transistor M6 are connected to the word line WL (W o rd Line ) , and the drain of the transistor M5 is connected to the bit line Connection, the drain of the transistor M6 is connected to the bit line BL (Bit Line), the bit line BL and the bit line
  • WL word line
  • BL bit line
  • the signals are opposite to each other, the source of the transistor M5 is connected to the drain of the transistor M1, and the source of the transistor M6 is connected to the drain of the transistor M3.
  • the 6T SRAM unit is used as the smallest unit, wherein transistors M1 and M3 are NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor field effect) transistors, and transistors M2 and M4 are PMOS (positive channel Metal Oxide Semiconductor, p-type metal oxide semiconductor field effect) transistors, transistors M5 and M6 are transmission gate NMOS transistors.
  • the transistors M1 and M2 constitute a first CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor), and the transistors M3 and M4 constitute a second CMOS.
  • the drains of transistors M1 and M2 are connected to the instrument to form the output node OUT1 of the first CMOS, and the drains of transistors M3 and M4 are connected to the instrument to form the output node OUT2 of the second CMOS.
  • the gates of the transistors M1 and M2 are connected together to form the input node IN1 of the first CMOS, and the gates of the transistors M3 and M4 are connected together to form the input node IN2 of the second CMOS.
  • the 6T SRAM unit has been described in detail above, and the storage device provided by the embodiment of the present disclosure below uses the 6T SRAM unit as the smallest storage unit, has fewer transistors, simplifies the storage and calculation structure of the computer, and saves Computing resources, while improving the calculation schedule and efficiency.
  • the memory device includes: a substrate; a memory cell array on the substrate, including a plurality of memory cells, wherein each memory cell includes: left stacked layers and right stacked layers arranged at intervals in the horizontal direction, Both the left stack and the right stack include a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer, and a second NMOS layer stacked on the substrate in sequence, and the PMOS layer, the first NMOS layer, and the second NMOS layer Each includes a vertically stacked first source/drain layer, a channel layer and a second source/drain layer, the channel layer is laterally recessed relative to the first source/drain layer and the second source/drain layer; the gate stack, It is between the first source/drain layer and the second source/drain layer in the vertical direction, and is arranged on opposite sides of the channel layer to embed the lateral recess of the channel layer.
  • the memory device further includes: a hard mask layer disposed on the first source/drain layer of the second NMOS layer.
  • the gate stack includes a gate dielectric layer and a gate conductor layer, and the gate dielectric layer includes a work function adjusting metal and a gate conductive metal disposed on the work function adjusting metal.
  • the gate conductor layer includes a p-type gate conductor layer and an n-type gate conductor layer, wherein: the p-type gate conductor layer is disposed between the first source/drain layer and the second source/drain layer of the PMOS layer The n-type gate conductor layer is disposed between the first source/drain layer and the second source/drain layer of the first NMOS layer, and between the first source/drain layer and the second source/drain layer of the second NMOS layer .
  • the lateral peripheral portions of the first source/drain layer and the second source/drain layer are recessed and the recessed portions are filled with the third SiC layer; and/or the lateral peripheral portions of the gate conductor layer are recessed And the concave part is filled with the third SiC layer.
  • the outer sidewall of the third SiC layer is vertically coplanar with the left stack and the right stack.
  • the memory device further includes: a fifth SiO 2 layer formed on the substrate between the left stack and the right stack, the top of the fifth SiO 2 layer is higher than the first source of the PMOS layer bottom of the /drain layer and lower than the top of the first source/drain layer of the PMOS layer.
  • the memory device further includes: a first metal layer formed on the fifth SiO2 layer in the longitudinal middle position of the left stack and the right stack, the top of the first metal layer is higher than the PMOS layer The top of the first source/drain layer and the bottom of the second source/drain layer lower than the PMOS layer.
  • the memory device further includes: a sixth SiO 2 layer and a second metal layer sequentially formed on the first metal layer, the top of the sixth SiO 2 layer is higher than the first source of the first NMOS layer The top of the /drain layer and the bottom of the second source/drain layer lower than the first NMOS layer; the top of the second metal layer is higher than the bottom of the second source/drain layer of the first NMOS layer and lower than the first NMOS layer on top of the second source/drain layer.
  • the memory device further includes: a seventh SiO 2 layer formed on the fifth SiO 2 layer except for the middle position in the vertical direction, the top of the seventh SiO 2 layer is higher than the first source of the PMOS layer the top of the source/drain layer and the bottom of the second source/drain layer lower than the PMOS layer.
  • the memory device further includes: a third metal layer formed on the seventh SiO2 layer, the top of the third metal layer is higher than the top of the first source/drain layer of the first NMOS layer and lower at the bottom of the second source/drain layer of the first NMOS layer.
  • the memory device further includes: an eighth SiO 2 layer formed on the third metal layer, the top of the eighth SiO 2 layer is higher than the bottom of the first source/drain layer of the second NMOS layer and The top of the first source/drain layer lower than the second NMOS layer; the middle position of the top of the eighth SiO 2 layer is relatively recessed and exposes the third metal layer, forming a second spacer separated from the left and right and in a stepped structure.
  • the inner sidewall and the bottom surface of the second spacer are formed with a fourth metal layer higher than the top of the eighth SiO2 layer; the top of the fourth metal layer is higher than the first source/drain of the second NMOS layer layer and below the top of the first source/drain layer of the second NMOS layer.
  • the memory device further includes: a fifth metal layer formed on one of the left stacked layer and the right stacked layer, and contacting the outer sidewall of the n- type gate conductor layer in the second NMOS layer;
  • the line is connected to the fifth metal layer, and the word line is connected between the left stacked layer and the right stacked layer at different vertical positions on the same memory cell, so as to contact and electrically connect to the left stacked layer or the right stacked layer in the second NMOS layer.
  • the outer sidewall of the n-type gate conductor layer is formed on one of the left stacked layer and the right stacked layer, and contacting the outer sidewall of the n- type gate conductor layer in the second NMOS layer.
  • the memory device further includes: a first contact part and a second contact part, the first contact part is embedded in the second source/drain layer of the second NMOS layer on the left stack, and the second contact part is embedded in On the second source/drain layer of the second NMOS layer stacked on the right, the first contact part and the second contact part are respectively connected to the first bit line and the second bit line with opposite signals.
  • An embodiment of the present disclosure also provides a method for manufacturing a storage device, including:
  • Step S1 forming left stacked layers and right stacked layers arranged at intervals in the horizontal direction on the substrate, and each of the left stacked layers and right stacked layers includes a lower isolation layer, a PMOS layer, a first NMOS layer, an upper
  • the isolation layer and the second NMOS layer, the PMOS layer, the first NMOS layer and the second NMOS layer all include a vertically stacked first source/drain layer, a channel layer and a second source/drain layer, the channel The channel layer is laterally recessed relative to the first source/drain layer and the second source/drain layer;
  • Step S2 sequentially depositing a gate dielectric layer and a p-type gate conductor layer in the lateral recess of the channel layer;
  • Step S3 depositing SiO 2 on the bottom of the left stack and the right stack, and then etching the SiO 2 and stopping at a first preset height to form a first spacer;
  • Step S4 etching the p-type gate conductor layer corresponding to the first NMOS layer and the second NMOS layer, and depositing an n-type gate conductor layer on the corresponding position of the etched p-type gate conductor layer;
  • Step S5 etching the first spacer to form a memory cell, and the memory device includes a memory cell array of a plurality of memory cells.
  • FIGS. 2 to 29 schematically show flow charts at different stages of a method for fabricating a storage device according to an embodiment of the present disclosure.
  • Fig. 2 schematically shows a cross-sectional view of forming a stack on a substrate.
  • a substrate 1001 is provided.
  • the substrate 1001 may be various types of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrate is used as an example for description.
  • a silicon wafer is provided as a substrate 1001 .
  • a well region may be formed. If a p-type device is to be formed, the well region can be an n-type well; if an n-type device is to be formed, the well region can be a p-type well. Therefore, a p-type well can be formed, for example, by implanting a p-type dopant such as boron (B) in the substrate 1001, and then performing thermal annealing.
  • a p-type dopant such as boron (B)
  • a PMOS layer, a first NMOS layer and a second NMOS layer stacked on the substrate in sequence may be formed by epitaxial growth.
  • the PMOS layer is a p-type device, and both the first NMOS layer and the second NMOS layer are n-type devices.
  • the doping of semiconductor materials can be achieved by in-situ doping during epitaxial growth, or by other doping methods such as ion implantation. By properly adjusting the conductivity type of the doping, a p-type device or an n-type device can be formed.
  • the PMOS layer includes a first source/drain layer 10031 , a channel defining layer 10051 and a second source/drain layer 10071 vertically stacked in sequence.
  • the first NMOS layer includes a first source/drain layer 10032 , a channel defining layer 10052 and a second source/drain layer 10072 vertically stacked in sequence.
  • the second NMOS layer includes a first source/drain layer 10033 , a channel defining layer 10053 and a second source/drain layer 10073 vertically stacked in sequence.
  • the thickness of the first source/drain layer 10031/10032/10033 is, for example, about 20 nm to 50 nm
  • the thickness of the channel defining layer 10051/10052/10053 is, for example, about 15 nm to 100 nm
  • the thickness of the second source/drain layer 10071/10072/10073 The thickness is, for example, about 20 nm to 50 nm.
  • a lower isolation layer 10021 is provided between the substrate 1001 and the first source/drain layer 10031 of the PMOS layer, and a lower isolation layer 10021 is provided between the second source/drain layer 10072 of the first NMOS layer and the first An upper isolation layer 10022 is provided between the source/drain layers 10033 .
  • Adjacent layers on the above-mentioned substrate 1001 may have etch selectivity relative to each other.
  • the first source/drain layer 10031/10032/10033 may include Si; the channel defining layer 10051/10052/10053 may be SiGe, and the composition of Ge is about 10% to 20%; the second source/drain layer 10071/ 10072/10073 can be Si.
  • Both the upper isolation layer 10022 and the lower isolation layer 10021 can be made of SiGe, with a thickness of about 10nm-20nm, and a composition of Ge of about 10%-20%.
  • a hard mask layer 1009 is also deposited on the second source/drain layer 10073 of the second NMOS layer to facilitate patterning.
  • the hard mask layer 1009 may include nitride, such as SiN, with a thickness of about 50nm ⁇ 200nm.
  • Figure 3(a) schematically shows a top view of the photoresist patterned area.
  • Fig. 3(b) is a cross-sectional view along line AA' formed according to Fig. 3(a).
  • the photoresist is spin-coated on the hard mask layer 1009, and the photoresist is patterned into the photoresist defined in Figure 3(a) through processes such as exposure and development. According to the shape of the device region, and using the patterned photoresist as a mask, etch the hard mask layer 1009 to the upper surface of the substrate 1001 sequentially along the vertical direction, and then remove the photoresist.
  • the A-A sectional view in Figure 3(b) only intercepts the A-A section in the rectangular frame area outside the thick double-dot dash line in Figure 3(a), and the subsequent AA' section, 11' section, BB Both the 'section and the CC' section are the sections taken from the corresponding top view corresponding to the area of the rectangular frame outside the thick double-dashed line.
  • the display area of the subsequent top view is obviously larger than the cross-sectional area, just to show the overall shape of the memory array formed by the interconnection of a plurality of minimum SRAM memory cells in the top view.
  • the PR (Photoresist, photoresist) area in Figure 4(a) indicates the area of spin-coated photoresist, which is not etched away and retains the original stack structure; the dark area indicates the area without photoresist, also That is, the region of the substrate 1001 is exposed in the plan view after etching.
  • each stacked layer is The cross section on the substrate 1001 is formed in a rectangular columnar shape.
  • the respective sidewalls of the layers in the stack can be vertically coplanar.
  • Figure 4(a) schematically shows a top view of the photoresist patterned area.
  • Fig. 4(b) is a cross-sectional view along line AA' formed according to Fig. 4(a).
  • a first SiC layer 2001 is deposited in the area where the upper and lower horizontal stripes and multiple vertical stripes in the horizontal direction are located, and the first SiC layer 2001 is controlled by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the first SiC layer 2001 deposited on the upper and lower horizontal stripes is etched from top to bottom, and the etching stops at the bottom of the substrate 1001. upper surface.
  • the material of the first SiC layer 2001 is SiC.
  • the upper and lower two horizontal stripes expose the substrate 1001 , and the other exposed regions of the substrate 1001 are filled with the first SiC layer 2001 .
  • the hard mask layer 1009 on the top layer of the stack structure and the first SiC layer 2001 are alternately arranged horizontally, and the hard mask layer 1009 and The upper surface of the first SiC layer 2001 is coated with photoresist.
  • Figure 5(a) schematically shows a top view of the photoresist patterned area.
  • Fig. 5(b) is a cross-sectional view along line 11' formed according to Fig. 5(a).
  • the photoresist in Figure 4(b) is removed, and the lower isolation is partially etched along the direction perpendicular to the upper and lower horizontal stripes, that is, the vertical direction.
  • the lateral SiGe grooves are shown. Since the lower isolation layer 10021 , the upper isolation layer 10022 and the channel defining layer 10051 / 10052 / 10053 can all be SiGe, it is convenient for unified etching.
  • a first SiO 2 layer 2011 is deposited in the lateral SiGe groove, and the first SiO 2 layer 2011 can be filled and occupied by reactive ion etching (Reactive Ion Etching, RIE). SiGe groove, and keep the outer sidewall of the first SiO 2 layer 2011 and the outer sidewall of the laminated layer aligned with each other.
  • the material of the first SiO 2 layer 2011 is SiO 2 .
  • a part of the lower isolation layer 10021, the upper isolation layer 10022, and the channel defining layer 10051/10052/10053 are respectively etched away, while the other part remains, wherein the etched part forms a lateral SiGe groove, and then the first SiO 2 layer 2011 replacement.
  • Figure 6(a) schematically shows a top view of the photoresist patterned area.
  • Fig. 6(b) is a cross-sectional view along line 11' formed according to Fig. 6(a).
  • Fig. 6(c) is a cross-sectional view along line AA' formed according to Fig. 6(a).
  • the first SiC layer 2001 is deposited on the exposed area of the substrate 1001 where the upper and lower two horizontal stripes are located, and the deposition of the first SiC layer 2001 is controlled by CMP to stop at the hard mask layer 1009's upper surface. Then, the formed first SiC layer 2001 is etched downward at the longitudinal narrow stripes in FIG. 6( a ), and the etching stops at the upper surface of the substrate 1001 .
  • the end point detection method can be used to determine the etching stop time.
  • a first SiC layer up to the hard mask layer 1009 is deposited on the substrate 1001 where the two transverse stripes are located. 2001, both the upper surface of the hard mask layer 1009 and the first SiC layer 2001 are coated with photoresist.
  • a first SiC layer 2001 with a height reaching the hard mask layer 1009 is deposited between the left stack and the right stack, and the left stack and the right stack.
  • the outer side of the first SiC layer 2001 is etched away at the position where the first SiC layer 2001 was formed before, forming a groove up to the substrate 1001 .
  • Fig. 7 schematically shows a cross-sectional view along line AA'.
  • the photoresist is removed, and then the lower isolation layer 10021, the upper isolation layer 10022, and the channel defining layer 10051/10052/10053 are partially etched on the section along the AA' line, so that the lower isolation layer 10021 , the upper isolation layer 10022 and the channel defining layer 10051/10052/10053 all form lateral SiGe grooves.
  • the first epitaxial layer 3001 is formed epitaxially after the lateral SiGe groove formed after etching and extending to the entire device except the outer surface of the substrate 1001 .
  • the first epitaxial layer 3001 may be SiGe, and the composition of Ge is about 10%-40%.
  • the epitaxial thickness of the first epitaxial layer 3001 needs to be controlled to be greater than half of the maximum thickness of the lower isolation layer 10021 and the upper isolation layer 10022 and less than half of the maximum thickness of the channel defining layer 10051/10052/10053.
  • the lateral SiG e grooves can still be formed inside the channel defining layer 10051/10052/10053, and the groove spaces of the lower isolation layer 10021 and the upper isolation layer 10022 are substantially filled by the first epitaxial layer 3001 Full.
  • Fig. 8 schematically shows a cross-sectional view along line AA'.
  • the first epitaxial layer 3001 is isotropically etched. Since the groove space of the lower isolation layer 10021 and the upper isolation layer 10022 is approximately filled by the first epitaxial layer 3001, the first epitaxial layer 3001 filled in the groove space can be retained during the isotropic etching process, FIG. 7 Other parts of the first epitaxial layer 3001 are etched away.
  • Fig. 9 schematically shows a cross-sectional view along line AA'.
  • a second SiO 2 layer 2012 is deposited in the lateral SiGe groove of the channel defining layer 10051/10052/10053 in FIG.
  • the outer sidewall of the second SiO 2 layer 2012 fills and occupies the lateral SiGe groove, and keeps the outer sidewall of the second SiO 2 layer 2012 aligned with the outer sidewall of the stack.
  • the material of the second SiO 2 layer 2012 is SiO 2 .
  • the etched part of each of the channel defining layers 10051 / 10052 / 10053 is filled with the second SiO 2 layer 2012 .
  • Fig. 10 schematically shows a cross-sectional view along line AA'.
  • the first epitaxial layer 3001 filled with the lower isolation layer 10021, the upper isolation layer 10022, and the groove space of the lower isolation layer 10021 and the upper isolation layer 10022 is etched, and the lower isolation layer 10021 and the upper isolation layer 10022
  • the second SiC layer 2002 is deposited on the corresponding position, and then the second SiC layer 2002 is etched back, so that the outer sidewall of the second SiC layer 2002 and the outer sidewall of the stack are aligned with each other.
  • the material of the second SiC layer 2002 is SiC.
  • the lower spacer layer 10021 and the upper spacer layer 10022 are replaced by the second SiC layer 2002 . Since the first SiC layer 2001 is formed between the left stack and the right stack in the middle of FIG.
  • the second SiC layer 2002 not only forms the interlayer isolation of different stacks, but also forms the interlayer isolation of different material layers within the same stack.
  • Fig. 11 schematically shows a cross-sectional view along line AA'.
  • the second SiO 2 layer 2012 is etched, and the first source/drain layer 10031/10032/10033 and the channel definition layer are etched in the vicinity of the second SiO 2 layer 2012 with the same predetermined thickness.
  • 10051/10052/10053 and the second source/drain layer 10071/10072/10073 epitaxially generate the second epitaxial layer 3002 on the etched position, and then anisotropically etch the second epitaxial layer 3002, so that the same MOS A "C"-shaped channel is formed between the first source/drain layer, the channel defining layer and the second epitaxial layer 3002 of the second source/drain layer.
  • the material of the second epitaxial layer 3002 may be Si.
  • the “C”-shaped channel is marked as the channel layer 200 .
  • Fig. 12 schematically shows a cross-sectional view along line AA'.
  • a third SiO2 layer 2013 is deposited on the outer grooves of the left and right stacks in the middle, and the deposition of the third SiO2 layer 2013 is controlled by CMP to stop at the hard mask layer 1009. of the upper surface. Then, the first SiC layer 2001 between the left stack and the right stack is etched downward, and the etching stops at the upper surface of the substrate 1001 .
  • the material of the third SiO 2 layer 2013 is SiO 2 , and the end point detection method can be used to determine the etching stop time.
  • Fig. 13 schematically shows a cross-sectional view along line AA'.
  • the channel defining layer 10051/10052/10053 is selectively etched, and a fourth SiO2 layer 2014 is deposited on the corresponding position of the channel defining layer 10051/10052/10053, and the fourth SiO2 layer 2014 is controlled by CMP.
  • Three SiO 2 layers 2013 are deposited to stop on the upper surface of the hard mask layer 1009 .
  • the fourth SiO 2 layer 2014 between the left stack and the right stack and the third SiO 2 layer 2013 formed outside the left stack and the right stack are etched downward, so that the fourth SiO 2 layer 2014 and The outer sidewall of the third SiO 2 layer 2013 is aligned with the outer sidewall of the stack.
  • the channel defining layers 10051/10052/10053 previously in different MOS layers are all replaced by the third SiO 2 layer 2013, the fourth SiO 2 layer 2014 and between the third SiO 2 layer 2013 and the fourth SiO 2 layer 2014
  • the intervening channel layer 200 is replaced.
  • Fig. 14 schematically shows a cross-sectional view along line AA'.
  • the fourth SiO 2 layer 2014 and the third SiO 2 layer 2013 are etched, and the gate dielectric layer 4001 and The p-type gate conductor layer 4002 forms a p-type gate stack.
  • the gate dielectric layer 4001 is filled into the recesses of the fourth SiO 2 layer 2014 and the third SiO 2 layer 2013 , and the p-type gate conductor layer 4002 fills the inner wall of the gate dielectric layer 4001 .
  • the gate dielectric layer 4001 can be made of a dielectric material with a high dielectric constant, such as HfO2, with a thickness of about 1 nm to 5 nm.
  • the p-type gate conductor layer 4002 can be deposited on the surface of the gate dielectric layer 4001 in a substantially conformal manner, so as to fill the inner wall of the gate dielectric layer 4001 .
  • the p-type gate conductor layer 4002 may include a p-type work function adjusting metal and a p-type gate conductive metal.
  • the p-type gate stack formed in this way (including the gate dielectric layer 4001 and the p-type gate conductor layer 4002) is respectively formed on the lateral periphery of the channel layer 200 where the PMOS layer, the first NMOS layer and the second NMOS layer are located.
  • the gate stack may be embedded between the first source/drain layer 10031/10032/10033 and the second source/drain layer 10071/10072/10073 and surround the lateral periphery of the channel layer 200 .
  • Fig. 15 schematically shows a cross-sectional view along line AA'.
  • the first spacer 301 deposit SiO 2 at the bottom of each stack, and then etch the SiO 2 and stop at a first predetermined height to form a first spacer 301 .
  • the first preset height is higher than the bottom of the second source/drain layer 10071 of the PMOS layer and lower than the top of the first source/drain layer 10032 of the first NMOS layer.
  • the first spacer 301 can isolate the p-type gate conductor layer 4002 where the PMOS layer is located, avoiding subsequent influences.
  • the p-type gate conductor layer 4002 at the corresponding position of the first NMOS layer and the second NMOS layer is etched, and the n-type gate conductor layer 4003 is deposited at the corresponding position of the p-type gate conductor layer 4002 to form an n-type gate stack.
  • the etching depth it is necessary to etch back the formed n-type gate conductor layer 4003 at last.
  • the n- type gate conductor layer 4003 can be deposited on the surface of the gate dielectric layer 4001 in a substantially conformal manner, so as to fill the inner wall of the gate dielectric layer 4001 .
  • the n-type gate conductor layer 4003 may include an n-type work function adjustment metal and an n-type gate conductive metal.
  • the n-type gate stack formed in this way (including the gate dielectric layer 4001 and the n-type gate conductor layer 4003) is respectively formed on the lateral periphery of the channel layer 200 where the first NMOS layer and the second NMOS layer are located, and the n-type gate stack can be It is embedded between the first source/drain layer 10032/10033 and the second source/drain layer 10072/10073, and surrounds the lateral periphery of the channel layer 200.
  • Fig. 16 schematically shows a cross-sectional view along line AA'.
  • the first spacer 301 is etched to form the structure of the smallest SRAM memory cell.
  • the SRAM storage unit may include: a substrate; a storage unit array on the substrate, including a plurality of storage units, wherein each storage unit includes: a left stack and a right stack arranged at intervals in the horizontal direction, the left Both the stacked layer and the right stacked layer include a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer, and a second NMOS layer stacked on the substrate in sequence, and the PMOS layer, the first NMOS layer, and the second NMOS layer are all Including vertically stacked first source/drain layer, channel layer and second source/drain layer, the channel layer is laterally recessed relative to the first source/drain layer and the second source/drain layer; gate stack, in It is between the first source/drain layer and the second source/drain layer in the vertical direction, and is arranged on opposite sides of the channel layer to embed the lateral recess of the channel layer.
  • the SRAM memory unit further includes: a hard mask layer disposed on the
  • Figure 17(a) schematically shows a top view of the photoresist patterned area.
  • Fig. 17(b) is a cross-sectional view along line AA' formed according to Fig. 17(a).
  • Fig. 17(c) is a cross-sectional view along line BB' formed according to Fig. 17(a).
  • the photoresist is spin-coated in the region where the PR is located, and the first source/drain layer 10031/10032/10033 and the second source/drain layer 10031/10032/10033 and the second source are partially etched in the horizontal direction in the region where the photoresist is not spin-coated.
  • /drain layer 10071/10072/10073 Preferably, the etching depths of the first source/drain layer 10031/10032/10033 and the second source/drain layer 10071/10072/10073 can be equal to the depth of the p-type gate conductor layer 4002 or the n-type gate conductor layer 4003 along the horizontal direction. Half.
  • the section along the line AA' is coated with photoresist PR and thus not etched.
  • the middle left layer stacked on the section along the BB' line is not spin-coated with photoresist, then the first source/drain layer 10031/10032/10033 and the second source/drain layer of this part 10071/10072/10073 are partially etched, and the etching depth is approximately half of the horizontal direction of the p-type gate conductor layer 4002 or n-type gate conductor layer 4003 .
  • Figure 18(a) schematically shows a top view of the photoresist patterned area.
  • Fig. 18(b) is a cross-sectional view along line AA' formed according to Fig. 18(a).
  • Fig. 18(c) is a cross-sectional view along line BB' formed according to Fig. 18(a).
  • Fig. 18(d) is a cross-sectional view along line CC' formed according to Fig. 18(a).
  • photoresist is spin-coated in the region where PR is located, and the p-type gate conductor layer 4002 and n-type gate conductor layer 4003 are partially etched horizontally in the region where the photoresist is not spin-coated.
  • the etching depths of the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 can be half of the horizontal direction of the p-type gate conductor layer 4002 or the n-type gate conductor layer 4003 .
  • PR region in Figure 18(a) is complementary to the PR region in Figure 17(a) in the best case, that is, the two regions have no common intersection and together constitute the device outline of the entire top view.
  • no photoresist is spin-coated on the section along the AA' line, and the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 of this section are partially etched, and the The etching depth is approximately half of the horizontal direction of the p-type gate conductor layer 4002 or the n-type gate conductor layer 4003 .
  • the middle left stack layer on the section along the BB' line is coated with photoresist and the right stack layer is not coated with photoresist, then the p-type gate conductor layer 4002 and the right stack layer in the figure are The n-type gate conductor layer 4003 is partially etched.
  • the middle left stack layer on this section is not covered by photoresist in the aforementioned Figure 17(a)
  • the drain layers 10071/10072/10073 are all partially etched in the aforementioned FIG. 17( a ).
  • the first source/drain layer 10031/10032/10033, the second source/drain layer 10071/10072/10073, the p-type gate conductor layer 4002 and the n-type gate conductor layer of the middle left stack in Fig. 18(d) 4003 is partially etched, and due to the unavoidable gap in the photolithography process, several gate metal nanowires protruding from the gate metal and source/drain layers can be seen.
  • Figure 19(a) schematically shows a top view of the photoresist patterned area.
  • Fig. 19(b) is a cross-sectional view along line AA' formed according to Fig. 19(a).
  • Fig. 19(c) is a cross-sectional view along line BB' formed according to Fig. 19(a).
  • Fig. 19(d) is a cross-sectional view along line CC' formed according to Fig. 19(a).
  • a third SiC layer 2003 is deposited on the exposed area of the substrate 1001 , and the deposition of the third SiC layer 2003 is controlled to stop on the upper surface of the hard mask layer 1009 by CMP. Then, the formed third SiC layer 2003 is etched downward, and the etching stops at the upper surface of the substrate 1001 .
  • the third SiC layer 2003 can be made of SiC material, and an end point detection method can be used to determine the etching stop time.
  • the recesses exposed by partial etching before each stack are filled with the third SiC layer 2003 to isolate the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 at different heights of the same stack.
  • the respective outer sidewalls of the layers in the stack may be vertically coplanar.
  • Figure 18(c) is in the first source/drain layer 10031/10032/10033 and the second source/drain layer 10071/10072/10073 of different MOS layers And the recesses of the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 are all filled by the third SiC layer 2003 .
  • Figure 18(d) is in the first source/drain layer 10031/10032/10033, the second source/drain layer 10071/ 10072/10073 and the recesses of the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 are all filled with the third SiC layer 2003 .
  • Fig. 20 schematically shows a cross-sectional view along line AA'.
  • a fifth SiO2 layer 2015 is deposited on the exposed area of the substrate 1001, and the deposition of the fifth SiO2 layer 2015 is controlled by CMP to stop at the hard mask layer 1009's upper surface. Therefore, the fifth SiO 2 layer 2015 can form a shallow trench isolation (Shallow Trench Isolation, STI) between the left stack and the right stack.
  • STI shallow Trench Isolation
  • Figure 21(a) schematically shows a top view of a photoresist patterned area.
  • Fig. 21(b) is a cross-sectional view along line AA' formed according to Fig. 21(a).
  • the horizontal wide stripes on the upper and lower sides of the AA' section are not covered by photoresist, and other parts are covered by photoresist.
  • the fifth SiO 2 layer 2015 is etched downward at the horizontal wide stripe, and the etching stops at the second preset height.
  • the second preset height is higher than the bottom of the first source/drain layer 10031 and lower than the top of the first source/drain layer 10031 .
  • Silicide can make the metal not react with the contacting SiO 2 material, so Silicide can be well aligned with the active area and the polysilicon gate.
  • a first metal layer 5001 is deposited on the etched fifth SiO 2 layer 2015 , and the deposition of the first metal layer 5001 is controlled to stop on the upper surface of the hard mask layer 1009 by CMP. Then, the first metal layer 5001 is etched downward, and the etching stops at a third preset height.
  • the third preset height is higher than the top of the first source/drain layer 10031 and lower than the bottom of the second source/drain layer 10071 . It can be seen from FIG. 1 that the first metal layer 5001 can be used to form the power line Vdd.
  • Fig. 22 schematically shows a cross-sectional view along line AA'.
  • a sixth SiO 2 layer 2016 and a second metal layer 5002 are sequentially formed on the first metal layer 5001 .
  • the etching of the sixth SiO 2 layer 2016 stops at the fourth preset height
  • the etching of the second metal layer 5002 stops at the fifth preset height .
  • the sixth SiO 2 layer 2016 is deposited on the first metal layer 5001, and the deposition of the sixth SiO 2 layer 2016 is controlled by CMP to stop on the upper surface of the hard mask layer 1009, so that the sixth SiO 2 layer 2016 An STI is formed between the left stack and the right stack. Then, the sixth SiO 2 layer 2016 is etched downward, and the etching stops at a fourth predetermined height, thereby realizing the formation of the sixth SiO 2 layer 2016 on the first metal layer 5001 .
  • a second metal layer 5002 is deposited on the sixth SiO 2 layer 2016 , and the deposition of the second metal layer 5002 is controlled to stop on the upper surface of the hard mask layer 1009 by CMP. Then, the second metal layer 5002 is etched downward, and the etching stops at the fourth preset height, thereby forming the second metal layer 5002 on the sixth SiO 2 layer 2016 .
  • the fourth preset height is higher than the top of the first source/drain layer 10032 and lower than the bottom of the second source/drain layer 10072 .
  • the sixth SiO 2 layer 2016 can form a shallow trench isolation between the left stack and the right stack.
  • the fifth predetermined height is higher than the bottom of the second source/drain layer 10072 and lower than the top of the second source/drain layer 10072 . It can be seen from FIG. 1 that the second metal layer 5002 can be used to form the ground line GND.
  • a seventh SiO 2 layer 2017 needs to be deposited on the second metal layer 5002 , and the deposition of the seventh SiO 2 layer 2017 is controlled to stop on the upper surface of the hard mask layer 1009 by CMP.
  • Figure 23(a) schematically shows a top view of a photoresist patterned area.
  • Fig. 23(b) is a sectional view along line BB' formed according to Fig. 23(a).
  • the small rectangular frames on the upper and lower sides of the BB' section are not covered by photoresist, and belong to the exposed area of the substrate 1001, and other parts are covered with photoresist. Engraving PR. Moreover, the exposed area of the substrate 1001 just exposes the area between the left stacked layer and the right stacked layer of a single smallest SRAM memory unit.
  • the seventh SiO 2 layer 2017 is etched downward in the rectangular frame areas on the upper and lower sides of the BB' section, the etching stops at the sixth preset height, and then the photoresist is removed.
  • the sixth predetermined height is higher than the top of the first source/drain layer 10031 and lower than the bottom of the second source/drain layer 10071 .
  • Fig. 24 schematically shows a cross-sectional view along line BB'.
  • a third metal layer 5003 is deposited on the seventh SiO 2 layer 2017 in the BB' section, and the deposition of the third metal layer 5003 is controlled to stop on the upper surface of the hard mask layer 1009 by CMP. Then, the third metal layer 5003 is etched downward, and the etching stops at the seventh preset height.
  • the seventh preset height is higher than the top of the first source/drain layer 10032 and lower than the bottom of the second source/drain layer 10072 . It can be seen from FIG. 1 that the third metal layer 5003 can be used to connect the input node IN1 of the first CMOS to the output node OUT2 of the second CMOS, and at the same time connect the input node IN2 of the second CMOS to the output node OUT1 of the first CMOS. .
  • Fig. 25 schematically shows a cross-sectional view along line BB'.
  • a fourth SiC layer 2004 is deposited on the third metal layer 5003 in the BB' section, and the deposition of the fourth SiC layer 2004 is controlled by CMP to stop on the upper surface of the hard mask layer 1009 . Then, etch the fourth SiC layer 2004 downwards and stop at the eighth preset height, continue to etch at the middle of the top of the fourth SiC layer 2004 and stop at the upper surface of the third metal layer 5003 to form left and right spaced and The second partition part in a stepped structure.
  • the eighth preset height is higher than the bottom of the first source/drain layer 10033 and lower than the top of the first source/drain layer 10033 .
  • the second spacer can isolate the n-type gate conductor layer 4003 of the first NMOS layer to avoid subsequent influences.
  • Fig. 26 schematically shows a cross-sectional view along line BB'.
  • a fourth metal layer 5004 is deposited on the inner sidewall, bottom surface, and upper surface of the second spacer in the BB' section, and the deposition of the fourth metal layer 5004 is controlled by CMP to stop at the hard mask layer 1009. of the upper surface. Then, etch down the fourth metal layer 5004 and stop at the ninth preset height.
  • the ninth preset height is higher than the bottom of the first source/drain layer 10033 and lower than the top of the first source/drain layer 10033 .
  • the fourth metal layer 5004 can be used to connect the input node IN1 of the first CMOS and the output node OUT2 of the second CMOS to the source of the transistor M6, and at the same time connect the input node IN2 of the second CMOS to the first
  • the CMOS output node OUT1 is connected to the source of the transistor M5.
  • Figure 27(a) schematically shows a top view of a photoresist patterned area.
  • Fig. 27(b) is a cross-sectional view along line BB' formed according to Fig. 27(a).
  • the photoresist is removed, and an eighth SiO 2 layer 2018 is deposited on all upper surfaces, so that the upper surfaces of all material layers are covered with the eighth SiO 2 layer 2018.
  • Figure 28(a) schematically shows a top view of a photoresist patterned area.
  • Fig. 28(b) is a cross-sectional view along line BB' formed according to Fig. 28( a ).
  • a photoresist (not shown in the figure) is spin-coated on the upper surface of the eighth SiO 2 layer 2018 to define the shape of the region of the word line WL.
  • the word line WL bridges the front end of the left stack and the rear end of the right stack on the same memory cell.
  • the eighth SiO 2 layer 2018 is etched downward, and the etching stops at the tenth preset height.
  • the tenth preset height is higher than the top of the first source/drain layer 10033 and lower than the bottom of the second source/drain layer 10073, so that the n-type gate conductor layer 4003 in the second NMOS layer is partially exposed.
  • a fifth metal layer 5005 is deposited on the outer sidewall of the n-type gate conductor layer 4003 in the second NMOS layer, and the deposition of the fifth metal layer 5005 is controlled to stop on the upper surface of the hard mask layer 1009 by CMP. Then, etch down the fifth metal layer 5005 and stop at the eleventh predetermined height.
  • the eleventh preset height is higher than the bottom of the second source/drain layer 10073 and lower than the top of the second source/drain layer 10073 .
  • the fifth metal layer 5005 adjacent to the outer sidewall of the n-type gate conductor layer 4003 is partially etched, so that the etched fifth metal layer 5005 is respectively opposite to the left stack and the right stack.
  • the outer wall is isolated.
  • the fifth metal layer 5005 can be used to define the word line WL, so that the word line WL straddles the front end surface of the left stacked layer and the rear end surface of the right stacked layer on the same memory cell, so as to contact and electrically connect to
  • the front end surface of the left stack or the rear end surface of the right stack is located on the outer sidewall of the n-type gate conductor layer 4003 of the second NMOS layer.
  • Fig. 29 schematically shows a cross-sectional view along line BB'.
  • metal contacts are formed on the second source/drain layers 10073 of the left stack and the right stack respectively. It can be seen from FIG. 1 that the metal contact portion can be used to form a bit line BL and a bit line with opposite signals to each other.
  • the metal contact portion includes: a first contact portion 6001 embedded in the second source/drain layer 10073 of the left stack, and a second contact portion 6001 embedded in the second source/drain layer 10073 of the right stack .
  • the first contact portion 6001 can be connected to the bit line BL, for example, and correspondingly, the second contact portion 6002 can be connected to the bit line
  • the metal contacts can be formed using conventional processes.
  • the metal contact portion can be formed by sequentially etching holes in the hard mask layer 1009 and the second source/drain layer 10073 and filling them with a conductive material such as metal.
  • the storage device of the embodiment of the present disclosure is prepared.
  • the storage device uses a 6T SRAM unit as the smallest storage unit, has fewer transistors, simplifies the storage and calculation structure of the computer, saves computing resources, and improves the computing power at the same time. Schedule and computational efficiency.
  • a memory device may be applied to various electronic devices.
  • an electronic device may include a memory device and a processor.
  • Storage devices can store data required for the operation of electronic equipment or obtained during operation.
  • the processor can operate based on data and/or applications stored in the memory device.
  • Such electronic devices include smart phones, computers, tablet computers (PCs), wearable smart devices, artificial intelligence devices, mobile power supplies, and the like.

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Abstract

一种存储器件及其制备方法，涉及半导体技术领域。该存储器件包括：衬底；衬底上的存储单元阵列，包括多个存储单元，其中，每个存储单元包括：水平方向间隔排布的左叠层和右叠层，左叠层和右叠层均包括依次叠置于衬底上的下隔离层、PMOS层、第一NMOS层、上隔离层和第二NMOS层，PMOS层、第一NMOS层和第二NMOS层均包括竖直叠置的第一源/漏层、沟道层和第二源/漏层，沟道层相对于第一源/漏层和第二源/漏层横向凹入；栅堆叠，在竖直方向上介于第一源/漏层与第二源/漏层之间，且设于沟道层的相对两侧以嵌入沟道层的横向凹入。

Description

存储器件及其制备方法 技术领域
本公开涉及半导体领域，具体涉及一种存储器件及其制备方法。
背景技术
随着半导体器件的不断小型化，越来越难以制造高密度的互连结构，因为在横向上难以缩减尺寸。另外，为了增加集成度，可以堆叠多层器件。基于此，期望能够以灵活的方式为这种堆叠器件设置互连。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种能够减小待机漏电且无需提高器件阈值电压的存储器件及其制备方法。
根据本公开的一个方面，提供了一种存储器件，包括：衬底；衬底上的存储单元阵列，包括多个存储单元，其中，每个存储单元包括：水平方向间隔排布的左叠层和右叠层，左叠层和右叠层均包括依次叠置于衬底上的下隔离层、PMOS层、第一NMOS层、上隔离层和第二NMOS层，PMOS层、第一NMOS层和第二NMOS层均包括竖直叠置的第一源/漏层、沟道层和第二源/漏层，沟道层相对于第一源/漏层和第二源/漏层横向凹入；栅堆叠，在竖直方向上介于第一源/漏层与第二源/漏层之间，且设于沟道层的相对两侧以嵌入沟道层的横向凹入。
根据本公开的另一方面，提供了一种存储器件的制备方法，包括：在衬底上形成水平方向间隔排布的左叠层和右叠层，左叠层和右叠层均包括依次叠置的下隔离层、PMOS层、第一NMOS层、上隔离层和第二NMOS层，PMOS层、第一NMOS层和第二NMOS层均包括竖直叠置的第一源/漏层、沟道层和第二源/漏层，沟道层相对于第一源/漏层和第二源/漏层横向凹入；在沟道层的横向凹入依次淀积栅介质层和p型栅导 体层；在左叠层和右叠层的底部淀积SiO 2，然后刻蚀该SiO 2并停止于第一预设高度，形成第一间隔部；刻蚀第一NMOS层与第二NMOS层对应位置上的p型栅导体层，在刻蚀掉的p型栅导体层的对应位置上淀积n型栅导体层；刻蚀第一间隔部，形成存储单元，存储器件包括多个存储单元的存储单元阵列。
根据本公开的另一方面，提供了一种电子设备，包括上述存储器件。
与现有技术相比，本公开提供的存储器件及其制备方法，至少具有以下有益效果：该存储器件以6T SRAM单元作为最小的存储单元，具有更少的晶体管数量，简化了计算机的存算结构，节省了计算资源，同时提高了计算进度和计算效率。
另外，对于半导体器件的竖直叠层，可以设置与之横向上邻接的侧壁互连结构。对于若干层器件，可以利用一个掩模层，因此可以减少制造工艺中的光刻步骤并降低制造成本。另外，三维构造使得器件之间的互连可以由更多空间，并因此可以具有低电阻和高带宽。由于侧壁互连结构的存在，半导体装置可以具有引出端子，因此可以将半导体装置的制造与金属化叠层的制造相分离。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1示意性示出了6T SRAM单元的电路原理图；
图2至29示意性示出了根据本公开实施例的存储器件的制备方法依次处于不同阶段的截面图，在这些附图中：
图2示意性示出了在衬底上形成叠层的截面图；
图3(a)示意性示出了光刻胶构图区域的俯视图；图3(b)为根据图3(a)形成的沿AA′线的截面图；
图4(a)示意性示出了光刻胶构图区域的俯视图；图4(b)为根据图4(a)形成的沿AA′线的截面图；
图5(a)示意性示出了光刻胶构图区域的俯视图；图5(b)为根据图5(a)形成的沿11′线的截面图；
图6(a)示意性示出了光刻胶构图区域的俯视图；图6(b)为根据图6(a)形成的沿11′线的截面图；图6(c)为根据图6(a)形成的沿AA′线的截面图；
图7示意性示出了沿AA′线的截面图；
图8示意性示出了沿AA′线的截面图；
图9示意性示出了沿AA′线的截面图；
图10示意性示出了沿AA′线的截面图；
图11示意性示出了沿AA′线的截面图；
图12示意性示出了沿AA′线的截面图；
图13示意性示出了沿AA′线的截面图；
图14示意性示出了沿AA′线的截面图；
图15示意性示出了沿AA′线的截面图；
图16示意性示出了沿AA′线的截面图；
图17(a)示意性示出了光刻胶构图区域的俯视图；图17(b)为根据图17(a)形成的沿AA′线的截面图；图17(c)为根据图17(a)形成的沿BB′线的截面图；
图18(a)示意性示出了光刻胶构图区域的俯视图；图18(b)为根据图18(a)形成的沿AA′线的截面图；图18(c)为根据图18(a)形成的沿BB′线的截面图；图18(d)为根据图18(a)形成的沿CC′线的截面图；
图19(a)示意性示出了光刻胶构图区域的俯视图；图19(b)为根据图19(a)形成的沿AA′线的截面图；图19(c)为根据图19(a)形成的沿BB′线的截面图；图19(d)为根据图19(a)形成的沿CC′线的截面图；
图20示意性示出了沿AA′线的截面图；
图21(a)示意性示出了光刻胶构图区域的俯视图；图21(b)为根据图21(a)形成的沿AA′线的截面图；
图22示意性示出了沿AA′线的截面图；
图23(a)示意性示出了光刻胶构图区域的俯视图；图23(b)为根据图23(a)形成的沿BB′线的截面图；
图24示意性示出了沿BB′线的截面图；
图25示意性示出了沿BB′线的截面图；
图26示意性示出了沿BB′线的截面图；
图27(a)示意性示出了光刻胶构图区域的俯视图；图27(b)为根据图27(a)形成的沿BB′线的截面图；
图28(a)示意性示出了光刻胶构图区域的俯视图；图28(b)为根据图28(a)形成的沿BB′线的截面图；
图29示意性示出了沿BB′线的截面图。
附图标记说明：
1001-衬底；10021-下隔离层；10022-上隔离层；
10031/10032/10033-第一源/漏层；10051/10052/10053-沟道限定层；
10071/10072/10073-第二源/漏层；1009-硬掩膜层；
2001-第一SiC层；2002-第二SiC层；2003-第三SiC层；
2004-第四SiC层；2011-第一SiO 2层；2012-第二SiO 2层；
2013-第三SiO 2层；2014-第四SiO 2层；2015-第五SiO 2层；
2016-第六SiO 2层；2017-第七SiO 2层；2018-第八SiO 2层；
3001-第一外延层；3002-第二外延层；4001-栅介质层；
4002-p型栅导体层；4003-n型栅导体层；200-沟道层；
301-第一间隔部；302-第二间隔部；5001-第一金属层；
5002-第二金属层；5003-第三金属层；5004-第四金属层；
5005-第五金属层；6001-第一接触部；6002-第二接触部。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。附图并非一定是按比例绘制的，特别是为清楚起见，截面图的绘制比例不同于俯视图的绘制比例。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中， 省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1示意性示出了6T SRAM单元的电路原理图。
如图1所示，该6T SRAM单元包括晶体管M1～M6，图中的G表示晶体管的栅极，S表示晶体管的源极，D表示晶体管的漏极。其中，晶体管M2的源极和晶体管M4的源极均与电源Vdd连接，晶体管M1的源极和晶体管M3的源极均接地GND，晶体管M1的漏极与晶体管M2的漏极连接，晶体管M3的漏极与晶体管M4的漏极连接；晶体管M1的栅极、晶体管M2的栅极和晶体管M3的漏极连接，晶体管M3的栅极、晶体管M4的栅极和晶体管M1的漏极连接。
晶体管M5的栅极和晶体管M6的栅极均与字线WL(W ord Lin e)连接，晶体管M5的漏极与位线
Figure PCTCN2021137861-appb-000001
连接，晶体管M6的漏极与位线BL (Bit Line)连接，位线BL和位线
Figure PCTCN2021137861-appb-000002
是互为相反的信号，晶体管M5的源极与晶体管M1的漏极连接，晶体管M6的源极与晶体管M3的漏极连接。
由此，该6T SRAM单元作为最小单元，其中，晶体管M1和M3为NMOS(N-Metal-Oxide-Semiconductor，N型金属氧化物半导体场效应)晶体管，晶体管M2和M4为PMOS(positive channel Metal Oxide Semiconductor，p型金属氧化物半导体场效应)晶体管，晶体管M5和M6为传输门NMOS晶体管。晶体管M1和M2构成第一CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)，晶体管M3和M4构成第二CMOS。
为便于内外交换数据，晶体管M1和M2的漏极连在仪器上构成第一CMOS的输出节点OUT1，晶体管M3和M4的漏极连在仪器上构成第二CMOS的输出节点OUT2。晶体管M1和M2的栅极连接在一起构成第一CMOS的输入节点IN1，晶体管M3与M4的栅极连接在一起构成第二CMOS的输入节点IN2。
以上对6T SRAM单元进行了详细的描述，本公开实施例在以下提供的存储器件，以该6T SRAM单元作为最小的存储单元，具有更少的晶体管数量，简化了计算机的存算结构，节省了计算资源，同时提高了计算进度和计算效率。
本公开实施例提供的存储器件，包括：衬底；衬底上的存储单元阵列，包括多个存储单元，其中，每个存储单元包括：水平方向间隔排布的左叠层和右叠层，左叠层和右叠层均包括依次叠置于衬底上的下隔离层、PMOS层、第一NMOS层、上隔离层和第二NMOS层，PMOS层、第一NMOS层和第二NMOS层均包括竖直叠置的第一源/漏层、沟道层和第二源/漏层，沟道层相对于第一源/漏层和第二源/漏层横向凹入；栅堆叠，在竖直方向上介于第一源/漏层与第二源/漏层之间，且设于沟道层的相对两侧以嵌入沟道层的横向凹入。
根据本公开的实施例，该存储器件还包括：硬掩膜层，设置于第二NMOS层的第一源/漏层上。
根据本公开的实施例，栅堆叠包括栅介质层和栅导体层，栅介质层包括功函数调节金属和设置于功函数调节金属上的栅导电金属。
根据本公开的实施例，栅导体层包括p型栅导体层和n型栅导体层，其中：p型栅导体层设置于PMOS层的第一源/漏层与第二源/漏层之间；n型栅导体层设置于第一NMOS层的第一源/漏层与第二源/漏层之间，以及第二NMOS层的第一源/漏层与第二源/漏层之间。
根据本公开的实施例，第一源/漏层和第二源/漏层的横向外周部分凹入且凹入的部分填充有第三SiC层；和/或栅导体层的横向外周部分凹入且凹入的部分填充有第三SiC层。
根据本公开的实施例，第三SiC层的外侧壁与左叠层和右叠层在竖直方向上共面。
根据本公开的实施例，该存储器件还包括：第五SiO 2层，形成于左叠层与右叠层之间的衬底上，第五SiO 2层的顶部高于PMOS层的第一源/漏层的底部且低于PMOS层的第一源/漏层的顶部。
根据本公开的实施例，该存储器件还包括：第一金属层，形成于在左叠层和右叠层的纵向中部位置的第五SiO 2层上，第一金属层的顶部高于PMOS层的第一源/漏层的顶部且低于PMOS层的第二源/漏层的底部。
根据本公开的实施例，该存储器件还包括：依次形成于第一金属层上的第六SiO 2层和第二金属层，第六SiO 2层的顶部高于第一NMOS层的第一源/漏层的顶部且低于第一NMOS层的第二源/漏层的底部；第二金属层的顶部高于第一NMOS层的第二源/漏层的底部且低于第一NMOS层的第二源/漏层的顶部。
根据本公开的实施例，该存储器件还包括：第七SiO 2层，形成于除纵向中部位置之外的第五SiO 2层上，第七SiO 2层的顶部高于PMOS层的第一源/漏层的顶部且低于PMOS层的第二源/漏层的底部。
根据本公开的实施例，该存储器件还包括：第三金属层，形成于第七SiO 2层上，第三金属层的顶部高于第一NMOS层的第一源/漏层的顶部且低于第一NMOS层的第二源/漏层的底部。
根据本公开的实施例，该存储器件还包括：第八SiO 2层，形成于第 三金属层上，第八SiO 2层的顶部高于第二NMOS层的第一源/漏层的底部且低于第二NMOS层的第一源/漏层的顶部；第八SiO 2层的顶部中间位置相对凹陷并露出第三金属层，形成左右隔开且呈台阶结构的第二间隔部。
根据本公开的实施例，第二间隔部的内侧壁和底面形成有高于第八SiO 2层顶部的第四金属层；第四金属层的顶部高于第二NMOS层的第一源/漏层的底部且低于第二NMOS层的第一源/漏层的顶部。
根据本公开的实施例，该存储器件还包括：第五金属层，形成于左叠层与右叠层的其中之一，且接触处于第二NMOS层的 n型栅导体层的外侧壁；字线，连接于第五金属层，字线跨接同一存储单元上不同纵向位置的左叠层与右叠层之间，以接触并电连接到左叠层或右叠层处于第二NMOS层的n型栅导体层的外侧壁。
根据本公开的实施例，该存储器件还包括：第一接触部和第二接触部，第一接触部嵌入于左叠层的第二NMOS层的第二源/漏层，第二接触部嵌入于右叠层的第二NMOS层的第二源/漏层，第一接触部和第二接触部分别连接互为相反信号的第一位线和第二位线。
需要说明的是，装置部分的实施例方式与方法部分的实施例方式对应类似，并且所达到的技术效果也对应类似，具体细节请参照一下方法部分的实施例方式，在此不再赘述。
本公开实施例还提供了一种存储器件的制备方法，包括：
步骤S1，在衬底上形成水平方向间隔排布的左叠层和右叠层，所述左叠层和右叠层均包括依次叠置的下隔离层、PMOS层、第一NMOS层、上隔离层和第二NMOS层，所述PMOS层、第一NMOS层和第二NMOS层均包括竖直叠置的第一源/漏层、沟道层和第二源/漏层，所述沟道层相对于第一源/漏层和第二源/漏层横向凹入；
步骤S2，在所述沟道层的横向凹入依次淀积栅介质层和p型栅导体层；
步骤S3，在左叠层和右叠层的底部淀积SiO 2，然后刻蚀该SiO2并停止于第一预设高度，形成第一间隔部；
步骤S4，刻蚀第一NMOS层与第二NMOS层对应位置上的p型栅导体层，在刻蚀掉的p型栅导体层的对应位置上淀积n型栅导体层；
步骤S5，刻蚀所述第一间隔部，形成存储单元，所述存储器件包括多个所述存储单元的存储单元阵列。
以下通过图2～图29对本公开实施例的存储器件的制备方法进行详细描述。图2至29示意性示出了根据本公开实施例的存储器件的制备方法处于不同阶段的流程图。
图2示意性示出了在衬底上形成叠层的截面图。如图2所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在此，提供硅晶片作为衬底1001。
在衬底1001中，可以形成阱区。如果要形成p型器件，则阱区可以是n型阱；如果要形成n型器件，则阱区可以是p型阱。因此，例如可以通过在衬底1001中注入p型掺杂剂如硼(B)，且随后进行热退火来形成p型阱。
在衬底1001上，可以通过外延生长，形成依次叠置于衬底上的PMOS层、第一NMOS层和第二NMOS层。PMOS层为p型器件，第一NMOS层和第二NMOS层均为n型器件。本领域技术人员知晓，半导体材料的掺杂可以通过外延生长时原位掺杂来实现，或者可以通过其他掺杂方式如离子注入来实现。通过适当调整掺杂的导电类型，可以形成p型器件或n型器件。
其中，PMOS层包括依次竖直叠置的第一源/漏层10031、沟道限定层10051和第二源/漏层10071。类似地，第一NMOS层包括依次竖直叠置的第一源/漏层10032、沟道限定层10052和第二源/漏层10072。第二NMOS层包括依次竖直叠置的第一源/漏层10033、沟道限定层10053和第二源/漏层10073。第一源/漏层10031/10032/10033的厚度例如为约20nm～50nm，沟道限定层10051/10052/10053的厚度例如为约15nm～100nm，第二源/漏层10071/10072/10073的厚度例如为约 20nm～50nm。
为区分不同MOS层，在衬底1001与PMOS层的第一源/漏层10031之间设置下隔离层10021，在第一NMOS层的第二源/漏层10072与第二NMOS层的第一源/漏层10033之间设置上隔离层10022。
上述衬底1001上相邻的层相对于彼此可以具有刻蚀选择性。例如，第一源/漏层10031/10032/10033可以包括Si；沟道限定层10051/10052/10053可以是SiGe，Ge的组分为约10％～20％；第二源/漏层10071/10072/10073可以是Si。上隔离层10022和下隔离层10021均可以是SiGe，厚度约为10nm～20nm，Ge的组分为约10％～20％。
另外，在第二NMOS层的第二源/漏层10073上，还淀积有硬掩膜层1009，以方便构图。硬掩膜层1009可以包括氮化物，例如SiN，厚度约为50nm～200nm。
图3(a)示意性示出了光刻胶构图区域的俯视图。图3(b)为根据图3(a)形成的沿AA′线的截面图。
接着，如图3(a)和3(b)所示，在硬掩膜层1009上旋涂光刻胶，通过曝光、显影等过程将光刻胶构图为图3(a)定义的光刻器件区域形状，并以构图后的光刻胶为掩模，沿竖直方向依次刻蚀硬掩膜层1009直至衬底1001上表面，然后再去除光刻胶。
需要说明的是，图3(b)的A-A截面图仅仅截取了图3(a)中的加粗双点划线外矩形框区域中的A-A截面，后续的AA′截面、11′截面、BB′截面和CC′截面均为相应的俯视图中对应该加粗双点划线外矩形框区域截取出的截面。后续的俯视图显示区域明显大于该截面截取区域，仅仅是为了显示俯视图上多个最小SRAM存储单元互连形成的存储阵列的整体形状。图4(a)中的PR(Photoresist，光刻胶)区域表示旋涂光刻胶的区域，未被刻蚀掉而保留原有叠层结构；深色区域表示无光刻胶的区域，也即经过刻蚀后俯视图中露出衬底1001的区域。
于是，如图3(b)的所示，在沿AA′线的截面上的单个SRAM存储单元上，刻蚀后形成水平方向间隔排布的左叠层和右叠层，每个叠层在衬底1001上的截面形成为矩形的柱状。由此，叠层中的各层相应侧壁可 以在竖直方向上共面。
另外，仅仅为了说明最小SRAM存储单元的具体结构，图3(b)中部的左叠层和右叠层之间留有的间距明显大于图3(a)中沿水平方向的相邻两矩形光刻胶的间距。
图4(a)示意性示出了光刻胶构图区域的俯视图。图4(b)为根据图4(a)形成的沿AA′线的截面图。
接着，如图4(a)所示，在上下两条横向条纹以及水平方向多条纵向条纹所在区域淀积第一SiC层2001，通过化学机械抛光(Chemical Mechanical Polishing，CMP)控制该第一SiC层2001淀积停止于硬掩膜层1009的上表面。然后，除了上下两条横向条纹保留外，其他部位均旋涂光刻胶，由上至下刻蚀掉上下两条横向条纹上淀积的第一SiC层2001，刻蚀停止于衬底1001的上表面。第一SiC层2001的材料为SiC。
于是，上下两条横向条纹露出衬底1001，其他部分之前衬底1001的露出区域均填充有第一SiC层2001。
如图4(b)所示，在AA′截面上且处于刻蚀之前，位于叠层结构顶层的硬掩膜层1009与第一SiC层2001沿水平方向依次交错排列，硬掩膜层1009与第一SiC层2001上表面均涂有光刻胶。
图5(a)示意性示出了光刻胶构图区域的俯视图。图5(b)为根据图5(a)形成的沿11′线的截面图。
接着，如图5(a)和4(b)所示，去除图4(b)的光刻胶，沿垂直于上下两条横向条纹处的方向，也即竖直方向，部分刻蚀下隔离层10021、上隔离层10022以及沟道限定层10051/10052/10053的相应侧壁，于是在下隔离层10021、上隔离层10022以及沟道限定层10051/10052/10053均形成如图5(b)所示的横向SiGe凹槽。由于下隔离层10021、上隔离层10022以及沟道限定层10051/10052/10053均可以是SiGe，方便统一刻蚀。
然后，在该横向SiGe凹槽淀积第一SiO 2层2011，可以通过反应离子刻蚀(Reactive Ion Etching，RIE)该第一SiO 2层2011，使第一SiO 2层2011填充并占据该横向SiGe凹槽，并保持第一SiO 2层2011外侧壁 与叠层外侧壁相互齐整。第一SiO 2层2011的材料为SiO 2。
于是，下隔离层10021、上隔离层10022以及沟道限定层10051/10052/10053各自被刻蚀掉一部分，而保留另一部分，其中，刻蚀掉的一部分形成横向SiGe凹槽，然后被第一SiO 2层2011替代。
图6(a)示意性示出了光刻胶构图区域的俯视图。图6(b)为根据图6(a)形成的沿11′线的截面图。图6(c)为根据图6(a)形成的沿AA′线的截面图。
接着，如图6(a)所示，在上下两条横向条纹处所在的衬底1001露出区域淀积第一SiC层2001，通过CMP控制该第一SiC层2001淀积停止于硬掩膜层1009的上表面。然后，在图6(a)中的纵向窄条纹处向下刻蚀已形成的第一SiC层2001，刻蚀停止于衬底1001的上表面。可以利用终点检测方法判断刻蚀停止时刻。
于是，如图6(b)所示，沿11′线的截面上且处于刻蚀之前，两条横向条纹处所在的衬底1001上淀积有高度至硬掩膜层1009的第一SiC层2001，硬掩膜层1009与第一SiC层2001上表面均涂有光刻胶。
如图6(c)所示，沿AA′线的截面上，左叠层与右叠层之间淀积有高度至硬掩膜层1009的第一SiC层2001，左叠层和右叠层的外侧在之前形成有第一SiC层2001的位置被刻蚀掉，形成直至衬底1001的凹槽。
图7示意性示出了沿AA′线的截面图。
接着，如图7所示，去除光刻胶，然后在沿AA′线的截面上部分刻蚀下隔离层10021、上隔离层10022以及沟道限定层10051/10052/10053，于是在下隔离层10021、上隔离层10022以及沟道限定层10051/10052/10053均形成横向SiGe凹槽。
在刻蚀后形成的横向SiGe凹槽以及延伸至整个器件除了衬底1001的外表面上，外延生成第一外延层3001。其中，第一外延层3001可以为SiGe，Ge的组分为约10％～40％。
需要说明的是，由于下隔离层10021和上隔离层10022厚度相对较小，第一外延层3001的外延厚度需要控制在大于下隔离层10021和上隔离层10022的最大厚度的二分之一且小于沟道限定层10051/10052/10053的最大厚度的二分之一。由此，可以在外延过程之后， 保持沟道限定层10051/10052/10053内部仍形成横向SiG e凹槽，而下隔离层10021和上隔离层10022的凹槽空间被第一外延层3001大致填满。
图8示意性示出了沿AA′线的截面图。
接着，如图8所示，各向同性刻蚀第一外延层3001。由于下隔离层10021和上隔离层10022的凹槽空间被第一外延层3001大致填满，在各向同性刻蚀过程中可以保留该凹槽空间内部填满的第一外延层3001，图7的其他部分的第一外延层3001均被刻蚀掉。
图9示意性示出了沿AA′线的截面图。
接着，如图9所示，在图8的沟道限定层10051/10052/10053的横向SiGe凹槽内淀积第二SiO 2层2012，然后各向异性刻蚀该第二SiO 2层2012的外侧壁，使第二SiO 2层2012填充并占据该横向SiGe凹槽，并保持第二SiO 2层2012外侧壁与叠层的外侧壁相互齐整。第二SiO 2层2012的材料为SiO 2。
于是，沟道限定层10051/10052/10053各自被刻蚀掉的一部分被第二SiO 2层2012填满。
图10示意性示出了沿AA′线的截面图。
接着，如图10所示，刻蚀下隔离层10021、上隔离层10022以及下隔离层10021、上隔离层10022的凹槽空间填充的第一外延层3001，在下隔离层10021和上隔离层10022的对应位置上淀积第二SiC层2002，然后回刻第二SiC层2002，使第二SiC层2002外侧壁与叠层的外侧壁相互齐整。第二SiC层2002的材料为SiC。
由此，下隔离层10021和上隔离层10022被第二SiC层2002替代。由于图10中部的左叠层与右叠层之间之前形成有第一SiC层2001，左叠层与右叠层内部的第二SiC层2002可以连通属于同一材料的第一SiC层2001，因此第二SiC层2002不仅形成不同叠层的层间隔离，也形成同一叠层内部不同材料层的层间隔离。
图11示意性示出了沿AA′线的截面图。
接着，如图11所示，刻蚀第二SiO 2层2012，在第二SiO 2层2012的附近位置按照同一预设厚度刻蚀第一源/漏层10031/10032/10033、沟 道限定层10051/10052/10053以及第二源/漏层10071/10072/10073，在刻蚀掉的位置上外延生成第二外延层3002，然后各向异性刻蚀该第二外延层3002，使得处于同一MOS层的相邻第一源/漏层、沟道限定层和第二源/漏层的第二外延层3002之间形成“C”字形沟道。其中，第二外延层3002的材料可以为Si。为了便于说明，标记该“C”字形沟道为沟道层200。
图12示意性示出了沿AA′线的截面图。
接着，如图12所示，在中部的左叠层和右叠层的外侧凹槽淀积第三SiO 2层2013，通过CMP控制该第三SiO 2层2013淀积停止于硬掩膜层1009的上表面。然后，向下刻蚀左叠层与右叠层之间的第一SiC层2001，刻蚀停止于衬底1001的上表面。
其中，第三SiO 2层2013的材料为SiO 2，可以利用终点检测方法判断刻蚀停止时刻。
图13示意性示出了沿AA′线的截面图。
接着，如图13所示，选择性刻蚀沟道限定层10051/10052/10053，在沟道限定层10051/10052/10053的对应位置上淀积第四SiO 2层2014，通过CMP控制该第三SiO 2层2013淀积停止于硬掩膜层1009的上表面。然后，向下刻蚀左叠层与右叠层之间的第四SiO 2层2014以及左叠层和右叠层的外侧已形成的第三SiO 2层2013，使第四SiO 2层2014和第三SiO 2层2013的外侧壁与叠层的外侧壁相互齐整。
由此，之前处于不同MOS层的沟道限定层10051/10052/10053均被第三SiO 2层2013、第四SiO 2层2014以及设置于第三SiO 2层2013与第四SiO 2层2014之间的沟道层200所取代。
图14示意性示出了沿AA′线的截面图。
接着，如图14所示，刻蚀第四SiO 2层2014和第三SiO 2层2013，在第四SiO 2层2014和第三SiO 2层2013的对应位置上依次淀积栅介质层4001和p型栅导体层4002，形成p型栅堆叠。由此，栅介质层4001填充到第四SiO 2层2014和第三SiO 2层2013的凹入部中，p型栅导体层4002充满栅介质层4001的内壁。为控制刻蚀深度，最后还需对形成的 p型栅导体层4002进行回刻。
其中，栅介质层4001可以选用具有高介电常数的介电材料，例如HfO2，厚度为约1nm～5nm。p型栅导体层4002可以大致共形的方式淀积形成于栅介质层4001表面，从而充满栅介质层4001的内壁。p型栅导体层4002可以包括p型功函数调节金属和p型栅导电金属。
如此形成的p型栅堆叠(包括栅介质层4001和p型栅导体层4002)分别形成于PMOS层、第一NMOS层和第二NMOS层所处的沟道层200的横向外周，该p型栅堆叠可以嵌入到第一源/漏层10031/10032/10033与第二源/漏层10071/10072/10073之间，并围绕沟道层200的横向外周。
图15示意性示出了沿AA′线的截面图。
接着，如图15所示，在每个叠层底部淀积SiO 2，然后刻蚀该SiO 2并停止于第一预设高度，形成第一间隔部301。具体地，该第一预设高度高于PMOS层的第二源/漏层10071的底部，且低于第一NMOS层的第一源/漏层10032的顶部。由此，第一间隔部301可以将PMOS层所处的p型栅导体层4002隔离开，避免后续影响。
然后，刻蚀第一NMOS层与第二NMOS层对应位置上的p型栅导体层4002，在p型栅导体层4002对应位置上淀积n型栅导体层4003，形成n型栅堆叠。为控制刻蚀深度，最后还需对形成的n型栅导体层4003进行回刻。
于是，在第一NMOS层与第二NMOS层上， n型栅导体层4003可以大致共形的方式淀积形成于栅介质层4001表面，从而充满栅介质层4001的内壁。n型栅导体层4003可以包括n型功函数调节金属和n型栅导电金属。
如此形成的n型栅堆叠(包括栅介质层4001和n型栅导体层4003)分别形成于第一NMOS层与第二NMOS层所处的沟道层200的横向外周，该n型栅堆叠可以嵌入到第一源/漏层10032/10033与第二源/漏层10072/10073之间，并围绕沟道层200的横向外周。
图16示意性示出了沿AA′线的截面图。
接着，如图16所示，刻蚀第一间隔部301，形成最小的SRAM存 储单元的结构。
具体地，该SRAM存储单元可以包括：衬底；衬底上的存储单元阵列，包括多个存储单元，其中，每个存储单元包括：水平方向间隔排布的左叠层和右叠层，左叠层和右叠层均包括依次叠置于衬底上的下隔离层、PMOS层、第一NMOS层、上隔离层和第二NMOS层，PMOS层、第一NMOS层和第二NMOS层均包括竖直叠置的第一源/漏层、沟道层和第二源/漏层，沟道层相对于第一源/漏层和第二源/漏层横向凹入；栅堆叠，在竖直方向上介于第一源/漏层与第二源/漏层之间，且设于沟道层的相对两侧以嵌入沟道层的横向凹入。同时，SRAM存储单元还包括：硬掩膜层，设置于第二NMOS层的第一源/漏层上。
图17(a)示意性示出了光刻胶构图区域的俯视图。图17(b)为根据图17(a)形成的沿AA′线的截面图。图17(c)为根据图17(a)形成的沿BB′线的截面图。
接着，如图17(a)所示，在PR所在区域旋涂光刻胶，未旋涂光刻胶的区域沿水平方向部分刻蚀第一源/漏层10031/10032/10033和第二源/漏层10071/10072/10073。优选地，第一源/漏层10031/10032/10033和第二源/漏层10071/10072/10073的刻蚀深度均可以为p型栅导体层4002或n型栅导体层4003沿水平方向的二分之一。
于是，如图17(b)所示，沿AA′线的截面上涂有光刻胶PR，因此未被刻蚀。如图17(c)所示，沿BB′线的截面上的中部左叠层未旋涂光刻胶，则该部分的第一源/漏层10031/10032/10033和第二源/漏层10071/10072/10073均被部分刻蚀，刻蚀深度近似为p型栅导体层4002或n型栅导体层4003沿水平方向的二分之一。
图18(a)示意性示出了光刻胶构图区域的俯视图。图18(b)为根据图18(a)形成的沿AA′线的截面图。图18(c)为根据图18(a)形成的沿BB′线的截面图。图18(d)为根据图18(a)形成的沿CC′线的截面图。
接着，如图18(a)所示，在PR所在区域旋涂光刻胶，未旋涂光刻胶的区域沿水平方向部分刻蚀p型栅导体层4002和n型栅导体层4003。优选地，p型栅导体层4002和n型栅导体层4003的刻蚀深度均可以为 p型栅导体层4002或n型栅导体层4003沿水平方向的二分之一。
需要说明的是，图18(a)中的PR所在区域在最佳情况下与图17(a)中的PR所在区域互补，也即两区域无共同交集且共同构成整个俯视图的器件外轮廓。
于是，如图18(b)所示，沿AA′线的截面上均未旋涂光刻胶，则该截面的p型栅导体层4002和n型栅导体层4003均被部分刻蚀，刻蚀深度近似为p型栅导体层4002或n型栅导体层4003沿水平方向的二分之一。
如图18(c)所示，沿BB′线的截面上的中部左叠层涂有光刻胶而右叠层未涂光刻胶，则图中的右叠层上的p型栅导体层4002和n型栅导体层4003被部分刻蚀。另外，由于该截面上的中部左叠层在前述图17(a)中未被光刻胶覆盖，该图中的左叠层上的第一源/漏层10031/10032/10033和第二源/漏层10071/10072/10073均在前述图17(a)被部分刻蚀。
如图18(d)所示，沿CC′线的截面均未涂光刻胶，则所有叠层结构上的p型栅导体层4002和n型栅导体层4003均被部分刻蚀。还需要说明的是，由于该沿CC′线的截面的中部左叠层在前述图17(a)中也暴露于外，也即未被光刻胶覆盖，则该截面上的中部左叠层的第一源/漏层10031/10032/10033和第二源/漏层10071/10072/10073也均被部分刻蚀。因此，图18(d)中的中部左叠层的第一源/漏层10031/10032/10033、第二源/漏层10071/10072/10073以及p型栅导体层4002和n型栅导体层4003均被部分刻蚀，由于光刻工艺的间隙无法避免，导致栅极金属和源/漏层可以看到外伸出的若干条栅极金属纳米线。
图19(a)示意性示出了光刻胶构图区域的俯视图。图19(b)为根据图19(a)形成的沿AA′线的截面图。图19(c)为根据图19(a)形成的沿BB′线的截面图。图19(d)为根据图19(a)形成的沿CC′线的截面图。
接着，如图19(a)所示，在衬底1001的露出区域淀积第三SiC层2003，通过CMP控制该第三SiC层2003淀积停止于硬掩膜层1009的上表面。然后，向下刻蚀已形成的第三SiC层2003，刻蚀停止于衬底1001的上表面。第三SiC层2003可以为SiC材料，可以利用终点检测方法判断刻蚀停止时刻。
由此，各个叠层之前因部分刻蚀而露出的凹入部均被第三SiC层2003填满，以隔离同一叠层不同高度下的p型栅导体层4002和n型栅导体层4003。并且，叠层中的各层相应外侧壁可以在竖直方向上共面。
于是，如图19(b)所示，沿AA′线的截面上，图18(b)中处于不同MOS层的p型栅导体层4002和n型栅导体层4003的凹入部均被第三SiC层2003填满。
如图19(c)所示，沿BB′线的截面上，图18(c)处于不同MOS层的第一源/漏层10031/10032/10033、第二源/漏层10071/10072/10073以及p型栅导体层4002和n型栅导体层4003的凹入部均被第三SiC层2003填满。类似地，如图19(d)所示，沿CC′线的截面上，图18(d)处于不同MOS层的第一源/漏层10031/10032/10033、第二源/漏层10071/10072/10073以及p型栅导体层4002和n型栅导体层4003的凹入部均被第三SiC层2003填满。
图20示意性示出了沿AA′线的截面图。
接着，如图20所示，沿AA′线的截面上，在衬底1001的露出区域淀积第五SiO 2层2015，通过CMP控制该第五SiO 2层2015淀积停止于硬掩膜层1009的上表面。由此，第五SiO 2层2015可以在左叠层与右叠层之间形成浅槽隔离(Shallow Trench Isolation，STI)。
图21(a)示意性示出了光刻胶构图区域的俯视图。图21(b)为根据图21(a)形成的沿AA′线的截面图。
如图21(a)所示，在AA′截面的上下两侧的水平宽条纹未被光刻胶覆盖，其他部位均覆盖有光刻胶。在该水平宽条纹处向下刻蚀第五SiO 2层2015，刻蚀停止于第二预设高度。该第二预设高度高于第一源/漏层10031的底部且低于第一源/漏层10031的顶部。
然后，为了降低有源区的串联电阻和接触电阻，也需要在有源区上形成金属硅化物，通过金属硅化物工艺(Silicide)对第五SiO 2层2015表面进行处理。Silicide可以使得金属不会与接触的SiO 2材料发生反应，所以Silicide能够很好地与有源区和多晶硅栅对准。
接着，在刻蚀后的第五SiO 2层2015上淀积第一金属层5001，通过 CMP控制第一金属层5001淀积停止于硬掩膜层1009的上表面。然后，向下刻蚀该第一金属层5001，刻蚀停止于第三预设高度。
该第三预设高度高于第一源/漏层10031的顶部且低于第二源/漏层10071的底部。结合附图1可知，第一金属层5001可以用于形成电源线Vdd。
图22示意性示出了沿AA′线的截面图。
接着，如图22所示，参照图20、图21(a)和20(b)工艺，在第一金属层5001上依次形成第六SiO 2层2016和第二金属层5002。与前述图20、图21(a)和20(b)工艺不同的是，第六SiO 2层2016刻蚀停止于第四预设高度，第二金属层5002刻蚀停止于第五预设高度。
具体来说，在第一金属层5001上淀积第六SiO 2层2016，通过CMP控制该第六SiO 2层2016淀积停止于硬掩膜层1009的上表面，从而第六SiO 2层2016在左叠层与右叠层之间形成STI。然后，向下刻蚀该第六SiO 2层2016，刻蚀停止于第四预设高度，由此实现在第一金属层5001上形成第六SiO 2层2016。
接着，在第六SiO 2层2016上淀积第二金属层5002，通过CMP控制该第二金属层5002淀积停止于硬掩膜层1009的上表面。然后，向下刻蚀该第二金属层5002，刻蚀停止于第四预设高度，由此实现在第六SiO 2层2016上形成第二金属层5002。
该第四预设高度高于第一源/漏层10032的顶部且低于第二源/漏层10072的底部。由此，第六SiO 2层2016可以在左叠层与右叠层之间形成浅槽隔离。
该第五预设高度高于第二源/漏层10072的底部且低于第二源/漏层10072的顶部。结合附图1可知，第二金属层5002可以用于形成接地线GND。
在第二金属层5002形成之后，还需在第二金属层5002上淀积第七SiO 2层2017，通过CMP控制该第七SiO 2层2017淀积停止于硬掩膜层1009的上表面。
图23(a)示意性示出了光刻胶构图区域的俯视图。图23(b)为根据图 23(a)形成的沿BB′线的截面图。
接着，如图23(a)和图23(b)所示，在BB′截面的上下两侧的小矩形框未被光刻胶覆盖，属于衬底1001的露出区域，其他部位均覆盖有光刻胶PR。并且，该衬底1001的露出区域正好将单个最小SRAM存储单元的左叠层与右叠层之间的区域露出。
在该BB′截面的上下两侧的矩形框区域向下刻蚀第七SiO 2层2017，刻蚀停止于第六预设高度，然后去除光刻胶。该第六预设高度高于第一源/漏层10031的顶部且低于第二源/漏层10071的底部。
为了降低有源区的串联电阻和接触电阻，也需要在有源区上形成金属硅化物，通过金属硅化物工艺(Silicide)对第七SiO 2层2017表面进行处理。
图24示意性示出了沿BB′线的截面图。
接着，如图24所示，在BB′截面的第七SiO 2层2017上淀积第三金属层5003，通过CMP控制第三金属层5003淀积停止于硬掩膜层1009的上表面。然后，向下刻蚀该第三金属层5003，刻蚀停止于第七预设高度。
该第七预设高度高于第一源/漏层10032的顶部且低于第二源/漏层10072的底部。结合附图1可知，第三金属层5003可以用于将第一CMOS的输入节点IN1与第二CMOS的输出节点OUT2相连，同时将第二CMOS的输入节点IN2与第一CMOS的输出节点OUT1相连。
图25示意性示出了沿BB′线的截面图。
接着，如图25所示，在BB′截面的第三金属层5003上淀积第四SiC层2004，通过CMP控制第四SiC层2004淀积停止于硬掩膜层1009的上表面。然后，向下刻蚀该第四SiC层2004并停止于第八预设高度，在第四SiC层2004的顶部中间位置继续刻蚀并停止于第三金属层5003上表面，形成左右隔开且呈台阶结构的第二间隔部。
其中，该第八预设高度高于第一源/漏层10033的底部且低于第一源/漏层10033的顶部。由此，第二间隔部可以将第一NMOS层的n型栅导体层4003隔离开，避免后续影响。
图26示意性示出了沿BB′线的截面图。
接着，如图26所示，在BB′截面的第二间隔部的内侧壁、底面以及上表面淀积第四金属层5004，通过CMP控制第四金属层5004淀积停止于硬掩膜层1009的上表面。然后，向下刻蚀该第四金属层5004并停止于第九预设高度。
其中，该第九预设高度高于第一源/漏层10033的底部且低于第一源/漏层10033的顶部。结合附图1可知，第四金属层5004可以用于将第一CMOS的输入节点IN1、第二CMOS的输出节点OUT2与晶体管M6的源极相连，同时将第二CMOS的输入节点IN2、第一CMOS的输出节点OUT1与晶体管M5的源极相连。
图27(a)示意性示出了光刻胶构图区域的俯视图。图27(b)为根据图27(a)形成的沿BB′线的截面图。
接着，如图27(a)和图27(b)所示，去除光刻胶，在所有上表面淀积第八SiO 2层2018，使所有材料层上表面覆盖有第八SiO 2层2018。
图28(a)示意性示出了光刻胶构图区域的俯视图。图28(b)为根据图28( a)形成的沿BB′线的截面图。
接着，如图28(a)所示，在第八SiO 2层2018的上表面旋涂光刻胶(图中未示出)以定义字线WL的区域形状。从俯视图上看，该字线WL跨接同一存储单元上左叠层的前端面与右叠层的后端面。以构图后的光刻胶为掩模，向下刻蚀第八SiO 2层2018，刻蚀停止于第十预设高度。该第十预设高度高于第一源/漏层10033的顶部且低于第二源/漏层10073的底部，使处于第二NMOS层的n型栅导体层4003部分显露出来。
然后，在处于第二NMOS层的n型栅导体层4003的外侧壁上淀积第五金属层5005，通过CMP控制第五金属层5005淀积停止于硬掩膜层1009的上表面。然后，向下刻蚀该第五金属层5005并停止于第十一预设高度。该第十一预设高度高于第二源/漏层10073的底部且低于第二源/漏层10073的顶部。同时，沿BB′截面上，部分刻蚀邻近于n型栅导体层4003外侧壁的第五金属层5005，使刻蚀后的第五金属层5005分别与左叠层与右叠层相对设置的外侧壁隔离开。
于是，如图28(b)所示，在沿水平方向的BB′截面上，仅有左叠层的处于第二NMOS层的n型栅导体层4003不与第五金属层5005相接触，右叠层的处于第二NMOS层的n型栅导体层4003也不与第五金属层5005相接触，由此形成类似阶梯形的连接线。
结合附图1可知，第五金属层5005可以用于定义字线WL，使得该字线WL跨接同一存储单元上左叠层的前端面与右叠层的后端面，以接触并电连接到左叠层的前端面或右叠层的后端面处于第二NMOS层的n型栅导体层4003的外侧壁。
图29示意性示出了沿BB′线的截面图。
接着，如图29所示，分别在左叠层与右叠层的第二源/漏层10073上形成金属接触部。结合附图1可知，该金属接触部可以用于形成互为相反信号的位线BL和位线
Figure PCTCN2021137861-appb-000003
具体地，该金属接触部包括：嵌于左叠层的第二源/漏层10073的第一接触部6001，以及，嵌于右叠层的第二源/漏层10073的第二接触部6001。第一接触部6001例如可以连接位线BL，相应地，第二接触部6002例如可以连接位线
Figure PCTCN2021137861-appb-000004
可以采用常规工艺来形成该金属接触部。例如，金属接触部可以通过依次在硬掩膜层1009和第二源/漏层10073中刻蚀孔洞，并在其中填充导电材料例如金属来形成。
由此，制备完成本公开实施例的存储器件，该存储器件以6T SRAM单元作为最小的存储单元，具有更少的晶体管数量，简化了计算机的存算结构，节省了计算资源，同时提高了计算进度和计算效率。
根据本公开实施例的存储器件可以应用于各种电子设备。例如，电子设备可以包括存储器件和处理器。存储器件可以存储电子设备操作所需或运行过程中得到的数据。处理器可以基于存储器件中存储的数据和/或应用而运行。这种电子设备例如智能电话、计算机、平板电脑(PC)、可穿戴智能设备、人工智能设备、移动电源等。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来 形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (33)

  1. 一种存储器件，包括：
    衬底；
    所述衬底上的存储单元阵列，包括多个存储单元，
    其中，每个存储单元包括：
    水平方向间隔排布的左叠层和右叠层，所述左叠层和右叠层均包括依次叠置于所述衬底上的下隔离层、PMOS层、第一NMOS层、上隔离层和第二NMOS层，所述PMOS层、第一NMOS层和第二NMOS层均包括竖直叠置的第一源/漏层、沟道层和第二源/漏层，所述沟道层相对于第一源/漏层和第二源/漏层横向凹入；
    栅堆叠，在竖直方向上介于所述第一源/漏层与第二源/漏层之间，且设于所述沟道层的相对两侧以嵌入所述沟道层的横向凹入。
  2. 根据权利要求1所述的存储器件，还包括：
    硬掩膜层，设置于所述第二NMOS层的第一源/漏层上。
  3. 根据权利要求1所述的存储器件，其中，所述栅堆叠包括栅介质层和栅导体层，所述栅介质层包括功函数调节金属和设置于所述功函数调节金属上的栅导电金属。
  4. 根据权利要求3所述的存储器件，其中，所述栅导体层包括p型栅导体层和n型栅导体层，其中：
    所述p型栅导体层设置于所述PMOS层的第一源/漏层与第二源/漏层之间；
    所述n型栅导体层设置于所述第一NMOS层的第一源/漏层与第二源/漏层之间，以及所述第二NMOS层的第一源/漏层与第二源/漏层之间。
  5. 根据权利要求3所述的存储器件，其中，所述第一源/漏层和第二源/漏层的横向外周部分凹入且凹入的部分填充有第三SiC层；和/或
    所述栅导体层的横向外周部分凹入且凹入的部分填充有第三SiC层。
  6. 根据权利要求5所述的存储器件，其中，所述第三SiC层的外侧壁与所述左叠层和右叠层在竖直方向上共面。
  7. 根据权利要求1所述的存储器件，还包括：
    第五SiO 2层，形成于所述左叠层与右叠层之间的衬底上，所述第五SiO 2层的顶部高于所述PMOS层的第一源/漏层的底部且低于所述PMOS层的第一源/漏层的顶部。
  8. 根据权利要求7所述的存储器件，还包括：
    第一金属层，形成于在所述左叠层和右叠层的纵向中部位置的所述第五SiO 2层上，所述第一金属层的顶部高于所述PMOS层的第一源/漏层的顶部且低于所述PMOS层的第二源/漏层的底部。
  9. 根据权利要求8所述的存储器件，还包括：
    依次形成于所述第一金属层上的第六SiO 2层和第二金属层，
    所述第六SiO 2层的顶部高于所述第一NMOS层的第一源/漏层的顶部且低于所述第一NMOS层的第二源/漏层的底部；
    所述第二金属层的顶部高于所述第一NMOS层的第二源/漏层的底部且低于所述第一NMOS层的第二源/漏层的顶部。
  10. 根据权利要求8所述的存储器件，还包括：
    第七SiO 2层，形成于除所述纵向中部位置之外的所述第五SiO 2层上，所述第七SiO 2层的顶部高于所述PMOS层的第一源/漏层的顶部且低于所述PMOS层的第二源/漏层的底部。
  11. 根据权利要求10所述的存储器件，还包括：
    第三金属层，形成于所述第七SiO 2层上，所述第三金属层的顶部高于所述第一NMOS层的第一源/漏层的顶部且低于所述第一NMOS层的第二源/漏层的底部。
  12. 根据权利要求11所述的存储器件，还包括：
    第四SiC层，形成于所述第三金属层上，所述第八SiO 2层的顶 部高于所述第二NMOS层的第一源/漏层的底部且低于所述第二NMOS层的第一源/漏层的顶部；
    所述第四SiC层的顶部中间位置相对凹陷并露出所述第三金属层，形成左右隔开且呈台阶结构的第二间隔部。
  13. 根据权利要求12所述的存储器件，其中，所述第二间隔部的内侧壁和底面形成有高于所述第四SiC层顶部的第四金属层；
    所述第四金属层的顶部高于所述第二NMOS层的第一源/漏层的底部且低于所述第二NMOS层的第一源/漏层的顶部。
  14. 根据权利要求4所述的存储器件，还包括：
    第五金属层，形成于所述左叠层的前端面与右叠层的后端面，且接触处于第二NMOS层的所述n型栅导体层的外侧壁；
    字线，连接于所述第五金属层，所述字线跨接同一存储单元的左叠层的前端面与右叠层的后端面，以接触并电连接到左叠层或右叠层处于第二NMOS层的n型栅导体层的外侧壁。
  15. 根据权利要求1所述的存储器件，还包括：
    第一接触部和第二接触部，所述第一接触部嵌入于所述左叠层的第二NMOS层的第二源/漏层，所述第二接触部嵌入于所述右叠层的第二NMOS层的第二源/漏层，所述第一接触部和第二接触部分别连接互为相反信号的第一位线和第二位线。
  16. 一种存储器件的制备方法，包括：
    在衬底上形成水平方向间隔排布的左叠层和右叠层，所述左叠层和右叠层均包括依次叠置的下隔离层、PMOS层、第一NMOS层、上隔离层和第二NMOS层，所述PMOS层、第一NMOS层和第二NMOS层均包括竖直叠置的第一源/漏层、沟道层和第二源/漏层，所述沟道层相对于第一源/漏层和第二源/漏层横向凹入；
    在所述沟道层的横向凹入依次淀积栅介质层和p型栅导体层；
    在左叠层和右叠层的底部淀积SiO 2，然后刻蚀该SiO 2并停止于第一预设高度，形成第一间隔部；
    刻蚀第一NMOS层与第二NMOS层对应位置上的p型栅导体层，在刻蚀掉的p型栅导体层的对应位置上淀积n型栅导体层；
    刻蚀所述第一间隔部，形成存储单元，所述存储器件包括多个所述存储单元的存储单元阵列。
  17. 根据权利要求16所述的制备方法，其中，所述第一源/漏层和第二源/漏层的材料为Si，所述下隔离层、上隔离层和沟道层的材料为SiGe。
  18. 根据权利要求16所述的制备方法，其中，所述第一预设高度高于PMOS层的第二源/漏层的底部，且低于第一NMOS层的第一源/漏层的顶部。
  19. 根据权利要求16所述的制备方法，还包括：
    在左叠层的第一纵向位置与右叠层的第二纵向位置，沿水平方向部分刻蚀第一源/漏层和第二源/漏层；和/或
    在左叠层的第二纵向位置与右叠层的第一纵向位置，沿水平方向部分刻蚀p型栅导体层和n型栅导体层。
  20. 根据权利要求19所述的制备方法，其中，所述第一源/漏层、第二源/漏层、p型栅导体层和n型栅导体层的刻蚀深度各自为p型栅导体层或n型栅导体层沿水平方向的二分之一。
  21. 根据权利要求19所述的制备方法，还包括：
    在所述第一源/漏层和第二源/漏层被部分刻蚀的区域淀积第三SiC层；
    在所述p型栅导体层和n型栅导体层被部分刻蚀的区域淀积第三SiC层，使得所述第三SiC层的外侧壁与所述左叠层和右叠层在竖直方向上共面。
  22. 根据权利要求16所述的制备方法，还包括：
    在所述左叠层与右叠层之间的衬底上淀积第五SiO 2层，使得所述第五SiO 2层的顶部高于所述PMOS层的第一源/漏层的底部且低于所述PMOS层的第一源/漏层的顶部。
  23. 根据权利要求22所述的制备方法，还包括：
    在所述左叠层和右叠层的纵向中部位置的所述第五SiO 2层上淀积第一金属层，使得所述第一金属层的顶部高于所述PMOS层的第一源/漏层的顶部且低于所述PMOS层的第二源/漏层的底部。
  24. 根据权利要求23所述的制备方法，其中，所述淀积第一金属层的步骤之前，还包括：
    通过金属硅化物工艺对所述第五SiO 2层的表面进行处理。
  25. 根据权利要求23所述的制备方法，还包括：
    在所述第一金属层上依次形成第六SiO 2层和第二金属层，使得所述第六SiO 2层的顶部高于所述第一NMOS层的第一源/漏层的顶部且低于所述第一NMOS层的第二源/漏层的底部；以及
    所述第二金属层的顶部高于所述第一NMOS层的第二源/漏层的底部且低于所述第一NMOS层的第二源/漏层的顶部。
  26. 根据权利要求23所述的制备方法，还包括：
    在除所述纵向中部位置之外的所述第五SiO 2层上淀积第七SiO 2层，使得所述第七SiO 2层的顶部高于所述PMOS层的第一源/漏层的顶部且低于所述PMOS层的第二源/漏层的底部。
  27. 根据权利要求26所述的制备方法，还包括：
    在所述第七SiO 2层上淀积第三金属层，使得所述第三金属层的顶部高于所述第一NMOS层的第一源/漏层的顶部且低于所述第一NMOS层的第二源/漏层的底部。
  28. 根据权利要求27所述的制备方法，还包括：
    在所述第三金属层上淀积第四SiC层，使得所述第四SiC层的顶部高于所述第二NMOS层的第一源/漏层的底部且低于所述第二NMOS层的第一源/漏层的顶部；
    所述第四SiC层的顶部中间位置刻蚀并停止于所述第三金属层的上表面，形成左右隔开且呈台阶结构的第二间隔部。
  29. 根据权利要求28所述的制备方法，还包括：
    在所述第二间隔部的内侧壁、底面以及上表面淀积第四金属层，使得所述第四金属层的顶部高于所述第二NMOS层的第一源/漏层的底部且低于所述第二NMOS层的第一源/漏层的顶部。
  30. 根据权利要求16所述的制备方法，还包括：
    在处于第二NMOS层的所述n型栅导体层的外侧壁上淀积第五金属层，使得所述第五金属层跨接同一存储单元上左叠层的前端面与右叠层的后端面，以接触并电连接到左叠层或右叠层处于第二NMOS层的n型栅导体层的外侧壁。
  31. 根据权利要求16所述的制备方法，还包括：
    在所述左叠层的第二NMOS层的第二源/漏层上嵌入第一接触部，在所述右叠层的第二NMOS层的第二源/漏层上嵌入第二接触部；
    所述第一接触部和第二接触部分别连接互为相反信号的第一位线和第二位线。
  32. 一种电子设备，包括如权利要求1至16中任一项所述的存储器件。
  33. 根据权利要求32所述的电子设备，其中，所述电子设备包括智能电话、计算机、平板电脑、可穿戴智能设备、人工智能设备、移动电源。
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