WO2023097720A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2023097720A1
WO2023097720A1 PCT/CN2021/136549 CN2021136549W WO2023097720A1 WO 2023097720 A1 WO2023097720 A1 WO 2023097720A1 CN 2021136549 W CN2021136549 W CN 2021136549W WO 2023097720 A1 WO2023097720 A1 WO 2023097720A1
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Prior art keywords
layer
metal layer
metal
groove
insulating layer
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PCT/CN2021/136549
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English (en)
French (fr)
Inventor
沈海燕
黄灿
鲜于文旭
张春鹏
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武汉华星光电半导体显示技术有限公司
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Publication of WO2023097720A1 publication Critical patent/WO2023097720A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display panel.
  • TFT Thin Film Transistor, thin film transistor
  • LCD Liquid Crystal Display, liquid crystal display
  • OLED Organic Light Emitting Diode, organic light emitting diode
  • the active layer semiconductor material used for TFT has undergone a transition from silicon-based to oxide, and the performance of TFT is also continuously improving.
  • the width-to-length ratio (W/L) of the channel of the active layer of the TFT is limited by the process line width and wiring, and cannot be adjusted flexibly, which limits the influence of the width-to-length ratio (W/L) on the TFT characteristics. adjustment. Therefore, it is necessary to improve this defect.
  • the embodiment of the present application provides an array substrate, which is used to solve the technical problem that the width-to-length ratio of the channel of the TFT active layer of the array substrate in the prior art cannot be flexibly adjusted due to the limitation of the process line width and wiring.
  • An embodiment of the present application provides an array substrate, including a substrate layer and at least one thin film transistor located on the substrate layer; wherein, the thin film transistor includes an electrode layer, a gate insulating layer, and an active layer; the electrode layer It includes a first metal layer, a second metal layer and a third metal layer stacked, and the second metal layer is insulated from the first metal layer and the third metal layer; the gate insulating layer is set on the sidewall of the electrode layer; the active layer is disposed on the surface of the gate insulating layer away from the electrode layer, and the first end of the active layer is electrically connected to the first metal layer connected, the second end of the active layer is electrically connected to the third metal layer; wherein, in the direction from the first metal layer to the third metal layer, the second metal layer includes at least The two metal sub-layers are stacked, and the adjacent two metal sub-layers are insulated.
  • the active layer includes a first doped portion, a second doped portion, and a channel portion, and the channel portion is located between the first doped portion and the second doped portion. Between two doped parts; wherein, the first doped part is electrically connected to the first metal layer; the second doped part is electrically connected to the third metal layer.
  • the first doped part is located on the surface of the first metal layer facing the second metal layer; the second doped part is located on the third metal layer layer away from the surface of one side of the second metal layer.
  • the material of the active layer is metal oxide or amorphous silicon.
  • the thin film transistor further includes a first insulating layer, a second insulating layer, and a third insulating layer; the first insulating layer is located between the second metal layer and the first insulating layer. between the metal layers; the second insulating layer is located between the second metal layer and the third metal layer; the third insulating layer is located between two adjacent metal sub-layers.
  • the thickness of the first insulating layer and/or the second insulating layer is greater than that of the first insulating layer.
  • the thickness of the three insulating layers is greater than that of the first insulating layer.
  • the first insulating layer, the second insulating layer, and the third insulating layer are all greater than or equal to 500 angstroms and less than or equal to 4000 angstroms.
  • the ratio of the thickness of the third insulating layer to the thickness of the first insulating layer is the second A ratio
  • the ratio of the thickness of the third insulating layer to the thickness of the second insulating layer is a second ratio
  • the first ratio and/or the second ratio is greater than or equal to one-fifth and less than or equal to one-half.
  • the thin film transistor includes at least two third insulating layers, and in the direction from the first metal layer to the third metal layer, at least two of the third insulating layers The thickness of the three insulating layers is equal.
  • the angle between the gate insulating layer and the first metal layer is greater than or equal to 60 degrees and Less than or equal to 90 degrees.
  • the electrode layer includes a first groove, and the first groove extends from the third metal layer to a surface of the first metal layer away from the substrate layer,
  • the gate insulating layer is located on the inner wall of the first groove.
  • the shape of the first groove is circular or polygonal.
  • the array substrate includes at least two thin film transistors, wherein the electrode layer further includes a second groove and at least two dividing grooves; the second groove runs through The active layer and the first metal layer, the second groove communicates with the first groove, and the orthographic projection of the second groove on the substrate layer falls on the first Within the scope of the orthographic projection of the groove on the substrate layer, the second groove is combined with the first groove to form a through groove; the dividing groove runs through the electrode layer, the gate insulating layer and In the active layer, at least two of the division grooves communicate with the through grooves, at least two of the division grooves are arranged around the through grooves, any of the division grooves is located between two adjacent films between transistors.
  • the thin film transistors in the top view direction of the thin film transistors, at least two of the thin film transistors have different areas.
  • the shape of the second groove is circular or polygonal.
  • any of the division grooves has a shape of a rectangle or a trapezoid.
  • An embodiment of the present application provides a method for preparing an array substrate, including: sequentially forming a first metal layer, a second metal layer, and a third metal layer constituting an electrode layer on a substrate layer, wherein the second metal layer and The first metal layer and the third metal layer are insulated, and in the direction from the first metal layer to the third metal layer, the second metal layer includes at least two stacked metal sub-layers , two adjacent metal sub-layers are insulated; a gate insulating layer is formed on the sidewall of the electrode layer; an active layer is formed on the surface of the gate insulating layer away from the electrode layer, the A first end of the active layer is electrically connected to the first metal layer, and a second end of the active layer is electrically connected to the third metal layer.
  • the step of forming a gate insulating layer on the sidewall of the electrode layer includes: forming a first groove on the electrode layer, and the second A groove extends from the third metal layer to the surface of the first metal layer away from the substrate layer; a gate insulating layer is formed on the inner wall of the first groove.
  • the method for preparing the array substrate further includes: forming a second groove on the electrode layer, the second groove passing through the active layer and the The first metal layer, the second groove communicates with the first groove, and the orthographic projection of the second groove on the substrate layer falls on the first groove on the substrate layer
  • the second groove and the first groove are combined into a through groove; at least two dividing grooves are formed on the electrode layer, and the dividing grooves penetrate through the electrode layer, the The gate insulating layer and the active layer, at least two of the division grooves communicate with the through groove, at least two of the division grooves are arranged around the through groove, and the adjacent two of the division grooves Between them is a thin film transistor.
  • the embodiment of the present application also provides a display panel, including an array substrate, the array substrate includes a substrate layer and at least one thin film transistor located on the substrate layer; wherein, the thin film transistor includes an electrode layer, a gate insulating layer and an active layer; the electrode layer includes a stacked first metal layer, a second metal layer and a third metal layer, the second metal layer is respectively insulated from the first metal layer and the third metal layer set; the gate insulating layer is set on the sidewall of the electrode layer; the active layer is set on the surface of the gate insulating layer away from the electrode layer, and the first end of the active layer Electrically connected to the first metal layer, the second end of the active layer is electrically connected to the third metal layer; wherein, in the direction from the first metal layer to the third metal layer
  • the second metal layer includes at least two stacked metal sub-layers, and two adjacent metal sub-layers are insulated.
  • An array substrate provided by an embodiment of the present application includes a substrate layer and at least one thin film transistor located on the substrate layer; the thin film transistor includes an electrode layer, a gate insulating layer and an active layer; the electrode layer includes a stacked first metal layer, the second metal layer and the third metal layer, the second metal layer is insulated from the first metal layer and the third metal layer respectively; the gate insulating layer is disposed on the side wall of the electrode layer; the active layer is disposed on the gate On the surface of the insulating layer away from the electrode layer, the first end of the active layer is electrically connected to the first metal layer, and the second end of the active layer is electrically connected to the third metal layer; In the direction of the three metal layers, the second metal layer includes at least two stacked metal sub-layers, and the adjacent two metal sub-layers are insulated; the present application uses the first metal layer, the second metal layer and the The third metal layer is stacked, and the channel of the active layer is set on the side wall of the electrode layer, and the second metal layer is divided
  • FIG. 1 is a schematic diagram of the basic structure of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a top view of a thin film transistor provided by an embodiment of the present application.
  • Fig. 3 is a cross-sectional view of another array substrate provided by an embodiment of the present application along the direction A-A' in Fig. 2 .
  • FIG. 4 is a top view of another thin film transistor provided by an embodiment of the present application.
  • Fig. 5 is a cross-sectional view of another array substrate provided in the embodiment of the present application along the direction B-B' in Fig. 4 .
  • FIG. 6 is a top view of another thin film transistor provided by an embodiment of the present application.
  • FIG. 7 is a flowchart of a method for preparing an array substrate provided in an embodiment of the present application.
  • 8a to 8g are schematic diagrams of the basic structure of each component in the manufacturing process flow of the array substrate provided by the embodiment of the present application.
  • 9a to 9c are schematic diagrams of the basic structures of components in the manufacturing process flow of another array substrate provided by the embodiment of the present application.
  • the array substrate includes a substrate layer 1 and at least one thin film transistor 3 located on the substrate layer 1; wherein the thin film transistor 3 includes an electrode layer 30, a gate insulating layer 31, and an active layer 32; the electrode layer 30 includes a stacked first metal layer 301, a second metal layer 302, and a third metal layer 303, and the second metal layer 302 are respectively insulated from the first metal layer 301 and the third metal layer 303; the gate insulating layer 31 is disposed on the sidewall of the electrode layer 30; the active layer 32 is disposed on the On the surface of the gate insulating layer 31 away from the electrode layer 30, the first end of the active layer 32 is electrically connected to the first metal layer 301, and the second end of the active layer 32 is electrically connected to the The third metal layer 303 is electrically connected; wherein, in the direction from the first metal layer 301 to the third metal layer 303, the second metal layer
  • the gate insulating layer 31 is disposed on the sidewall of the electrode layer 30 , where the sidewall refers to a plane forming a certain angle with the plane where the electrode layer 30 is located.
  • the plane where the electrode layer 30 is located is a horizontal plane, that is, the plane where the gate insulating layer 31 is located forms a certain angle with the horizontal plane.
  • the embodiment of the present application provides a thin film transistor 3 structure with a vertical channel.
  • the second metal layer 302 corresponds to the gate layer
  • the first metal layer 301 and the third metal layer 303 correspond to the source layer and the drain layer.
  • the third metal layer 303 corresponds to the drain layer; when the first metal layer 301 corresponds to the drain layer, the third metal layer 303 corresponds to the source layer.
  • the gate insulating layer 31 and the active layer 32 of the present application are respectively formed on the sidewalls of the electrode layer 30.
  • the active layer 32 includes a first doped portion 321, a second doped portion 322, and a channel portion 323.
  • the channel The portion 323 is located between the first doped portion 321 and the second doped portion 322 .
  • the first doped part 321 is electrically connected to the first metal layer 301 ;
  • the second doped part 322 is electrically connected to the third metal layer 303 .
  • the channel portion 323 is approximately perpendicular to the electrode layer 30, and the length of the channel portion 323 can be adjusted by adjusting the thickness H and the number of metal sub-layers 3021.
  • FIG. 1 only the second metal layer 302 Including three metal sub-layers 3021 is shown as an example.
  • the leakage current I ds refers to: when the voltage of the gate (ie, the second metal layer 302 ) is 0, at a certain source-drain (ie, The current between the source and the drain under the voltage of the first metal layer 301 and the third metal layer 303 ).
  • the leakage current I ds ⁇ C i (W/L)[(V gs -V th )V ds -V ds 2 /2], where ⁇ is the mobility and C i is The capacitance per unit area of the gate insulating layer 31, W is the width of the channel portion 323, L is the length of the channel portion 323, V gs is the gate-source voltage, V ds is the drain-source voltage, and V th is the threshold voltage. It can be drawn from the above formula that the larger the (W/L) is, the larger the I ds will be.
  • the embodiment of the present application can adjust the length L of the channel portion 323 by adjusting the thickness H and the number of the metal sub-layers 3021, that is, the active layer 32 can be adjusted.
  • the width-to-length ratio (W/L) of the channel portion 323 achieves the purpose of flexibly adjusting the characteristics of the thin film transistor 3 .
  • the length L of the channel portion 323 is determined according to the thickness of the second metal layer 302 (ie, the cumulative sum of the thicknesses H of all the metal sub-layers 3021 ). Specifically, because the thickness of the single-layer metal is too thick and easy to peel off, the thickness of the single-layer metal generally does not exceed 8000 angstroms, which limits the control of the length L of the channel portion 323 . In the embodiment of the present application, by dividing the second metal layer 302 into a plurality of stacked metal sub-layers 3021, the thickness H of the multiple metal sub-layers 3021 can be accumulated.
  • the sum of thicknesses H of the metal sub-layers 3021 can be flexibly adjusted according to the number of sub-layers 3021 . That is, the present application can flexibly adjust the width-to-length ratio (W/L) of the channel portion 323 of the active layer 32 by adjusting the thickness H and the number of the metal sub-layers 3021 .
  • the value of the width-to-length ratio (W/L) of the channel portion 323 is about 2.
  • the value of (W/L) is different according to the function of the thin film transistor 3 , for example, the value of (W/L) is different for the driving thin film transistor and the switching thin film transistor.
  • the first doped part 321 is located on the side surface of the first metal layer 301 facing the second metal layer 302; the second doped part 322 is located on the third metal layer The surface of the layer 303 is away from the side of the second metal layer 302 . That is, the first doped portion 321 is electrically connected to the portion of the first metal layer 301 not covered by the second metal layer 302 and the third metal layer 303 .
  • the semiconductor layer is usually doped by an ion implanter to form the first doped portion 321 and the second doped portion 322, and the undoped portion is the channel portion 323, since the ion implantation direction is toward the direction from the thin film transistor 3 to the substrate layer 1, that is, the side of the first metal layer 301 facing the second metal layer 302 and the side of the third metal layer 303 away from the second metal layer 302 will be adulterated.
  • this embodiment is described by setting the first metal layer 301 close to the substrate layer 1.
  • the third metal layer 303 may also be set close to the substrate layer 1.
  • the first doped part 321 is located on the side surface of the third metal layer 303 facing the second metal layer 302; the second doped part 322 is located on the first metal layer 301 is away from the side surface of the second metal layer 302 .
  • the first metal layer 301 when the first metal layer 301 is arranged close to the substrate layer 1, the first metal layer 301 is the source layer, and the third metal layer 303 is the drain layer; when the third metal layer 303 is close to the substrate layer 1 When set, the third metal layer 303 is the source layer, and the first metal layer 301 is the drain layer. It can be understood that the thin film transistor 3 needs to connect the drain layer to the outside of the thin film transistor 3 through a via hole. In this embodiment, it is more convenient to connect the drain layer by arranging the drain layer on a side away from the substrate layer 1 .
  • the material of the active layer 32 is metal oxide or amorphous silicon. It can be understood that low-temperature polysilicon needs to crystallize amorphous silicon, and this process requires a flat surface. A part of the active layer 32 provided in the present application is located on the first metal layer 301 and the third metal layer 303 , and another part is located on the sidewall of the electrode layer 30 , which is not a flat surface. Therefore, the active layer 32 provided in the embodiment of the present application is not suitable for manufacturing by low temperature polysilicon.
  • the thin film transistor 3 further includes a first insulating layer 304, a second insulating layer 305, and a third insulating layer 306; the first insulating layer 304 is located between the second metal layer 302 and the Between the first metal layer 301; the second insulating layer 305 is located between the second metal layer 302 and the third metal layer 303; the third insulating layer 306 is located between two adjacent metal layers between sublayers 3021.
  • the resistance of the third insulating layer 306 is connected in series with the resistance of multiple metal sub-layers 3021, which is equivalent to increasing
  • the equivalent resistance between the first metal layer 301 and the third metal layer 303 is improved, so that the leakage current between the first metal layer 301 and the third metal layer 303 can be reduced. That is, the present application sets the second metal layer 302 as an overlapping structure of the metal sub-layer 3021 and the third insulating layer 306, and the adjacent metal sub-layer 3021 is separated by the third insulating layer 306, which can effectively reduce the size of the thin film transistor. 3 leakage current.
  • the material of the first insulating layer 304 , the second insulating layer 305 and the third insulating layer 306 is silicon dioxide or silicon nitride.
  • the thickness of the first insulating layer 304 and/or the second insulating layer 305 is greater than that of the first insulating layer 304.
  • the thickness of the three insulating layers 306 It can be understood that the first insulating layer 304 is located between the first metal layer 301 and the second metal layer 302, and the second insulating layer 305 is located between the second metal layer 302 and the third metal layer 303, that is, the first insulating layer 304 and the second insulating layer 305 mainly serve as a spacer layer and play a role of isolation.
  • the thickness of the third insulating layer 306 is set to be smaller than the thickness of the first insulating layer 304 and/or the second insulating layer 305, which can achieve The effect of stress between the multiple metal sub-layers 3021 is reduced to prevent the metal sub-layer 3021 from being peeled off from the third insulating layer 306 due to excessive stress.
  • the thicknesses of the first insulating layer 304, the second insulating layer 305, and the third insulating layer 306 are all greater than or equal to 500 Angstroms and less than Or equal to 4000 angstroms to prevent the channel part 323 of the active layer 32 from being unable to conduct due to the thickness of the first insulating layer 304 , the second insulating layer 305 and the third insulating layer 306 being too thick.
  • the ratio of the thickness of the third insulating layer 306 to the thickness of the first insulating layer 304 is the second A ratio
  • the ratio of the thickness of the third insulating layer 306 to the thickness of the second insulating layer 305 is a second ratio
  • the first ratio and/or the second ratio is greater than or equal to one-fifth and less than or equal to one-half.
  • the thin film transistor 3 includes at least two third insulating layers 306, and in the direction from the first metal layer 301 to the third metal layer 303, at least two of the third insulating layers The thicknesses of the three insulating layers 306 are equal.
  • the array substrate further includes a fourth insulating layer 2 , and the fourth insulating layer 2 is located between the substrate layer 1 and the thin film transistor 3 .
  • the material of the fourth insulating layer 2 is silicon dioxide or silicon nitride.
  • the thickness of the fourth insulating layer 2 is greater than or equal to 4000 angstroms and less than or equal to 8000 angstroms.
  • the fourth insulating layer 2 can function as a barrier to prevent alkaline ions in the substrate layer 1 from diffusing into the thin film transistor 3 and can also isolate water and oxygen in the air.
  • the array substrate further includes a passivation layer 4 located on the fourth insulating layer 2 , and the passivation layer 4 covers at least one thin film transistor 3 .
  • the included angle C between the gate insulating layer 31 and the first metal layer 301 is greater than or equal to 60 degrees And less than or equal to 90 degrees. It can be understood that since the active layer 32 is located on the surface of the gate insulating layer 31 facing away from the electrode layer 30 , the plane where the channel portion 323 of the active layer 32 is located is parallel to the plane where the gate insulating layer 31 is located. Therefore, the inclination angle of the channel portion 323 of the active layer 32 relative to the first metal layer 301 is equal to the included angle C.
  • the doping amount of the channel part 323 will be very small or even during the ion implantation process. No doping is used to prevent dopant ions from affecting the current efficiency of the channel portion 323 .
  • the active layer 32 when the inclination angle is 90 degrees, can be formed by atomic deposition. It can be understood that when the inclination angle is 90 degrees, the gate insulating layer 31 is perpendicular to the substrate layer 1 , and the active layer 32 cannot cover the gate insulating layer 31 by using a common physical deposition method.
  • Atomic deposition is a chemical deposition method, which is a method of forming a deposited film by alternately passing pulses of gaseous precursors into the reactor and chemically adsorbing and reacting on the deposition substrate.
  • the gate insulating layer 31 is perpendicular to the substrate layer 1 , it does not affect the chemical adsorption and surface reaction between the vapor phase precursor and the deposition substrate, and the formed active layer 32 can cover the gate insulating layer 31 .
  • FIG. 2 and FIG. 3 are respectively the top view of the thin film transistor provided by the embodiment of the present application and the cross-sectional view of another array substrate provided by the embodiment of the present application along the AA' direction in FIG.
  • the electrode layer 30 in this embodiment includes a first groove 307, and the first groove 307 extends from the third metal layer 303 to the first metal layer 301 is away from the surface of the substrate layer 1 , and the gate insulating layer 31 is located on the inner wall of the first groove 307 .
  • the first groove 307 is etched on the electrode layer 30 to expose the first metal layer 301 disposed close to the substrate layer 1, and the gate insulating layer 31 is disposed in the first groove.
  • the active layer 32 is arranged on the surface of the gate insulating layer 31 away from the electrode layer 30, the first end of the active layer 32 is located at the bottom of the first groove 307, and the exposed first metal
  • the layer 301 is electrically connected
  • the second end of the active layer 32 is located on the surface of the third metal layer 303 away from the second metal layer 302, and is electrically connected to the third metal layer 303, between the first end and the second end
  • the channel is located on the slope of the gate insulating layer 31 and is approximately perpendicular to the electrode layer 30 , that is, the thin film transistor 3 structure with a vertical channel is formed.
  • the shape of the first groove 307 is circular or polygonal. Specifically, please refer to FIG. 2 .
  • the top view of the first groove 307 is shown as a square as an example. It can be understood that, in FIG. 2 and FIG. 3, only one thin film transistor 3 is provided on the substrate layer 1 for illustration, and the width of the channel portion 323 of the thin film transistor 3 in FIG. 2 and FIG. The circumference W of the inner wall of a groove 307 (as shown in FIG. 2 ). It should be noted that a plurality of thin film transistors 3 as shown in FIG. 2 and FIG. 3 may be disposed on the substrate layer 1 .
  • the array substrate includes a substrate layer 1 and at least one thin film transistor 3 located on the substrate layer 1; wherein the thin film transistor 3 includes an electrode layer 30.
  • the electrode layer 30 includes a first groove 307, and the first groove 307 extends from the third metal layer 303 to the surface of the first metal layer 301 away from the substrate layer 1 , the gate insulating layer 31 is located on the inner wall of the first groove 307 .
  • the shape of the first groove 307 is circular or polygonal. Specifically, please refer to FIG. 4 . In this embodiment, the top view of the first groove 307 is shown as a square as an example.
  • the array substrate includes at least two thin film transistors 3, wherein the electrode layer 30 further includes a second groove 308 and at least two dividing grooves 309; the second groove 308 Through the active layer 32 and the first metal layer 301, the second groove 308 communicates with the first groove 307, and the positive side of the second groove 308 on the substrate layer 1
  • the projection falls within the range of the orthographic projection of the first groove 307 on the substrate layer 1, the second groove 308 and the first groove 307 are combined into a through groove; the dividing groove 309 runs through
  • this embodiment is also provided with a second groove 308 and at least two dividing grooves 309 (only two dividing grooves 309 are shown in Fig. 4 Groove 309 is used as an example for illustration), wherein, the second groove 308 continues to etch downwards on the basis of the first groove 307, penetrating through the active layer 32 and the first metal layer 301, the second groove 308 and the first groove 308 A groove 307 is combined into a through groove, and the through groove runs through the entire thin film transistor 3.
  • at least two dividing grooves 309 are provided, and at least two dividing grooves 309 are connected to the through groove.
  • At least two The dividing groove 309 also runs through the entire thin film transistor 3, that is, the first groove 307, the second groove 308, and at least two of the dividing grooves 309 work together to divide one thin film transistor into at least two thin film transistors. transistor.
  • the electrode layer 30 includes two dividing grooves 309 as an example. In FIG. equal area in top view.
  • the dividing grooves 309 are distributed asymmetrically, thin film transistors with unequal areas can be divided, and thin film transistors with unequal areas have different channel widths W.
  • the channel length L of the thin film transistors has Fixed, different width-to-length ratios (W/L) can be formed by adjusting the position of the dividing groove 309 to meet the requirements of different thin film transistors in the driving circuit.
  • the shape of the second groove 308 is circular or polygonal. Specifically, please refer to FIG. 4 . In this embodiment, the top view of the second groove 308 is shown as a square as an example.
  • the shape of any one of the dividing grooves 309 is a rectangle or a trapezoid. Specifically, please refer to FIG. 4 .
  • the top view of the dividing groove 309 is a rectangle as an example for illustration.
  • FIG. 4 and FIG. 5 only two thin film transistors 3 are provided on the substrate layer 1 for illustration.
  • the sum of the widths of the two dividing grooves 309 corresponds to the perimeter of the inner wall of the first groove 307 .
  • multiple sets of two thin film transistors 3 as shown in FIG. 4 and FIG. 5 can be arranged on the substrate layer 1 .
  • FIG. 6 is a top view of another thin film transistor provided by the embodiment of the present application.
  • the electrode layer 30 (as in FIG. 5 ) also includes a second groove 308 and four dividing grooves 309;
  • the groove 308 runs through the active layer 32 (as shown in FIG. 5 ) and the first metal layer 301 (as shown in FIG. 5 ), the second groove 308 communicates with the first groove 307 , and the first The orthographic projection of the second groove 308 on the substrate layer 1 (as shown in FIG.
  • the division groove 309 falls within the range of the orthographic projection of the first groove 307 on the substrate layer 1, and the second groove 308 and The first groove 307 is combined into a through groove; the division groove 309 runs through the electrode layer 30, the gate insulating layer 31 (as shown in FIG. 5 ) and the active layer 32, and four division grooves 309 is in communication with the through groove, four of the division grooves 309 are arranged around the through groove, and any of the division grooves 309 is located between two adjacent thin film transistors.
  • the electrode layer 30 includes four dividing grooves 309 .
  • the four division grooves 309 are all connected with the through groove, and the four division grooves 309 all run through the whole thin film transistor, that is, the first groove 307, the second groove 308 and the four division grooves
  • the grooves 309 work together to divide one thin film transistor into four thin film transistors.
  • the shape of any one of the dividing grooves 309 is a rectangle or a trapezoid. Specifically, please refer to FIG. 6 .
  • the top view of the dividing groove 309 is trapezoidal as an example.
  • FIG. 6 only four thin film transistors are provided on the substrate layer 1 (as shown in FIG. 5 ) as an example for illustration.
  • the sum of the widths of 309 corresponds to the perimeter of the inner wall of the first groove 307 . It should be noted that multiple sets of four thin film transistors as shown in FIG. 6 can be arranged on the substrate layer 1 .
  • one thin film transistor can be divided not only into 2 or 4, but also into 3, 5 and so on.
  • the thin film transistors provided in the embodiments of the present application do not correspond to sub-pixels alone, but can be connected in a certain driving connection manner to form a driving circuit.
  • FIG. 7 is a flow chart of the method for preparing the array substrate provided in the embodiment of the present application.
  • the method includes:
  • the second metal layer sequentially forming a first metal layer, a second metal layer, and a third metal layer constituting an electrode layer on the substrate layer, wherein the second metal layer is respectively connected to the first metal layer and the third metal layer Insulation arrangement, in the direction from the first metal layer to the third metal layer, the second metal layer includes at least two stacked metal sub-layers, and two adjacent metal sub-layers are insulated;
  • the first metal layer, the second metal layer and the third metal layer constituting the electrode layer are sequentially stacked, and the gate insulating layer and the active layer are formed on the sidewall of the electrode layer, A thin-film transistor structure with a vertical channel is formed; the second metal layer is divided into multiple metal sub-layers stacked, and the thickness and quantity of the metal sub-layers can be adjusted, so that the width and length of the channel of the active layer can be adjusted ratio, to achieve the purpose of flexibly adjusting the characteristics of the thin film transistor.
  • the second metal layer corresponds to the gate layer
  • the first metal layer and the third metal layer correspond to the source layer and the drain layer.
  • the third metal layer corresponds to the drain layer; when the first metal layer corresponds to the drain layer, the third metal layer corresponds to the source layer.
  • the gate insulating layer and the active layer of the present application are respectively formed on the side walls of the electrode layer, the active layer includes a first doped part, a second doped part and a channel part, and the channel part is located in the first doped part and between the second doped portion.
  • the first doped part is electrically connected with the first metal layer; the second doped part is electrically connected with the third metal layer.
  • the thickness of the single-layer metal is too thick and easy to peel off, so the thickness of the single-layer metal generally does not exceed 8000 angstroms.
  • the thickness of the multiple metal sub-layers can be accumulated.
  • the number of metal sub-layers can be adjusted.
  • the cumulative sum of the thicknesses of the metal sublayers can be flexibly adjusted. That is, the present application can flexibly adjust the width-to-length ratio (W/L) of the channel portion of the active layer by adjusting the thickness and quantity of the metal sub-layer.
  • the first metal layer is disposed close to the substrate layer for illustration, and in other embodiments, the third metal layer may also be disposed close to the substrate layer.
  • the first metal layer is the source layer
  • the third metal layer is the drain layer
  • the third metal layer is the source layer
  • the third metal layer is the drain layer.
  • a metal layer is the drain layer. It can be understood that the thin film transistor needs to connect the drain layer to the outside of the thin film transistor through a via hole. In this embodiment, it is more convenient to connect the drain layer by arranging the drain layer on a side away from the substrate layer.
  • the material of the active layer is metal oxide or amorphous silicon. It can be understood that low-temperature polysilicon needs to crystallize amorphous silicon, and this process requires a flat surface. A part of the active layer provided by the present application is located on the first metal layer and the third metal layer, and another part is located on the side wall of the electrode layer, which is not a flat surface. Therefore, the active layer provided in the embodiment of the present application is not suitable for manufacturing by using low-temperature polysilicon.
  • the thin film transistor further includes a first insulating layer, a second insulating layer, and a third insulating layer; the first insulating layer is located between the second metal layer and the first metal layer ; The second insulating layer is located between the second metal layer and the third metal layer; The third insulating layer is located between two adjacent metal sub-layers. It can be understood that in this embodiment, a third insulating layer is provided between two adjacent metal sub-layers, and the resistance of the third insulating layer is connected in series with the resistance of multiple metal sub-layers, which is equivalent to increasing the resistance of the first metal sub-layer. The equivalent resistance between the first metal layer and the third metal layer can reduce the leakage current between the first metal layer and the third metal layer.
  • the second metal layer as an overlapping structure of metal sub-layers and third insulating layers, adjacent metal sub-layers are separated by the third insulating layer, which can effectively reduce the leakage current of the thin film transistor.
  • the material of the first insulating layer, the second insulating layer and the third insulating layer is silicon dioxide or silicon nitride.
  • the thickness of the first insulating layer and/or the second insulating layer is greater than that of the third insulating layer. thickness.
  • the first insulating layer is located between the first metal layer and the second metal layer
  • the second insulating layer is located between the second metal layer and the third metal layer, that is, the first insulating layer and the second insulating layer are mainly As a spacer layer, it plays the role of isolation.
  • the thickness of the third insulating layer in this embodiment, by setting the thickness of the third insulating layer to be smaller than the thickness of the first insulating layer and/or the second insulating layer, it can reduce the thickness of multiple metal layers. The effect of the stress between the sub-layers prevents the metal sub-layer from being peeled off from the third insulating layer due to excessive stress.
  • the thicknesses of the first insulating layer, the second insulating layer and the third insulating layer are all greater than or equal to 500 angstroms and less than or equal to 4000 angstroms, In order to prevent the channel part of the active layer from being unable to conduct due to the thickness of the first insulating layer, the second insulating layer and the third insulating layer being too thick.
  • the array substrate further includes a fourth insulating layer, and the fourth insulating layer is located between the substrate layer and the thin film transistor.
  • the material of the fourth insulating layer is silicon dioxide or silicon nitride.
  • the thickness of the fourth insulating layer is greater than or equal to 4000 angstroms and less than or equal to 8000 angstroms.
  • the fourth insulating layer can function as a barrier to prevent alkaline ions in the substrate layer from diffusing into the thin film transistor, and can also isolate water and oxygen in the air.
  • the array substrate further includes a passivation layer, the passivation layer is located on the fourth insulating layer, and the passivation layer covers at least one of the thin film transistors.
  • the angle between the gate insulating layer and the first metal layer is greater than or equal to 60 degrees and less than or equal to 90 degrees.
  • Spend since the active layer is located on the surface of the gate insulating layer away from the electrode layer, that is, the plane where the channel portion of the active layer is located is parallel to the plane where the gate insulating layer is located. Therefore, the inclination angle of the channel portion of the active layer relative to the first metal layer is equal to the included angle.
  • the doping amount of the channel part will be little or even no doping during the ion implantation process, The effect of dopant ions on the current efficiency of the channel portion is avoided.
  • the active layer when the inclination angle is 90 degrees, can be formed by atomic deposition. It can be understood that when the inclination angle is 90 degrees, the gate insulating layer is perpendicular to the substrate layer, and the active layer cannot cover the gate insulating layer by ordinary physical deposition methods.
  • Atomic deposition is a chemical deposition method, which is a method of forming a deposited film by alternately passing pulses of gaseous precursors into the reactor and chemically adsorbing and reacting on the deposition substrate. Therefore, even if the gate insulating layer is perpendicular to the substrate layer, it does not affect the chemical adsorption and surface reaction between the gas phase precursor and the deposition substrate, and the formed active layer can cover the gate insulating layer.
  • the step of forming a gate insulating layer on the sidewall of the electrode layer includes: forming a first groove on the electrode layer, the first groove extending from the first The three metal layers extend to the surface of the first metal layer away from the substrate layer; a gate insulating layer is formed on the inner wall of the first groove.
  • the method for preparing the array substrate further includes: forming a second groove on the electrode layer, the second groove passing through the active layer and the first metal layer, so The second groove communicates with the first groove, and the orthographic projection of the second groove on the substrate layer falls within the range of the orthographic projection of the first groove on the substrate layer , the combination of the second groove and the first groove is a through groove; at least two dividing grooves are formed on the electrode layer, and the dividing grooves pass through the electrode layer, the gate insulating layer and the In the active layer, at least two of the division grooves communicate with the through groove, at least two of the division grooves are arranged around the through groove, and a thin film transistor is located between two adjacent division grooves.
  • FIG. 8a ⁇ FIG. 8g are schematic diagrams of the basic structure of each component in the manufacturing process flow of the array substrate provided by the embodiment of the present application.
  • the fourth insulating layer is sequentially deposited on the substrate layer 1 2.
  • the direction from the metal layer 301 to the third metal layer 303 is stacked and mutually insulated metal sub-layers 3021 (Fig.
  • the metal sublayers 3021 are separated by the third insulating layer 306 .
  • the first metal layer 301 , the second metal layer 302 and the third metal layer 303 constitute the electrode layer 30 .
  • a first groove 307 is formed on the electrode layer 30, the first groove 307 extends from the third metal layer 303 to the first metal layer 301 away from the The surface of the substrate layer 1.
  • an insulating layer 300 is deposited on the electrode layer 30 .
  • the insulating layer 300 is patterned to form a gate insulating layer 31 , and the gate insulating layer 31 is located on the inner wall of the first groove 307 .
  • a semiconductor layer 400 is deposited on the electrode layer 30 .
  • the semiconductor layer 400 is patterned to form the active layer 32 .
  • the active layer 32 is ion-doped to form a first doped portion 321 , a second doped portion 322 and a channel portion 323 , that is, a thin film transistor 3 is prepared.
  • the channel portion 323 is located between the first doped portion 321 and the second doped portion 322 .
  • the first doped part 321 is electrically connected to the first metal layer 301 ; the second doped part 322 is electrically connected to the third metal layer 303 .
  • the included angle C between the gate insulating layer 31 and the first metal layer 301 is greater than or equal to 60 degrees and less than or equal to 90 degrees. Spend. It can be understood that since the active layer 32 is located on the surface of the gate insulating layer 31 facing away from the electrode layer 30 , the plane where the channel portion 323 of the active layer 32 is located is parallel to the plane where the gate insulating layer 31 is located. Therefore, the inclination angle of the channel portion 323 of the active layer 32 relative to the first metal layer 301 is equal to the included angle C.
  • the doping amount of the channel part 323 will be very small or even during the ion implantation process. No doping is used to prevent dopant ions from affecting the current efficiency of the channel portion 323 .
  • a passivation layer 4 is formed on the fourth insulating layer 2 , and the passivation layer 4 covers the thin film transistor layer 3 .
  • the manufacturing process flow of the array substrate provided in this embodiment is only described by taking a thin film transistor 3 disposed on the substrate layer 1 as an example.
  • a doped protection layer (not shown) is formed on the surface of the inner wall of the active layer 32 away from the gate insulating layer 31 . It can be understood that, in this embodiment, a doping protective layer is first formed in the region corresponding to the channel portion 323, and then ion doping is performed, so that the dopant ions will not be implanted into the channel portion 323. The manufacturing method does not need to limit the size of the angle C between the gate insulating layer 31 and the first metal layer 301 .
  • FIG. 9a ⁇ FIG. 9c are schematic diagrams of the basic structure of each component in the manufacturing process flow of another array substrate provided by the embodiment of the present application.
  • a second groove 308 is formed on the electrode layer 30, the second groove 308 runs through the active layer 32 and the first metal layer 301, and the second groove 308 Connected with the first groove 307, the orthographic projection of the second groove 308 on the substrate layer 1 falls within the range of the orthographic projection of the first groove 307 on the substrate layer 1 , the combination of the second groove 308 and the first groove 307 is a through groove.
  • FIG. 9 b four dividing grooves 309 are formed on the electrode layer 30 , and the dividing grooves 309 penetrate the electrode layer 30 , the gate insulating layer 31 and the active layer 32 ,
  • the four division grooves 309 communicate with the through groove, the four division grooves 309 are arranged around the through groove, and a thin film transistor is located between two adjacent division grooves 309 .
  • a passivation layer 4 is formed on the fourth insulating layer 2 , and the passivation layer 4 covers the thin film transistor 3 .
  • the manufacturing process flow of the array substrate provided in this embodiment is only described by dividing one thin film transistor into four thin film transistors as an example, and it can also be divided into two, three, five and so on.
  • An embodiment of the present application further provides a display panel, including the above-mentioned array substrate.
  • the display panel provided in the embodiment of the present application may be a liquid crystal display panel or an organic light emitting diode display panel.
  • An embodiment of the present application further provides a display terminal, including the above-mentioned display panel.
  • the display terminal provided in the embodiment of the present application may be a product or component having a display function such as a mobile phone, a tablet computer, a notebook computer, a television, a digital camera, and a navigator.
  • an array substrate provided by an embodiment of the present application includes a substrate layer and at least one thin film transistor located on the substrate layer; the thin film transistor includes an electrode layer, a gate insulating layer, and an active layer; the electrode layer includes a laminated The first metal layer, the second metal layer and the third metal layer are provided, and the second metal layer is respectively insulated from the first metal layer and the third metal layer; the gate insulating layer is provided on the side wall of the electrode layer; the active layer is disposed on the surface of the gate insulating layer away from the electrode layer, the first end of the active layer is electrically connected to the first metal layer, and the second end of the active layer is electrically connected to the third metal layer; wherein, at the In the direction from the first metal layer to the third metal layer, the second metal layer includes at least two stacked metal sub-layers, and the adjacent two metal sub-layers are insulated; The second metal layer and the third metal layer are stacked, and the channel of the active layer is set on the side wall of the electrode layer, and the
  • the thickness and quantity of the layer are regulated, so that the width-to-length ratio of the channel of the active layer can be regulated, and the purpose of flexibly adjusting the characteristics of the thin film transistor is achieved, which solves the problem of the channel width of the active layer of the TFT of the array substrate in the prior art.
  • the length ratio is limited by the process line width and wiring, and it is a technical problem that cannot be adjusted flexibly.

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Abstract

本申请提供一种阵列基板及其制备方法、显示面板，阵列基板包括电极层、栅极绝缘层以及有源层，电极层包括层叠设置的第一金属层、第二金属层以及第三金属层，有源层的第一端与第一金属层电性连接，有源层的第二端与第三金属层电性连接，第二金属层包括至少两个层叠设置的金属子层。

Description

阵列基板及其制备方法、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示面板。
 背景技术
近年来，TFT(Thin Film Transistor，薄膜晶体管)在LCD(Liquid Crystal Display，液晶显示器)和OLED(Organic Light Emitting Diode，有机发光二极管)显示装置中的应用受到广泛关注。用于TFT的有源层半导体材料经历了由硅基到氧化物的转变，TFT的性能也在不断地提高。
在传统工艺制程中，TFT的有源层的沟道的宽长比(W/L)受到工艺线宽及布线的限制，不能灵活调节，即限制了宽长比(W/L)对TFT特性的调节。故，有必要改善这一缺陷。
 技术问题
本申请实施例提供一种阵列基板，用于解决现有技术的阵列基板的TFT的有源层的沟道的宽长比受到工艺线宽及布线的限制，不能灵活调节的技术问题。
 技术解决方案
本申请实施例提供一种阵列基板，包括衬底层以及位于所述衬底层之上的至少一薄膜晶体管；其中，所述薄膜晶体管包括电极层、栅极绝缘层以及有源层；所述电极层包括层叠设置的第一金属层、第二金属层以及第三金属层，所述第二金属层分别与所述第一金属层和所述第三金属层绝缘设置；所述栅极绝缘层设置于所述电极层的侧壁上；所述有源层设置于所述栅极绝缘层背离所述电极层的表面上，所述有源层的第一端与所述第一金属层电性连接，所述有源层的第二端与所述第三金属层电性连接；其中，在所述第一金属层至所述第三金属层的方向上，所述第二金属层包括至少两个层叠设置的金属子层，相邻两个所述金属子层绝缘设置。
在本申请实施例提供的阵列基板中，所述有源层包括第一掺杂部、第二掺杂部以及沟道部，所述沟道部位于所述第一掺杂部和所述第二掺杂部之间；其中，所述第一掺杂部与所述第一金属层电性连接；所述第二掺杂部与所述第三金属层电性连接。
在本申请实施例提供的阵列基板中，所述第一掺杂部位于所述第一金属层面向所述第二金属层的一侧表面；所述第二掺杂部位于所述第三金属层远离所述第二金属层的一侧表面。
在本申请实施例提供的阵列基板中，所述有源层的材料为金属氧化物或非晶硅。
在本申请实施例提供的阵列基板中，所述薄膜晶体管还包括第一绝缘层、第二绝缘层以及第三绝缘层；所述第一绝缘层位于所述第二金属层与所述第一金属层之间；所述第二绝缘层位于所述第二金属层与所述第三金属层之间；所述第三绝缘层位于相邻的两个所述金属子层之间。
在本申请实施例提供的阵列基板中，在所述第一金属层至所述第三金属层的方向上，所述第一绝缘层和/或所述第二绝缘层的厚度大于所述第三绝缘层的厚度。
在本申请实施例提供的阵列基板中，在所述第一金属层至所述第三金属层的方向上，所述第一绝缘层、所述第二绝缘层以及所述第三绝缘层的厚度均大于或等于500埃且小于或等于4000埃。
在本申请实施例提供的阵列基板中，在所述第一金属层至所述第三金属层的方向上，所述第三绝缘层的厚度与所述第一绝缘层的厚度之比为第一比值，所述第三绝缘层的厚度与所述第二绝缘层的厚度之比为第二比值，所述第一比值和/或所述第二比值大于或等于五分之一且小于或等于二分之一。
在本申请实施例提供的阵列基板中，所述薄膜晶体管包括至少两个所述第三绝缘层，在所述第一金属层至所述第三金属层的方向上，至少两个所述第三绝缘层的厚度相等。
在本申请实施例提供的阵列基板中，在所述有源层至所述栅极绝缘层的方向上，所述栅极绝缘层至所述第一金属层的夹角大于或等于60度且小于或等于90度。
在本申请实施例提供的阵列基板中，所述电极层包括第一凹槽，所述第一凹槽从所述第三金属层延伸至所述第一金属层背离所述衬底层的表面，所述栅极绝缘层位于所述第一凹槽的内壁上。
在本申请实施例提供的阵列基板中，在所述薄膜晶体管的俯视图方向上，所述第一凹槽的形状为圆形或多边形。
在本申请实施例提供的阵列基板中，所述阵列基板包括至少两个所述薄膜晶体管，其中，所述电极层还包括第二凹槽和至少两个分割槽；所述第二凹槽贯穿所述有源层和所述第一金属层，所述第二凹槽与所述第一凹槽相连通，所述第二凹槽在所述衬底层上的正投影落在所述第一凹槽在所述衬底层上的正投影的范围内，所述第二凹槽与所述第一凹槽组合为通槽；所述分割槽贯穿所述电极层、所述栅极绝缘层以及所述有源层，至少两个所述分割槽与所述通槽相连通，至少两个所述分割槽围绕所述通槽设置，任一所述分割槽位于相邻的两个所述薄膜晶体管之间。
在本申请实施例提供的阵列基板中，在所述薄膜晶体管的俯视图方向上，至少两个所述薄膜晶体管的面积不相等。
在本申请实施例提供的阵列基板中，在所述薄膜晶体管的俯视图方向上，所述第二凹槽的形状为圆形或多边形。
在本申请实施例提供的阵列基板中，在所述薄膜晶体管的俯视图方向上，任一所述分割槽的形状为矩形或梯形。
本申请实施例提供一种阵列基板的制备方法，包括：在衬底层上依次形成构成电极层的第一金属层、第二金属层以及第三金属层，其中，所述第二金属层分别与所述第一金属层和所述第三金属层绝缘设置，在所述第一金属层至所述第三金属层的方向上，所述第二金属层包括至少两个层叠设置的金属子层，相邻两个所述金属子层绝缘设置；在所述电极层的侧壁上形成栅极绝缘层；在所述栅极绝缘层背离所述电极层的表面上形成有源层，所述有源层的第一端与所述第一金属层电性连接，所述有源层的第二端与所述第三金属层电性连接。
在本申请实施例提供的阵列基板的制备方法中，所述在所述电极层的侧壁上形成栅极绝缘层的步骤，包括：在所述电极层上形成第一凹槽，所述第一凹槽从所述第三金属层延伸至所述第一金属层背离所述衬底层的表面；在所述第一凹槽的内壁上形成栅极绝缘层。
在本申请实施例提供的阵列基板的制备方法中，所述阵列基板的制备方法还包括：在所述电极层上形成第二凹槽，所述第二凹槽贯穿所述有源层和所述第一金属层，所述第二凹槽与所述第一凹槽相连通，所述第二凹槽在所述衬底层上的正投影落在所述第一凹槽在所述衬底层上的正投影的范围内，所述第二凹槽与所述第一凹槽组合为通槽；在所述电极层上形成至少两个分割槽，所述分割槽贯穿所述电极层、所述栅极绝缘层以及所述有源层，至少两个所述分割槽与所述通槽相连通，至少两个所述分割槽围绕所述通槽设置，相邻的两个所述分割槽之间为一个薄膜晶体管。
本申请实施例还提供一种显示面板，包括阵列基板，所述阵列基板包括衬底层以及位于所述衬底层之上的至少一薄膜晶体管；其中，所述薄膜晶体管包括电极层、栅极绝缘层以及有源层；所述电极层包括层叠设置的第一金属层、第二金属层以及第三金属层，所述第二金属层分别与所述第一金属层和所述第三金属层绝缘设置；所述栅极绝缘层设置于所述电极层的侧壁上；所述有源层设置于所述栅极绝缘层背离所述电极层的表面上，所述有源层的第一端与所述第一金属层电性连接，所述有源层的第二端与所述第三金属层电性连接；其中，在所述第一金属层至所述第三金属层的方向上，所述第二金属层包括至少两个层叠设置的金属子层，相邻两个所述金属子层绝缘设置。
 有益效果
本申请实施例提供的一种阵列基板，包括衬底层以及位于衬底层之上的至少一薄膜晶体管；薄膜晶体管包括电极层、栅极绝缘层以及有源层；电极层包括层叠设置的第一金属层、第二金属层以及第三金属层，第二金属层分别与第一金属层和第三金属层绝缘设置；栅极绝缘层设置于电极层的侧壁上；有源层设置于栅极绝缘层背离电极层的表面上，有源层的第一端与第一金属层电性连接，有源层的第二端与第三金属层电性连接；其中，在第一金属层至第三金属层的方向上，第二金属层包括至少两个层叠设置的金属子层，相邻两个金属子层绝缘设置；本申请通过将构成电极层的第一金属层、第二金属层以及第三金属层层叠设置，并且将有源层的沟道设置在电极层的侧壁上，将第二金属层分为多个层叠设置的金属子层，可以通过对金属子层的厚度及数量进行调控，从而可以调控有源层的沟道的宽长比，达到灵活调节薄膜晶体管特性的目的。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。
图1是本申请实施例提供的阵列基板的基本结构示意图。
图2是本申请实施例提供的薄膜晶体管的俯视图。
图3是本申请实施例提供的另一阵列基板沿图2中A-A’方向的剖面图。
图4是本申请实施例提供的另一薄膜晶体管的俯视图。
图5是本申请实施例提供的又一阵列基板沿图4中B-B’方向的剖面图。
图6是本申请实施例提供的又一薄膜晶体管的俯视图。
图7是本申请实施例提供的阵列基板的制备方法流程图。
图8a~图8g是本申请实施例提供的阵列基板的制备工艺流程中各组件的基本结构示意图。
图9a~图9c是本申请实施例提供的另一阵列基板的制备工艺流程中各组件的基本结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。在附图中，为了清晰及便于理解和描述，附图中绘示的组件的尺寸和厚度并未按照比例。
如图1所示，为本申请实施例提供的阵列基板的基本结构示意图，所述阵列基板包括衬底层1以及位于所述衬底层1之上的至少一薄膜晶体管3；其中，所述薄膜晶体管3包括电极层30、栅极绝缘层31以及有源层32；所述电极层30包括层叠设置的第一金属层301、第二金属层302以及第三金属层303，所述第二金属层302分别与所述第一金属层301和所述第三金属层303绝缘设置；所述栅极绝缘层31设置于所述电极层30的侧壁上；所述有源层32设置于所述栅极绝缘层31背离所述电极层30的表面上，所述有源层32的第一端与所述第一金属层301电性连接，所述有源层32的第二端与所述第三金属层303电性连接；其中，在所述第一金属层301至所述第三金属层303的方向上，所述第二金属层302包括至少两个层叠设置的金属子层3021，相邻两个所述金属子层3021绝缘设置。
需要说明的是，所述栅极绝缘层31设置于所述电极层30的侧壁上，这里的侧壁指的是与所述电极层30所在的平面呈一定夹角的一个平面。结合图1来理解，所述电极层30所在的平面为水平面，即所述栅极绝缘层31所在的平面与水平面呈一定夹角。
可以理解的是，本申请实施例提供了一种垂直沟道的薄膜晶体管3结构。其中，第二金属层302对应栅极层，第一金属层301和第三金属层303与源极层和漏极层相对应。当第一金属层301对应源极层时，第三金属层303则对应漏极层；当第一金属层301对应漏极层时，第三金属层303则对应源极层。本申请的栅极绝缘层31和有源层32分别形成在电极层30的侧壁上，有源层32包括第一掺杂部321、第二掺杂部322以及沟道部323，沟道部323位于第一掺杂部321和第二掺杂部322之间。其中，第一掺杂部321与第一金属层301电性连接；第二掺杂部322与第三金属层303电性连接。从图1中可以看出，沟道部323与电极层30大致垂直，沟道部323的长度可通过调节金属子层3021的厚度H和数量来调节，图1中仅以第二金属层302包括3个金属子层3021为例进行绘示。
需要说明的是，薄膜晶体管3的特性之一为漏电流I ds，漏电流I ds指的是：在栅极(即第二金属层302)电压为0时，在一定的源漏极(即第一金属层301和第三金属层303)电压下源漏极之间的电流。当薄膜晶体管3工作在线性区时，漏电流I ds=μC i(W/L)[(V gs-V th)V ds-V ds 2/2]，其中，μ为迁移率，C i为栅极绝缘层31单位面积电容，W为沟道部323的宽度，L为沟道部323的长度，V gs为栅源电压，V ds为漏源电压，V th为阈值电压。从上述公式可以得出(W/L)越大，I ds会越大。假设沟道部323的宽度W保持不变的情况下，本申请实施例可通过调节金属子层3021的厚度H和数量，从而调节沟道部323的长度L，即可以调控有源层32的沟道部323的宽长比(W/L)，达到灵活调节薄膜晶体管3特性的目的。
需要说明的是，沟道部323的长度L是根据第二金属层302的厚度(即所有金属子层3021的厚度H累加之和)来决定的。具体的，因为单层金属的厚度太厚容易剥落，所以单层金属的厚度一般不会超过8000埃，这样就限制了对沟道部323的长度L的调控。本申请实施例通过将第二金属层302分为多个层叠设置的金属子层3021，多个金属子层3021的厚度H可以累积，在不使得金属子层3021剥落的前提下，通过调节金属子层3021的数量来灵活调节金属子层3021的厚度H累加之和。即本申请可以通过对金属子层3021的厚度H和数量的调节，可以灵活调节有源层32的沟道部323的宽长比(W/L)。
在一种实施例中，所述沟道部323的宽长比(W/L)的值在2左右。其中，根据薄膜晶体管3的作用不同，(W/L)的值不同，例如驱动薄膜晶体管和开关薄膜晶体管的(W/L)的值就不同。
在一种实施例中，所述第一掺杂部321位于所述第一金属层301面向所述第二金属层302的一侧表面；所述第二掺杂部322位于所述第三金属层303远离所述第二金属层302的一侧表面。即所述第一掺杂部321与所述第一金属层301未被所述第二金属层302和所述第三金属层303覆盖的部分电性连接。可以理解的是，在工艺制程中，通常采用离子植入机对半导体层进行掺杂，从而形成第一掺杂部321和第二掺杂部322，未进行掺杂的部分即为沟道部323，由于离子植入方向是朝向薄膜晶体管3至衬底层1的方向，即位于第一金属层301面向第二金属层302的一侧以及第三金属层303远离第二金属层302的一侧会被掺杂。需要说明的是，本实施例以第一金属层301靠近衬底层1设置来进行说明，在其他实施例中，也可以是第三金属层303靠近衬底层1设置，当第三金属层303靠近衬底层1设置时，所述第一掺杂部321位于所述第三金属层303面向所述第二金属层302的一侧表面；所述第二掺杂部322位于所述第一金属层301远离所述第二金属层302的一侧表面。
在一种实施例中，当第一金属层301靠近衬底层1设置时，第一金属层301为源极层，第三金属层303为漏极层；当第三金属层303靠近衬底层1设置时，第三金属层303为源极层，第一金属层301为漏极层。可以理解的是，薄膜晶体管3需要通过过孔将漏极层向薄膜晶体管3的外部进行连线，本实施例通过将漏极层设置在远离衬底层1的一侧更加方便连线。
在一种实施例中，所述有源层32的材料为金属氧化物或非晶硅。可以理解的是，低温多晶硅需要将非晶硅进行晶化，此过程需要一个平整的表面。本申请提供的有源层32一部分位于第一金属层301和第三金属层303上，另一部分位于电极层30的侧壁上，并不是一个平整的表面。因此，本申请实施例提供的有源层32不适于采用低温多晶硅制备。
在一种实施例中，所述薄膜晶体管3还包括第一绝缘层304、第二绝缘层305以及第三绝缘层306；所述第一绝缘层304位于所述第二金属层302与所述第一金属层301之间；所述第二绝缘层305位于所述第二金属层302与所述第三金属层303之间；所述第三绝缘层306位于相邻的两个所述金属子层3021之间。可以理解的是，本实施例通过在相邻的两个金属子层3021之间设置第三绝缘层306，第三绝缘层306的电阻与多个金属子层3021的电阻串联，相当于增大了第一金属层301和第三金属层303之间的等效电阻，从而可以减小第一金属层301和第三金属层303之间的漏电流。即本申请通过将第二金属层302设置为金属子层3021和第三绝缘层306的交叠结构，相邻金属子层3021之间采用第三绝缘层306隔开，可以有效减小薄膜晶体管3的漏电流。
在一种实施例中，所述第一绝缘层304、所述第二绝缘层305以及所述第三绝缘层306的材料为二氧化硅或氮化硅。
在一种实施例中，在所述第一金属层301至所述第三金属层303的方向上，所述第一绝缘层304和/或所述第二绝缘层305的厚度大于所述第三绝缘层306的厚度。可以理解的是，第一绝缘层304位于第一金属层301和第二金属层302之间，第二绝缘层305位于第二金属层302和第三金属层303之间，即第一绝缘层304和第二绝缘层305主要作为间隔层，起到隔绝的作用。在第一金属层301至第三金属层303的方向上，本实施例通过将第三绝缘层306的厚度设置为小于第一绝缘层304和/或第二绝缘层305的厚度，可以起到减小多个金属子层3021之间的应力的作用，防止应力过大导致金属子层3021与第三绝缘层306剥离。
在一种实施例中，在第一金属层301至第三金属层303的方向上，第一绝缘层304、第二绝缘层305以及第三绝缘层306的厚度均大于或等于500埃且小于或等于4000埃，以防止因第一绝缘层304、第二绝缘层305以及第三绝缘层306的厚度太厚使得有源层32的沟道部323无法导通。
在一种实施例中，在所述第一金属层301至所述第三金属层303的方向上，所述第三绝缘层306的厚度与所述第一绝缘层304的厚度之比为第一比值，所述第三绝缘层306的厚度与所述第二绝缘层305的厚度之比为第二比值，所述第一比值和/或所述第二比值大于或等于五分之一且小于或等于二分之一。
在一种实施例中，所述薄膜晶体管3包括至少两个所述第三绝缘层306，在所述第一金属层301至所述第三金属层303的方向上，至少两个所述第三绝缘层306的厚度相等。
在一种实施例中，所述阵列基板还包括第四绝缘层2，所述第四绝缘层2位于衬底层1和薄膜晶体管3之间。所述第四绝缘层2的材料为二氧化硅或氮化硅。在第一金属层301至第三金属层303的方向上，所述第四绝缘层2的厚度大于或等于4000埃且小于或等于8000埃。所述第四绝缘层2可以起到阻挡作用，以防止衬底层1中的碱性离子扩散到薄膜晶体管3中，还可以隔绝空气中的水氧。
在一种实施例中，所述阵列基板还包括钝化层4，所述钝化层4位于所述第四绝缘层2上，所述钝化层4覆盖至少一个所述薄膜晶体管3。
在一种实施例中，在所述有源层32至所述栅极绝缘层31的方向上，所述栅极绝缘层31至所述第一金属层301的夹角C大于或等于60度且小于或等于90度。可以理解的是，由于有源层32位于栅极绝缘层31背离电极层30的表面上，即有源层32的沟道部323所在的平面与栅极绝缘层31所在的平面相互平行。因此，有源层32的沟道部323相对于第一金属层301的倾斜角度与所述夹角C相等。当有源层32的沟道部323相对于第一金属层301的倾斜角度在60度至90度之间时，在进行离子植入制程时，沟道部323的掺杂量会很少甚至无掺杂，避免掺杂离子对沟道部323的电流效率产生影响。
在一种实施例中，当倾斜角度为90度时，有源层32可以通过原子沉积的方法形成。可以理解的是，当倾斜角度为90度时，栅极绝缘层31与衬底层1垂直，采用普通的物理沉积方法沉积有源层32，无法覆盖栅极绝缘层31。而原子沉积是一种化学沉积方法，是通过将气相前驱体脉冲交替地通入反应器并在沉积基体上化学吸附并反应而形成沉积膜的一种方法。因此，即使栅极绝缘层31与衬底层1垂直，也不影响气相前驱体与沉积基体化学吸附并发生表面反应，形成的有源层32能覆盖栅极绝缘层31。
接下来，请参阅图2和图3，分别为本申请实施例提供的薄膜晶体管的俯视图和本申请实施例提供的另一阵列基板沿图2中A-A’方向的剖面图，与图1实施例提供的阵列基板不同的是，本实施例中的所述电极层30包括第一凹槽307，所述第一凹槽307从所述第三金属层303延伸至所述第一金属层301背离所述衬底层1的表面，所述栅极绝缘层31位于所述第一凹槽307的内壁上。可以理解的是，本实施例通过在电极层30上刻蚀出第一凹槽307，以暴露出靠近衬底层1设置的第一金属层301，通过将栅极绝缘层31设置在第一凹槽307的内壁上，再将有源层32设置在栅极绝缘层31背离电极层30的表面，有源层32的第一端位于第一凹槽307的底部，与暴露出的第一金属层301电性连接，有源层32的第二端位于第三金属层303远离第二金属层302的一侧表面，与第三金属层303电性连接，第一端与第二端之间的沟道位于栅极绝缘层31的斜面上，与电极层30大致垂直，即形成了垂直沟道的薄膜晶体管3结构。
在一种实施例中，在所述薄膜晶体管3的俯视图方向上，所述第一凹槽307的形状为圆形或多边形。具体的，请参阅图2，本实施例以第一凹槽307的俯视图为正方形为例进行绘示。可以理解的是，图2和图3中仅以衬底层1上设置有一个薄膜晶体管3为例进行说明，图2和图3中的薄膜晶体管3的沟道部323的宽度对应于所述第一凹槽307的内壁的周长W(如图2)。需要说明的是，衬底层1上可以设置多个如图2和图3所述的薄膜晶体管3。
接下来，以衬底层1上设置有至少两个薄膜晶体管3为例进行说明，请参阅图4和图5，为本申请实施例提供的另一薄膜晶体管的俯视图和本申请实施例提供的又一阵列基板沿图4中B-B’方向的剖面图，所述阵列基板包括衬底层1以及位于所述衬底层1之上的至少一薄膜晶体管3；其中，所述薄膜晶体管3包括电极层30、栅极绝缘层31以及有源层32；所述电极层30包括层叠设置的第一金属层301、第二金属层302以及第三金属层303，所述第二金属层302分别与所述第一金属层301和所述第三金属层303绝缘设置；所述栅极绝缘层31设置于所述电极层30的侧壁上；所述有源层32设置于所述栅极绝缘层31背离所述电极层30的表面上，所述有源层32的第一端与所述第一金属层301电性连接，所述有源层32的第二端与所述第三金属层303电性连接；其中，在所述第一金属层301至所述第三金属层303的方向上，所述第二金属层302包括至少两个层叠设置的金属子层3021，相邻两个所述金属子层3021绝缘设置。
在本实施例中，所述电极层30包括第一凹槽307，所述第一凹槽307从所述第三金属层303延伸至所述第一金属层301背离所述衬底层1的表面，所述栅极绝缘层31位于所述第一凹槽307的内壁上。
在一种实施例中，在所述薄膜晶体管3的俯视图方向上，所述第一凹槽307的形状为圆形或多边形。具体的，请参阅图4，本实施例以第一凹槽307的俯视图为正方形为例进行绘示。
在一种实施例中，所述阵列基板包括至少两个所述薄膜晶体管3，其中，所述电极层30还包括第二凹槽308和至少两个分割槽309；所述第二凹槽308贯穿所述有源层32和所述第一金属层301，所述第二凹槽308与所述第一凹槽307相连通，所述第二凹槽308在所述衬底层1上的正投影落在所述第一凹槽307在所述衬底层1上的正投影的范围内，所述第二凹槽308与所述第一凹槽307组合为通槽；所述分割槽309贯穿所述电极层30、所述栅极绝缘层31以及所述有源层32，至少两个所述分割槽309与所述通槽相连通，至少两个所述分割槽309围绕所述通槽设置，任一所述分割槽309位于相邻的两个所述薄膜晶体管3之间。
可以理解的是，本实施例与图2和图3的实施例不同的是，本实施例还设置有第二凹槽308和至少两个分割槽309(图4中仅绘示出两个分割槽309为例进行说明)，其中，第二凹槽308在第一凹槽307的基础上，继续向下蚀刻，贯穿了有源层32和第一金属层301，第二凹槽308与第一凹槽307组合为通槽，所述通槽贯穿了整个薄膜晶体管3，本实施例再通过设置至少两个分割槽309，至少两个分割槽309与所述通槽相连通，至少两个分割槽309也贯穿了整个薄膜晶体管3，即所述第一凹槽307、所述第二凹槽308以及至少两个所述分割槽309共同作用可将1个薄膜晶体管分割成至少2个薄膜晶体管。
在一种实施例中，在所述薄膜晶体管3的俯视图方向上，至少两个所述薄膜晶体管3的面积不相等，此实施例未进行图示。可以理解的是，图4中以电极层30包括两个分割槽309为例进行绘示，在图4中，两个分割槽309关于所述通槽对称分布，使得分割后的2个薄膜晶体管在俯视图上的面积相等。但是在其他实施例中，当分割槽309不对称分布时，可分割出面积不相等的薄膜晶体管，面积不相等的薄膜晶体管具有不同的沟道宽度W，此时薄膜晶体管的沟道长度L已固定不变，可通过调整分割槽309的位置从而形成不同的宽长比(W/L)，以满足驱动电路中不同薄膜晶体管的需求。
在一种实施例中，在所述薄膜晶体管3的俯视图方向上，所述第二凹槽308的形状为圆形或多边形。具体的，请参阅图4，本实施例以第二凹槽308的俯视图为正方形为例进行绘示。
在一种实施例中，在所述薄膜晶体管3的俯视图方向上，任一所述分割槽309的形状为矩形或梯形。具体的，请参阅图4，本实施例以分割槽309的俯视图为矩形为例进行绘示。
需要说明的是，图4和图5中仅以衬底层1上设置有两个薄膜晶体管3为例进行说明，图4和图5中两个薄膜晶体管3的沟道部323的宽度W以及两个分割槽309的宽度之和，对应于所述第一凹槽307的内壁的周长。需要说明的是，衬底层1上可以设置多组如图4和图5所述的两个薄膜晶体管3。
接下来，请参阅图6，为本申请实施例提供的又一薄膜晶体管的俯视图，所述电极层30(如图5)还包括第二凹槽308和四个分割槽309；所述第二凹槽308贯穿所述有源层32(如图5)和所述第一金属层301(如图5)，所述第二凹槽308与所述第一凹槽307相连通，所述第二凹槽308在所述衬底层1(如图5)上的正投影落在所述第一凹槽307在所述衬底层1上的正投影的范围内，所述第二凹槽308与所述第一凹槽307组合为通槽；所述分割槽309贯穿所述电极层30、所述栅极绝缘层31(如图5)以及所述有源层32，四个所述分割槽309与所述通槽相连通，四个所述分割槽309围绕所述通槽设置，任一所述分割槽309位于相邻的两个所述薄膜晶体管之间。
可以理解的是，本实施例与图4和图5的实施例不同的是，电极层30包括四个分割槽309。其中，四个分割槽309均与所述通槽相连通，四个分割槽309均贯穿了整个薄膜晶体管，即所述第一凹槽307、所述第二凹槽308以及四个所述分割槽309共同作用可将1个薄膜晶体管分割成4个薄膜晶体管。
在一种实施例中，在所述薄膜晶体管的俯视图方向上，任一所述分割槽309的形状为矩形或梯形。具体的，请参阅图6，本实施例以分割槽309的俯视图为梯形为例进行绘示。
需要说明的是，图6中仅以衬底层1(如图5)上设置有4个薄膜晶体管为例进行说明，图6中四个薄膜晶体管的沟道部323的宽度W以及四个分割槽309的宽度之和，对应于所述第一凹槽307的内壁的周长。需要说明的是，衬底层1上可以设置多组如图6所述的4个薄膜晶体管。
需要说明的是，采用本申请实施例提供的阵列基板的结构，1个薄膜晶体管不仅可以分割成2个或4个，还可以分割成3个、5个等。本申请实施例提供的薄膜晶体管不单独对应子像素，可以按一定的驱动连接方式连接形成驱动电路。
接下来，请参阅图7，为本申请实施例提供的阵列基板的制备方法流程图，所述制备方法包括：
S10、在衬底层上依次形成构成电极层的第一金属层、第二金属层以及第三金属层，其中，所述第二金属层分别与所述第一金属层和所述第三金属层绝缘设置，在所述第一金属层至所述第三金属层的方向上，所述第二金属层包括至少两个层叠设置的金属子层，相邻两个所述金属子层绝缘设置；
S20、在所述电极层的侧壁上形成栅极绝缘层；
S30、在所述栅极绝缘层背离所述电极层的表面上形成有源层，所述有源层的第一端与所述第一金属层电性连接，所述有源层的第二端与所述第三金属层电性连接。
可以理解的是，本申请通过将构成电极层的第一金属层、第二金属层以及第三金属层依次层叠形成，并且将栅极绝缘层和有源层形成在电极层的侧壁上，形成垂直沟道的薄膜晶体管结构；将第二金属层分为多个层叠设置的金属子层，可以通过对金属子层的厚度及数量进行调控，从而可以调控有源层的沟道的宽长比，达到灵活调节薄膜晶体管特性的目的。
需要说明的是，第二金属层对应栅极层，第一金属层和第三金属层与源极层和漏极层相对应。当第一金属层对应源极层时，第三金属层则对应漏极层；当第一金属层对应漏极层时，第三金属层则对应源极层。本申请的栅极绝缘层和有源层分别形成在电极层的侧壁上，有源层包括第一掺杂部、第二掺杂部以及沟道部，沟道部位于第一掺杂部和第二掺杂部之间。其中，第一掺杂部与第一金属层电性连接；第二掺杂部与第三金属层电性连接。
需要说明的是，单层金属的厚度太厚容易剥落，所以单层金属的厚度一般不会超过8000埃。本申请实施例通过将第二金属层分为多个层叠设置的金属子层，多个金属子层的厚度可以累积，在不使得金属子层剥落的前提下，通过调节金属子层的数量来灵活调节金属子层的厚度累加之和。即本申请可以通过对金属子层的厚度和数量的调节，可以灵活调节有源层的沟道部的宽长比(W/L)。
需要说明的是，本实施例以第一金属层靠近衬底层设置来进行说明，在其他实施例中，也可以是第三金属层靠近衬底层设置。当第一金属层靠近衬底层设置时，第一金属层为源极层，第三金属层为漏极层；当第三金属层靠近衬底层设置时，第三金属层为源极层，第一金属层为漏极层。可以理解的是，薄膜晶体管需要通过过孔将漏极层向薄膜晶体管的外部进行连线，本实施例通过将漏极层设置在远离衬底层的一侧更加方便连线。
在一种实施例中，所述有源层的材料为金属氧化物或非晶硅。可以理解的是，低温多晶硅需要将非晶硅进行晶化，此过程需要一个平整的表面。本申请提供的有源层一部分位于第一金属层和第三金属层上，另一部分位于电极层的侧壁上，并不是一个平整的表面。因此，本申请实施例提供的有源层不适于采用低温多晶硅制备。
在一种实施例中，所述薄膜晶体管还包括第一绝缘层、第二绝缘层以及第三绝缘层；所述第一绝缘层位于所述第二金属层与所述第一金属层之间；所述第二绝缘层位于所述第二金属层与所述第三金属层之间；所述第三绝缘层位于相邻的两个所述金属子层之间。可以理解的是，本实施例通过在相邻的两个金属子层之间设置第三绝缘层，第三绝缘层的电阻与多个金属子层的电阻串联，相当于增大了第一金属层和第三金属层之间的等效电阻，从而可以减小第一金属层和第三金属层之间的漏电流。即本申请通过将第二金属层设置为金属子层和第三绝缘层的交叠结构，相邻金属子层之间采用第三绝缘层隔开，可以有效减小薄膜晶体管的漏电流。
在一种实施例中，所述第一绝缘层、所述第二绝缘层以及所述第三绝缘层的材料为二氧化硅或氮化硅。
在一种实施例中，在所述第一金属层至所述第三金属层的方向上，所述第一绝缘层和/或所述第二绝缘层的厚度大于所述第三绝缘层的厚度。可以理解的是，第一绝缘层位于第一金属层和第二金属层之间，第二绝缘层位于第二金属层和第三金属层之间，即第一绝缘层和第二绝缘层主要作为间隔层，起到隔绝的作用。在第一金属层至第三金属层的方向上，本实施例通过将第三绝缘层的厚度设置为小于第一绝缘层和/或第二绝缘层的厚度，可以起到减小多个金属子层之间的应力的作用，防止应力过大导致金属子层与第三绝缘层剥离。
在一种实施例中，在第一金属层至第三金属层的方向上，第一绝缘层、第二绝缘层以及第三绝缘层的厚度均大于或等于500埃且小于或等于4000埃，以防止因第一绝缘层、第二绝缘层以及第三绝缘层的厚度太厚使得有源层的沟道部无法导通。
在一种实施例中，所述阵列基板还包括第四绝缘层，所述第四绝缘层位于衬底层和薄膜晶体管之间。所述第四绝缘层的材料为二氧化硅或氮化硅。在第一金属层至第三金属层的方向上，所述第四绝缘层的厚度大于或等于4000埃且小于或等于8000埃。所述第四绝缘层可以起到阻挡作用，以防止衬底层中的碱性离子扩散到薄膜晶体管中，还可以隔绝空气中的水氧。
在一种实施例中，所述阵列基板还包括钝化层，所述钝化层位于所述第四绝缘层上，所述钝化层覆盖至少一个所述薄膜晶体管。
在一种实施例中，在所述有源层至所述栅极绝缘层的方向上，所述栅极绝缘层至所述第一金属层的夹角大于或等于60度且小于或等于90度。可以理解的是，由于有源层位于栅极绝缘层背离电极层的表面上，即有源层的沟道部所在的平面与栅极绝缘层所在的平面相互平行。因此，有源层的沟道部相对于第一金属层的倾斜角度与所述夹角相等。当有源层的沟道部相对于第一金属层的倾斜角度在60度至90度之间时，在进行离子植入制程时，沟道部的掺杂量会很少甚至无掺杂，避免掺杂离子对沟道部的电流效率产生影响。
在一种实施例中，当倾斜角度为90度时，有源层可以通过原子沉积的方法形成。可以理解的是，当倾斜角度为90度时，栅极绝缘层与衬底层垂直，采用普通的物理沉积方法沉积有源层，无法覆盖栅极绝缘层。而原子沉积是一种化学沉积方法，是通过将气相前驱体脉冲交替地通入反应器并在沉积基体上化学吸附并反应而形成沉积膜的一种方法。因此，即使栅极绝缘层与衬底层垂直，也不影响气相前驱体与沉积基体化学吸附并发生表面反应，形成的有源层能覆盖栅极绝缘层。
在一种实施例中，所述在所述电极层的侧壁上形成栅极绝缘层的步骤，包括：在所述电极层上形成第一凹槽，所述第一凹槽从所述第三金属层延伸至所述第一金属层背离所述衬底层的表面；在所述第一凹槽的内壁上形成栅极绝缘层。
在一种实施例中，所述阵列基板的制备方法还包括：在所述电极层上形成第二凹槽，所述第二凹槽贯穿所述有源层和所述第一金属层，所述第二凹槽与所述第一凹槽相连通，所述第二凹槽在所述衬底层上的正投影落在所述第一凹槽在所述衬底层上的正投影的范围内，所述第二凹槽与所述第一凹槽组合为通槽；在所述电极层上形成至少两个分割槽，所述分割槽贯穿所述电极层、所述栅极绝缘层以及所述有源层，至少两个所述分割槽与所述通槽相连通，至少两个所述分割槽围绕所述通槽设置，相邻的两个所述分割槽之间为一个薄膜晶体管。
接下来，请参阅图8a~图8g，为本申请实施例提供的阵列基板的制备工艺流程中各组件的基本结构示意图，首先如图8a所示，在衬底层1上依次沉积第四绝缘层2、第一金属层301、第一绝缘层304、第二金属层302、第二绝缘层305以及第三金属层303，其中，所述第二金属层302包括至少两个沿所述第一金属层301至所述第三金属层303的方向层叠设置且相互绝缘的金属子层3021(图8a以第二金属层302包括3个金属子层3021为例进行绘示)，相邻的两个金属子层3021之间通过第三绝缘层306间隔开。其中，第一金属层301、第二金属层302以及第三金属层303构成电极层30。
接下来，如图8b所示，在所述电极层30上形成第一凹槽307，所述第一凹槽307从所述第三金属层303延伸至所述第一金属层301背离所述衬底层1的表面。
接下来，如图8c所示，在所述电极层30上沉积一层绝缘层300。
接下来，如图8d所示，图案化所述绝缘层300，形成栅极绝缘层31，所述栅极绝缘层31位于所述第一凹槽307的内壁上。
接下来，如图8e所示，在所述电极层30上沉积一层半导体层400。
接下来，如图8f所示，图案化所述半导体层400，形成有源层32。对所述有源层32进行离子掺杂，形成第一掺杂部321、第二掺杂部322以及沟道部323，即制备完成一个薄膜晶体管3。沟道部323位于第一掺杂部321和第二掺杂部322之间。其中，第一掺杂部321与第一金属层301电性连接；第二掺杂部322与第三金属层303电性连接。其中，在所述有源层32至所述栅极绝缘层31的方向上，所述栅极绝缘层31至所述第一金属层301的夹角C大于或等于60度且小于或等于90度。可以理解的是，由于有源层32位于栅极绝缘层31背离电极层30的表面上，即有源层32的沟道部323所在的平面与栅极绝缘层31所在的平面相互平行。因此，有源层32的沟道部323相对于第一金属层301的倾斜角度与所述夹角C相等。当有源层32的沟道部323相对于第一金属层301的倾斜角度在60度至90度之间时，在进行离子植入制程时，沟道部323的掺杂量会很少甚至无掺杂，避免掺杂离子对沟道部323的电流效率产生影响。
最后，如图8g所示，在所述第四绝缘层2之上形成钝化层4，所述钝化层4覆盖所述薄膜晶体管层3。
需要说明的是，本实施例提供的阵列基板的制备工艺流程，仅以衬底层1上设置有一个薄膜晶体管3为例进行说明。
在一种实施例中，在图案化所述半导体层400形成有源层32之后，在对所述有源层32进行离子掺杂之前，还包括步骤：在对应于所述第一凹槽307的内壁的所述有源层32远离所述栅极绝缘层31的一侧表面形成掺杂保护层(未图示)。可以理解的是，本实施例通过在对应于沟道部323的区域先形成掺杂保护层，再进行离子掺杂，如此便不会将掺杂离子注入沟道部323，采用本实施例的制备方法可不用再限制栅极绝缘层31与第一金属层301之间的夹角C的大小。
接下来，请参阅图9a~图9c，为本申请实施例提供的另一阵列基板的制备工艺流程中各组件的基本结构示意图，首先，在进行如图9a的步骤之前，需先进行图8a至图8f的步骤，即本实施例是在图8f的基础上继续实施的。
如图9a所示，在所述电极层30上形成第二凹槽308，所述第二凹槽308贯穿所述有源层32和所述第一金属层301，所述第二凹槽308与所述第一凹槽307相连通，所述第二凹槽308在所述衬底层1上的正投影落在所述第一凹槽307在所述衬底层1上的正投影的范围内，所述第二凹槽308与所述第一凹槽307组合为通槽。
接下来，如图9b所示，在所述电极层30上形成四个分割槽309，所述分割槽309贯穿所述电极层30、所述栅极绝缘层31以及所述有源层32，四个所述分割槽309与所述通槽相连通，四个所述分割槽309围绕所述通槽设置，相邻的两个所述分割槽309之间为一个薄膜晶体管。
最后，如图9c所示，在所述第四绝缘层2之上形成钝化层4，所述钝化层4覆盖所述薄膜晶体管3。
需要说明的是，本实施例提供的阵列基板的制备工艺流程，仅以1个薄膜晶体管分割成4个薄膜晶体管为例进行说明，还可以分割成2个、3个、5个等。
本申请实施例还提供一种显示面板，包括上述的阵列基板。本申请实施例提供的显示面板可以为液晶显示面板或有机发光二极管显示面板。
本申请实施例还提供一种显示终端，包括上述的显示面板。本申请实施例提供的显示终端可以为：手机、平板电脑、笔记本电脑、电视机、数码相机、导航仪等具有显示功能的产品或部件。
综上所述，本申请实施例提供的一种阵列基板，包括衬底层以及位于衬底层之上的至少一薄膜晶体管；薄膜晶体管包括电极层、栅极绝缘层以及有源层；电极层包括层叠设置的第一金属层、第二金属层以及第三金属层，第二金属层分别与第一金属层和第三金属层绝缘设置；栅极绝缘层设置于电极层的侧壁上；有源层设置于栅极绝缘层背离电极层的表面上，有源层的第一端与第一金属层电性连接，有源层的第二端与第三金属层电性连接；其中，在第一金属层至第三金属层的方向上，第二金属层包括至少两个层叠设置的金属子层，相邻两个金属子层绝缘设置；本申请通过将构成电极层的第一金属层、第二金属层以及第三金属层层叠设置，并且将有源层的沟道设置在电极层的侧壁上，将第二金属层分为多个层叠设置的金属子层，可以通过对金属子层的厚度及数量进行调控，从而可以调控有源层的沟道的宽长比，达到灵活调节薄膜晶体管特性的目的，解决了现有技术的阵列基板的TFT的有源层的沟道的宽长比受到工艺线宽及布线的限制，不能灵活调节的技术问题。
以上对本申请实施例所提供的一种阵列基板及其制备方法、显示面板进行了详细介绍。应理解，本文所述的示例性实施方式应仅被认为是描述性的，用于帮助理解本申请的方法及其核心思想，而并不用于限制本申请。

Claims (20)

  1. 一种阵列基板，其包括衬底层以及位于所述衬底层之上的至少一薄膜晶体管；其中，所述薄膜晶体管包括：
    电极层，包括层叠设置的第一金属层、第二金属层以及第三金属层，所述第二金属层分别与所述第一金属层和所述第三金属层绝缘设置；
    栅极绝缘层，设置于所述电极层的侧壁上；
    有源层，设置于所述栅极绝缘层背离所述电极层的表面上，所述有源层的第一端与所述第一金属层电性连接，所述有源层的第二端与所述第三金属层电性连接；
    其中，在所述第一金属层至所述第三金属层的方向上，所述第二金属层包括至少两个层叠设置的金属子层，相邻两个所述金属子层绝缘设置。
  2. 如权利要求1所述的阵列基板，其中，所述有源层包括第一掺杂部、第二掺杂部以及沟道部，所述沟道部位于所述第一掺杂部和所述第二掺杂部之间；
    其中，所述第一掺杂部与所述第一金属层电性连接，所述第二掺杂部与所述第三金属层电性连接。
  3. 如权利要求2所述的阵列基板，其中，所述第一掺杂部位于所述第一金属层面向所述第二金属层的一侧表面，所述第二掺杂部位于所述第三金属层远离所述第二金属层的一侧表面。
  4. 如权利要求2所述的阵列基板，其中，所述有源层的材料为金属氧化物或非晶硅。
  5. 如权利要求1所述的阵列基板，其中，所述薄膜晶体管还包括：
    第一绝缘层，位于所述第二金属层与所述第一金属层之间；
    第二绝缘层，位于所述第二金属层与所述第三金属层之间；
    第三绝缘层，位于相邻的两个所述金属子层之间。
  6. 如权利要求5所述的阵列基板，其中，在所述第一金属层至所述第三金属层的方向上，所述第一绝缘层和/或所述第二绝缘层的厚度大于所述第三绝缘层的厚度。
  7. 如权利要求6所述的阵列基板，其中，在所述第一金属层至所述第三金属层的方向上，所述第一绝缘层、所述第二绝缘层以及所述第三绝缘层的厚度均大于或等于500埃且小于或等于4000埃。
  8. 如权利要求7所述的阵列基板，其中，在所述第一金属层至所述第三金属层的方向上，所述第三绝缘层的厚度与所述第一绝缘层的厚度之比为第一比值，所述第三绝缘层的厚度与所述第二绝缘层的厚度之比为第二比值，所述第一比值和/或所述第二比值大于或等于五分之一且小于或等于二分之一。
  9. 如权利要求5所述的阵列基板，其中，所述薄膜晶体管包括至少两个所述第三绝缘层，在所述第一金属层至所述第三金属层的方向上，至少两个所述第三绝缘层的厚度相等。
  10. 如权利要求1所述的阵列基板，其中，在所述有源层至所述栅极绝缘层的方向上，所述栅极绝缘层至所述第一金属层的夹角大于或等于60度且小于或等于90度。
  11. 如权利要求1所述的阵列基板，其中，所述电极层包括第一凹槽，所述第一凹槽从所述第三金属层延伸至所述第一金属层背离所述衬底层的表面，所述栅极绝缘层位于所述第一凹槽的内壁上。
  12. 如权利要求11所述的阵列基板，其中，在所述薄膜晶体管的俯视图方向上，所述第一凹槽的形状为圆形或多边形。
  13. 如权利要求11所述的阵列基板，其中，所述阵列基板包括至少两个所述薄膜晶体管，其中，所述电极层还包括第二凹槽和至少两个分割槽；
    所述第二凹槽贯穿所述有源层和所述第一金属层，所述第二凹槽与所述第一凹槽相连通，所述第二凹槽在所述衬底层上的正投影落在所述第一凹槽在所述衬底层上的正投影的范围内，所述第二凹槽与所述第一凹槽组合为通槽；
    所述分割槽贯穿所述电极层、所述栅极绝缘层以及所述有源层，至少两个所述分割槽与所述通槽相连通，至少两个所述分割槽围绕所述通槽设置，任一所述分割槽位于相邻的两个所述薄膜晶体管之间。
  14. 如权利要求13所述的阵列基板，其中，在所述薄膜晶体管的俯视图方向上，至少两个所述薄膜晶体管的面积不相等。
  15. 如权利要求13所述的阵列基板，其中，在所述薄膜晶体管的俯视图方向上，所述第二凹槽的形状为圆形或多边形。
  16. 如权利要求13所述的阵列基板，其中，在所述薄膜晶体管的俯视图方向上，任一所述分割槽的形状为矩形或梯形。
  17. 一种阵列基板的制备方法，其包括：
    在衬底层上依次形成构成电极层的第一金属层、第二金属层以及第三金属层，其中，所述第二金属层分别与所述第一金属层和所述第三金属层绝缘设置，在所述第一金属层至所述第三金属层的方向上，所述第二金属层包括至少两个层叠设置的金属子层，相邻两个所述金属子层绝缘设置；
    在所述电极层的侧壁上形成栅极绝缘层；
    在所述栅极绝缘层背离所述电极层的表面上形成有源层，所述有源层的第一端与所述第一金属层电性连接，所述有源层的第二端与所述第三金属层电性连接。
  18. 如权利要求17所述的阵列基板的制备方法，其中，所述在所述电极层的侧壁上形成栅极绝缘层的步骤，包括：
    在所述电极层上形成第一凹槽，所述第一凹槽从所述第三金属层延伸至所述第一金属层背离所述衬底层的表面；
    在所述第一凹槽的内壁上形成栅极绝缘层。
  19. 如权利要求18所述的阵列基板的制备方法，其中，所述阵列基板的制备方法还包括：
    在所述电极层上形成第二凹槽，所述第二凹槽贯穿所述有源层和所述第一金属层，所述第二凹槽与所述第一凹槽相连通，所述第二凹槽在所述衬底层上的正投影落在所述第一凹槽在所述衬底层上的正投影的范围内，所述第二凹槽与所述第一凹槽组合为通槽；
    在所述电极层上形成至少两个分割槽，所述分割槽贯穿所述电极层、所述栅极绝缘层以及所述有源层，至少两个所述分割槽与所述通槽相连通，至少两个所述分割槽围绕所述通槽设置，相邻的两个所述分割槽之间为一个薄膜晶体管。
  20. 一种显示面板，其包括阵列基板，所述阵列基板包括衬底层以及位于所述衬底层之上的至少一薄膜晶体管；其中，所述薄膜晶体管包括：
    电极层，包括层叠设置的第一金属层、第二金属层以及第三金属层，所述第二金属层分别与所述第一金属层和所述第三金属层绝缘设置；
    栅极绝缘层，设置于所述电极层的侧壁上；
    有源层，设置于所述栅极绝缘层背离所述电极层的表面上，所述有源层的第一端与所述第一金属层电性连接，所述有源层的第二端与所述第三金属层电性连接；
    其中，在所述第一金属层至所述第三金属层的方向上，所述第二金属层包括至少两个层叠设置的金属子层，相邻两个所述金属子层绝缘设置。
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