WO2023093103A1 - 像素电路及其驱动方法和显示面板 - Google Patents

像素电路及其驱动方法和显示面板 Download PDF

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Publication number
WO2023093103A1
WO2023093103A1 PCT/CN2022/108517 CN2022108517W WO2023093103A1 WO 2023093103 A1 WO2023093103 A1 WO 2023093103A1 CN 2022108517 W CN2022108517 W CN 2022108517W WO 2023093103 A1 WO2023093103 A1 WO 2023093103A1
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Prior art keywords
module
transistor
pole
sub
voltage
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PCT/CN2022/108517
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English (en)
French (fr)
Inventor
郭恩卿
盖翠丽
李俊峰
陈发祥
潘康观
邢汝博
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云谷（固安）科技有限公司
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Priority to EP22897199.0A priority Critical patent/EP4297007A1/en
Priority to KR1020237033535A priority patent/KR20230148378A/ko
Publication of WO2023093103A1 publication Critical patent/WO2023093103A1/zh
Priority to US18/240,713 priority patent/US20230410745A1/en

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
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    • G—PHYSICS
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    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the embodiments of the present application relate to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display panel.
  • organic light emitting diode Organic Light Emitting Diode, OLED
  • OLED Organic Light Emitting Diode
  • a display panel generally includes a plurality of pixel circuits, wherein the pixel circuits include driving transistors that generate driving signals to drive light-emitting elements to emit light for display.
  • the pixel circuits include driving transistors that generate driving signals to drive light-emitting elements to emit light for display.
  • PPI Pixel Per Inch
  • Embodiments of the present application provide a pixel circuit, a driving method thereof, and a display panel, so as to improve the layout of the pixel circuit and reduce the layout area of the pixel, thereby improving PPI.
  • the embodiment of the present application provides a pixel circuit, including: a driving module, a data writing module, an auxiliary module, a compensation module, a storage module, a coupling module and a light emitting module;
  • the data writing module is configured to write a voltage related to the data voltage to the control terminal of the driving module through the auxiliary module;
  • the compensation module is connected between the first terminal and the control terminal of the driving module, and is configured to compensate the threshold voltage of the driving module;
  • the coupling module is connected to the compensation module, and is configured to adjust the voltage of the control terminal of the driving module through the compensation module according to the received jump voltage;
  • the storage module is connected to the control terminal of the driving module, and is configured to store the voltage of the control terminal of the driving module; the driving module is configured to provide a driving signal to the light emitting module according to the voltage of the control terminal, and drive the light emitting module to emit light .
  • the embodiment of the present application also provides a driving method of a pixel circuit
  • the pixel circuit includes a driving module, a data writing module, an auxiliary module, a compensation module, a storage module, a coupling module and a light emitting module, the data
  • the writing module is connected to the driving module
  • the compensation module is connected between the first terminal and the control terminal of the driving module
  • the coupling module is connected to the compensation module
  • the storage module is connected to the driving module The control terminal connection;
  • the driving method of the pixel circuit includes:
  • the data writing module is controlled to write a voltage related to the data voltage to the control terminal of the driving module through the auxiliary module, and the voltage related to the driving module is controlled by the compensation module. Threshold voltage for compensation;
  • the compensation adjustment stage controlling the coupling module to adjust the voltage of the control terminal of the driving module through the compensation module according to the received jump voltage
  • the driving module is controlled to provide a driving signal to the light-emitting module according to the voltage of the control terminal, so as to drive the light-emitting module to emit light.
  • the embodiment of the present application further provides a display panel, which includes the pixel circuit provided in any embodiment of the present application.
  • the data voltage provided by the data line is passed through the data writing module, the auxiliary module, the driving module and the compensation module.
  • the module writes the voltage related to the data voltage to the control terminal of the driving module to realize data writing and threshold compensation to the driving module.
  • the jump voltage is coupled to the compensation module through the coupling module, so that the voltage of the control terminal of the driving module is fine-tuned through the compensation module, so that the driving currents generated by different pixel circuits at the same gray scale voltage are consistent, Therefore, the effect of threshold value compensation is improved, and the uniformity of display brightness is improved.
  • the signal can be directly transmitted through the active layer, which is beneficial to reduce the number of via holes, optimize the layout of the layout, reduce the layout area of pixels, and thus help to achieve high PPI.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 10 is a control timing diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 12 is a flow chart of a method for driving a pixel circuit provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by the embodiment of the present application. Referring to FIG. module 150 , coupling module 160 and light emitting module 170 .
  • the data writing module 120 is configured to write a voltage related to the data voltage to the control terminal G of the driving module 110 through the auxiliary module 130;
  • the compensation module 140 is connected between the first terminal of the driving module 110 and the control terminal G, and is configured to The threshold voltage of the driving module 110 is compensated;
  • the coupling module 160 is connected to the compensation module 140, and is set to adjust the voltage of the control terminal G of the driving module 110 through the compensation module 140 according to the received jump voltage V1;
  • the storage module 150 and the driving module 110 The control terminal G is connected and set to store the voltage of the control terminal G of the driving module 110;
  • the driving module 110 is set to provide a driving signal to the light emitting module 170 according to the voltage of the control terminal G, and drive the light emitting module 170 to emit light.
  • the compensation module 140 is connected between the first terminal of the driving module 110 and the control terminal G, and is configured to realize compensation for the threshold voltage of the driving module 110 .
  • the coupling module 160 is connected with the compensation module 140, and is configured to fine-tune the voltage of the control terminal G of the driving module 110 after compensating the threshold voltage, so as to make up for the incomplete compensation of the threshold voltage and improve the threshold compensation effect.
  • the working process of the pixel circuit provided by the embodiment of the present application may at least include a data writing and threshold compensation phase, a compensation adjustment phase, and a light emitting phase.
  • the data writing module 120, the auxiliary module 130 and the compensation module 140 are turned on, and the data voltage provided by the data line Data passes through the data writing module 120, the auxiliary module 130, the driving module 110 and the compensation module 140 Then write the voltage related to the data voltage to the control terminal G of the driving module 110.
  • the compensation module 140 can compensate the threshold voltage of the driving module 110, the voltage of the control terminal G of the driving module 110 can be equal to the data voltage
  • the voltage associated with the threshold voltage is stored in the storage module 150 to implement data voltage writing and threshold voltage compensation for the driving module 110 .
  • the jump voltage V1 is coupled to the internal node of the compensation module 140 through the coupling module 160, and fine-tuned by the compensation module 140
  • the voltage of the control terminal G of the driving module 110 for example, in the compensation process, the voltage of the control terminal G of the driving module 110 after compensation is Vdata+Vth, wherein, Vdata is the data voltage on the data line Data, and Vth is the driving module 110 threshold voltage.
  • the voltage at the control terminal G of the driving module 110 is not equal to Vdata+Vth, and as the pixel circuit continues to work, the subthreshold swing (SS) of the driving module 110 is caused. increase, the voltage of the control terminal G of the driving module 110 is changed, so that there is a large error between the voltage of the control terminal G of the driving module 110 and Vdata+Vth after the data writing and compensation phase ends, resulting in different driving modules 110 Driving currents generated at the same gray scale voltage are different.
  • the driving module 110 works in the sub-threshold region, and a small error in the voltage of the control terminal G can cause a large change in the driving current, so a small error in the data voltage Vdata can cause a large change in the driving current.
  • fine-tuning the voltage of the control terminal G of the driving module 110 in the compensation adjustment stage to ensure that the driving currents generated by different driving modules 110 according to the voltage of the control terminal G in the light-emitting stage are consistent, so as to improve the uniformity of display brightness and further improve the display effect.
  • the auxiliary module 130 is added, and the signal can be transmitted directly through the active layer by rationally designing the layout, thereby reducing the number of via holes in the layout, which is beneficial to reducing the layout area of the pixel, thereby improving the PPI .
  • the data voltage provided by the data line is passed through the data writing module, auxiliary module,
  • the driving module and the compensation module then write the voltage related to the data voltage to the control terminal of the driving module, so as to realize data writing and threshold compensation to the driving module.
  • the jump voltage is coupled to the compensation module through the coupling module, so that the voltage of the control terminal of the driving module is fine-tuned through the compensation module, so that the driving currents generated by different pixel circuits at the same gray scale voltage are consistent, Therefore, the effect of threshold value compensation is improved, and the uniformity of display brightness is improved. Even if the driving frequency changes, a good compensation effect can be achieved through reasonable level coupling. And by adding auxiliary modules, the signal can be directly transmitted through the active layer, which is beneficial to reduce the number of via holes, optimize the layout of the layout, reduce the layout area of pixels, and thus help to achieve high PPI.
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present application.
  • the storage module 150 includes a first capacitor C1, and the first capacitor The first pole of C1 is connected to a fixed voltage, the second pole of the first capacitor C1 is connected to the control terminal G of the driving module 110;
  • the auxiliary module 130 includes a first transistor T1, the gate of the first transistor T1 is connected to the first scanning line S1, The first terminal of the first transistor T1 is connected to the second terminal of the data writing module 120 , the second terminal of the first transistor T1 is connected to the second terminal of the driving module 110 , and the first terminal of the data writing module 120 is connected to the data line Data.
  • the first capacitor C1 is set to store the voltage of the control terminal G of the drive module 110, and the fixed voltage connected to its first pole may be the first power supply voltage VDD provided by the first power line, or other voltages with a constant value.
  • the first transistor T1 is connected to the same scanning signal line as the compensation module 140. Since the first transistor T1 is connected between the data writing module 120 and the second terminal of the driving module 110, the first transistor T1 will not affect the pixel circuit. work process.
  • the driving module 110 generally includes a driving transistor.
  • the gate of the transistor is formed at the overlapping position of the metal layer and the active layer, and the source and drain are respectively formed on the active layer on both sides of the gate.
  • FIG. 3 is a schematic structural diagram of another pixel circuit provided by the embodiment of the present application
  • FIG. 4 is a schematic structural diagram of another pixel circuit provided by the embodiment of the present application.
  • the auxiliary module 130 may further include a second capacitor C2, the gate of the first transistor T1 is connected to the first scanning line S1, the first electrode of the first transistor T1 is connected to the second terminal of the data writing module 120, and the first The second pole of a transistor T1 is connected to the second terminal of the driving module 110, the first terminal of the data writing module 120 is connected to the data line Data, the first terminal of the second capacitor C2 is connected to a fixed voltage, and the second terminal of the second capacitor C2 It is connected with the first pole or the second pole of the first transistor T1.
  • the fixed voltage connected to the second capacitor C2 can be the first power supply voltage VDD.
  • the voltage stability of the second end of the driving module 110 can be maintained, and at the same time, the data write In the input and threshold compensation stage, the data voltage transmitted on the data line Data can be stored on the second capacitor C2.
  • the data voltage stored on the second capacitor C2 continues to charge the control terminal G of the driving module 110 through the compensation module 140 .
  • the charging current is small, and the voltage of the control terminal G of the driving module 110 can be fine-tuned, thereby improving the sub-threshold swing caused by the process With a discrete condition, the sub-threshold swing is compensated.
  • the first transistor T1 the number of via holes in the pixel circuit can be reduced to improve the PPI.
  • FIG. 5 is a schematic structural diagram of another pixel circuit provided by the embodiment of the present application.
  • the compensation module 140 includes a second transistor T2, and the second transistor T2 is a dual A gate transistor, the second transistor includes a first sub-transistor T2-1 and a second sub-transistor T2-2;
  • Both the gate of the first sub-transistor T2-1 and the gate of the second sub-transistor T2-2 are connected to the first scanning line S1, and the first pole of the first sub-transistor T2-1 is connected to the first end of the driving module 110,
  • the second pole of the first sub-transistor T2-1 is connected to the first pole of the second sub-transistor T2-2, and the second pole of the second sub-transistor T2-2 is connected to the control terminal G of the driving module 110;
  • the coupling module 160 includes The third capacitor C3, the first electrode of the third capacitor C3 is connected to the pulse voltage, and the second electrode of the third capacitor C3 is connected to the first electrode of the second sub-transistor T2-2.
  • the data writing module 120 is turned on in response to the scanning signal on the second scanning line S2, and the auxiliary module 130 and the second transistor T2 are turned on in response to the scanning signal on the first scanning line S1.
  • the data voltage on the data line Data passes through the data writing module 120, the auxiliary module 130, the driving module 110 and the second transistor T2, and then writes a voltage related to the data voltage to the control terminal G of the driving module 110, and passes through the second transistor T2.
  • the second transistor T2 compensates the threshold voltage of the driving module 110 .
  • the data writing module 120 is turned off in response to the scan signal on the second scan line S2, and when the second transistor T2 is turned off in response to the scan signal on the first scan line S1, the pulse at the first pole of the third capacitor C3 The voltage jumps, and through the coupling effect of the third capacitor C3, the potential at the first node N1 changes.
  • the second transistor T2 Since the second transistor T2 is in the off state, and the potential of the control terminal G of the driving module 110 is the same as that of the first node N1 The potentials are not equal, that is, there is a voltage difference between the control terminal G of the driving module 110 and the first node N1, and the voltage of the control terminal G of the driving module 110 can be fine-tuned under the action of the leakage of the second sub-transistor T2-2.
  • make the driving current generated by the driving module 110 consistent so as to make up for the insufficient threshold compensation of the driving module 110 in the data writing and threshold compensation stages, improve the compensation effect, and thus help to improve the display brightness. Uniformity.
  • Table 1 shows the luminance values of nine points in the panel at 32 grayscales obtained by using the 7T1C pixel circuit in the related art
  • Table 2 shows the same nine points in the panel obtained at 32 grayscales using the pixel circuit provided by the embodiment of the present application. The brightness value of the point.
  • FIG. 6 is a schematic structural diagram of another pixel circuit provided by the embodiment of the present application.
  • the compensation module 140 includes a second transistor T2, and the second transistor T2 is three Gate transistors, the second transistor T2 includes a first sub-transistor T2-1, a second sub-transistor T2-2 and a third sub-transistor T2-3;
  • the gate of the first sub-transistor T2-1, the gate of the second sub-transistor T2-2 and the gate of the third sub-transistor T2-3 are all connected to the first scanning line S1, and the first pole is connected to the first end of the driving module 110, the second pole of the first sub-transistor T2-1 is connected to the first pole of the second sub-transistor T2-2, the second pole of the second sub-transistor T2-2 is connected to the third The first pole of the sub-transistor T2-3 is connected, and the second pole of the third sub-transistor T2-3 is connected to the control terminal G of the driving module 110; the coupling module 160 is configured to couple the jump voltage V1 to the second sub-transistor T2- 2 and/or the second pole of the second sub-transistor T2-2.
  • the coupling module 160 includes a third capacitor C3 and a fourth capacitor C4, the first pole of the third capacitor C3 is connected to the pulse voltage, the second pole of the third capacitor C3 is connected to the second sub-transistor T2- 2, the first pole of the fourth capacitor C4 is connected to the pulse voltage or fixed voltage, and the second pole of the fourth capacitor C4 is connected to the first pole of the second sub-transistor T2-2.
  • the data writing module 120 is turned on in response to the scanning signal on the second scanning line S2, and the auxiliary module 130 and the second transistor T2 are turned on in response to the scanning signal on the first scanning line S1,
  • the data voltage on the data line Data passes through the data writing module 120, the auxiliary module 130, the driving module 110 and the second transistor T2, and then writes a voltage related to the data voltage to the control terminal G of the driving module 110, and passes through the second transistor T2
  • the threshold voltage of the driving module 110 is compensated.
  • the data writing module 120 is turned off in response to the scan signal on the second scan line S2, when the second transistor T2 is turned off in response to the scan signal on the first scan line S1, and when the first electrode of the fourth capacitor C4 is connected to
  • the pulse voltage since the third capacitor C3 and the fourth capacitor C4 are connected to the pulse voltage, after the first sub-transistor T2-1, the second sub-transistor T2-2 and the third sub-transistor T2-3 are turned off, the jump voltage The level of V1 jumps, the third capacitor C3 couples the jump voltage V1 to the first node N1, the fourth capacitor C4 couples the jump voltage V1 to the second node N2, and the second node N2 and the first node N1 The potential changes at the same time.
  • the second transistor T2 Since the second transistor T2 is turned off and there is a voltage difference between the potential of the control terminal G of the driving module 110 and the potential of the first node N1 or the second node N2, the voltage of the control terminal G of the driving module 110 can be fine-tuned.
  • the driving current generated by the driving module 110 is consistent for different pixel circuits, so as to make up for the insufficient threshold compensation of the driving module 110 during the data writing and threshold compensation stages, and improve the compensation effect, which is beneficial to Improve the uniformity of display brightness.
  • the first pole of the fourth capacitor C4 is connected to a fixed voltage, for example, the first pole of the fourth capacitor C4 is connected to the first power supply voltage VDD provided by the first power line.
  • the fixed voltage may be other voltages with stable values. Since the fixed voltage will not jump, the fourth capacitor C4 can maintain the stability of the potential of the second node N2, thereby reducing the leakage between the control terminal G of the driving module 110 and the compensation module 140, which is beneficial to the driving module. 110 The voltage of the control terminal G is fine-tuned.
  • FIG. 7 is a schematic structural diagram of another pixel circuit provided by the embodiment of the present application.
  • the compensation module 140 includes a second transistor T2, and the second transistor T2 is four Gate transistors, the second transistor T2 includes a first sub-transistor T2-1, a second sub-transistor T2-2, a third sub-transistor T2-3 and a fourth sub-transistor T2-4;
  • the gate of the first sub-transistor T2-1, the gate of the second sub-transistor T2-2, the gate of the third sub-transistor T2-3 and the gate of the fourth sub-transistor T2-4 are all connected to the first scanning line S1 , the first pole of the first sub-transistor T2-1 is connected to the first end of the driving module 110, the second pole of the first sub-transistor T2-1 is connected to the first pole of the second sub-transistor T2-2, and the second sub-transistor The second pole of the transistor T2-2 is connected to the first pole of the third sub-transistor T2-3, the second pole of the third sub-transistor T2-3 is connected to the first pole of the fourth sub-transistor T2-4, and the fourth sub-transistor The second pole of the transistor T2-4 is connected to the control terminal G of the driving module 110; the coupling module 160 is configured to couple the jump voltage V1 to the first pole of the second sub-transistor T2-2, and the second pole of the second sub-transistor T
  • the coupling module 160 includes a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5.
  • the first pole of the third capacitor C3 is connected to the pulse voltage, and the second pole of the third capacitor C3 is connected to the fifth capacitor C5.
  • the second pole of the three sub-transistor T2-3 is connected, the first pole of the fourth capacitor C4 is connected to a pulse voltage or a fixed voltage, the second pole of the fourth capacitor C4 is connected to the second pole of the second sub-transistor T2-2, and the second pole of the fourth capacitor C4 is connected to the second pole of the second sub-transistor T2-2.
  • the first pole of the fifth capacitor C5 is connected to the pulse voltage or the fixed voltage, and the second pole of the fifth capacitor C5 is connected to the second pole of the first sub-transistor T2-1.
  • the pixel circuit shown in FIG. 7 changes the second transistor T2 from a tri-gate transistor to a quad-gate transistor, and adds a fifth capacitor C5 at the same time. Its specific working principle is the same as that described above. This will not be repeated here.
  • the jump voltage V1 is specifically a pulse voltage
  • the pulse of the voltage signal is after the pulse of the first pulse signal S1 transmitted by the first scanning line. That is to say, the pulse voltage is configured to undergo a level transition when the compensation module 140 is turned off. That is to say, after the pixel circuit completes compensation for the threshold value of the driving module 110 through the compensation module 140, the compensation module 140 is disconnected, and the pulse voltage jumps at this time (the voltage change amount of the jump can be set according to the actual situation) , because the potential of one end of the coupling module 160 changes, the coupling action of the coupling module 160 is triggered, and the change in the voltage of one end is coupled to the other end, so that the voltage of the internal node of the compensation module 140 changes. Since the compensation module 140 has been turned off Therefore, the voltage of the control terminal G of the driving module 110 can be fine-tuned, thereby adjusting the driving current, so as to improve the threshold compensation effect and ensure the consistency of the driving current generated by the driving module 110 .
  • FIG. 8 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present application.
  • the pixel circuit provided in the embodiment of the present application further includes an initialization module 200, A light emission control module 180 and a second light emission control module 190 .
  • the initialization module 200 is connected between the initialization signal line Vref and the first end of the light emitting module 170
  • the first light emitting control module 180 is connected between the first power line VDD and the second end of the driving module 110
  • the second light emitting control module 190 It is connected between the first end of the driving module 110 and the first end of the light emitting module 170 .
  • FIG. 9 is a schematic structural diagram of another pixel circuit provided by the embodiment of the present application, and shows the specific structure of the pixel circuit shown in FIG. 8.
  • the second transistor T2 is a double-gate transistor as an example. Be explained.
  • the driving module 110 includes a third transistor T3, the data writing module 120 includes a fourth transistor T4, the first light emission control module 180 includes a fifth transistor T5, the second light emission control module 190 includes a sixth transistor T6, and the initialization module 200 includes a seventh transistor T6.
  • Transistor T7 the gate of the fourth transistor T4 is connected to the second scan line S2, the first pole of the fourth transistor T4 is connected to the data line Data, and the second pole of the fourth transistor T4 is connected to the first pole of the third transistor T3 through the auxiliary module 130
  • One pole, the first pole of the fifth transistor T5 is connected to the first power supply line VDD
  • the second pole of the fifth transistor T5 is connected to the first pole of the third transistor T3
  • the second pole of the third transistor T3 passes through the sixth transistor T6 It is connected to the first end of the light-emitting module 170, the second end of the light-emitting module 170 is connected to the second power line VSS, the gate of the fifth transistor T5 and the gate of the sixth transistor T6 are connected to the light-emitting control signal line EM;
  • the seventh transistor The first pole of T7 is connected to the initialization signal line Vref
  • the second pole of the seventh transistor T7 is connected to the first end of the light emitting module 170, the
  • the signal line and the voltage it transmits are represented by the same symbol, and the light emitting module 170 may be a light emitting diode OLED.
  • Fig. 10 is a control timing diagram of a pixel circuit provided by the embodiment of the present application, which is applicable to the pixel circuit shown in Fig. 9.
  • This embodiment exemplarily shows the first transistor T1, the second transistor T2, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all P-type transistors.
  • the working process of the pixel circuit provided by the embodiment of the present application may include an initialization phase t1, a data writing and threshold compensation phase t2, a compensation adjustment phase t3, and a lighting phase t4.
  • the first scan signal S1 provided by the first scan line is at low level
  • the second scan signal S2 provided by the second scan line is at high level
  • the third scan signal S3 provided by the third scan signal line is Low level
  • the light emission control signal EM provided by the light emission control signal line is low level.
  • the first transistor T1 and the second transistor T2 are turned on in response to the first scanning signal S1
  • the fourth transistor T4 is turned off in response to the second scanning signal S2
  • the fifth transistor T5 and the sixth transistor T6 are turned on in response to the light emission control signal EM
  • the seventh transistor T4 is turned on in response to the light emission control signal EM.
  • the transistor T7 is turned on in response to the third scan signal S3, and the initialization voltage Vref on the initialization signal line is transmitted to the first pole of the light-emitting diode OLED, and transmitted to the gate of the third transistor T3 through the sixth transistor T6 and the second transistor T2, To initialize the potential of the gate of the third transistor T3 and the first electrode of the light emitting diode OLED.
  • VG represents the gate voltage of the third transistor T3
  • VD represents the voltage of the first pole of the light emitting diode OLED.
  • the third transistor T3 is turned on by configuring the initialization voltage Vref, therefore, the first power line VDD, the fifth transistor T5, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 A path is formed between the third transistor T3 and the initialization signal line Vref, and the third transistor T3 generates a current to flush the charge in the third transistor T3, so that the charge amount in the third transistor T3 is initialized to the charge amount corresponding to the initialization voltage Vref, so as to reduce
  • the characteristic shift of the third transistor T3 due to the hysteresis effect can improve the afterimage phenomenon.
  • the second transistor T2 is a double-gate transistor, it has a smaller leakage current than a single-gate transistor, and there is only one leakage path for the gate voltage of the third transistor T3, which can maintain the gate voltage of the third transistor T3.
  • the stability of the voltage is conducive to improving the display effect.
  • the first scanning signal S1 provided by the first scanning line is at low level
  • the second scanning signal S2 provided by the second scanning line is at low level
  • the first scanning signal S2 provided by the third scanning signal line is at low level.
  • the three-scanning signal S3 is at a high level
  • the light emission control signal EM provided by the light emission control signal line is at a high level.
  • the first transistor T1 and the second transistor T2 continue to be turned on in response to the first scan signal S1, the fourth transistor T4 is turned on in response to the second scan signal S2, the fifth transistor T5 and the sixth transistor T6 are turned off in response to the light emission control signal EM, and the fourth transistor T4 is turned on in response to the light emission control signal EM.
  • the seven transistors T7 are turned off in response to the third scan signal S3.
  • the data voltage on the data line Data passes through the fourth transistor T4, the first transistor T1, the third transistor T3 and the second transistor T2, and then writes a voltage related to the data voltage to the gate of the third transistor T3, while the second transistor T2
  • the threshold voltage of the third transistor T3 is compensated to implement writing of the data voltage of the driving module 110 and compensation of the threshold voltage.
  • the first capacitor C1 stores the gate voltage of the third transistor T3, and the stored voltage is associated with the data voltage and the threshold voltage.
  • the conduction time of the second transistor T2 is relatively short, it cannot be guaranteed to fully compensate the threshold voltage of the third transistor T3 , which may easily lead to non-uniform display brightness at low gray scales.
  • the first scan signal S1 provided by the first scan line is at high level
  • the second scan signal S2 provided by the second scan line is at high level
  • the third scan signal S3 provided by the third scan signal line is at high level.
  • the light emission control signal EM provided by the light emission control signal line is high level.
  • the first transistor T1 and the second transistor T2 are turned off in response to the first scan signal S1, the fourth transistor T4 is turned off in response to the second scan signal S2, the fifth transistor T5 and the sixth transistor T6 are turned off in response to the light emission control signal EM, and the seventh transistor T4 is turned off in response to the light emission control signal EM.
  • the transistor T7 is turned off in response to the third scan signal S3.
  • the level of the pulse voltage transitions from high level to low level, and passes through the third capacitor C3 Due to the coupling effect of the first node N1, the potential of the first node N1 changes, resulting in a voltage difference between the gate of the third transistor T3 and the first node. Since the second transistor T2 is in the off state, the second sub-transistor T2-2 Under the action of leakage current, the gate voltage of the third transistor T3 can be fine-tuned, thereby making up for the fact that the third transistor T3 cannot be fully compensated, so as to ensure that the driving current generated by the third transistor T3 is consistent, so as to improve the uniformity of display brightness.
  • the pulse width (low level maintenance time) of the pulse voltage can be set according to the sub-threshold swing fluctuation range of the driving module 110, so as to reduce the fluctuation caused by the sub-threshold swing fluctuation of the driving module 110 through the jump of the pulse voltage. Shows unevenness.
  • the first scan signal S1 provided by the first scan line is at high level
  • the second scan signal S2 provided by the second scan line is at high level
  • the third scan signal S3 provided by the third scan signal line is high level
  • the light emission control signal EM provided by the light emission control signal line is low level.
  • the first transistor T1 and the second transistor T2 are turned off in response to the first scan signal S1
  • the fourth transistor T4 is turned off in response to the second scan signal S2
  • the fifth transistor T5 and the sixth transistor T6 are turned on in response to the light emission control signal EM
  • the seventh transistor T4 is turned off in response to the light emission control signal EM.
  • the transistor T7 is turned off in response to the third scan signal S3.
  • the third transistor T3 generates a drive current under the control of its gate voltage. Since the gate voltage has been adjusted in the previous stage, it can ensure that the light-emitting diode OLED has the same gray-scale voltage in the light-emitting stage t4. Drive current to improve the uniformity of display brightness.
  • the first transistor T1 functions to improve the layout of the pixel circuit without affecting the working principle of the pixel circuit.
  • the number of via holes in the layout can be reduced, thereby reducing the layout area of the pixel circuit, so as to improve the PPI of the display panel.
  • the second transistor T2 can be replaced by the tri-gate transistor or the quad-gate transistor described in the above embodiments, and the fixed voltage can be any one of the first power supply voltage VDD or the initialization voltage Vref.
  • the pixel circuit The working principle remains unchanged, and reference may be made to relevant descriptions in the foregoing embodiments, and details are not repeated here.
  • FIG. 11 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present application.
  • the auxiliary module 130 in this embodiment includes a first transistor T1 and The second capacitor C2, wherein the second capacitor C2 may be connected to the first pole or the second pole of the first transistor T1.
  • the first transistor T1 can be omitted, and the second capacitor C2 is reserved, which will not affect the working principle of the pixel circuit.
  • the first scanning signal S1 provided by the first scanning line is at low level
  • the second scanning signal S2 provided by the second scanning line is at low level
  • the first scanning signal S2 provided by the third scanning signal line is at low level.
  • the three-scanning signal S3 is at a high level
  • the light emission control signal EM provided by the light emission control signal line is at a high level.
  • the first transistor T1 and the second transistor T2 are turned on in response to the first scan signal S1
  • the fourth transistor T4 is turned on in response to the second scan signal S2
  • the fifth transistor T5 and the sixth transistor T6 are turned off in response to the light emission control signal EM
  • the seventh transistor T4 is turned on in response to the light emission control signal EM.
  • the transistor T7 is turned off in response to the third scan signal S3.
  • the data voltage on the data line Data passes through the fourth transistor T4, the first transistor T1, the third transistor T3 and the second transistor T2, and then writes a voltage related to the data voltage to the gate of the third transistor T3, and stores the data voltage In the second capacitor C2.
  • the second transistor T2 compensates the threshold voltage of the third transistor T3, so as to realize writing of the data voltage of the driving module 110 and compensation of the threshold voltage.
  • the first capacitor C1 stores the gate voltage of the third transistor T3, and the stored voltage is associated with the data voltage and the threshold voltage.
  • the first scan signal S1 is at low level
  • the second scan signal S2 is at high level
  • the fourth transistor T4 is turned off
  • the first transistor T1 and the second transistor T2 are turned on. Since the data voltage is stored on the second capacitor C2, the data voltage on the second capacitor C2 can continue to charge the gate of the third transistor T3 through the first transistor T1, the third transistor T3, and the second transistor T2, that is, , in the sub-threshold swing compensation phase t2', the first scan signal S1 output by the first scan line controls the auxiliary module 130 and the compensation module 140 to be turned on, and the second scan signal S2 output by the second scan line controls the data writing module 120 When it is turned off, the data voltage stored on the second capacitor C2 adjusts the voltage of the control terminal of the driving module 110 through the driving module 110 and the compensation module 140 .
  • the charging current is small, and the gate voltage of the third transistor T3 can be fine-tuned, thereby improving the third transistor T3 caused by the process.
  • the sub-threshold swing of the transistor T3 is discrete, resulting in non-uniform display effects, which realizes compensation for the sub-threshold swing and ensures the consistency of the driving current generated by the driving module 110 .
  • the current charged in the t2' stage is usually a small current, and the time corresponding to t2' is longer than the time corresponding to t2, so as to realize effective compensation for the change of the driving current caused by the dispersion of the subthreshold swing at low gray levels.
  • the pulse voltage jumps from high level to low level, and the potential of the first node N1 changes through the coupling effect of the third capacitor C3 , so that there is a voltage difference between the gate of the third transistor T3 and the first node, since the second transistor T2 is in the off state, under the action of the leakage of the second sub-transistor T2-2, the voltage of the third transistor T3 can be fine-tuned
  • the gate voltage further compensates for the fact that the third transistor T3 cannot be fully compensated, so as to further ensure that the driving current generated by the third transistor T3 is consistent, so as to improve the uniformity of display brightness.
  • the sub-threshold swing of the third transistor T3 can be compensated by the second capacitor C2 and the third capacitor C3, and after the gate voltage of the third transistor T3 is increased by the second capacitor C2, the
  • the third capacitor C3 couples the jump voltage V1 to the interior of the compensation module 140 to fine-tune the gate voltage of the third transistor T3, which can reduce the adjustment range of the gate voltage of the third transistor T3, and can improve the
  • the accuracy of adjusting the gate voltage of the third transistor T3 is beneficial to realize the accuracy control of the driving current generated by it.
  • any of the embodiments of the present application can be combined with each other, and can achieve the effect of improving the compensation effect and improving the uniformity of display brightness.
  • the embodiment of the present application also provides a driving method for a pixel circuit
  • FIG. 12 is a flow chart of a driving method for a pixel circuit provided in the embodiment of the present application.
  • the pixel circuit includes Drive module 110, data writing module 120, auxiliary module 130, compensation module 140, storage module 150, coupling module 160 and light emitting module 170, data writing module 120 is connected to driving module 110 through auxiliary module 130, compensation module 140 is connected to Between the first terminal of the driving module 110 and the control terminal G, the coupling module 160 is connected to the compensation module 140, and the storage module 150 is connected to the control terminal G of the driving module 110;
  • the driving method of the pixel circuit includes:
  • control data writing module writes a voltage related to the data voltage to the control terminal of the driving module through the auxiliary module, and compensates the threshold voltage of the driving module through the compensation module.
  • control coupling module adjusts the voltage of the control terminal of the driving module through the compensation module according to the received jump voltage.
  • control drive module provides a driving signal to the light emitting module according to the voltage of the control terminal, and drives the light emitting module to emit light.
  • the driving method of the pixel circuit provided by the embodiment of the present application, in the data writing and threshold compensation stages, by controlling the data writing module and the compensation module to respond to different scanning signals respectively, the data voltage provided by the data line is passed through the data writing module, The auxiliary module, the driving module and the compensation module write the voltage related to the data voltage to the control terminal of the driving module to realize data writing and threshold compensation to the driving module.
  • the jump voltage is coupled to the compensation module through the coupling module, so that the voltage of the control terminal of the driving module is fine-tuned through the compensation module, so that the driving currents generated by different pixel circuits at the same gray scale voltage are consistent, Therefore, the effect of threshold value compensation is improved, and the uniformity of display brightness is improved.
  • the signal can be directly transmitted through the active layer, which is beneficial to reduce the number of via holes, optimize the layout of the layout, reduce the layout area of pixels, and thus help to achieve high PPI.
  • the control terminal of the auxiliary module 130 is connected to the first scan line
  • the control terminal of the compensation module 140 is connected to the first scan line S1
  • the control terminal of the data writing module 120 is connected to the second scan line S2
  • the pixel circuit also includes an initialization module 200, a first light emission control module 180 and a second light emission control module 190
  • the control end of the initialization module 200 is connected to the third scanning line S3
  • the first end of the initialization module 200 is connected to the initialization signal line Vref
  • the second end of 200 is connected to the first end of the light emitting module 170
  • the control end of the first light emitting control module 180 and the control end of the second light emitting control module 190 are both connected to the light emitting control signal line EM
  • the second end of the first light emitting control module 180 One end is connected to the first power line VDD
  • the second end of the first light emission control module 180 is connected to the second end of the driving module 110
  • the auxiliary module 130 includes a first transistor T1, the compensation module 140 includes a second transistor T2, the second transistor T2 is a double-gate transistor, the driving module 110 includes a third transistor T3, the data writing module 120 includes a fourth transistor T4, and the first light emitting
  • the control module 180 includes a fifth transistor T5, the second light emission control module 190 includes a sixth transistor T6, and the initialization module 200 includes a seventh transistor T7.
  • the pixel circuit driving method provided in the embodiment of the present application include:
  • the first scan signal S1 output by the first scan line controls the auxiliary module 130 and the compensation module 140 to conduct
  • the third scan signal S3 output by the third scan line controls the initialization module 200 to conduct
  • the light emission control signal line outputs
  • the light emission control signal EM controls the first light emission control module 180 and the second light emission control module 190 to conduct.
  • the initialization voltage Vref on the initialization signal line is transmitted to the first pole of the light-emitting diode OLED, and is transmitted to the gate of the third transistor T3 through the sixth transistor T6 and the second transistor T2, so as to control the gate of the third transistor T3 and emit light.
  • the potential of the first pole of the diode OLED is initialized.
  • the third transistor T3 is turned on by configuring the initialization voltage Vref, therefore, the first power line VDD, the fifth transistor T5, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 A path is formed between the third transistor T3 and the initialization signal line Vref, and the third transistor T3 generates a current to flush the charge in the third transistor T3, so that the charge amount in the third transistor T3 is initialized to the charge amount corresponding to the initialization voltage Vref, so as to reduce
  • the characteristic shift of the third transistor T3 due to the hysteresis effect can improve the afterimage phenomenon.
  • the second transistor T2 since the second transistor T2 is a double-gate transistor, it has a smaller leakage current than a single-gate transistor, and there is only one leakage path for the gate voltage of the third transistor T3, which can maintain the current of the third transistor T3.
  • the stability of the gate voltage of T3 is beneficial to improve the display effect.
  • the first scanning signal S1 output from the first scanning line controls the auxiliary module 130 and the compensation module 140 to conduct
  • the second scanning signal S2 output from the second scanning line controls the data writing module 120 to conduct.
  • the data voltage on the data line Data passes through the fourth transistor T4, the first transistor T1, the third transistor T3 and the second transistor T2, and then writes a voltage related to the data voltage to the gate of the third transistor T3, while the second transistor T2
  • the threshold voltage of the third transistor T3 is compensated to implement writing of the data voltage of the driving module 110 and compensation of the threshold voltage.
  • the first capacitor C1 stores the gate voltage of the third transistor T3, and the stored voltage is associated with the data voltage and the threshold voltage.
  • the first scan signal S1 output by the first scan line controls the auxiliary module 130 and the compensation module 140 to turn off, and controls the coupling module 160 to adjust the control terminal G of the drive module 110 through the compensation module 140 according to the received jump voltage. voltage.
  • the level of the pulse voltage at one end of the third capacitor C3 transitions from high level to low level , through the coupling effect of the third capacitor C3, the potential of the first node N1 changes, thus resulting in a voltage difference between the gate of the third transistor T3 and the first node, because the second transistor T2 is in the off state, at the Under the action of the leakage of the second sub-transistor T2-2, the gate voltage of the third transistor T3 can be fine-tuned, thereby making up for the situation that the third transistor T3 cannot be fully compensated, so as to ensure that the driving current generated by the third transistor T3 is consistent, so as to improve Displays the uniformity of brightness.
  • the light-emitting control signal EM output from the light-emitting control signal line controls the first light-emitting control module 180 and the second light-emitting control module 190 to conduct.
  • the third transistor T3 generates a drive current under the control of its gate voltage. Since the gate voltage has been adjusted in the previous stage, it can ensure that the light-emitting diode OLED has the same gray-scale voltage in the light-emitting stage t4. Drive current to improve the uniformity of display brightness.
  • the embodiment of the present application further provides a display panel, which includes the pixel circuit provided in the embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a display panel provided in the embodiment of the present application.
  • the display panel is a mobile phone display panel, which can be applied to tablets, watches, wearable devices, and all other display-related devices such as vehicle displays, camera displays, TVs, and computer screens. Since the display panel includes the pixel circuit provided by any embodiment of the present application, the display panel provided by the embodiment of the present application also has the beneficial effects described in any embodiment of the present application.

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Abstract

一种像素电路及其驱动方法和显示面板。像素电路包括驱动模块(110)、数据写入模块(120)、辅助模块(130)、补偿模块(140)、存储模块(150)、耦合模块(160)和发光模块(170)；数据写入模块(120)设置为通过辅助模块(130)向驱动模块(110)的控制端(G)写入与数据电压相关的电压；补偿模块(140)连接于驱动模块(110)的第一端和控制端(G)之间，设置为对驱动模块(110)的阈值电压进行补偿；耦合模块(160)与补偿模块(140)连接，设置为根据接收到的跳变电压通过补偿模块(140)调整驱动模块(110)控制端(G)的电压；存储模块(150)与驱动模块(110)的控制端(G)连接，驱动模块(110)设置为根据控制端(G)的电压向发光模块(170)提供驱动信号，驱动发光模块(170)发光。

Description

像素电路及其驱动方法和显示面板
本申请要求在2021年11月25日提交中国专利局、申请号为202111415705.6的中国专利申请的优先权，以上申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，尤其涉及一种像素电路及其驱动方法和显示面板。
背景技术
随着显示技术的不断发展，有机发光二极管(Organic Light Emitting Diode，OLED)显示面板凭借自发光、高亮度、宽视角等优良特性，在光电显示领域有着广泛的应用。
显示面板中通常包括多个像素电路，其中像素电路包括驱动晶体管，驱动晶体管生成驱动信号以驱动发光元件发光显示。在相关技术中，像素电路的版图存在大量过孔，导致像素布局面积较大，不利于实现高PPI(Pixels Per Inch)。
发明内容
本申请实施例提供一种像素电路及其驱动方法和显示面板，以改善像素电路的版图布局，减小像素布局面积，从而有利于提高PPI。
第一方面，本申请实施例提供了一种像素电路，包括：驱动模块、数据写入模块、辅助模块、补偿模块、存储模块、耦合模块和发光模块；
所述数据写入模块设置为通过所述辅助模块向所述驱动模块的控制端写入与数据电压相关的电压；
所述补偿模块连接于所述驱动模块的第一端和控制端之间，设置为对所述驱动模块的阈值电压进行补偿；
所述耦合模块与所述补偿模块连接，设置为根据接收到的跳变电压通过所述补偿模块调整所述驱动模块控制端的电压；
所述存储模块与所述驱动模块的控制端连接，设置为存储所述驱动模块控制端的电压；所述驱动模块设置为根据控制端的电压向所述发光模块提供驱动信号，驱动所述发光模块发光。
第二方面，本申请实施例还提供了一种像素电路的驱动方法，所述像素电路包括驱动模块、数据写入模块、辅助模块、补偿模块、存储模块、耦合模块 和发光模块，所述数据写入模块与所述驱动模块连接，所述补偿模块连接于所述驱动模块的第一端和控制端之间，所述耦合模块与所述补偿模块连接，所述存储模块与所述驱动模块的控制端连接；
所述像素电路的驱动方法包括：
在数据写入和阈值补偿阶段，控制所述数据写入模块通过所述辅助模块向所述驱动模块的控制端写入与数据电压相关的电压，并通过所述补偿模块对所述驱动模块的阈值电压进行补偿；
在补偿调整阶段，控制所述耦合模块根据接收到的跳变电压通过所述补偿模块调整所述驱动模块控制端的电压；
在发光阶段，控制所述驱动模块根据控制端的电压向所述发光模块提供驱动信号，驱动所述发光模块发光。
第三方面，本申请实施例还提供了一种显示面板，该显示面板包括本申请任意实施例所提供的像素电路。
本申请实施例，在数据写入和阈值补偿阶段，通过控制数据写入模块和补偿模块分别响应不同的扫描信号，使得数据线提供的数据电压经数据写入模块、辅助模块、驱动模块和补偿模块后写入与数据电压相关的电压至驱动模块的控制端，实现对驱动模块的数据写入和阈值补偿。在对驱动模块的阈值进行补偿后，通过耦合模块将跳变电压耦合至补偿模块中，以通过补偿模块微调驱动模块控制端的电压，使得不同像素电路在同一灰阶电压下产生的驱动电流一致，从而改善阈值补偿效果，提高显示亮度的均一性。即使驱动频率变化，通过合理的电平耦合，也可以实现良好的补偿效果。且通过增加辅助模块，使得信号能够直接通过有源层进行传输，从而有利于减少过孔数量，优化了版图布局，降低了像素的布局面积，进而有利于实现高PPI。
附图说明
图1为本申请实施例提供的一种像素电路的结构示意图；
图2为本申请实施例提供的另一种像素电路的结构示意图；
图3为本申请实施例提供的另一种像素电路的结构示意图；
图4为本申请实施例提供的另一种像素电路的结构示意图；
图5为本申请实施例提供的另一种像素电路的结构示意图；
图6为本申请实施例提供的另一种像素电路的结构示意图；
图7为本申请实施例提供的另一种像素电路的结构示意图；
图8为本申请实施例提供的另一种像素电路的结构示意图；
图9为本申请实施例提供的另一种像素电路的结构示意图；
图10为本申请实施例提供的一种像素电路的控制时序图；
图11为本申请实施例提供的另一种像素电路的结构示意图；
图12为本申请实施例提供的一种像素电路的驱动方法的流程图；
图13为本申请实施例提供的一种显示面板的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
图1为本申请实施例提供的一种像素电路的结构示意图，参考图1，本申请实施例提供的像素电路包括：驱动模块110、数据写入模块120、辅助模块130、补偿模块140、存储模块150、耦合模块160和发光模块170。
数据写入模块120设置为通过辅助模块130向驱动模块110的控制端G写入与数据电压相关的电压；补偿模块140连接于驱动模块110的第一端和控制端G之间，设置为对驱动模块110的阈值电压进行补偿；耦合模块160与补偿模块140连接，设置为根据接收到的跳变电压V1通过补偿模块140调整驱动模块110控制端G的电压；存储模块150与驱动模块110的控制端G连接，设置为存储驱动模块110控制端G的电压；驱动模块110设置为根据控制端G的电压向发光模块170提供驱动信号，驱动发光模块170发光。
具体地，在本实施例中，补偿模块140连接在驱动模块110的第一端和控制端G之间，设置为实现对驱动模块110的阈值电压进行补偿。耦合模块160与补偿模块140连接，设置为在补偿阈值电压后微调驱动模块110控制端G的电压，以弥补阈值电压不被完全补偿的不足，改善阈值补偿效果。本申请实施例提供的像素电路的工作过程可以至少包括数据写入和阈值补偿阶段、补偿调整阶段和发光阶段。
在数据写入和阈值补偿阶段，数据写入模块120、辅助模块130和补偿模块140导通，数据线Data提供的数据电压通过数据写入模块120、辅助模块130、驱动模块110和补偿模块140后写入与数据电压相关的电压至驱动模块110的控制端G，同时，由于补偿模块140能够对驱动模块110的阈值电压进行补偿， 从而可以使得驱动模块110控制端G的电压为与数据电压和阈值电压相关联的电压，并将该电压存储在存储模块150中，实现了对驱动模块110的数据电压写入和阈值电压补偿。
在补偿调整阶段，为了避免在数据写入和阈值补偿阶段时对驱动模块110的阈值电压补偿不完全，通过耦合模块160将跳变电压V1耦合至补偿模块140内部节点，并通过补偿模块140微调驱动模块110控制端G的电压，示例性地，在补偿过程中，经过补偿后的驱动模块110控制端G的电压为Vdata+Vth，其中，Vdata为数据线Data上的数据电压，Vth为驱动模块110的阈值电压。但是由于补偿模块140的导通时间较短导致驱动模块110控制端G的电压不等于Vdata+Vth，且随着像素电路工作的持续，导致驱动模块110的亚阈值摆幅(Subthreshold Swing，SS)增大，改变了驱动模块110控制端G的电压，因此使得驱动模块110的控制端G电压在数据写入及补偿阶段结束后与Vdata+Vth之间存在较大误差，导致不同的驱动模块110在同一灰阶电压下生成的驱动电流不同。在低灰阶下，驱动模块110工作于亚阈值区，微小的控制端G电压误差能引起驱动电流较大的变化，所以数据电压Vdata的微小误差就能够导致驱动电流发生较大变化。通过在补偿调整阶段微调驱动模块110控制端G的电压，以保证不同驱动模块110在发光阶段根据其控制端G的电压产生的驱动电流一致，以提高显示亮度的均一性，进而改善显示效果。
在进行版图布局时，至少一层金属层需要打孔换线至有源层实现信号的传输。在本实施例中，增加了辅助模块130，通过合理设计布局，能够使得信号直接通过有源层进行传输，从而减少了版图中的过孔数量，有利于减小像素的布局面积，进而提高PPI。
本申请实施例提供的像素电路，在数据写入和阈值补偿阶段，通过控制数据写入模块和补偿模块分别响应不同的扫描信号，使得数据线提供的数据电压经数据写入模块、辅助模块、驱动模块和补偿模块后写入与数据电压相关的电压至驱动模块的控制端，实现对驱动模块的数据写入和阈值补偿。在对驱动模块的阈值进行补偿后，通过耦合模块将跳变电压耦合至补偿模块中，以通过补偿模块微调驱动模块控制端的电压，使得不同像素电路在同一灰阶电压下产生的驱动电流一致，从而改善阈值补偿效果，提高显示亮度的均一性。即使驱动频率变化，通过合理的电平耦合，也可以实现良好的补偿效果。且通过增加辅助模块，使得信号能够直接通过有源层进行传输，从而有利于减少过孔数量，优化了版图布局，降低了像素的布局面积，进而有利于实现高PPI。
可选地，图2为本申请实施例提供的另一种像素电路的结构示意图，参考图2，在上述实施例的基础上，所述存储模块150包括第一电容C1，所述第一电容C1的第一极连接固定电压，第一电容C1的第二极与驱动模块110的控制端G连接；辅助模块130包括第一晶体管T1，第一晶体管T1的栅极连接第一扫描线S1，第一晶体管T1的第一极连接数据写入模块120的第二端，第一晶体管T1的第二极连接驱动模块110的第二端，数据写入模块120的第一端连接数据线Data。
具体地，第一电容C1设置为存储驱动模块110控制端G的电压，其第一极连接的固定电压可以为第一电源线提供的第一电源电压VDD，也可以为其他具有恒定值的电压。第一晶体管T1与补偿模块140连接同一扫描信号线，由于第一晶体管T1连接在数据写入模块120和驱动模块110的第二端之间，因此，第一晶体管T1并不会影响像素电路的工作过程。驱动模块110通常包括驱动晶体管，金属层与有源层交叠位置形成晶体管栅极，栅极两侧的有源层上分别形成源极和漏极，在版图布局时，通过增加第一晶体管T1，使得对应第一扫描线S1的金属层与有源层之间形成第一晶体管T1的电极，可以使得信号直接通过有源层进行传输，避免在有源层与金属层之间打孔，从而能够减少版图中的过孔数量。
可选地，图3为本申请实施例提供的另一种像素电路的结构示意图，图4为本申请实施例提供的另一种像素电路的结构示意图，在上述实施例的基础上，参考图3和图4，辅助模块130还可以包括第二电容C2，第一晶体管T1的栅极连接第一扫描线S1，第一晶体管T1的第一极连接数据写入模块120的第二端，第一晶体管T1的第二极连接驱动模块110的第二端，数据写入模块120的第一端连接数据线Data，第二电容C2的第一端连接固定电压，第二电容C2的第二端与第一晶体管T1的第一极或第二极连接。
具体地，第二电容C2连接的固定电压可以为第一电源电压VDD，通过在驱动模块110的第二端设置第二电容C2，能够维持驱动模块110第二端的电压稳定性，同时在数据写入和阈值补偿阶段，数据线Data上传输的数据电压能够存储在第二电容C2上。在数据写入模块120关断后，且在第一晶体管T1和补偿模块140关断之前，第二电容C2上存储的数据电压继续通过补偿模块140向驱动模块110的控制端G充电。在低灰阶下通过第二电容C2对驱动模块110控制端G充电过程中，充电电流较小，能够对驱动模块110控制端G的电压进行微调，从而改善因工艺原因造成的亚阈值摆幅具有离散型的状况，实现对亚 阈值摆幅进行补偿。同时，通过设置第一晶体管T1还能够减少像素电路的过孔数量，以提高PPI，具体可参考上述相关描述，在此不再赘述。
可选地，图5为本申请实施例提供的另一种像素电路的结构示意图，在上述各实施例的基础上，参考图5，补偿模块140包括第二晶体管T2，第二晶体管T2为双栅晶体管，第二晶体管包括第一子晶体管T2-1和第二子晶体管T2-2；
第一子晶体管T2-1的栅极和第二子晶体管T2-2的栅极均连接第一扫描线S1，第一子晶体管T2-1的第一极与驱动模块110的第一端连接，第一子晶体管T2-1的第二极与第二子晶体管T2-2的第一极连接，第二子晶体管T2-2的第二极与驱动模块110的控制端G连接；耦合模块160包括第三电容C3，第三电容C3的第一极连接脉冲电压，第三电容C3的第二极与第二子晶体管T2-2的第一极连接。
具体地，在数据写入和阈值补偿阶段，数据写入模块120响应第二扫描线S2上的扫描信号而导通，辅助模块130和第二晶体管T2响应第一扫描线S1上的扫描信号而导通，数据线Data上的数据电压通过数据写入模块120、辅助模块130、驱动模块110和第二晶体管T2后写入与数据电压相关的电压至驱动模块110的控制端G，并通过第二晶体管T2对驱动模块110的阈值电压进行补偿。然后数据写入模块120响应第二扫描线S2上的扫描信号而关断，当第二晶体管T2响应第一扫描线S1上的扫描信号而关断时，第三电容C3第一极处的脉冲电压发生跳变，经第三电容C3的耦合作用，使得第一节点N1处的电位发生变化，由于第二晶体管T2处于关断状态，且驱动模块110控制端G的电位与第一节点N1的电位不相等，也即驱动模块110控制端G与第一节点N1之间存在电压差，在第二子晶体管T2-2的漏电作用下能够微调驱动模块110控制端G的电压，在低灰阶下，针对不同的像素电路，使得驱动模块110产生的驱动电流一致，以弥补在数据写入和阈值补偿阶段对驱动模块110的阈值补偿不足的情况，改善补偿效果，从而有利于提高显示亮度的均一性。
表一为采用相关技术中7T1C像素电路获取到的32灰阶下面板内九个点的亮度值，表二为采用本申请实施例提供的像素电路在32灰阶获取到的面板内相同九个点的亮度值。
根据表一和表二中的数据可以看出，通过调整驱动模块110在补偿后的控制端G的电压，在同一灰阶下，能够明显提高面板亮度的均一性，从而改善补偿效果。
表一
Figure PCTCN2022108517-appb-000001
表二
Figure PCTCN2022108517-appb-000002
可选地，图6为本申请实施例提供的另一种像素电路的结构示意图，在上述各实施例的基础上，参考图6，补偿模块140包括第二晶体管T2，第二晶体管T2为三栅晶体管，第二晶体管T2包括第一子晶体管T2-1、第二子晶体管T2-2和第三子晶体管T2-3；
第一子晶体管T2-1的栅极、第二子晶体管T2-2的栅极和第三子晶体管T2-3的栅极均连接第一扫描线S1，第一子晶体管T2-1的第一极与驱动模块110的第一端连接，第一子晶体管T2-1的第二极与第二子晶体管T2-2的第一极连接，第二子晶体管T2-2的第二极与第三子晶体管T2-3的第一极连接，第三子晶体管T2-3的第二极与驱动模块110的控制端G连接；耦合模块160设置为将跳变电压V1耦合至第二子晶体管T2-2的第一极和/或第二子晶体管T2-2的第二极。
具体地，在本实施例中，耦合模块160包括第三电容C3和第四电容C4，第三电容C3的第一极连接脉冲电压，第三电容C3的第二极与第二子晶体管T2-2的第二极连接，第四电容C4的第一极连接脉冲电压或固定电压，第四电容C4的第二极与第二子晶体管T2-2的第一极连接。在数据写入和阈值补偿阶段，数据写入模块120响应第二扫描线S2上的扫描信号而导通，辅助模块130和第二晶体管T2响应第一扫描线S1上的扫描信号而导通，数据线Data上的数据电压通过数据写入模块120、辅助模块130、驱动模块110和第二晶体管T2后写入与数据电压相关的电压至驱动模块110的控制端G，并通过第二晶体管T2对驱动模块110的阈值电压进行补偿。然后数据写入模块120响应第二扫描线S2上 的扫描信号而关断，当第二晶体管T2响应第一扫描线S1上的扫描信号而关断，且当第四电容C4的第一极连接脉冲电压时，由于第三电容C3和第四电容C4均连接脉冲电压，在第一子晶体管T2-1、第二子晶体管T2-2和第三子晶体管T2-3关断后，跳变电压V1的电平发生跳变，第三电容C3将跳变电压V1耦合至第一节点N1，第四电容C4将跳变电压V1耦合至第二节点N2，第二节点N2和第一节点N1的电位同时发生变化。由于第二晶体管T2处于关断状态，且驱动模块110控制端G的电位与第一节点N1或第二节点N2的电位之间存在电压差，因此能够微调驱动模块110控制端G的电压。在低灰阶下，针对不同的像素电路，使得驱动模块110产生的驱动电流一致，以弥补在数据写入和阈值补偿阶段对驱动模块110的阈值补偿不足的情况，改善补偿效果，从而有利于提高显示亮度的均一性。
继续参考图6，第四电容C4的第一极连接固定电压，例如，第四电容C4的第一极连接第一电源线提供的第一电源电压VDD。当然，在其他实施例中，固定电压可以为其他具有稳定值的电压。由于固定电压不会发生跳变，因此第四电容C4能够维持第二节点N2电位的稳定性，进而能够减小驱动模块110的控制端G和补偿模块140之间的漏电，有利于对驱动模块110控制端G的电压实现微调。
可选地，图7为本申请实施例提供的另一种像素电路的结构示意图，在上述各实施例的基础上，参考图7，补偿模块140包括第二晶体管T2，第二晶体管T2为四栅晶体管，第二晶体管T2包括第一子晶体管T2-1、第二子晶体管T2-2、第三子晶体管T2-3和第四子晶体管T2-4；
第一子晶体管T2-1的栅极、第二子晶体管T2-2的栅极、第三子晶体管T2-3的栅极和第四子晶体管T2-4的栅极均连接第一扫描线S1，第一子晶体管T2-1的第一极与驱动模块110的第一端连接，第一子晶体管T2-1的第二极与第二子晶体管T2-2的第一极连接，第二子晶体管T2-2的第二极与第三子晶体管T2-3的第一极连接，第三子晶体管T2-3的第二极与第四子晶体管T2-4的第一极连接，第四子晶体管T2-4的第二极与驱动模块110的控制端G连接；耦合模块160设置为将跳变电压V1耦合至第二子晶体管T2-2的第一极、第二子晶体管T2-2的第二极或第三子晶体管T2-3的第二极中的至少一者。
具体地，在本实施例中，耦合模块160包括第三电容C3、第四电容C4和第五电容C5，第三电容C3的第一极连接脉冲电压，第三电容C3的第二极与第三子晶体管T2-3的第二极连接，第四电容C4的第一极连接脉冲电压或固定电 压，第四电容C4的第二极与第二子晶体管T2-2的第二极连接，第五电容C5的第一极连接脉冲电压或固定电压，第五电容C5的第二极与第一子晶体管T2-1的第二极连接。相比于图6所示像素电路结构，图7所示像素电路将第二晶体管T2由三栅晶体管更改为四栅晶体管，同时增加了第五电容C5，其具体工作原理同上述所述，在此不再赘述。
在本实施例中，跳变电压V1具体为脉冲电压，其电压信号的脉冲在第一扫描线传输的第一脉冲信号S1上的脉冲之后。也就是说，脉冲电压被配置为在补偿模块140关断期间发生电平跳变。也就是说，在像素电路通过补偿模块140完成对驱动模块110的阈值进行补偿后，补偿模块140断开，此时脉冲电压发生跳变(其跳变的电压变化量可根据实际情况进行设置)，由于耦合模块160一端的电位发生变化，触发耦合模块160的耦合作用，将其一端的电压的变化量耦合至另一端，使得补偿模块140内部节点的电压发生变化，由于补偿模块140已经关断，因此，能够微调驱动模块110控制端G的电压，从而调节驱动电流，以改善阈值补偿效果，保证驱动模块110产生的驱动电流一致性。
可选地，图8为本申请实施例提供的另一种像素电路的结构示意图，参考图8，在上述各实施例的基础上，本申请实施例提供的像素电路还包括初始化模块200、第一发光控制模块180和第二发光控制模块190。初始化模块200连接在初始化信号线Vref和发光模块170的第一端之间，第一发光控制模块180连接在第一电源线VDD和驱动模块110的第二端之间，第二发光控制模块190连接在驱动模块110的第一端和发光模块170的第一端之间。
具体地，图9为本申请实施例提供的另一种像素电路的结构示意图，并示出了图8所示像素电路的具体结构，参考图9，以第二晶体管T2为双栅晶体管为例进行说明。驱动模块110包括第三晶体管T3，数据写入模块120包括第四晶体管T4，第一发光控制模块180包括第五晶体管T5，第二发光控制模块190包括第六晶体管T6，初始化模块200包括第七晶体管T7；第四晶体管T4的栅极连接第二扫描线S2，第四晶体管T4的第一极连接数据线Data，第四晶体管T4的第二极通过辅助模块130连接至第三晶体管T3的第一极，第五晶体管T5的第一极连接第一电源线VDD，第五晶体管T5的第二极与第三晶体管T3的第一极连接，第三晶体管T3的第二极通过第六晶体管T6与发光模块170的第一端连接，发光模块170的第二端连接第二电源线VSS，第五晶体管T5的栅极和第六晶体管T6的栅极均连接发光控制信号线EM；第七晶体管T7的第一极连接初始化信号线Vref，第七晶体管T7的第二极连接发光模块170的第一端，第 七晶体管T7的栅极连接第三扫描线S3；第五晶体管T5和第六晶体管T6被配置为在初始化阶段和发光阶段导通。
在本实施例中，信号线与其传输的电压采用同一标记进行表示，发光模块170可以为发光二极管OLED。
图10为本申请实施例提供的一种像素电路的控制时序图，适用于图9所示的像素电路，本实施例示例性地示出了第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7均为P型管。参考图9和图10，本申请实施例提供的像素电路的工作过程可以包括初始化阶段t1、数据写入和阈值补偿阶段t2、补偿调整阶段t3和发光阶段t4。
在初始化阶段t1，第一扫描线提供的第一扫描信号S1为低电平，第二扫描线提供的第二扫描信号S2为高电平，第三扫描信号线提供的第三扫描信号S3为低电平，发光控制信号线提供的发光控制信号EM为低电平。第一晶体管T1和第二晶体管T2响应第一扫描信号S1导通，第四晶体管T4响应第二扫描信号S2关断，第五晶体管T5和第六晶体管T6响应发光控制信号EM导通，第七晶体管T7响应第三扫描信号S3导通，初始化信号线上的初始化电压Vref传输至发光二极管OLED的第一极，并且通过第六晶体管T6和第二晶体管T2传输至第三晶体管T3的栅极，以对第三晶体管T3的栅极和发光二极管OLED的第一极的电位进行初始化。其中，VG表示为第三晶体管T3的栅极电压，VD表示为发光二极管OLED第一极电压。同时，由于第五晶体管T5导通，通过配置初始化电压Vref使得第三晶体管T3导通，因此，第一电源线VDD、第五晶体管T5、第三晶体管T3、第六晶体管T6、第七晶体管T7和初始化信号线Vref之间形成通路，第三晶体管T3产生电流，对第三晶体管T3中的电荷进行冲刷，使得第三晶体管T3中的电荷量初始化为初始化电压Vref对应的电荷量，以减小第三晶体管T3因迟滞效应带来的特性偏移，从而能够改善残影的现象。
进一步地，由于第二晶体管T2为双栅晶体管，相比于单栅管，具有更小的漏电流，且第三晶体管T3栅极电压的漏电路径仅有一条，能够维持第三晶体管T3栅极电压的稳定，有利于提高显示效果。
在数据写入和阈值补偿阶段t2，第一扫描线提供的第一扫描信号S1为低电平，第二扫描线提供的第二扫描信号S2为低电平，第三扫描信号线提供的第三扫描信号S3为高电平，发光控制信号线提供的发光控制信号EM为高电平。第一晶体管T1和第二晶体管T2响应第一扫描信号S1继续导通，第四晶体管T4响应第二扫描信号S2导通，第五晶体管T5和第六晶体管T6响应发光控制信号 EM关断，第七晶体管T7响应第三扫描信号S3关断。数据线Data上的数据电压通过第四晶体管T4、第一晶体管T1、第三晶体管T3和第二晶体管T2后写入与数据电压相关的电压至第三晶体管T3的栅极，同时第二晶体管T2对第三晶体管T3的阈值电压进行补偿，实现驱动模块110数据电压的写入和阈值电压的补偿。第一电容C1对第三晶体管T3的栅极电压进行存储，该存储的电压与数据电压和阈值电压相关联。
由于第二晶体管T2的导通时间较短，不能保证对第三晶体管T3的阈值电压进行完全补偿，在低灰阶下，容易导致显示亮度不均一。在补偿调整阶段t3，第一扫描线提供的第一扫描信号S1为高电平，第二扫描线提供的第二扫描信号S2为高电平，第三扫描信号线提供的第三扫描信号S3为高电平，发光控制信号线提供的发光控制信号EM为高电平。第一晶体管T1和第二晶体管T2响应第一扫描信号S1关断，第四晶体管T4响应第二扫描信号S2关断，第五晶体管T5和第六晶体管T6响应发光控制信号EM关断，第七晶体管T7响应第三扫描信号S3关断。在第一扫描信号S1由低电平跳变为高电平后(也即第二晶体管T2关断后)，脉冲电压的电平由高电平跳变至低电平，经过第三电容C3的耦合作用，第一节点N1的电位发生变化，从而导致第三晶体管T3的栅极和第一节点之间存在电压差，由于第二晶体管T2处于关断状态，在第二子晶体管T2-2的漏电作用下，能够微调第三晶体管T3的栅极电压，进而弥补了第三晶体管T3不能被完全补偿的情况，以保证第三晶体管T3产生的驱动电流一致，以提高显示亮度的均一性。并且在发光控制信号EM跳变之前(也即发光二极管OLED发光之前)，脉冲电压的电平由低电平跳变为高电平，防止在发光二极管OLED发光后导致第三晶体管T3栅极电位不稳定，造成显示不均一。在本实施例中，脉冲电压的脉冲宽度(低电平维持时间)可以根据驱动模块110亚阈值摆幅波动范围进行设置，以通过脉冲电压的跳变降低驱动模块110亚阈值摆幅波动导致的显示不均一。
在发光阶段t4，第一扫描线提供的第一扫描信号S1为高电平，第二扫描线提供的第二扫描信号S2为高电平，第三扫描信号线提供的第三扫描信号S3为高电平，发光控制信号线提供的发光控制信号EM为低电平。第一晶体管T1和第二晶体管T2响应第一扫描信号S1关断，第四晶体管T4响应第二扫描信号S2关断，第五晶体管T5和第六晶体管T6响应发光控制信号EM导通，第七晶体管T7响应第三扫描信号S3关断。第三晶体管T3在其栅极电压的控制下产生驱动电流，由于在上一阶段已经对栅极电压进行了调整，因此，在发光阶段t4 能够保证发光二极管OLED在同一灰阶电压下具有相同的驱动电流，以提高显示亮度的均一性。
第一晶体管T1起到改善像素电路的版图布局的功能，不会影响像素电路的工作原理。通过设置第一晶体管T1，能够减少版图的过孔数量，进而减小像素电路的布局面积，以提高显示面板的PPI。在本实施例中，第二晶体管T2可以替换为上述实施例中所述的三栅晶体管或四栅晶体管，固定电压可以为第一电源电压VDD或初始化电压Vref中的任一个，这里的像素电路的工作原理不变，可参考上述实施例中的相关描述，不再赘述。
可选地，图11为本申请实施例提供的另一种像素电路的结构示意图，参考图10和11，在上述实施例的基础上，本实施例中的辅助模块130包括第一晶体管T1和第二电容C2，其中第二电容C2可以连接在第一晶体管T1的第一极或第二极。在其他实施例中，第一晶体管T1可以省略，保留第二电容C2，不会影响像素电路的工作原理。
在数据写入和阈值补偿阶段t2，第一扫描线提供的第一扫描信号S1为低电平，第二扫描线提供的第二扫描信号S2为低电平，第三扫描信号线提供的第三扫描信号S3为高电平，发光控制信号线提供的发光控制信号EM为高电平。第一晶体管T1和第二晶体管T2响应第一扫描信号S1导通，第四晶体管T4响应第二扫描信号S2导通，第五晶体管T5和第六晶体管T6响应发光控制信号EM关断，第七晶体管T7响应第三扫描信号S3关断。数据线Data上的数据电压通过第四晶体管T4、第一晶体管T1、第三晶体管T3和第二晶体管T2后写入与数据电压相关的电压至第三晶体管T3的栅极，并将数据电压存储在第二电容C2中。同时第二晶体管T2对第三晶体管T3的阈值电压进行补偿，实现驱动模块110数据电压的写入和阈值电压的补偿。第一电容C1对第三晶体管T3的栅极电压进行存储，该存储的电压与数据电压和阈值电压相关联。
在亚阈值摆幅补偿阶段t2’，第一扫描信号S1为低电平，第二扫描信号S2为高电平，第四晶体管T4关断，第一晶体管T1和第二晶体管T2导通。由于第二电容C2上存储了数据电压，因此，第二电容C2上的数据电压可经第一晶体管T1、第三晶体管T3、第二晶体管T2继续向第三晶体管T3的栅极充电，也就是，在亚阈值摆幅补偿阶段t2’，第一扫描线输出的第一扫描信号S1控制辅助模块130和补偿模块140导通，第二扫描线输出的第二扫描信号S2控制数据写入模块120关断，第二电容C2上存储的数据电压经过驱动模块110和补偿模块140对驱动模块110控制端的电压进行调整。在低灰阶下通过第二电容C2对第 三晶体管T3的栅极充电过程中，充电电流较小，能够对第三晶体管T3的栅极电压进行微调，从而能够改善因工艺原因造成的第三晶体管T3亚阈值摆幅具有离散型的状况所造成的显示效果不均一，实现了对亚阈值摆幅进行补偿，保证驱动模块110产生的驱动电流的一致性。t2’阶段充电的电流通常为小电流，t2’对应的时长大于t2对应的时长，以实现在低灰阶对亚阈值摆幅离散造成的驱动电流变化进行有效补偿。
在补偿调整阶段t3，第一晶体管T1和第二晶体管T2处于关断状态，脉冲电压由高电平跳变至低电平，经过第三电容C3的耦合作用，第一节点N1的电位发生变化，从而导致第三晶体管T3的栅极和第一节点之间存在电压差，由于第二晶体管T2处于关断状态，在第二子晶体管T2-2的漏电作用下，能够微调第三晶体管T3的栅极电压，进而弥补了第三晶体管T3不能被完全补偿的情况，以进一步保证第三晶体管T3产生的驱动电流一致，以提高显示亮度的均一性。
其中，初始化阶段t1和发光阶段t4的工作原理可参照对图9所示像素电路的相关描述，在此不再赘述。
在本实施例中，通过第二电容C2和第三电容C3均能够对第三晶体管T3的亚阈值摆幅进行补偿，而先通过第二电容C2提高第三晶体管T3栅极电压后，在通过第三电容C3将跳变电压V1耦合至补偿模块140内部，以微调第三晶体管T3的栅极电压，能够减小对第三晶体管T3栅极电压调整的幅度，在低灰阶下，能够提高对第三晶体管T3栅极电压调整的精度，有利于实现对其产生的驱动电流的精度控制。
本申请任意实施例均能够相互结合，均能够实现改善补偿效果，提高显示亮度均一性的效果。
可选地，本申请实施例还提供了一种像素电路的驱动方法，图12为本申请实施例提供的一种像素电路的驱动方法的流程图，参考图1和图12，该像素电路包括驱动模块110、数据写入模块120、辅助模块130、补偿模块140、存储模块150、耦合模块160和发光模块170，数据写入模块120通过辅助模块130与驱动模块110连接，补偿模块140连接于驱动模块110的第一端和控制端G之间，耦合模块160与补偿模块140连接，存储模块150与驱动模块110的控制端G连接；
该像素电路的驱动方法包括：
S110、在数据写入和阈值补偿阶段，控制数据写入模块通过辅助模块向驱动模块的控制端写入与数据电压相关的电压，并通过补偿模块对驱动模块的阈 值电压进行补偿。
S120、在补偿调整阶段，控制耦合模块根据接收到的跳变电压通过补偿模块调整驱动模块控制端的电压。
S130、在发光阶段，控制驱动模块根据控制端的电压向发光模块提供驱动信号，驱动发光模块发光。
本申请实施例提供的像素电路的驱动方法，在数据写入和阈值补偿阶段，通过控制数据写入模块和补偿模块分别响应不同的扫描信号，使得数据线提供的数据电压经数据写入模块、辅助模块、驱动模块和补偿模块后写入与数据电压相关的电压至驱动模块的控制端，实现对驱动模块的数据写入和阈值补偿。在对驱动模块的阈值进行补偿后，通过耦合模块将跳变电压耦合至补偿模块中，以通过补偿模块微调驱动模块控制端的电压，使得不同像素电路在同一灰阶电压下产生的驱动电流一致，从而改善阈值补偿效果，提高显示亮度的均一性。且通过增加辅助模块，使得信号能够直接通过有源层进行传输，从而有利于减少过孔数量，优化了版图布局，降低了像素的布局面积，进而有利于实现高PPI。
进一步地，参考图8和图9，辅助模块130的控制端连接第一扫描线，补偿模块140的控制端连接第一扫描线S1，数据写入模块120的控制端连接第二扫描线S2，像素电路还包括初始化模块200、第一发光控制模块180和第二发光控制模块190，初始化模块200的控制端连接第三扫描线S3，初始化模块200的第一端连接初始化信号线Vref，初始化模块200的第二端与发光模块170的第一端连接，第一发光控制模块180的控制端和第二发光控制模块190的控制端均连接发光控制信号线EM，第一发光控制模块180的第一端与第一电源线VDD连接，第一发光控制模块180的第二端与驱动模块110的第二端连接，第二发光控制模块190的第一端与驱动模块110的第一端连接，第二发光控制模块190的第二端与发光模块170的第一端连接，发光模块170的第二端连接第二电源线VSS。
辅助模块130包括第一晶体管T1，补偿模块140包括第二晶体管T2，第二晶体管T2为双栅晶体管，驱动模块110包括第三晶体管T3，数据写入模块120包括第四晶体管T4，第一发光控制模块180包括第五晶体管T5，第二发光控制模块190包括第六晶体管T6，初始化模块200包括第七晶体管T7，结合图10所示的控制时序，本申请实施例提供的像素电路的驱动方法包括：
在初始化阶段t1，第一扫描线输出的第一扫描信号S1控制辅助模块130和补偿模块140导通，第三扫描线输出的第三扫描信号S3控制初始化模块200导 通，发光控制信号线输出的发光控制信号EM控制第一发光控制模块180和第二发光控制模块190导通。初始化信号线上的初始化电压Vref传输至发光二极管OLED的第一极，并且通过第六晶体管T6和第二晶体管T2传输至第三晶体管T3的栅极，以对第三晶体管T3的栅极和发光二极管OLED的第一极的电位进行初始化。同时，由于第五晶体管T5导通，通过配置初始化电压Vref使得第三晶体管T3导通，因此，第一电源线VDD、第五晶体管T5、第三晶体管T3、第六晶体管T6、第七晶体管T7和初始化信号线Vref之间形成通路，第三晶体管T3产生电流，对第三晶体管T3中的电荷进行冲刷，使得第三晶体管T3中的电荷量初始化为初始化电压Vref对应的电荷量，以减小第三晶体管T3因迟滞效应带来的特性偏移，从而能够改善残影的现象。
在本实施例中，由于第二晶体管T2为双栅晶体管，相比于单栅管，具有更小的漏电流，且第三晶体管T3栅极电压的漏电路径仅有一条，能够维持第三晶体管T3栅极电压的稳定，有利于提高显示效果。
在数据写入和阈值补偿阶段t2，第一扫描线输出的第一扫描信号S1控制辅助模块130和补偿模块140导通，第二扫描线输出的第二扫描信号S2控制数据写入模块120导通。数据线Data上的数据电压通过第四晶体管T4、第一晶体管T1、第三晶体管T3和第二晶体管T2后写入与数据电压相关的电压至第三晶体管T3的栅极，同时第二晶体管T2对第三晶体管T3的阈值电压进行补偿，实现驱动模块110数据电压的写入和阈值电压的补偿。第一电容C1对第三晶体管T3的栅极电压进行存储，该存储的电压与数据电压和阈值电压相关联。
在补偿调整阶段t3，第一扫描线输出的第一扫描信号S1控制辅助模块130和补偿模块140关断，控制耦合模块160根据接收到的跳变电压通过补偿模块140调整驱动模块110控制端G的电压。在第一扫描信号S1由低电平跳变为高电平后(也即第二晶体管T2关断后)，第三电容C3一端的脉冲电压的电平由高电平跳变至低电平，经过第三电容C3的耦合作用，第一节点N1的电位发生变化，从而导致第三晶体管T3的栅极和第一节点之间存在电压差，由于第二晶体管T2处于关断状态，在第二子晶体管T2-2的漏电作用下，能够微调第三晶体管T3的栅极电压，进而弥补了第三晶体管T3不能被完全补偿的情况，以保证第三晶体管T3产生的驱动电流一致，以提高显示亮度的均一性。
在发光阶段t4，发光控制信号线输出的发光控制信号EM控制第一发光控制模块180和第二发光控制模块190导通。第三晶体管T3在其栅极电压的控制下产生驱动电流，由于在上一阶段已经对栅极电压进行了调整，因此，在发光 阶段t4能够保证发光二极管OLED在同一灰阶电压下具有相同的驱动电流，以提高显示亮度的均一性。
可选地，本申请实施例还提供了一种显示面板，该显示面板包括本申请实施例所提供的像素电路，图13为本申请实施例提供的一种显示面板的结构示意图，图13所示显示面板为手机显示面板，该显示面板可以应用到平板、手表、可穿戴设备，以及车载显示、相机显示、电视和电脑屏幕等其他所有的与显示相关的设备中。由于该显示面板包括本申请任意实施例所提供的像素电路，因此，本申请实施例提供的显示面板也具备本申请任意实施例所描述的有益效果。
注意，上述仅为本申请的较佳实施例及所运用技术原理。本领域技术人员会理解，本申请不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本申请的保护范围。因此，虽然通过以上实施例对本申请进行了较为详细的说明，但是本申请不仅仅限于以上实施例，在不脱离本发明构思的情况下，还可以包括更多其他等效实施例，而本申请的范围由所附的权利要求范围决定。

Claims (20)

  1. 一种像素电路，包括：驱动模块、数据写入模块、辅助模块、补偿模块、存储模块、耦合模块和发光模块；
    所述数据写入模块设置为通过所述辅助模块向所述驱动模块的控制端写入与数据电压相关的电压；
    所述补偿模块连接于所述驱动模块的第一端和控制端之间，设置为对所述驱动模块的阈值电压进行补偿；
    所述耦合模块与所述补偿模块连接，设置为根据接收到的跳变电压通过所述补偿模块调整所述驱动模块控制端的电压；
    所述存储模块与所述驱动模块的控制端连接，设置为存储所述驱动模块控制端的电压；
    所述驱动模块设置为根据控制端的电压向所述发光模块提供驱动信号，驱动所述发光模块发光。
  2. 根据权利要求1所述的像素电路，其中，所述存储模块包括第一电容，所述第一电容的第一极连接固定电压，所述第一电容的第二极与所述驱动模块的控制端连接。
  3. 根据权利要求1或2所述的像素电路，其中，所述辅助模块包括第一晶体管，所述第一晶体管的栅极连接第一扫描线，所述第一晶体管的第一极连接所述数据写入模块的第二端，所述第一晶体管的第二极连接所述驱动模块的第二端，所述数据写入模块的第一端连接数据线。
  4. 根据权利要求1或2所述的像素电路，其中，所述辅助模块包括所述第一晶体管和第二电容，所述第一晶体管的栅极连接第一扫描线，所述第一晶体管的第一极连接所述数据写入模块的第二端，所述第一晶体管的第二极连接所述驱动模块的第二端，所述数据写入模块的第一端连接数据线，所述第二电容的第一端连接固定电压，所述第二电容的第二端与所述第一晶体管的第一极或第二极连接。
  5. 根据权利要求1所述的像素电路，其中，所述补偿模块包括第二晶体管，所述第二晶体管为双栅晶体管，所述第二晶体管包括第一子晶体管和第二子晶体管；
    所述第一子晶体管的栅极和所述第二子晶体管的栅极分别连接第一扫描线，所述第一子晶体管的第一极与所述驱动模块的第一端连接，所述第一子晶体管的第二极与所述第二子晶体管的第一极连接，所述第二子晶体管的第二极与所述驱动模块的控制端连接。
  6. 根据权利要求5所述的像素电路，其中，所述跳变电压为脉冲电压，所述耦合模块包括第三电容，所述第三电容的第一极接入所述脉冲电压，所述第三电容的第二极与所述第二子晶体管的第一极连接。
  7. 根据权利要求1所述的像素电路，其中，所述补偿模块包括第二晶体管，所述第二晶体管为三栅晶体管，所述第二晶体管包括第一子晶体管、第二子晶体管和第三子晶体管；
    所述第一子晶体管的栅极、所述第二子晶体管的栅极和所述第三子晶体管的栅极分别连接第一扫描线，所述第一子晶体管的第一极与所述驱动模块的第一端连接，所述第一子晶体管的第二极与所述第二子晶体管的第一极连接，所述第二子晶体管的第二极与所述第三子晶体管的第一极连接，所述第三子晶体管的第二极与所述驱动模块的控制端连接。
  8. 根据权利要求7所述的像素电路，其中，所述耦合模块设置为将所述跳变电压耦合至所述第二子晶体管的第一极和所述第二子晶体管的第二极中的至少一个。
  9. 根据权利要求8所述的像素电路，其中，所述跳变电压为脉冲电压，所述耦合模块包括第三电容和第四电容，所述第三电容的第一极接入所述脉冲电压，所述第三电容的第二极与所述第二子晶体管的第二极连接，所述第四电容的第一极接入所述脉冲电压或固定电压，所述第四电容的第二极与所述第二子晶体管的第一极连接。
  10. 根据权利要求1所述的像素电路，其中，所述补偿模块包括第二晶体管，所述第二晶体管为四栅晶体管，所述第二晶体管包括第一子晶体管、第二子晶体管、第三子晶体管和第四子晶体管；
    所述第一子晶体管的栅极、所述第二子晶体管的栅极、所述第三子晶体管的栅极和所述第四子晶体管的栅极分别连接第一扫描线，所述第一子晶体管的第一极与所述驱动模块的第一端连接，所述第一子晶体管的第二极与所述第二子晶体管的第一极连接，所述第二子晶体管的第二极与所述第三子晶体管的第一极连接，所述第三子晶体管的第二极与所述第四子晶体管的第一极连接，所述第四子晶体管的第二极与所述驱动模块的控制端连接；所述耦合模块设置为将所述跳变电压耦合至所述第二子晶体管的第一极、所述第二子晶体管的第二极和所述第三子晶体管的第二极中的至少一者。
  11. 根据权利要求10所述的像素电路，其中，所述跳变电压为脉冲电压，所述耦合模块包括第三电容、第四电容和第五电容，所述第三电容的第一极接 入所述脉冲电压，所述第三电容的第二极与所述第三子晶体管的第二极连接，所述第四电容的第一极接入所述脉冲电压或固定电压，所述第四电容的第二极与所述第二子晶体管的第二极连接，所述第五电容的第一极接入所述脉冲电压或固定电压，所述第五电容的第二极与所述第一子晶体管的第二极连接。
  12. 根据权利要求6、9或11所述的像素电路，其中，所述脉冲电压的脉冲在所述第一扫描线上传输的脉冲信号之后。
  13. 根据权利要求12所述的像素电路，其中，所述脉冲电压在所述补偿模块关断后由高电平跳变至低电平，并在所述发光模块发光之前由低电平跳变为高电平；或者，所述脉冲电压在所述补偿模块关断后由低电平跳变至高电平，并在所述发光模块发光之前由高电平跳变为低电平。
  14. 根据权利要求1所述的像素电路，其中，所述辅助模块的控制端和所述补偿模块的控制端分别连接第一扫描线，所述像素电路还包括第一发光控制模块和第二发光控制模块，所述驱动模块包括第三晶体管，所述数据写入模块包括第四晶体管，所述第一发光控制模块包括第五晶体管，所述第二发光控制模块包括第六晶体管；
    所述第四晶体管的栅极连接第二扫描线，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极通过所述辅助模块连接至所述第三晶体管的第一极，所述第五晶体管的第一极连接第一电源线，所述第五晶体管的第二极与所述第三晶体管的第一极连接，所述第三晶体管的第二极通过所述第六晶体管与所述发光模块的第一端连接，所述发光模块的第二端连接第二电源线，所述第五晶体管的栅极和所述第六晶体管的栅极分别连接发光控制信号线；所述第五晶体管和所述第六晶体管被配置为在初始化阶段和发光阶段导通。
  15. 根据权利要求14所述的像素电路，所述像素电路还包括初始化模块，所述初始化模块包括第七晶体管；
    所述第七晶体管的第一极连接初始化信号线，所述第七晶体管的第二极连接所述发光模块的第一端，所述第七晶体管的栅极连接第三扫描线。
  16. 根据权利要求15所述的像素电路，其中，所述第一扫描线、所述第二扫描线、所述第三扫描线和所述发光控制信号线被配置为传输扫描信号以满足：
    在初始化阶段，所述辅助模块、所述补偿模块、所述初始化模块、所述第一发光控制模块和所述第二发光控制模块导通；
    在数据写入和阈值补偿阶段，所述数据写入模块、所述辅助模块和所述补偿模块导通；
    在补偿调整阶段，所述辅助模块和所述补偿模块关断；
    在发光阶段，所述第一发光控制模块和所述第二发光控制模块导通。
  17. 一种像素电路的驱动方法，所述像素电路包括驱动模块、数据写入模块、辅助模块、补偿模块、存储模块、耦合模块和发光模块，所述数据写入模块通过所述辅助模块与所述驱动模块连接，所述补偿模块连接于所述驱动模块的第一端和控制端之间，所述耦合模块与所述补偿模块连接，所述存储模块与所述驱动模块的控制端连接；
    所述像素电路的驱动方法包括：
    在数据写入和阈值补偿阶段，控制所述数据写入模块通过所述辅助模块向所述驱动模块的控制端写入与数据电压相关的电压，并通过所述补偿模块对所述驱动模块的阈值电压进行补偿；
    在补偿调整阶段，控制所述耦合模块根据接收到的跳变电压通过所述补偿模块调整所述驱动模块控制端的电压；
    在发光阶段，控制所述驱动模块根据控制端的电压向所述发光模块提供驱动信号，驱动所述发光模块发光。
  18. 根据权利要求17所述的像素电路的驱动方法，其中，所述辅助模块的控制端连接第一扫描线，所述补偿模块的控制端连接所述第一扫描线，所述数据写入模块的控制端连接第二扫描线，所述像素电路还包括初始化模块、第一发光控制模块和第二发光控制模块，所述初始化模块的控制端连接第三扫描线，所述初始化模块的第一端连接初始化信号线，所述初始化模块的第二端与所述发光模块的第一端连接，所述第一发光控制模块的控制端和所述第二发光控制模块的控制端分别连接发光控制信号线，所述第一发光控制模块的第一端与第一电源线连接，所述第一发光控制模块的第二端与所述驱动模块的第二端连接，所述第二发光控制模块的第一端与所述驱动模块的第一端连接，所述第二发光控制模块的第二端与所述发光模块的第一端连接，所述发光模块的第二端连接第二电源线；
    所述像素电路的驱动方法包括：
    在初始化阶段，所述第一扫描线输出的第一扫描信号控制所述辅助模块和所述补偿模块导通，所述第三扫描线输出的第三扫描信号控制所述初始化模块导通，所述发光控制信号线输出的发光控制信号控制所述第一发光控制模块和第二发光控制模块导通；
    在数据写入和阈值补偿阶段，所述第一扫描线输出的第一扫描信号控制所 述辅助模块和所述补偿模块导通，所述第二扫描线输出的第二扫描信号控制所述数据写入模块导通；
    在补偿调整阶段，所述第一扫描线输出的第一扫描信号控制所述辅助模块和所述补偿模块关断，控制所述耦合模块根据接收到的跳变电压通过所述补偿模块调整所述驱动模块控制端的电压；
    在发光阶段，所述发光控制信号线输出的发光控制信号控制所述第一发光控制模块和第二发光控制模块导通。
  19. 根据权利要求17或18所述的像素电路的驱动方法，其中，所述补偿模块的控制端连接所述第一扫描线，所述数据写入模块的控制端连接第二扫描线，所述辅助模块包括第一晶体管和第二电容，所述第一晶体管的栅极连接所述第一扫描线，所述第一晶体管的第一极连接所述数据写入模块的第二端，所述第一晶体管的第二极连接所述驱动模块的第二端，所述第二电容的第一端连接固定电压，所述第二电容的第二端与所述第一晶体管的第一极或第二极连接；
    所述像素电路的驱动方法包括：
    在亚阈值摆幅补偿阶段，所述第一扫描线输出的第一扫描信号控制所述辅助模块和所述补偿模块导通，所述第二扫描线输出的第二扫描信号控制所述数据写入模块关断，所述第二电容上存储的数据电压经过所述驱动模块和所述补偿模块对所述驱动模块控制端的电压进行调整。
  20. 一种显示面板，包括如权利要求1-16任一项所述的像素电路。
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