WO2023092683A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2023092683A1
WO2023092683A1 PCT/CN2021/136934 CN2021136934W WO2023092683A1 WO 2023092683 A1 WO2023092683 A1 WO 2023092683A1 CN 2021136934 W CN2021136934 W CN 2021136934W WO 2023092683 A1 WO2023092683 A1 WO 2023092683A1
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WO
WIPO (PCT)
Prior art keywords
photosensitive
layer
electrode
display panel
pixel definition
Prior art date
Application number
PCT/CN2021/136934
Other languages
English (en)
French (fr)
Inventor
孙垒涛
鲜于文旭
张春鹏
罗志猛
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/621,629 priority Critical patent/US20240107855A1/en
Publication of WO2023092683A1 publication Critical patent/WO2023092683A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
    • H01L31/125—Composite devices with photosensitive elements and electroluminescent elements within one single body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K65/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element and at least one organic radiation-sensitive element, e.g. organic opto-couplers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application relates to the display field, in particular to a display panel.
  • the performance of the internal materials will gradually deteriorate, which will lead to abnormal phenomena such as reduced display brightness and uneven display, and even affect the display performance of the display panel.
  • the existing display panels have the problems of luminance attenuation and poor luminance uniformity after long-term use, which need to be improved.
  • the present application provides a display panel to improve display brightness and brightness uniformity of the display panel.
  • the present application provides a display panel, which includes:
  • a pixel definition layer including light-emitting openings distributed in an array
  • the photosensitive element is arranged on the pixel definition layer, and the projection of the photosensitive element on the pixel definition layer is located outside the light emitting opening.
  • the photosensitive element includes a first photosensitive electrode, a second photosensitive electrode, and a photosensitive layer located between the first photosensitive electrode and the second photosensitive electrode, the The first photosensitive electrode, the photosensitive layer, and the second photosensitive electrode are sequentially stacked on the pixel definition layer.
  • the first photosensitive electrode is a transparent electrode
  • the second photosensitive electrode is a highly reflective electrode
  • the surface of the first photosensitive electrode close to the photosensitive layer is a concave-convex surface.
  • the display panel further includes a second photosensitive electrode lead, and the second photosensitive electrode lead is arranged on the same layer as the second photosensitive electrode and connected to the second photosensitive electrode. connect.
  • the display panel further includes a flat layer, the flat layer is disposed on the pixel definition layer and connected to the photosensitive element.
  • the surface of the flat layer away from the pixel definition layer is not lower than the surface of the photosensitive layer away from the pixel definition layer.
  • the display panel further includes a first light-emitting electrode and a second light-emitting electrode respectively arranged on both sides of the light-emitting layer, and the second light-emitting electrode is arranged on the display panel.
  • the light emitting side of the panel; the second light emitting electrode is arranged on the second photosensitive electrode and insulated from the second photosensitive electrode.
  • the display panel further includes a photosensitive circuit connected to the first photosensitive electrode.
  • the display panel further includes a driving circuit layer, and the photosensitive circuit is disposed in the driving circuit layer.
  • the photosensitive element is arranged around the light emitting opening.
  • annular opening in the photosensitive element, and the annular opening exposes the pixel definition layer.
  • the present application provides a display panel, which includes:
  • a pixel definition layer including light-emitting openings distributed in an array
  • the photosensitive element is arranged on the pixel definition layer, and the projection of the photosensitive element on the pixel definition layer is located outside the light emitting opening, and the photosensitive element and the light emitting layer are insulated from each other.
  • the photosensitive element includes a first photosensitive electrode, a second photosensitive electrode, and a photosensitive layer located between the first photosensitive electrode and the second photosensitive electrode, the The first photosensitive electrode, the photosensitive layer, and the second photosensitive electrode are sequentially stacked on the pixel definition layer.
  • the first photosensitive electrode is a transparent electrode
  • the second photosensitive electrode is a highly reflective electrode
  • the surface of the first photosensitive electrode close to the photosensitive layer is a concave-convex surface.
  • the display panel further includes a second photosensitive electrode lead, and the second photosensitive electrode lead is arranged on the same layer as the second photosensitive electrode and connected to the second photosensitive electrode. connect.
  • the display panel further includes a flat layer, the flat layer is disposed on the pixel definition layer and connected to the photosensitive element, the flat layer is far away from the The surface of the pixel definition layer is not lower than the surface of the photosensitive layer away from the pixel definition layer.
  • the photosensitive element is arranged around the light emitting opening.
  • annular opening in the photosensitive element, and the annular opening exposes the pixel definition layer.
  • the present application provides a display panel, which includes: a pixel definition layer, including light emitting openings distributed in an array; a light emitting layer, arranged in the light emitting openings; a photosensitive element, arranged on the pixel definition layer. Glowing openings outside.
  • the photosensitive element can better sense the light emitted upward by the light-emitting layer, and convert the optical signal into an electrical signal for feedback, thereby improving the luminous brightness of the display panel. Compensation is performed to solve the problems of brightness attenuation and poor brightness uniformity after long-term use in the existing display panel.
  • FIG. 1 is a schematic top view structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application
  • Fig. 3 is the first cross-sectional view of the array substrate provided in the embodiment of the present application in the AA' direction;
  • Fig. 4 is a second cross-sectional view of the array substrate provided in the embodiment of the present application in the AA' direction;
  • Fig. 5 is a first cross-sectional view of the array substrate provided in the embodiment of the present application in the direction of BB';
  • Fig. 6 is a second cross-sectional view of the array substrate provided in the embodiment of the present application in the direction of BB';
  • Fig. 7 is a third cross-sectional view of the array substrate provided in the embodiment of the present application in the direction of BB';
  • FIG. 8 is a schematic diagram of a brightness compensation system for a display panel provided by an embodiment of the present application.
  • FIG. 9 is a schematic flowchart of the first method for preparing an array substrate provided in the embodiment of the present application.
  • FIG. 10 is a schematic flowchart of a second method for preparing an array substrate provided in an embodiment of the present application.
  • Fig. 11 is a schematic structural diagram of the first method for preparing an array substrate provided in the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a second method for preparing an array substrate provided in an embodiment of the present application.
  • the present application provides a display panel that can solve this problem.
  • FIG. 1 shows a schematic top view of a display panel provided by an embodiment of the present invention
  • FIG. 2 shows a cross-section of a display panel provided by an embodiment of the present invention Structural schematic diagram
  • Fig. 3 shows the first cross-sectional view of the display panel provided by the embodiment of the present invention in the AA' direction
  • Fig. 4 shows the second cross-sectional view of the display panel provided by the embodiment of the present invention in the AA' direction
  • FIG. 5 shows the first cross-sectional view of the display panel provided by the embodiment of the present invention in the BB' direction
  • FIG. 6 shows the second cross-sectional view of the display panel provided by the embodiment of the present invention in the BB' direction
  • 7 shows a third cross-sectional view of the display panel provided by the embodiment of the present invention along the BB' direction.
  • the display panel provided by the embodiment of the present application includes:
  • a pixel definition layer 141 includes light emitting openings 101 distributed in an array
  • the light emitting layer 152 is arranged in the light emitting opening 101;
  • the photosensitive element 130 is disposed on the pixel definition layer 141 , and the projection of the photosensitive element 130 on the pixel definition layer 141 is outside the light emitting opening 101 .
  • This application implements that by arranging a photosensitive element obliquely above the light-emitting opening of the display panel, the photosensitive element can better sense the light emitted upwards from the light-emitting layer, and convert the optical signal into an electrical signal for feedback, and then provide feedback to the display panel.
  • the luminous brightness is compensated, which solves the problems of brightness attenuation and poor brightness uniformity after long-term use of the existing display panels.
  • the display panel 10 includes an array substrate 100, a light-emitting layer 152, and a second light-emitting electrode 153, the second light-emitting electrode 153 covers the array substrate 100 and the light-emitting layer 152, and the photosensitive element 130 is arranged on the array substrate 100. Inside the substrate 100.
  • the array substrate 100 includes a thin film transistor layer 120 disposed on a substrate 110 .
  • the thin film transistor layer 120 includes a light emitting circuit 121 and a photosensitive circuit 122 , the light emitting circuit 121 is electrically connected to the first light emitting electrode 151 , and the photosensitive circuit 122 is electrically connected to the photosensitive element 130 .
  • the thin film transistor includes a semiconductor active layer, a first insulating layer, a gate layer, a second insulating layer, a source and drain layer, and a third insulating layer that are sequentially stacked on a substrate.
  • the semiconductor active layer includes the active region of the thin film transistor in the light emitting circuit 121 and the active region of the thin film transistor in the photosensitive circuit 122
  • the gate layer includes the gate of the thin film transistor in the light emitting circuit 121 and the gate of the thin film transistor in the photosensitive circuit 122
  • the source-drain layer includes the source-drain of the TFT in the light-emitting circuit 121 and the source-drain of the TFT in the light-sensing circuit 122 .
  • the first light-emitting electrode 151 is connected to the source or drain of the thin film transistor in the light-emitting circuit 121 through the via hole penetrating the third insulating layer, and the photosensitive element 130 is connected to the photosensitive circuit 122 through the via hole penetrating the third insulating layer and surrounding the pixel definition layer 141 The source or drain connection of the inner thin film transistor.
  • the array substrate 100 includes a photosensitive element 130 , and the photosensitive element 130 includes a first photosensitive electrode 131 , a second photosensitive electrode 135 , and a photosensitive layer between the first photosensitive electrode 131 and the second photosensitive electrode 135 .
  • the first photosensitive electrode 131 , the photosensitive layer and the second photosensitive electrode 135 are sequentially stacked on the pixel definition layer 141 .
  • the photosensitive layer can be any one of PIN type photodiode or PN type photodiode.
  • the photosensitive layer is a PIN-type photodiode, including a P-type semiconductor layer, an N-type semiconductor layer, and a base between the P-type semiconductor layer and the N-type semiconductor layer.
  • the layer 132, layer 133, and layer 134 are respectively a P-type semiconductor layer, an intrinsic layer, and an N-type semiconductor layer.
  • the photosensitive layer is a PIN photodiode and the first photosensitive electrode 131 is an anode and the second photosensitive electrode 135 is a cathode.
  • the via hole is connected to the source or drain of the thin film transistor in the photosensitive circuit 122 .
  • the first photosensitive electrode 131 is a transparent electrode.
  • the transparent electrode provides the anode electrical signal for the photosensitive layer, and on the other hand, it is used to pass through the light emitted by the light emitting layer in the light emitting opening 101 of the display panel, so that the light emitted by the display panel passes through
  • the lower side of the photosensitive layer is captured by the photosensitive layer, improving the photoelectric conversion efficiency of the photosensitive element 130 .
  • the material of the first photosensitive electrode 131 is a transparent conductive material, including but not limited to aluminum-doped zinc oxide (AZO), indium tin oxide (ITO), and fluorine-doped tin oxide (FTO).
  • the surface of the first photosensitive electrode 131 close to the photosensitive layer is an uneven rough surface, and the uneven surface reduces the reflectivity of the first photosensitive electrode 131 to the display light incident on the photosensitive element 130, thereby further improving the photosensitive element 130. Photoelectric conversion efficiency.
  • the second photosensitive electrode 135 is an opaque electrode.
  • the opaque electrode provides the cathode electrical signal for the photosensitive layer; , which improves the performance of the photosensitive element 130; on the other hand, as a reflective layer, when the light emitted from the light-emitting layer of the display panel reaches the second photosensitive electrode 135, it is reflected back into the photosensitive layer by the second photosensitive electrode 135, thereby further improving The photoelectric conversion efficiency of the photosensitive element 130 .
  • the material of the second photosensitive electrode 135 is a conductive material with high reflectivity, including but not limited to silver (Ag), molybdenum (Mo) and aluminum (Al).
  • the array substrate 100 further includes a second photosensitive electrode lead, which is disposed on the same layer as the second photosensitive electrode 135 and connected to the second photosensitive electrode 135 .
  • the second photosensitive electrode leads include a second photosensitive electrode sub-lead 136 and a second photosensitive electrode main lead 137, and each second photosensitive electrode sub-lead 136 is connected to the second photosensitive electrode 135 in the same column, all The second photosensitive electrode sub-leads 136 are laterally connected to the same second photosensitive electrode main lead 137; it is also possible that each second photosensitive electrode sub-lead 136 is connected to the second photosensitive electrodes 135 in the same row, and all the second photosensitive electrodes
  • the electrode sub-leads 136 are longitudinally connected to the same second photosensitive electrode main lead 137; it is also possible that each second photosensitive electrode sub-lead 136 is connected to the second photosensitive electrodes 135 in different rows or columns, and all the second photosensitive electrode sub-leads 136 is connected
  • the array substrate 100 further includes a flat layer 142 , as shown in FIGS. 2 to 7 , the flat layer 142 is disposed on the pixel definition layer 141 and disposed on the same layer as the photosensitive element 130 .
  • the flat layer 142 is used to planarize the plane of the array substrate where the photosensitive layer is located, and provide a flat base for the preparation of the second photosensitive electrode 135 and the second photosensitive electrode lead, thereby preventing the second photosensitive electrode 135 and the second photosensitive electrode lead from being broken. line risk.
  • the surface of the flat layer 142 away from the pixel definition layer 142 is flush or substantially flush with the surface of the photosensitive layer away from the pixel definition layer 141, usually the surface of the flat layer 142 away from the pixel definition layer 142 is not lower than the photosensitive layer away from the pixel definition layer 141; so that the second photosensitive electrode leads and the second photosensitive electrode 135 are located on the same plane or substantially on the same plane, further avoiding the possible disconnection risk of the second photosensitive electrode 135 and the second photosensitive electrode leads, and improving the array substrate. photoelectric conversion performance.
  • the array substrate 100 also includes an electrode insulating layer 143. As shown in FIGS. In order to isolate the second photosensitive electrode 135 from the second light emitting electrode of the display panel, the photosensitive element 130 is prevented from being electrically connected to the second light emitting electrode of the display panel.
  • the electrode insulating layer 143 includes an insulating layer opening corresponding to the light emitting opening 101 , the insulating layer opening exposes the first light emitting electrode 151 and covers the light emitting opening 101 . In one embodiment, as shown in FIG. 5 and FIG.
  • the flat layer 142 is arranged around the photosensitive element 130 to fill the region on the pixel definition layer 141 outside the photosensitive element 130 and the light-emitting opening 101 , and the electrode insulating layer 143 also covers the photosensitive element. 130 sides.
  • the flat layer 142 fills the area on the pixel definition layer 141 other than the photosensitive element 130 and the light-emitting opening 101 , and the flat layer 142 also covers the sides of the photosensitive element 130 ,
  • the electrode insulating layer 143 is only disposed on the second photosensitive electrode 135 and the flat layer 142 .
  • the photosensitive element 130 is disposed around the light emitting opening 101 .
  • the photosensitive element 130 is disposed around the light emitting opening 101 so that the light emitted by the light emitting layer in the light emitting opening of the display panel to the surroundings can be captured by the photosensitive element 130 , improving the photoelectric conversion efficiency of the photosensitive element 130 .
  • the photosensitive element 130 may also be arranged in a non-surrounding manner, which is not limited here.
  • annular opening 103 in the photosensitive element 130.
  • the existence of the annular opening 103 leaves a blank area of the photosensitive element 130, which is used for the subsequent display panel.
  • the preparation of the second light-emitting electrode leaves a lead-out position, which avoids the risk of short circuit between the second light-emitting electrode and the photosensitive element 130 .
  • the film layer of the photosensitive element 130 is not provided in the annular opening 103, thereby exposing the pixel definition layer 141.
  • the flat layer 142 is not provided in the annular opening 103, so that the pixel definition layer 141 is formed at the annular opening 103.
  • the step of the pixel definition layer plays the role of the transition step, in the subsequent display panel manufacturing process, avoiding the climbing of the second light-emitting electrode due to the large step difference between the electrode insulating layer 143 and the first light-emitting electrode layer 151 Difficult, so as to cause the risk of disconnection of the second light-emitting electrode.
  • the electrode insulating layer 143 is disposed on the pixel definition layer 141 to cover the annular opening 103 , and further, the electrode insulating layer 143 may cover the sides of the pixel definition layer 141 around the light emitting opening 101 . In another embodiment, as shown in FIG.
  • the electrode insulating layer 143 is not provided in the annular opening 103, that is, at the position of the annular opening 103, the electrode insulating layer 143 only covers the sides of the flat layer 142 and the photosensitive element 130. , exposing the pixel definition layer 141 .
  • the light emitting layer 152 is disposed in the light emitting opening 101 of the pixel definition layer 141 for emitting display light.
  • the upper surface of the light emitting layer 152 is slightly lower than the upper surface of the pixel definition layer 141 .
  • the second light emitting electrode 153 is disposed on the electrode insulating layer 143 and covers the electrode insulating layer 143 , the pixel definition layer 141 and the light emitting layer 152 .
  • the embodiment of the present application further provides a brightness compensation system, and the brightness compensation system performs brightness compensation on any display panel provided in the embodiment of the present application.
  • FIG. 8 shows a brightness compensation system of a display panel provided by an embodiment of the present application.
  • the brightness compensation system includes: a light-emitting circuit 121, a photosensitive circuit 122, a light-emitting drive chip IC1, an electro-optic reduction chip IC2, and a brightness compensation chip IC3; wherein, the electro-optic reduction chip IC2 and the brightness compensation chip IC3 can be integrated into one chip.
  • the light emitted by the light-emitting layer 152 of the display panel irradiates the photosensitive element 130, and the photosensitive element 130 performs photoelectric conversion on the acquired display light to generate a current signal;
  • the signal is transmitted to the photosensitive circuit 122, driven by the photosensitive circuit 122, the current signal is further transmitted to the electro-optic reduction chip IC2; the photo-reduction chip IC2 restores the obtained current signal to a light intensity signal, thereby detecting the corresponding luminescent layer 152.
  • the detected luminous intensity is transmitted to the brightness compensation chip IC3; the brightness compensation chip IC3 compares the luminous intensity with the luminous curve, and obtains the corresponding compensation value through algorithm processing, and transmits the compensation value to the luminous
  • the driving chip IC1; the light-emitting driving chip IC1 compensates the corresponding sub-pixels, so as to realize the brightness compensation of the display panel.
  • the brightness compensation system provided by the embodiment of the present application uses the display panel provided by the embodiment of the present application to solve the problems of low display brightness and poor brightness uniformity of the existing display panel, and can realize calibration and real-time compensation at any time.
  • FIG. 9 shows the first schematic flow chart of the method for preparing the array substrate provided by the embodiment of the present application
  • FIG. 11 shows the array substrate provided by the implementation of the present application. Schematic diagram of the first structure of the preparation method.
  • the method for preparing the array substrate provided in the embodiment of the present application includes:
  • a semiconductor active layer, a first insulating layer, a gate layer, a second insulating layer, a source-drain layer, and a third insulating layer are sequentially stacked on the substrate 110 .
  • the semiconductor active layer is patterned to form the active area of the thin film transistor of the light emitting circuit and the active area of the thin film transistor of the photosensitive circuit
  • the gate layer is patterned to form the gate of the thin film transistor of the light emitting circuit and the thin film transistor of the photosensitive circuit.
  • gate; the source and drain layer is patterned to form the source and drain of the thin film transistor of the light emitting circuit and the source and drain of the thin film transistor of the photosensitive circuit.
  • the first light emitting electrode 151 is prepared on the thin film transistor layer 120 .
  • the material film of the first photosensitive electrode is deposited on the pixel definition layer 141; then, the material film of the first photosensitive electrode is cleaned with an alkaline release solution, and The surface of the first photosensitive electrode material film is subjected to texturing treatment; finally, the first photosensitive electrode material film is patterned by an etching process to obtain the first photosensitive electrode 131, and the first photosensitive electrode 131 passes through the pixel definition layer 141 and the second photosensitive electrode.
  • the via holes of the three insulating layers are connected with the photosensitive circuit.
  • the material of the first photosensitive electrode 131 is a transparent conductive material, including but not limited to aluminum doped zinc oxide (AZO), indium tin oxide (ITO), fluorine doped tin oxide (FTO)
  • a P-type semiconductor layer, an intrinsic layer and an N-type semiconductor layer are sequentially deposited on the first photosensitive electrode 131, and the P-type semiconductor layer, the intrinsic layer and the N-type semiconductor layer are etched by an etching process.
  • the N-type semiconductor layer is patterned to form a photosensitive layer.
  • a flat layer film is deposited on the pixel definition layer 141.
  • the thickness of the flat layer film is the sum of the thicknesses of the first photosensitive electrode 131 and the photosensitive layer, or slightly larger than the thickness of the first photosensitive electrode 131.
  • the sum of the thicknesses of the photosensitive electrode 131 and the photosensitive layer, the upper surface of the flat layer film is flush or substantially flush with the upper surface of the photosensitive layer; the flat layer film above the photosensitive layer is removed by an etching process to obtain a patterned flat layer 142.
  • the material of the second photosensitive electrode 135 is a conductive material with high reflectivity, including but not limited to silver (Ag), molybdenum (Mo) and aluminum (Al).
  • the electrode insulating layer 143 , the flat layer 142 and the pixel definition layer 141 are patterned by an etching process to expose the first light emitting electrode 151 and form the light emitting opening 101 .
  • FIG. 10 shows the second schematic flow chart of the method for preparing the array substrate provided by the embodiment of the present application
  • FIG. 12 shows the second method for preparing the array substrate provided by the implementation of the present application.
  • the embodiment of the present application provides a display panel, a brightness compensation system, and a method for manufacturing an array substrate.
  • the display panel includes: a pixel definition layer including light-emitting openings distributed in an array; a light-emitting layer disposed in the light-emitting openings
  • the photosensitive element is arranged on the pixel definition layer, and the projection of the photosensitive element on the pixel definition layer is located outside the light-emitting opening.
  • the photosensitive element can better sense the light emitted upward by the light-emitting layer, and convert the optical signal into an electrical signal for feedback, thereby improving the luminous brightness of the display panel. Compensation is performed to solve the problems of brightness attenuation and poor brightness uniformity after long-term use in the existing display panel.

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Abstract

一种显示面板（10），该显示面板（10）包括：像素定义层（141），包括阵列分布的发光开口（101）；发光层（152），设于发光开口（101）内；感光元件（130），设于像素定义层（141）之上，且感光元件（130）在像素定义层（141）上的投影位于发光开口（101）之外。通过在显示面板（10）的发光开口（101）的斜上方设置感光元件（130），感光元件（130）能够更好的感测发光层（152）向上发射出的光线并进行信号反馈。

Description

显示面板 技术领域
本申请涉及显示领域，尤其涉及一种显示面板。
 背景技术
显示面板随着使用时间增长，内部材料性能会逐渐变差，从而导致显示亮度降低、显示不均等异常现象的发生，以至影响显示面板的显示性能。
因此，现有显示面板存在长时间使用后亮度衰减和亮度均一性差的问题，需要改进。
 技术问题
本申请提供一种显示面板，以提高显示面板的显示亮度和亮度均一性。
 技术解决方案
本申请提供一种显示面板，所述显示面板包括：
像素定义层，包括阵列分布的发光开口；
发光层，设于所述发光开口内；以及
感光元件，设于所述像素定义层之上，且所述感光元件在所述像素定义层上的投影位于所述发光开口之外。
可选的，在本申请的一些实施例中，所述感光元件包括第一感光电极、第二感光电极和位于所述第一感光电极和所述第二感光电极之间的光敏层，所述第一感光电极、所述光敏层、所述第二感光电极在所述像素定义层上依次层叠设置。
可选的，在本申请的一些实施例中，所述第一感光电极为透明电极，所述第二感光电极为高反射电极。
可选的，在本申请的一些实施例中，所述第一感光电极靠近所述光敏层的表面为凹凸表面。
可选的，在本申请的一些实施例中，所述显示面板还包括第二感光电极引线，所述第二感光电极引线与所述第二感光电极同层设置且与所述第二感光电极连接。
可选的，在本申请的一些实施例中，所述显示面板还包括平坦层，所述平坦层设于所述像素定义层之上且与所述感光元件连接。
可选的，在本申请的一些实施例中，所述平坦层远离所述像素定义层的表面不低于所述光敏层远离所述像素定义层的表面。
可选的，在本申请的一些实施例中，所述显示面板还包括分别设于所述发光层两侧的第一发光电极和第二发光电极，所述第二发光电极设于所述显示面板的出光侧；所述第二发光电极设于所述第二感光电极之上且与所述第二感光电极绝缘。
可选的，在本申请的一些实施例中，所述显示面板还包括感光电路，所述感光电路连接所述第一感光电极。
可选的，在本申请的一些实施例中，所述显示面板还包括驱动电路层，所述感光电路设于所述驱动电路层内。
可选的，在本申请的一些实施例中，所述感光元件环绕所述发光开口设置。
可选的，在本申请的一些实施例中，所述感光元件存在环形开口，所述环形开口露出所述像素定义层。
本申请提供一种显示面板，所述显示面板包括：
像素定义层，包括阵列分布的发光开口；
发光层，设于所述发光开口内；以及
感光元件，设于所述像素定义层之上，且所述感光元件在所述像素定义层上的投影位于所述发光开口之外，所述感光元件与所述发光层相互绝缘。
可选的，在本申请的一些实施例中，所述感光元件包括第一感光电极、第二感光电极和位于所述第一感光电极和所述第二感光电极之间的光敏层，所述第一感光电极、所述光敏层、所述第二感光电极在所述像素定义层上依次层叠设置。
可选的，在本申请的一些实施例中，所述第一感光电极为透明电极，所述第二感光电极为高反射电极。
可选的，在本申请的一些实施例中，所述第一感光电极靠近所述光敏层的表面为凹凸表面。
可选的，在本申请的一些实施例中，所述显示面板还包括第二感光电极引线，所述第二感光电极引线与所述第二感光电极同层设置且与所述第二感光电极连接。
可选的，在本申请的一些实施例中，所述显示面板还包括平坦层，所述平坦层设于所述像素定义层之上且与所述感光元件连接，所述平坦层远离所述像素定义层的表面不低于所述光敏层远离所述像素定义层的表面。
可选的，在本申请的一些实施例中，所述感光元件环绕所述发光开口设置。
可选的，在本申请的一些实施例中，所述感光元件存在环形开口，所述环形开口露出所述像素定义层。
 有益效果
本申请提供了一种显示面板，该显示面板包括：像素定义层，包括阵列分布的发光开口；发光层，设于所述发光开口内；感光元件，设于所述像素定义层之上所述发光开口之外。本申请通过在显示面板的发光开口的斜上方设置感光元件，感光元件能够更好的感测发光层向上发射出的光线，并将光信号转换成电信号进行反馈，进而对显示面板的发光亮度进行补偿，解决了现有显示面板存在长时间使用后亮度衰减和亮度均一性差的问题。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的显示面板的俯视结构示意图；
图2为本申请实施例提供的显示面板的一种剖面结构示意图；
图3为本申请实施例提供的阵列基板在AA’方向上的第一种剖视图；
图4为本申请实施例提供的阵列基板在AA’方向上的第二种剖视图；
图5为本申请实施例提供的阵列基板在BB’方向上的第一种剖视图；
图6为本申请实施例提供的阵列基板在BB’方向上的第二种剖视图；
图7为本申请实施例提供的阵列基板在BB’方向上的第三种剖视图；
图8为本申请实施例提供的显示面板的亮度补偿系统的示意图；
图9为本申请实施例提供的阵列基板的第一种制备方法的流程示意图；
图10为本申请实施例提供的阵列基板的第二种制备方法的流程示意图；
图11为本申请实施例提供的阵列基板的第一种制备方法的结构示意图；
图12为本申请实施例提供的阵列基板的第二种制备方法的结构示意图。
 本发明的实施方式
针对现有显示面板存在长时间使用后亮度衰减、亮度均一性差的问题，本申请提供一种显示面板可以解决这个问题。
在一种实施例中，请参照图1至图7，图1示出了本发明实施例提供的显示面板的俯视结构示意图，图2示出了本发明实施例提供的显示面板的一种剖面结构示意图，图3示出了本发明实施例提供的显示面板在AA’方向上的第一种剖视图，图4示出了本发明实施例提供的显示面板在AA’方向上的第二种剖视图，图5示出了本发明实施例提供的显示面板在BB’方向上的第一种剖视图，图6示出了本发明实施例提供的显示面板在BB’方向上的第二种剖视图，图7示出了本发明实施例提供的显示面板在BB’方向上的第三种剖视图。如图所示，本申请实施例提供的显示面板包括：
像素定义层141，像素定义层141包括阵列分布的发光开口101；
发光层152，设于发光开口101内；
感光元件130，设于像素定义层141之上，且感光元件130在像素定义层141上的投影位于发光开口101之外。
本申请实施了通过在显示面板的发光开口的斜上方设置感光元件，感光元件能够更好的感测发光层向上发射出的光线，并将光信号转换成电信号进行反馈，进而对显示面板的发光亮度进行补偿，解决了现有显示面板存在长时间使用后亮度衰减和亮度均一性差的问题。
在一种实施例中，请参照图2，显示面板10包括阵列基板100、发光层152和第二发光电极153，第二发光电极153覆盖阵列基板100和发光层152，感光元件130设于阵列基板100内。
阵列基板100包括薄膜晶体管层120，薄膜晶体管层120设于衬底110上。薄膜晶体管层120包括发光电路121和感光电路122，发光电路121与第一发光电极151电连接，感光电路122与感光元件130电连接。具体的，薄膜晶体管包括在衬底上依次层叠设置的半导体有缘层、第一绝缘层、栅极层、第二绝缘层、源漏极层、第三绝缘层。其中，半导体有缘层包括发光电路121内薄膜晶体管的有缘区和感光电路122内薄膜晶体管的有缘区，栅极层包括发光电路121内薄膜晶体管的栅极和感光电路122内薄膜晶体管的栅极，源漏极层包括发光电路121内薄膜晶体管的源漏极和感光电路122内薄膜晶体管的源漏极。第一发光电极151通过贯穿第三绝缘层的过孔与发光电路121内薄膜晶体管的源极或漏极连接，感光元件130通过贯穿第三绝缘层环绕像素定义层141的过孔与感光电路122内薄膜晶体管的源极或漏极连接。
阵列基板100包括感光元件130，感光元件130包括第一感光电极131、第二感光电极135、以及位于第一感光电极131和第二感光电极135之间的光敏层。第一感光电极131、光敏层和第二感光电极135在像素定义层141上依次层叠设置。光敏层可以是PIN型光电二极管或PN型光电二极管中的任意一种。在一种实施方案中，如图2至图6所示，光敏层为PIN型光电二极管，包括P型半导体层、N型半导体层、以及位于P型半导体层和N型半导体层之间的本征层（I型层）；当第一感光电极131为阳极且第二感光电极135为阴极时，层132、层133、层134分别依次为P型半导体层、本征层、N型半导体层。本申请实施例以光敏层为PIN型光电二极管且第一感光电极131为阳极第二感光电极135为阴极做具体的解释说明，第一感光电极131通过贯穿第三绝缘层环绕像素定义层141的过孔与感光电路122内薄膜晶体管的源极或漏极连接。
第一感光电极131为透明电极，透明电极一方面为光敏层提供阳极电信号，另一方面用于透过显示面板的发光开口101内的发光层发出的光线，以使显示面板发出的光线从光敏层的下侧被光敏层获取，提高了感光元件130的光电转换效率。第一感光电极131的材料为透明导电材料，包括但不限于铝掺杂的氧化锌（AZO）、氧化铟锡（ITO）、氟掺杂的氧化锡（FTO）。进一步的，第一感光电极131靠近光敏层的表面为凹凸不平的粗糙表面，凹凸表面降低了第一感光电极131对射入感光元件130的显示光线的反射率，从而进一步提高了感光元件130的光电转换效率。
第二感光电极135为不透明的电极，不透明电极一方面为光敏层提供阴极电信号；另一方面起到遮光层的作用，避免了外界光线射入感光元件130对感光元件130的性能产生不良影响，提高了感光元件130的性能；再一方面作为反光层，使从显示面板的发光层发出的光线到达第二感光电极135时，被第二感光电极135反射回光敏层内，从而进一步提高了感光元件130的光电转换效率。第二感光电极135的材料为高反射率的导电材料，包括但不限于金属银（Ag）、金属钼（Mo）、金属铝（Al）。
阵列基板100还包括第二感光电极引线，第二感光电极引线与第二感光电极135同层设置且与第二感光电极135连接。如图1所示，第二感光电极引线包括第二感光电极分引线136和第二感光电极总引线137，每一条第二感光电极分引线136连接位于其同一列的第二感光电极135，所有的第二感光电极分引线136横向连接于同一条第二感光电极总引线137；也可以是每一条第二感光电极分引线136连接位于其同一行的第二感光电极135，所有的第二感光电极分引线136纵向连接于同一条第二感光电极总引线137；还可以是每一条第二感光电极分引线136连接不同行或不同列的第二感光电极135，所有的第二感光电极分引线136连接于同一条第二感光电极总引线137；第二感光电极引线也可以为网格状结构，每一个第二感光电极135均与第二感光电极引线的网格线连接。
阵列基板100还包括平坦层142，如图2至图7所示，平坦层142设于像素定义层141上，且与感光元件130同层设置。平坦层142用于平坦化光敏层所在的阵列基板平面，为第二感光电极135和第二感光电极引线的制备提供一个平坦的基底，从而避免第二感光电极135和第二感光电极引线出现断线的风险。进一步的，平坦层142远离像素定义层142的表面与光敏层远离像素定义层141的表面平齐或基本平齐，通常平坦层142远离像素定义层142的表面不低于光敏层远离像素定义层141的表面；从而使第二感光电极引线与第二感光电极135位于同一平面或基本位于同一平面，更进一步避免第二感光电极135和第二感光电极引线可能出现的断线风险，提高阵列基板的光电转换性能。
阵列基板100还包括电极绝缘层143，如图2至图7所示，电极绝缘层143设于第二感光电极135上，覆盖第二感光电极135、第二感光电极引线、平坦层142，用于隔绝第二感光电极135和显示面板的第二发光电极，避免感光元件130和显示面板的第二发光电极电连接。电极绝缘层143包括对应于发光开口101的绝缘层开口，绝缘层开口露出第一发光电极151且覆盖发光开口101。在一种实施方案中，如图5和图6所示，平坦层142围绕感光元件130设置填充素定义层141上、感光元件130和发光开口101以外的区域，电极绝缘层143还覆盖感光元件130的侧边。在另一种实施方案中，如图4和图7所示，平坦层142填充素定义层141上、感光元件130和发光开口101以外的区域，平坦层142还覆盖感光元件130的侧边，电极绝缘层143仅设于第二感光电极135和平坦层142上。
在一种实施例中，如图1和图2所示，感光元件130环绕发光开口101设置。感光元件130环绕发光开口101的设置方式，使得显示面板的发光开口内的发光层向周围发射发出的光线均能够被感光元件130获取，提高感光元件130的光电转换效率。在其他实施例中，感光元件130也可以使非环绕设置，在此不做限定。
在一种实施例中，如图1、图5至图7所示，感光元件130存在环形开口103，一方面，环形开口103的存在留出的感光元件130的空白区域，为后续显示面板的第二发光电极的制备留出了引出位置，避免了第二发光电极与感光元件130短接的风险。另一方面，在环形开口103内不设置感光元件130的膜层，从而露出像素定义层141，同样的，在环形开口103内不设置平坦层142，使得像素定义层141在环形开口103处形成像素定义层台阶，像素定义层台阶起到过渡段差的作用，在后续显示面板制程中，避免了第二发光电极由于电极绝缘层143和第一发光电极层151之间段差太大而出现爬坡困难，以至导致第二发光电极断线的风险。在一种实施方案中，如图5所示，电极绝缘层143设置于像素定义层141上覆盖环形开口103，进一步的，电极绝缘层143可以覆盖发光开口101外围像素定义层141的侧边。在另一种实施方案中，如图6所示，环形开口103内未设置电极绝缘层143，即在环形开口103所在的位置，电极绝缘层143仅覆盖平坦层142和感光元件130的侧边，露出像素定义层141。
发光层152，设于像素定义层141的发光开口101内，用于发出显示光线。发光层152的上表面略低于像素定义层141的上表面。
第二发光电极153，设于电极绝缘层143上，覆盖电极绝缘层143、像素定义层141、以及发光层152。
相应的，本申请实施例还提供一种亮度补偿系统，该亮度补偿系统对本申请实施例提供的任意一种显示面板进行亮度补偿。请参照图8，图8示出了本申请实施例提供的显示面板的亮度补偿系统。如图所示，该亮度补偿系统包括：发光电路121、感光电路122、发光驱动芯片IC1、电光还原芯片IC2、以及亮度补偿芯片IC3；其中，电光还原芯片IC2和亮度补偿芯片IC3可以集成为一个芯片。
具体的，结合本申请实施例提供的阵列基板100和显示面板，显示面板的发光层152发射的光线照射到感光元件130，感光元件130对获取到的显示光线进行光电转换，产生电流信号；电流信号传输到感光电路122，在感光电路122的驱动下，电流信号进一步传输至电光还原芯片IC2；光还原芯片IC2将获取的电流信号还原为光强信号，从而侦测对应的发光层152的发光强弱，并其侦测到的发光强度传输给亮度补偿芯片IC3；亮度补偿芯片IC3通过将该发光强度与发光曲线做对比，经过算法处理得到对应的补偿值，并将该补偿值传输给发光驱动芯片IC1；发光驱动芯片IC1对对应的子像素进行补偿，从而实现对显示面板的亮度补偿。本申请实施例提供的亮度补偿系统，利用本申请实施例提供的显示面板，解决了现有显示面板显示亮度低、亮度均一性差的问题，而且可以实现随时校准、实时补偿。
同时，本申请实施例还提供一种阵列基板的制备方法。在一种实施例中，请参照图9和图11，图9示出了本申请实施例提供的阵列基板的制备方法的第一种流程示意图，图11示出了本申请实施提供的阵列基板的制备方法的第一种结构示意图。如图9和图11所示，本申请实施例提供的阵列基板的制备方法包括：
S91、在衬底上制备薄膜晶体管层和第一发光电极，薄膜晶体管层包括发光电路和感光电路。
具体的，如图11中（a）所示，在衬底110上依次层叠设置半导体有缘层、第一绝缘层、栅极层、第二绝缘层、源漏极层、第三绝缘层。其中，半导体有缘层图案化处理，形成发光电路的薄膜晶体管的有缘区和感光电路的薄膜晶体管的有缘区；栅极层图案化处理，形成发光电路的薄膜晶体管的栅极和感光电路的薄膜晶体管的栅极；源漏极层图案化处理，形成发光电路的薄膜晶体管的源漏极和感光电路的薄膜晶体管的源漏极。在薄膜晶体管层120上制备第一发光电极151。
S92、在第一发光电极上沉积像素定义层，图案化形成对应于感光电路的过孔。
具体的，如图11中（b）所示。
S93、在像素定义层上制备感光元件的第一感光电极。
具体的，如图11中（c）所示，首先，在像素定义层141上沉积第一感光电极的材料薄膜；然后，对第一感光电极的材料薄膜采用碱性脱膜液进行清洗，对第一感光电极材料薄膜的表面进行制绒处理；最后采用刻蚀工艺对第一感光电极材料薄膜进行图案化处理，得到第一感光电极131，第一感光电极131通过贯穿像素定义层141和第三绝缘层的过孔与感光电路连接。第一感光电极131的材料为透明导电材料，包括但不限于铝掺杂的氧化锌（AZO）、氧化铟锡（ITO）、氟掺杂的氧化锡（FTO）
S94、在第一感光电极上制备光敏层。
具体的，如图11中（d）所示，在第一感光电极131上依次沉积P型半导体层、本征层和N型半导体层，采用刻蚀工艺对P型半导体层、本征层和N型半导体层进行图案化处理，形成光敏层。
S95、在像素定义层上制备平坦层。
具体的，如图11中（e）所示，在像素定义层141上沉积一层平坦层薄膜，平坦层薄膜的厚度为第一感光电极131和光敏层的厚度之和，或略大于第一感光电极131和光敏层的厚度之和，平坦层薄膜的上表面与光敏层的上表面平齐或基本平齐；通过刻蚀工艺去除光敏层上方的平坦层薄膜，得到图案化后的平坦层142。
S96、在平坦层上制备感光元件的第二感光电极。
具体的，如图11中（f）所示。第二感光电极135的材料为高反射率的导电材料，包括但不限于金属银（Ag）、金属钼（Mo）、金属铝（Al）。
S97、在第二感光电极上制备电极绝缘层。
具体的，如图11中（g）所示。
S98、图案化形成发光开口。
具体的，如图11中（h）所示，采用刻蚀工艺图案化处理电极绝缘层143、平坦层142和像素定义层141，露出第一发光电极151，形成发光开口101。
请参照图10和图12，图10示出了本申请实施例提供的阵列基板的制备方法的第二种流程示意图，图12示出了本申请实施提供的阵列基板的制备方法的第二种结构示意图。如图10和图12所示，本申请实施例提供的阵列基板的制备方法包括：
S101、在衬底上制备薄膜晶体管层和第一发光电极，薄膜晶体管层包括发光电路和感光电路。
S102、在第一发光电极上沉积像素定义层，图案化形成对应于感光电路的过孔。
S103、在像素定义层上制备感光元件的第一感光电极。
S104、在第一感光电极上制备光敏层。
S105、在像素定义层上制备平坦层。
S106、在平坦层上制备感光元件的第二感光电极。
S107、图案化处理平坦层和像素定义层，形成发光开口。具体如图12中（g）所示，采用刻蚀工艺去除感光元件130环形区域内的平坦层和像素定义层，以及环形开口处的平坦层，形成发光开口101和环形开口103。
S108、在第二感光电极上制备电极绝缘层。
具体的，如图12中（h）所示。
综上所述，本申请实施例提供了一种显示面板、亮度补偿系统以及阵列基板的制备方法，该显示面板包括：像素定义层，包括阵列分布的发光开口；发光层，设于发光开口内；感光元件，设于像素定义层之上，且所述感光元件在所述像素定义层上的投影位于发光开口之外。本申请通过在显示面板的发光开口的斜上方设置感光元件，感光元件能够更好的感测发光层向上发射出的光线，并将光信号转换成电信号进行反馈，进而对显示面板的发光亮度进行补偿，解决了现有显示面板存在长时间使用后亮度衰减和亮度均一性差的问题。
以上对本申请实施例所提供的显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括：
    像素定义层，包括阵列分布的发光开口；
    发光层，设于所述发光开口内；以及
    感光元件，设于所述像素定义层之上，且所述感光元件在所述像素定义层上的投影位于所述发光开口之外。
  2. 如权利要求1所述的显示面板，其中，所述感光元件包括第一感光电极、第二感光电极和位于所述第一感光电极和所述第二感光电极之间的光敏层，所述第一感光电极、所述光敏层、所述第二感光电极在所述像素定义层上依次层叠设置。
  3. 如权利要求2所述的显示面板，其中，所述第一感光电极为透明电极，所述第二感光电极为高反射电极。
  4. 如权利要求3所述的显示面板，其中，所述第一感光电极靠近所述光敏层的表面为凹凸表面。
  5. 如权利要求2所述的显示面板，其中，所述显示面板还包括第二感光电极引线，所述第二感光电极引线与所述第二感光电极同层设置且与所述第二感光电极连接。
  6. 如权利要求5所述的显示面板，其中，所述显示面板还包括平坦层，所述平坦层设于所述像素定义层之上且与所述感光元件连接。
  7. 如权利要求6所述的显示面板，其中，所述平坦层远离所述像素定义层的表面不低于所述光敏层远离所述像素定义层的表面。
  8. 如权利要求2所述的显示面板，其中，所述显示面板还包括分别设于所述发光层两侧的第一发光电极和第二发光电极，所述第二发光电极设于所述显示面板的出光侧；所述第二发光电极设于所述第二感光电极之上且与所述第二感光电极绝缘。
  9. 如权利要求2所述的显示面板，其中，所述显示面板还包括感光电路，所述感光电路连接所述第一感光电极。
  10. 如权利要求9所述的显示面板，其中，所述显示面板还包括驱动电路层，所述感光电路设于所述驱动电路层内。
  11. 如权利要求1所述的显示面板，其中，所述感光元件环绕所述发光开口设置。
  12. 如权利要求11所述的显示面板，其中，所述感光元件存在环形开口，所述环形开口露出所述像素定义层。
  13. 一种显示面板，其中，所述显示面板包括：
    像素定义层，包括阵列分布的发光开口；
    发光层，设于所述发光开口内；以及
    感光元件，设于所述像素定义层之上，且所述感光元件在所述像素定义层上的投影位于所述发光开口之外，所述感光元件与所述发光层相互绝缘。
  14. 如权利要求13所述的显示面板，其中，所述感光元件包括第一感光电极、第二感光电极和位于所述第一感光电极和所述第二感光电极之间的光敏层，所述第一感光电极、所述光敏层、所述第二感光电极在所述像素定义层上依次层叠设置。
  15. 如权利要求14所述的显示面板，其中，所述第一感光电极为透明电极，所述第二感光电极为高反射电极。
  16. 如权利要求15所述的显示面板，其中，所述第一感光电极靠近所述光敏层的表面为凹凸表面。
  17. 如权利要求14所述的显示面板，其中，所述显示面板还包括第二感光电极引线，所述第二感光电极引线与所述第二感光电极同层设置且与所述第二感光电极连接。
  18. 如权利要求17所述的显示面板，其中，所述显示面板还包括平坦层，所述平坦层设于所述像素定义层之上且与所述感光元件连接，所述平坦层远离所述像素定义层的表面不低于所述光敏层远离所述像素定义层的表面。
  19. 如权利要求13所述的显示面板，其中，所述感光元件环绕所述发光开口设置。
  20. 如权利要求19所述的显示面板，其中，所述感光元件存在环形开口，所述环形开口露出所述像素定义层。
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