WO2023092554A1 - 薄膜晶体管及其制备方法、阵列基板和显示面板 - Google Patents

薄膜晶体管及其制备方法、阵列基板和显示面板 Download PDF

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WO2023092554A1
WO2023092554A1 PCT/CN2021/133997 CN2021133997W WO2023092554A1 WO 2023092554 A1 WO2023092554 A1 WO 2023092554A1 CN 2021133997 W CN2021133997 W CN 2021133997W WO 2023092554 A1 WO2023092554 A1 WO 2023092554A1
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semiconductor layer
layer
oxide material
gate
substrate
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PCT/CN2021/133997
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English (en)
French (fr)
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黄杰
宁策
李正亮
胡合合
贺家煜
姚念琦
赵坤
李菲菲
雷利平
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京东方科技集团股份有限公司
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Priority to PCT/CN2021/133997 priority Critical patent/WO2023092554A1/zh
Priority to CN202180003703.8A priority patent/CN116783690A/zh
Publication of WO2023092554A1 publication Critical patent/WO2023092554A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present disclosure relates to the field of display technology, in particular to a thin film transistor and a manufacturing method thereof, an array substrate and a display panel.
  • oxide thin film transistor As the oxide thin film transistor (Oxide TFT) develops towards higher mobility, the stability of the device is gradually reduced, making it develop towards high-performance displays such as high resolution, high refresh rate, low power consumption, and narrow borders.
  • the stability of the product cannot be maintained at this time. For example, under the impact of high voltage and high current on the TFT, it is easy to cause the deviation of the TFT characteristics, and the GOA output is abnormal.
  • the present disclosure provides a thin film transistor, a preparation method thereof, an array substrate and a display panel.
  • a thin film transistor which includes: a substrate; and a gate, a gate insulating layer, an active layer, a source, and a drain disposed on the substrate, wherein the active
  • the layer includes a first semiconductor layer and a second semiconductor layer arranged in sequence along a direction perpendicular to the substrate, the second semiconductor layer is arranged on a side of the first semiconductor layer away from the gate; the first the semiconductor layer includes a first oxide material, the second semiconductor layer includes a second oxide material; the electron mobility of the first oxide material is higher than the electron mobility of the second oxide material; and the The bottom of the conduction band of the first oxide material is lower than the bottom of the conduction band of the second oxide material, and the difference between the bottom of the conduction band of the first oxide material and the bottom of the conduction band of the second oxide material
  • the absolute value of is greater than 0.2eV.
  • the active layer further includes a third semiconductor layer disposed on a side of the second semiconductor layer away from the gate, and the third semiconductor layer includes a crystalline oxide material.
  • the crystalline oxide material comprises crystalline IGZO.
  • the active layer further includes a fourth semiconductor layer disposed on a side of the first semiconductor layer close to the gate; the fourth semiconductor layer includes a fourth oxide material; and the The electron mobility of the fourth oxide material is smaller than the electron mobility of the first oxide material.
  • the fourth oxide material is the same as the second oxide material.
  • the first oxide material includes at least one of IGZO, IZO, IGTO, ITZO, and IGZTO; and the second oxide material includes at least one of GZO and Pr-GZO.
  • the gate insulating layer is on a side of the gate away from the substrate; the active layer is on a side of the gate away from the substrate; the first semiconductor layer and the second semiconductor layer have substantially the same orthographic area on the substrate; and the source and the drain are respectively the same as the first semiconductor layer and the second semiconductor layer on the gate insulating layer Opposite ends of the semiconductor layer are in contact.
  • the thin film transistor further includes a buffer layer and an interlayer dielectric layer disposed on the substrate, wherein the second semiconductor layer is disposed on a side of the buffer layer away from the substrate;
  • the first semiconductor layer is arranged on a side of the second semiconductor layer away from the substrate;
  • the gate insulating layer is arranged on a side of the first semiconductor layer away from the substrate;
  • the gate is arranged On a side of the gate insulating layer away from the substrate;
  • the interlayer dielectric layer is disposed on a side of the gate away from the substrate; the first semiconductor layer and the second semiconductor
  • the orthographic projection areas of the layers on the substrate are approximately the same; and the source electrode and the drain electrode respectively pass through the first via hole and the second via hole in the interlayer dielectric layer and the first semiconductor layer The opposite ends touch.
  • a method for manufacturing a thin film transistor which includes: forming a gate, a gate insulating layer, an active layer, a source, and a drain on a substrate, so that the active layer includes A first semiconductor layer and a second semiconductor layer arranged in sequence along a direction perpendicular to the substrate, the second semiconductor layer is arranged on a side of the first semiconductor layer away from the gate, the first semiconductor layer comprising a first oxide material, the second semiconductor layer comprising a second oxide material; the electron mobility of the first oxide material is higher than the electron mobility of the second oxide material; and the first The bottom of the conduction band of the oxide material is lower than the bottom of the conduction band of the second oxide material, and the absolute value of the difference between the bottom of the conduction band of the first oxide material and the bottom of the conduction band of the second oxide material The value is greater than 0.2eV.
  • the first oxide material includes at least one of IGZO, ITZO, IZO, IGTO, and IGZTO; and the second oxide material includes at least one of GZO and Pr-GZO.
  • forming the gate, the gate insulating layer, the active layer, the source and the drain on the substrate includes: forming a pattern of the gate on the substrate; forming a gate insulating layer on the pattern of the gate; A first oxide material layer and a second oxide material layer are sequentially formed on the gate insulating layer, and patterns of the first semiconductor layer and the second semiconductor layer are formed on the gate insulating layer through a patterning process using a first mask ;
  • a source-drain material layer on the pattern of the first semiconductor layer and the second semiconductor layer on the gate insulating layer, and etching the source-drain material layer to form a source electrode and a drain electrode at opposite ends of the first semiconductor layer; And a passivation layer is formed on the source and drain.
  • the third semiconductor layer comprises a crystalline oxide material.
  • forming the gate, the gate insulating layer, the active layer, the source and the drain on the substrate includes: forming a pattern of the gate on the substrate; forming a gate insulating layer on the pattern of the gate; A fourth oxide material layer, a first oxide material layer and a second oxide material layer are sequentially formed on the gate insulating layer, and a fourth semiconductor layer is formed on the gate insulating layer through a patterning process using a first mask , patterns of the first semiconductor layer and the second semiconductor layer;
  • a source-drain material layer is formed on the patterns of the fourth semiconductor layer, the first semiconductor layer and the second semiconductor layer on the gate insulating layer, and the source-drain material layer is etched to form sources respectively at opposite ends of the first semiconductor layer. electrode and drain; and forming a passivation layer on the source and drain.
  • forming the gate, the gate insulating layer, the active layer, the source and the drain on the substrate includes: sequentially forming a buffer layer, a second oxide material layer, and a first oxide material layer on the substrate , the gate insulating material layer and the gate material layer; using the first mask to form the pattern of the gate and the gate insulating layer through a patterning process; using the second mask to form the first semiconductor layer and the second patterning process through a patterning process The pattern of the second semiconductor layer; an interlayer dielectric layer is formed on the side of the gate away from the substrate; a first through hole and a second through hole are respectively formed in the interlayer dielectric layer corresponding to opposite ends of the first semiconductor layer. Two through holes; filling source and drain materials in the first through hole and the second through hole respectively to form source and drain; and forming a passivation layer on the source and drain.
  • the present disclosure also provides an array substrate, which includes a light emitting device and a driving circuit for driving the light emitting device to emit light, wherein the driving circuit includes the above-mentioned thin film transistor.
  • the present disclosure also provides a display panel, which includes the above-mentioned array substrate.
  • FIG. 1A and FIG. 1B show a schematic structural view of a thin film transistor of the related art
  • FIG. 2 shows a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure
  • Fig. 3 shows a schematic diagram of the energy levels of the first semiconductor layer and the second semiconductor layer of the thin film transistor shown in Fig. 2;
  • Fig. 4 shows the difference between the carrier concentration of the stacked channel composed of the first semiconductor layer and the second semiconductor layer and the conduction band energy level difference of the first material of the first semiconductor layer and the second material of the second semiconductor layer relationship between
  • FIG. 6A shows a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 6B shows a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 6C shows a schematic structural view of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 7 shows a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 8 shows a schematic diagram of a manufacturing process of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 9 shows a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure
  • FIG. 10 shows a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 11 shows a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • the active layer of the oxide thin film transistor in the related art is usually a single-layer high-mobility oxide material, such as a single-layer indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the side of the channel away from the substrate and close to the source and drain layer (referred to as the back channel) will be corroded by the S/D etchant.
  • a thin film transistor in the related art may include a substrate 100, a gate 101, a gate insulating layer 102, an active layer 103, a source 105, a drain 106, and a gate 101 sequentially formed on the substrate 100.
  • a passivation layer 107 covers the source 105 and the drain 106 .
  • the channel of the active layer 103 is actually in contact with the gate insulating layer 102 and the passivation layer 107, because the S/D etchant is active to the oxide material such as single-layer IGZO
  • the damage of layer 103 is so large that a large number of defects are formed in the back channel, resulting in a significant decrease in device stability and seriously affecting device characteristics.
  • etch barrier layer 1001 of oxide material on the basis of a single-layer oxide active layer, as shown in Figure 1B, without adding a mask process, it can improve Device Stability.
  • the solutions of related technologies generally use crystallized oxide as the etch stop layer 1001 to protect the channel, and the distance between the conduction band bottom E CBM of the etch stop layer 1001 and the conduction band bottom E CBM of the actual channel material The difference is small, usually the difference between the two is within 0.2eV, which will cause a certain amount of carriers 1000 inside the channel to still migrate to the back channel, that is, to the side of the etching barrier layer away from the semiconductor layer, In turn, it is trapped by back channel defects, resulting in reduced stability.
  • the conduction band is the energy space formed by free electrons, that is, the energy range of electrons that move freely in the solid structure;
  • CBM represents the lowest point of the conduction band (CBM);
  • E CBM represents The energy value of the distance from the bottom of the conduction band to the vacuum level Evac, the vacuum level Evac is 0eV;
  • the most important energy bands of semiconductors are the top of the valence band (VBM) and the bottom of the conduction band (CBM).
  • CBM minus VBM is the forbidden band width (band gap, energy gap).
  • crystalline IGZO for example IGZO (136), the atomic ratio of In:Ga:Zn in the film is 1:3:6) material can be used to prepare the etch stop layer 1001, and its E CBM is far from the vacuum energy level Evac The distance test is 4.3eV.
  • amorphous IGZO such as IGZO (111), the atomic ratio of In:Ga:Zn in the film is 1:1:1) to prepare the semiconductor layer of the thin film transistor, that is, the trench layer.
  • E CBM and Evac The distance between E CBM and Evac is 4.48eV, so the difference between the two E CBMs is ⁇ 0.2eV, which makes it easy to form a large number of back channel defects at the back channel of the active layer during the formation of source and drain patterns. It will make the device capture a large number of carriers 1000 during operation, resulting in reduced device stability.
  • the conduction bands of both the first material Oxide1 (such as IGZO (111)) of the first semiconductor layer constituting the active layer and the second material Oxide2 (such as IGZO (136)) of the second semiconductor layer The absolute value of the energy level difference between the bottoms is less than 0.2eV, that is,
  • Oxide1 is IGZO (111)
  • Oxide2 is IGZO (136)
  • the difference between the conduction band bottoms of the two is within 0.2eV, which cannot effectively prevent the migration of electrons.
  • embodiments of the present application provide a thin film transistor and a manufacturing method thereof.
  • the thin film transistor of the present disclosure includes, for example, a substrate 100 made of glass, a gate electrode 101, a gate insulating layer 102, a first semiconductor layer 103 and a second semiconductor layer 104 formed sequentially on the substrate 100. active layer, source 105 , drain 106 and passivation layer 107 .
  • the active layer is formed by stacking the first semiconductor layer 103 and the second semiconductor layer 104 of the thin film transistor of the present disclosure.
  • the first semiconductor layer 103 is a part of the active layer mainly used to form a channel, which is usually made of a high-mobility oxide material, and is disposed between the gate insulating layer 102 and the second semiconductor layer 104 .
  • metal oxide materials can be used to form the first semiconductor layer 103, the conduction band bottom E CBM ranges from 4.4eV to 5.2eV, the band gap Eg ranges from 2.0eV to 3.2eV, and the carrier concentration is within the order of magnitude of 5*E19.
  • the second semiconductor layer 104 is disposed on a side of the first semiconductor layer 103 away from the gate 101 .
  • the second semiconductor layer 104 is mainly used for interface matching and etching protection, and acts as an etching barrier layer.
  • the absolute value of the difference between the conduction band bottom of the first material of the first semiconductor layer 103 and the conduction band bottom of the second material of the second semiconductor layer 104 is greater than 0.2 eV.
  • both the first semiconductor layer 103 and the second semiconductor layer 104 are oxide semiconductor layers.
  • the first oxide material Oxide1 of the first semiconductor layer 103 and the second oxide material Oxide2 of the second semiconductor layer 104 should satisfy the absolute value of ( ECBM Oxide1-E CBM Oxide2)>0.2eV, and may be greater than 0.3eV.
  • the material of the first semiconductor layer 103 can be, for example, IGZO, which is used as a semiconductor layer material in the related art, and the material of the second semiconductor layer 104 can be, for example, GZO, which mainly functions as an etching stopper layer.
  • IGZO IGZO
  • GZO mainly functions as an etching stopper layer.
  • the material of the first semiconductor layer 103 may include at least one of IGZO, IZO, IGTO, ITZO and IGZTO, and these materials all have relatively high electron mobility;
  • the material of the second semiconductor layer 104 may be Including at least one of GZO and Pr-GZO (GZO is doped with a certain amount of Pr (praseodymium element)), these materials all have higher conduction band bottoms.
  • the patterns of the first semiconductor layer 103 and the second semiconductor layer 104 can be formed simultaneously by one patterning process.
  • a first oxide material layer and a second oxide material layer can be sequentially formed on the substrate 100, and then a patterning process (including coating of photoresist, exposure, development, and etching) is performed by using the same mask.
  • the patterns of the first semiconductor layer 103 and the second semiconductor layer 104 are formed simultaneously, and the orthographic projections of the thus formed patterns of the first semiconductor layer 103 and the second semiconductor layer 104 on the substrate 100 are substantially completely overlapped.
  • FIG. 3 shows the energy level diagram relationship of each layer when the first semiconductor layer 103 of the thin film transistor includes IGZO and the second semiconductor layer 104 includes GZO.
  • the band gap Eg1 of the first semiconductor layer 103 of IGZO is, for example, 3eV
  • the band gap Eg2 of the second semiconductor layer 104 of GZO is, for example, 4.03eV
  • the conduction band bottom of the first semiconductor layer 103 of IGZO is smaller than the second semiconductor layer 104 of GZO
  • the bottom of the conduction band, the absolute value of the difference between the bottom of the conduction band between the two is ⁇ Ecm.
  • the absolute value of ⁇ Ecm between the two is about 0.43eV, that is,
  • the active layer of a thin film transistor includes amorphous IGZO (such as IGZO (111)) and crystalline IGZO (such as IGZO (136)), amorphous IGZO (such as IGZO (111)) and crystalline IGZO (such as IGZO ( 136))
  • amorphous IGZO such as IGZO (111)
  • crystalline IGZO such as IGZO ( 136)
  • the active layer of the thin film transistor of the present disclosure replaces the crystalline IGZO in the related art, and adopts GZO, for example, a material with a high conduction band, as the material of the etching barrier layer, which is arranged on the first semiconductor layer 103 away from the gate 101 , where
  • GZO for example, a material with a high conduction band
  • Fig. 4 and Fig. 5 have respectively shown the channel carrier concentration of simulation, the back channel electric quantity and the conduction band bottom energy level difference (abbreviated as conduction band) between the material of the first semiconductor layer and the second semiconductor layer Schematic diagram of the relationship between the differences).
  • FIG. 4 shows a simulated diagram of the carrier concentration at various positions in the active layer as a stacked channel, where the abscissa indicates the distance between the active layer and the gate insulating layer 102, and the ordinate indicates the current carrier concentration. Subconcentration size.
  • the stacked channel is an N-type channel, the carriers are electrons.
  • the conduction band bottom E CBM of the second oxide material Oxide2 of the second semiconductor layer 104 is larger than the conduction band bottom E CBM of the first oxide material Oxide1 of the first semiconductor layer 103 , so that in the first oxide material Oxide1 Carriers need to overcome the larger potential energy of the two before they can migrate, which increases the difficulty of carrier migration to the second oxide material Oxide2.
  • the back channel carrier concentration is on the order of 1.0E11/cm 3 .
  • the conduction band difference is further increased, such as
  • the carrier concentration is on the order of 1.0E16/cm 3 , which is reduced by 10 orders of magnitude, thereby significantly improving the device stability.
  • the carrier concentration in the normal working state of the thin film transistor is the carrier concentration inside the first semiconductor layer.
  • the carrier concentration of the first semiconductor layer 103 is generally between 1*E15/cm 3 and 1*E19/cm 3 .
  • the absolute value of the difference between the conduction band bottoms of the first oxide material Oxide1 of the first semiconductor layer 103 and the second oxide material Oxide2 of the second semiconductor layer 104 is set to 0.2 eV and above, the carrier concentration of the back channel can be reduced to within the range of 1*E11/cm 3 -1*E1/cm 3 .
  • FIG. 5 illustrates by taking an example in which the first semiconductor layer 103 is made of amorphous IGZO (such as IGZO(111)) and the second semiconductor layer 104 is made of an oxide material (identified as IGZOX).
  • IGZOX oxide material
  • the distance between the conduction band bottom of the first oxide material Oxide1 of the first semiconductor layer 103 and the conduction band bottom of the second oxide material Oxide2 of the second semiconductor layer 104 When the difference is greater than 0.2eV, the carrier concentration in the back channel decreases significantly. Further increasing the difference between the conduction band bottom of the first oxide material Oxide1 of the first semiconductor layer 103 and the conduction band bottom of the second oxide material Oxide2 of the second semiconductor layer 104 can further reduce the back channel load. The carrier concentration can significantly improve the stability of the oxide thin film transistor.
  • FIG. 6A shows a schematic diagram of a thin film transistor according to an embodiment of the disclosure.
  • the thin film transistor may include a substrate 100 and a gate 101, a gate insulating layer 102, an active layer including a first semiconductor layer 103 and a second semiconductor layer 104, a source 105, a drain 106 and passivation layer 107 .
  • the active layer includes a first semiconductor layer 103, a second semiconductor layer 104, and a third semiconductor layer 108 stacked in sequence, and the second semiconductor layer 104 is disposed on the side of the first semiconductor layer 103 away from the gate 101.
  • One side, and the third semiconductor layer 108 is disposed on a side of the second semiconductor layer 104 away from the gate 101 .
  • the first semiconductor layer 103 is used as a part of the active layer mainly used to form a channel, which usually uses a high-mobility oxide material; the second semiconductor layer 103 104 uses an oxide material with a high conduction band bottom.
  • the first oxide material Oxide1 of the first semiconductor layer 103 is a conventional channel material, such as IGZO, IGTO, IZO, ITZO, IGZTO, etc.
  • the second oxide material Oxide2 of the second semiconductor layer 104 is GZO, Pr-GZO wait.
  • the active layer of the thin film transistor of this embodiment further includes a third semiconductor layer disposed on the side away from the gate 101 of the second semiconductor layer 104 mainly used as an etch stop layer. 108.
  • the material of the third semiconductor layer 108 may be a third oxide material Oxide3.
  • the third oxide material may be a crystalline oxide material, such as IGZO (136) or the like.
  • the energy level relationship of the conduction band bottom E CBM of the first oxide material Oxide1, the second oxide material Oxide2 and the third oxide material Oxide3 of the active layer can be set as:
  • the level relationship can be set as:
  • a crystalline oxide layer is added on the side of the active layer away from the gate 101 to improve the physical barrier properties and prevent H and O in the adjacent film layer or process. affect the semiconductor layer.
  • the stability of the high mobility oxide thin film transistor can be significantly improved.
  • FIG. 6B shows a schematic diagram of a thin film transistor according to an embodiment of the disclosure.
  • the thin film transistor may include a substrate 100, a gate electrode 101, a gate insulating layer 102, an active layer including a first semiconductor layer 103, a second semiconductor layer 104 and a fourth semiconductor layer 110, and a source electrode formed sequentially on the substrate 100. 105 , drain 106 and passivation layer 107 .
  • the active layer includes a fourth semiconductor layer 110, a first semiconductor layer 103, and a second semiconductor layer 104 stacked on the gate insulating layer 102 in sequence, and the second semiconductor layer 104 is disposed on the first semiconductor layer.
  • 103 on a side away from the gate 101
  • the fourth semiconductor layer 110 is disposed on a side of the first semiconductor layer 103 close to the gate 101 .
  • the first semiconductor layer 103 is used as a part of the active layer mainly used to form a channel, which usually uses a high-mobility oxide material; the second semiconductor layer 103 104 uses an oxide material with a high conduction band bottom.
  • the first oxide material Oxide1 of the first semiconductor layer 103 is a conventional channel material, such as IGZO, IGTO, IZO, ITZO, IGZTO, etc.
  • the second oxide material Oxide2 of the second semiconductor layer 104 is GZO, Pr-GZO wait.
  • the active layer of the thin film transistor of this embodiment further includes a fourth semiconductor layer disposed on the side close to the gate 101 of the first semiconductor layer 103 mainly used as a carrier channel.
  • the active layer includes a second semiconductor layer 104 and a fourth semiconductor layer 110 respectively disposed on both sides of the first semiconductor layer 103 .
  • the material of the fourth semiconductor layer 110 may be the same as that of the second semiconductor layer 104 , which is the second oxide material Oxide2.
  • the energy level relationship of the conduction band bottom E CBM of the first oxide material Oxide1 and the second oxide material Oxide2 of the active layer can be set as:
  • a third semiconductor layer 108 may be further provided on the second semiconductor layer 104 of the active layer of the thin film transistor shown in FIG. 6B , as shown in FIG. 6C .
  • the material of the third semiconductor layer 108 may be a third oxide material Oxide3.
  • the third oxide material may be a crystalline oxide material, such as IGZO (136) or the like.
  • FIG. 7 shows a schematic structural diagram of a top-gate thin film transistor according to an embodiment of the present disclosure.
  • the thin film transistor shown in FIG. 7 includes, for example, a substrate 100 made of glass, and a buffer layer 200, a second semiconductor layer 104, a first semiconductor layer 103, a gate insulating layer 102, a gate 101, and layers formed sequentially on the substrate 100.
  • the second semiconductor layer 104 is disposed on a side of the first semiconductor layer 103 away from the gate 101 .
  • carriers are in the first semiconductor layer 103 so that the first semiconductor layer 103 serves as a channel between the source electrode 105 and the drain electrode 106 when the thin film transistor operates.
  • Carrier transport; and the second semiconductor layer 104 is mainly used for interface matching and etching protection, and acts as an etching barrier layer.
  • the absolute value of the difference between the conduction band bottom of the first material of the first semiconductor layer 103 and the conduction band bottom of the second material of the second semiconductor layer 104 is greater than 0.2 eV.
  • both the first semiconductor layer 103 and the second semiconductor layer 104 are oxide semiconductor layers.
  • the first oxide material Oxide1 of the first semiconductor layer 103 and the second oxide material Oxide2 of the second semiconductor layer 104 should satisfy the absolute value of ( ECBM Oxide1-E CBM Oxide2)>0.2eV, and may be greater than 0.3eV.
  • the material of the first semiconductor layer 103 can be, for example, IGZO, which is used as a semiconductor layer material in the related art, and the material of the second semiconductor layer 104 can be, for example, GZO, which mainly functions as an etching stopper layer.
  • the absolute value of the difference ( ECBM Oxide1-E CBM Oxide2) is greater than 0.4eV, and at this time, most of the carriers in the first semiconductor layer 103 can be blocked and cannot migrate to The back channel cannot be trapped by the back channel, which improves the stability of the thin film transistor.
  • the material of the first semiconductor layer 103 may include at least one of IGZO, IZO, IGTO and IGZTO, and these materials all have high electron mobility;
  • the material of the second semiconductor layer 104 may include GZO And at least one of Pr-GZO (GZO doped with a certain amount of Pr (praseodymium element)), these materials all have a higher conduction band bottom.
  • the source electrode 105 and the drain electrode 106 pass through the two via holes extending through the interlayer dielectric layer 109 and the two holes of the first semiconductor layer 103 not covered by the gate electrode 101 and the gate insulating layer 102 respectively. electrical connection.
  • a single patterning process may be used to simultaneously form patterns of the second semiconductor layer 104 and the first semiconductor layer 103 .
  • the second oxide material layer and the first oxide material layer can be sequentially formed on the buffer layer 200 on the substrate 100, and then through the same patterning process (including coating photoresist, exposure, development, etching) to simultaneously form the patterns of the second semiconductor layer 104 and the first semiconductor layer 103, and the orthographic projections of the thus formed patterns of the first semiconductor layer 103 and the second semiconductor layer 104 on the substrate 100 substantially completely overlap each other.
  • the patterns of the gate 101 and the gate insulating layer 102 can also be formed simultaneously by using the same mask through the same patterning process.
  • step S101 as shown in (a) of FIG. 8 , a pattern of a gate 101 is formed on a substrate 100 such as glass; and then a gate insulating layer 102 is formed on the formed pattern of the gate 101 .
  • the present disclosure does not limit this, as long as the formed first oxide material Oxide1 of the first semiconductor layer 103 and the second oxide material Oxide2 of the second semiconductor layer 104 satisfy the absolute value of ( ECBM Oxide1-E CBM Oxide2) >0.2eV, so that most of the carriers in the first semiconductor layer 103 are blocked from migrating to the back channel, and then cannot be captured by the back channel, which improves the stability of the thin film transistor.
  • the same mask is used to simultaneously form the patterns of the first semiconductor layer 103 and the second semiconductor layer 104 through the same patterning process, so the stability of the device can be improved without adding a mask.
  • the material of the first semiconductor layer 103 may include at least one of IGZO, IZO, IGTO and IGZTO, and these materials all have relatively high electron mobility;
  • the material of the second semiconductor layer 104 may include At least one of GZO and Pr-GZO (GZO is doped with a certain amount of Pr (praseodymium element)), these materials all have a higher conduction band bottom.
  • a source-drain material layer is formed on the pattern of the first semiconductor layer 103 and the second semiconductor layer 104 on the gate insulating layer 102, and the source-drain material layer is wet-etched with an etchant to form a layer on the first semiconductor layer 103.
  • a source 105 and a drain 106 are respectively formed on both sides.
  • the second semiconductor layer 104 as an etching barrier layer can protect the material of the first semiconductor layer 103 from being damaged by the etchant.
  • the source electrode 105 and the drain electrode 106 formed in this step cover both ends of the first semiconductor layer 103 and the second semiconductor layer 104 at the same time, but as described above, in this disclosure , when the thin film transistor is working, only the first semiconductor layer 103 is used as an effective carrier channel to make the thin film transistor turn on, while the second semiconductor layer 104 is mainly used as an etching barrier layer and plays an interface matching role, so that the effective The carriers are confined in the first semiconductor layer 103 as far as possible, and the carriers are prevented from migrating to the second semiconductor layer 104 .
  • step S104 a passivation layer 107 is formed on the formed structure to protect the thin film transistor.
  • the manufacturing method includes steps S201 to S204 .
  • step S202 patterns of the first semiconductor layer 103 , the second semiconductor layer 104 and the third semiconductor layer 108 are formed on the gate insulating layer 102 .
  • a first oxide material layer, a second oxide material layer and a third oxide material layer are sequentially formed on the gate insulating layer 102, and then the first semiconductor layer 103, the second semiconductor layer 103,
  • the pattern of the second semiconductor layer 104 and the third semiconductor layer 108 specifically, for example, coating photoresist on the third oxide material layer, then exposing, developing and etching, simultaneously forming the first semiconductor layer 103, the second semiconductor layer layer layer 104 and a third semiconductor layer 108 .
  • the material of the third semiconductor layer 108 may be the third oxide material Oxide3.
  • the third oxide material may be a crystalline oxide material, such as IGZO (136) or the like.
  • the energy level relationship of the conduction band bottom E CBM of the first oxide material Oxide1, the second oxide material Oxide2 and the third oxide material Oxide3 of the active layer can be set as:
  • the level relationship can be set as:
  • the patterns of the first semiconductor layer 103, the second semiconductor layer 104, and the third semiconductor layer 108 are simultaneously formed by using the same mask through the same patterning process, so the performance of the device can be improved without adding a mask. stability.
  • step S204 a passivation layer 107 is formed on the formed structure to protect the thin film transistor.
  • the manufacturing method includes steps S301 to S305.
  • step S301 the buffer layer 200, the second material layer, the first material layer, the gate insulating material layer, and the gate material layer are sequentially formed on the substrate 100; the gate 101 is formed by using the same first mask plate through the same patterning process and the pattern of the gate insulating layer 102; then the first semiconductor layer 103 and the second semiconductor layer 104 are formed through the same patterning process using the same second mask.
  • the orthographic projection area of the first semiconductor layer 103 and the second semiconductor layer 104 on the substrate 100 is larger than that of the gate electrode 101 and the gate insulating layer 102 on the substrate. The area of the orthographic projection on 100.
  • step S302 an interlayer dielectric layer 109 is formed on a side of the gate 101 away from the substrate 100 .
  • step S303 a first through hole and a second through hole are formed in the interlayer dielectric layer 109 corresponding to two ends of the first semiconductor layer 103 .
  • step S304 the source and drain materials are respectively filled in the first through hole and the second through hole, thereby forming a source and a drain respectively.
  • step S305 a passivation layer is formed on the source and the drain.
  • the active layer includes a first semiconductor layer 103 and a second semiconductor layer 104, both of which are oxide semiconductor layers.
  • the first oxide material Oxide1 of the first semiconductor layer 103 and the second oxide material Oxide2 of the second semiconductor layer 104 should satisfy the absolute value of ( ECBM Oxide1-E CBM Oxide2)>0.2eV, and may be greater than 0.3eV.
  • the material of the first semiconductor layer 103 can be, for example, IGZO, which is used as a semiconductor layer material in the related art, and the material of the second semiconductor layer 104 can be, for example, GZO, which mainly functions as an etching stopper layer.
  • the absolute value of the difference ( ECBM Oxide1-E CBM Oxide2) is greater than 0.4eV, and at this time, most of the carriers in the first semiconductor layer 103 can be blocked and cannot migrate to The back channel cannot be trapped by the back channel, which improves the stability of the thin film transistor.
  • An embodiment of the present disclosure also provides an array substrate, including the above thin film transistor.
  • the array substrate includes a driving circuit.
  • a driving circuit of a light emitting device may include a plurality of thin film transistors, such as switching transistors and driving transistors, and at least one of these transistors may be the thin film transistor provided by the embodiments of the present disclosure.
  • An embodiment of the present disclosure also provides a display panel, including the above-mentioned array substrate.
  • the display panel may include various types of display panels, such as a liquid crystal display panel, an active matrix organic light emitting diode (Active-matrix OLED, AMOLED) display panel, a passive matrix organic electroluminescent diode (Passive matrix OLED, PMOLED) display panel, or a micro light emitting diode (Micro LED) display panel.
  • a liquid crystal display panel an active matrix organic light emitting diode (Active-matrix OLED, AMOLED) display panel, a passive matrix organic electroluminescent diode (Passive matrix OLED, PMOLED) display panel, or a micro light emitting diode (Micro LED) display panel.
  • AMOLED active matrix organic light emitting diode
  • Passive matrix OLED PMOLED
  • Micro LED micro light emitting diode

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Abstract

薄膜晶体管及其制备方法、阵列基板和显示面板，薄膜晶体管，包括：基板（100）；以及设置在基板（100）上的栅极（101）、栅极绝缘层（102）、有源层、源极（105）和漏极（106），有源层包括沿着垂直于基板（100）的方向依次设置的第一半导体层（103）和第二半导体层（104），第二半导体层（104）设置在第一半导体层（103）的远离栅极（101）的一侧，以及第一半导体层（103）的第一材料的导带底与第二半导体层（104）的第二材料的导带底的差值的绝对值大于0.2eV，使得作为沟道层的第一半导体层（103）中的绝大部分载流子被阻挡而无法迁移至背沟道，进而无法被背沟道所俘获，提高了薄膜晶体管的稳定性。

Description

薄膜晶体管及其制备方法、阵列基板和显示面板 技术领域
本公开涉及显示技术领域，具体地涉及一种薄膜晶体管及其制备方法、阵列基板和显示面板。
背景技术
随着氧化物薄膜晶体管(Oxide TFT)朝着更高迁移率发展，器件稳定性也逐渐降低，使得其在朝着高分辨率、高刷新率、低功耗、窄边框等高性能显示方向发展时无法保持产品的稳定性，如TFT在高电压、高电流情况冲击下，易造成TFT特性的偏移，GOA输出异常。
发明内容
本公开提供了薄膜晶体管及其制备方法、阵列基板和显示面板。
在本公开的第一方面，提供了一种薄膜晶体管，其包括：基板；以及设置在基板上的栅极、栅极绝缘层、有源层、源极和漏极，其中，所述有源层包括沿着垂直于所述基板的方向依次设置的第一半导体层和第二半导体层，所述第二半导体层设置在第一半导体层的远离所述栅极的一侧；所述第一半导体层包括第一氧化物材料，所述第二半导体层包括第二氧化物材料；所述第一氧化物材料的电子迁移率高于所述第二氧化物材料的电子迁移率；以及所述第一氧化物材料的导带底低于所述第二氧化物材料的导带底，并且所述第一氧化物材料的导带底与所述第二氧化物材料的导带底的差值的绝对值大于0.2eV。
在一个实施例中，所述有源层还包括设置在所述第二半导体层的远离所述栅极一侧的第三半导体层，以及所述第三半导体层包括结晶氧化物材料。
在一个实施例中，所述结晶氧化物材料包括结晶IGZO。
在一个实施例中，所述有源层还包括设置在所述第一半导体层的靠近所述 栅极一侧的第四半导体层；所述第四半导体层包括第四氧化物材料；以及所述第四氧化物材料的电子迁移率小于所述第一氧化物材料的电子迁移率。
在一个实施例中，所述第四氧化物材料与所述第二氧化物材料相同。
在一个实施例中，所述第一氧化物材料包括IGZO，IZO，IGTO，ITZO和IGZTO中的至少一种；以及所述第二氧化物材料包括GZO和Pr-GZO中的至少一种。
在一个实施例中，所述栅极绝缘层处于所述栅极的远离所述基板的一侧；所述有源层处于所述栅极的远离所述基板的一侧；所述第一半导体层和所述第二半导体层在所述基板上的正投影面积大致相同；以及所述源极和所述漏极分别与所述栅极绝缘层上所述第一半导体层和所述第二半导体层的相对两端接触。
在一个实施例中，所述薄膜晶体管还包括设置在基板上的缓冲层和层间介电层，其中，所述第二半导体层设置在所述缓冲层的远离所述基板的一侧；所述第一半导体层设置在所述第二半导体层的远离所述基板的一侧；所述栅极绝缘层设置在所述第一半导体层的远离所述基板的一侧；所述栅极设置在所述栅极绝缘层的远离所述基板的一侧；所述层间介电层设置在所述栅极的远离所述基板的一侧；所述第一半导体层和所述第二半导体层在所述基板上的正投影面积大致相同；以及所述源极和所述漏极分别通过所述层间介电层中的第一过孔和第二过孔与所述第一半导体层相对的两端接触。
在本公开的第二方面，提供了一种薄膜晶体管的制备方法，其包括：在基板上形成栅极、栅极绝缘层、有源层、源极和漏极，使得所述有源层包括沿着垂直于所述基板的方向依次设置的第一半导体层和第二半导体层，所述第二半导体层设置在第一半导体层的远离所述栅极的一侧，所述第一半导体层包括第一氧化物材料，所述第二半导体层包括第二氧化物材料；所述第一氧化物材料的电子迁移率高于所述第二氧化物材料的电子迁移率；以及所述第一氧化物材料的导带底低于所述第二氧化物材料的导带底，并且所述第一氧化物材料的导带底与所述第二氧化物材料的导带底的差值的绝对值大于0.2eV。
在一个实施例中，所述第一氧化物材料包括IGZO，ITZO，IZO，IGTO和IGZTO 中的至少一种；以及所述第二氧化物材料包括GZO和Pr-GZO中的至少一种。
在一个实施例中，在基板上形成栅极、栅极绝缘层、有源层、源极和漏极包括：在基板上形成栅极的图案；在栅极的图案上形成栅极绝缘层；在栅极绝缘层上依次形成第一氧化物材料层和第二氧化物材料层，并且利用第一掩膜通过一次构图工艺在栅极绝缘层上形成第一半导体层和第二半导体层的图案；
在栅极绝缘层上第一半导体层和第二半导体层的图案上形成源漏材料层，对源漏材料层进行蚀刻以在第一半导体层的相对的两端分别形成源极和漏极；以及在源极和漏极上形成钝化层。
在一个实施例中，在基板上形成栅极、栅极绝缘层、有源层、源极和漏极包括：在所述基板上形成栅极的图案；在栅极的图案上形成栅极绝缘层；在栅极绝缘层上依次形成第一氧化物材料层、第二氧化物材料层和第三氧化物材料层，并且利用第一掩膜通过一次构图工艺在栅极绝缘层上形成第一半导体层、第二半导体层和第三半导体层的图案；在栅极绝缘层上第一半导体层、第二半导体层和第三半导体层的图案上形成源漏材料层，对源漏材料层进行蚀刻以在第一半导体层的相对的两端分别形成源极和漏极；以及在源极和漏极上形成钝化层。
在一个实施例中，所述第三半导体层包括结晶氧化物材料。
在一个实施例中，在基板上形成栅极、栅极绝缘层、有源层、源极和漏极包括：在基板上形成栅极的图案；在栅极的图案上形成栅极绝缘层；在栅极绝缘层上依次形成第四氧化物材料层、第一氧化物材料层和第二氧化物材料层，并且利用第一掩膜通过一次构图工艺在栅极绝缘层上形成第四半导体层、第一半导体层和第二半导体层的图案；
在栅极绝缘层上第四半导体层、第一半导体层和第二半导体层的图案上形成源漏材料层，对源漏材料层进行蚀刻以在第一半导体层的相对的两端分别形成源极和漏极；以及在源极和漏极上形成钝化层。
在一个实施例中，在基板上形成栅极、栅极绝缘层、有源层、源极和漏极包括：在基板上依次形成缓冲层、第二氧化物材料层、第一氧化物材料层、栅 极绝缘材料层和栅极材料层；利用第一掩膜板通过一次构图工艺形成栅极和栅极绝缘层的图案；利用第二掩膜板通过一次构图工艺形成第一半导体层和第二半导体层的图案；在栅极的远离所述基板的一侧形成层间介电层；在层间介电层中对应于第一半导体层相对的两端位置分别形成第一通孔和第二通孔；在第一通孔和第二通孔中分别填充源漏极材料，形成源极和漏极；以及在源极和漏极上形成钝化层。
本公开还提供了一种阵列基板，其包括发光器件和用于驱动发光器件发光的驱动电路，其中，所述驱动电路包括上述薄膜晶体管。
本公开还提供了一种显示面板，其包括上述阵列基板。
附图说明
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1A和图1B示出了相关技术的薄膜晶体管的结构示意图；
图2示出了根据本公开实施例的薄膜晶体管的结构示意图；
图3示出了图2所示的薄膜晶体管的第一半导体层和第二半导体层的能级示意图；
图4示出了由第一半导体层和第二半导体层构成的叠层沟道的载流子浓度与第一半导体层的第一材料和第二半导体层的第二材料的导带能级差之间的关系；
图5示出了背沟道电荷数量与第一半导体层的第一材料和第二半导体层的第二材料的导带能级差之间的关系；
图6A示出了根据本公开实施例的薄膜晶体管的结构示意图；
图6B示出了根据本公开实施例的薄膜晶体管的结构示意图；
图6C示出了根据本公开实施例的薄膜晶体管的结构示意图；
图7示出了根据本公开实施例的薄膜晶体管的结构示意图；
图8示出了根据本公开实施例的薄膜晶体管的制备过程示意图；
图9示出了根据本公开实施例的薄膜晶体管的制备方法的流程图；
图10示出了根据本公开实施例的薄膜晶体管的制备方法的流程图；以及
图11示出了根据本公开实施例的薄膜晶体管的制备方法的流程图。
具体实施方式
本申请描述了多个实施例，但是这些实施例是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说，在本申请所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
此外，在描述具有代表性的实施例时，说明书可能已经将方法和/或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法和/或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本申请实施例的精神和范围内。
除非另外定义，本申请实施例公开使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的 或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述的对象的绝对位置改变后，则该相对位置关系也可能相应地改变；而且被描述的对象之间可以是直接接触的，也可以是非直接接触的。
相关技术的氧化物薄膜晶体管的有源层通常为单层高迁移率氧化物材料，例如单层铟镓锌氧化物(IGZO)，这种结构利用源漏(S/D)刻蚀液在湿法刻蚀形成源漏(S/D)极时会存在沟道的背离基板且靠近源漏层的一侧(称为背沟道)被S/D刻蚀液侵蚀的情况。例如，如图1A所示，相关技术中的薄膜晶体管可以包括基板100、在基板100上依次形成的栅极101、栅极绝缘层102、有源层103、源极105、漏极106、以及覆盖源极105和漏极106的钝化层107。
图1A所示的薄膜晶体管中，有源层103的沟道实际与栅极绝缘层102与钝化层107相接触，由于S/D刻蚀液对例如单层IGZO的氧化物材料的有源层103的损伤较大，以至于在背沟道形成大量缺陷，导致器件稳定性显著降低，严重影响器件特性，而实际沟道与栅极绝缘层或者钝化层接触时会存在一定的界面缺陷，这部分缺陷也会降低稳定性。为了解决这一问题，相关技术会在单层氧化物有源层的基础上，增加氧化物材料的刻蚀阻挡层1001，如图1B所示，在不增加掩膜工艺的情况下，可以提高器件稳定性。但是相关技术的方案一般会采用结晶化的氧化物作为刻蚀阻挡层1001对沟道进行保护，刻蚀阻挡层1001的导带底E CBM与实际沟道材料的导带底E CBM之间的差异较小，通常两者的差值在0.2eV以内，这会使得沟道内部一定量的载流子1000依然会迁移至背沟道，即迁移到蚀刻阻挡层的远离半导体层的一侧，进而被背沟道缺陷捕获，造成稳定性降低。
在本申请的说明书中，导带(conduction band)是由自由电子形成的能量空间，即固体结构内自由运动的电子所具有的能量范围；符号CBM表示导带最低点(CBM)；E CBM表示导带底距离真空能级Evac的能量值，真空能级Evac为0eV；半导体最重要的能带就是价带顶(VBM)和导带底(CBM)。CBM减去VBM就是禁带宽度(带隙,能隙)。
在相关技术中，可以利用结晶IGZO(例如IGZO(136)，薄膜中In：Ga：Zn的原子比为1：3：6)材料来制备蚀刻阻挡层1001,其E CBM距离真空能级Evac的距离测试为4.3eV，例如利用非晶IGZO(例如IGZO(111)，薄膜中In：Ga：Zn的原子比为1：1：1)材料来制备薄膜晶体管的半导体层，即沟槽层，其E CBM距离Evac距离测试为4.48eV，因此二者E CBM的差值<0.2eV，从而使得源漏图案形成过程中易在有源层背沟道处形成大量背沟道缺陷，背沟道缺陷会使得器件工作时捕获大量载流子1000，导致器件稳定性降低。
即，在相关技术中，构成有源层的第一半导体层的第一材料Oxide1(例如IGZO(111))和第二半导体层的第二材料Oxide2(例如IGZO(136))二者的导带底之间的能级差值的绝对值小于0.2eV，即|E CBMOxide1-E CBMOxide2|<0.2eV。例如Oxide1为IGZO(111)，Oxide2为IGZO(136)，两者导带底差值在0.2eV以内，无法有效阻止电子的迁移。
为了解决上述技术问题，本申请实施例提供了一种薄膜晶体管及其制备方法。
如图2所示，本公开的薄膜晶体管包括例如由玻璃制备的基板100以及在基板100上依次形成的栅极101、栅极绝缘层102、包括第一半导体层103和第二半导体层104的有源层、源极105、漏极106和钝化层107。
如图2所示，本公开的薄膜晶体管的第一半导体层103和第二半导体层104叠置形成了有源层。第一半导体层103作为有源层中主要用于形成沟道的部分，其通常采用高迁移率氧化物的材料，其设置在栅极绝缘层102和第二半导体层104之间。例如，可以采用金属氧化物材料形成第一半导体层103，其导带底E CBM范围为4.4eV至5.2eV，带隙Eg在2.0eV至3.2eV，载流子浓度在5*E19数量级以内。第二半导体层104设置在第一半导体层103的远离栅极101一侧。在本实施例的薄膜晶体管中，如上所述，期望载流子处于第一半导体层103中，使得在薄膜晶体管工作时第一半导体层103作为沟道层而在源极105和漏极106之间传输载流子；而第二半导体层104的主要作用为界面匹配和刻蚀保护，起到蚀刻阻挡层的作用。
具体地,在本公开中，所述第一半导体层103的第一材料的导带底与所述第二半导体层104的第二材料的导带底的差值的绝对值大于0.2eV。
在一个实施例中，第一半导体层103和第二半导体层104均为氧化物半导体层。第一半导体层103的第一氧化物材料Oxide1和第二半导体层104的第二氧化物材料Oxide2应当满足(E CBMOxide1-E CBMOxide2)的绝对值>0.2eV，进一步可以大于0.3eV。
第一半导体层103的材料例如可以为相关技术中作为半导体层材料的IGZO，而第二半导体层104的材料例如可以采用GZO,其主要作用为刻蚀阻挡层。在这种情况下，可以确保(E CBMOxide1-E CBMOxide2)的绝对值大于0.4eV，此时可以使得第一半导体层103中的绝大部分载流子被阻挡而无法迁移至背沟道，进而无法被背沟道所俘获，提高了薄膜晶体管的稳定性。
具体地，所述第一半导体层103的材料可以包括IGZO，IZO，IGTO、ITZO和IGZTO中的至少一种，这些材料均具有较高的电子迁移率；所述第二半导体层104的材料可以包括GZO和Pr-GZO(GZO中掺入一定量Pr(镨元素))中的至少一种，这些材料均具有较高的导带底。具体地,这些材料的导带底E CBM如下：IGZO(111)＝4.48eV，IZO(31)(薄膜中In：Zn的原子比为3:1)＝5.2eV，IZO(11)(薄膜中In：Zn的原子比为1:1)＝4.9eV，GZO(73)(薄膜中Ga：Zn的原子比为7:3)＝4.05eV，GZO(37)(薄膜中Ga：Zn的原子比为3:7)＝4.08eV。
在该实施例中，可以采用一次构图工艺同时形成第一半导体层103和第二半导体层104的图案。例如，可以在基板100上依次形成第一氧化物材料层和第二氧化物材料层，然后利用同一个掩膜版通过一次构图工艺(包括涂覆光刻胶、曝光、显影、刻蚀)来同时形成第一半导体层103和第二半导体层104的图案，如此形成的第一半导体层103和第二半导体层104的图案在基板100上的正投影大致完全重叠。
图3示出了薄膜晶体管的第一半导体层103包括IGZO和第二半导体层104包括GZO时各层的能级图关系。IGZO的第一半导体层103的带隙Eg1例如为3eV，GZO的第二半导体层104的带隙Eg2例如为4.03eV，IGZO的第一半导体层103 的导带底小于GZO的第二半导体层104的导带底，二者之间的导带底之间的差值的绝对值为ΔEcm。在第一半导体层103采用非晶IGZO(例如IGZO(111))而第二半导体层104采用GZO时，二者之间的ΔEcm的绝对值约为0.43eV，即，|E CBMIGZO-E CBMGZO|≈0.43eV。
在相关技术中，薄膜晶体管的有源层包括非晶IGZO(例如IGZO(111))和结晶IGZO(例如IGZO(136))，非晶IGZO(例如IGZO(111))和结晶IGZO(例如IGZO(136))二者的导带底相差在0.2eV内，因此无法有效阻挡电子的迁移。相对于相关技术，本公开的薄膜晶体管的有源层取代相关技术中的结晶IGZO，采用了例如高导带材料的GZO作为刻蚀阻挡层的材料设置在第一半导体层103的远离栅极101的一侧，其中，|E CBMOxide1-E CBMOxide2|>0.3eV，这种情况下可以使得底沟道绝大部分载流子被阻挡即无法迁移至背沟道，进而无法被背沟道缺陷所捕获，提高TFT稳定性。
图4和图5分别示出了模拟的沟道载流子浓度、背沟道电荷数量与第一半导体层和第二半导体层的材料之间的导带底能级差值(简称为导带差值)的关系的示意图。
具体地，图4示出了作为叠层沟道的有源层中各个位置的载流子浓度的模拟图，其中横坐标表示有源层距离栅极绝缘层102的距离，纵坐标表示载流子浓度大小。在叠层沟道为N型沟道时，载流子为电子。第二半导体层104的第二氧化物材料Oxide2的导带底E CBM较大程度的大于第一半导体层103的第一氧化物材料Oxide1的导带底E CBM，使得第一氧化物材料Oxide1中的载流子需克服两者的较大的势能后才能进行迁移，提高了载流子向第二氧化物材料Oxide2中迁移的难度。如下图所示，当(E CBMOxide1-E CBMOxide2的绝对值)(|E CBMOxide1-E CBMOxide2|)＜0.2eV时，背沟道载流子浓度在1.0E11/cm 3数量级左右，这样数量级的背沟道载流子会使得稳定性降低，但如果进一步提升导带差异，如|E CBMOxide1-E CBMOxide2|>0.3eV时，背沟道载流子浓度降低至1.0E8/cm 3数量级；进一步提升|E CBMOxide1-E CBMOxide2|>0.4eV时，背沟道载流子浓度降低至1.0E6/cm 3数量级，相较前沟道(即第一半导体层103)中的载 流子浓度1.0E16/cm 3数量级，降低了10个数量级，从而显著提高器件稳定性。
在本公开中，薄膜晶体管正常工作状态下的载流子浓度为第一半导体层内部载流子浓度。例如，第一半导体层103的载流子浓度值一般在1*E15/cm 3至1*E19/cm 3之间。在本公开实施例中，将第一半导体层103的第一氧化物材料Oxide1和第二半导体层104的第二氧化物材料Oxide2两种材料的导带底之间的差值绝对值设置为0.2eV及以上，可以将背沟道载流子浓度降低至1*E11/cm 3～1*E1/cm 3范围内。
图5以第一半导体层103由非晶IGZO(例如IGZO(111))制备而第二半导体层104由一种氧化物材料(标识为IGZOX)制备为例进行说明。由图5可以见，当第一半导体层的材料和第二半导体层的材料二者的导带差值在0.2eV时，背沟道载流子数量约在1*E11数量级；当导带差值大于0.3eV时，背沟道电荷数量约在1*E9数量级，降低两个数量级；进一步，当导带差值到达0.4eV，背沟道电荷数量约在1*E7数量级，又降低两个数量级。
由以上可以看出，在本公开的薄膜晶体管中，第一半导体层103的第一氧化物材料Oxide1的导带底与第二半导体层104的第二氧化物材料Oxide2的导带底之间的差值大于0.2eV时，背沟道载流子浓度显著降低。进一步增大第一半导体层103的第一氧化物材料Oxide1的导带底与第二半导体层104的第二氧化物材料Oxide2的导带底之间的差值，可以进一步减小背沟道载流子浓度，从而可以显著提升氧化物薄膜晶体管的稳定性。
图6A示出了根据本公开实施例的薄膜晶体管的示意图。该薄膜晶体管可以包括基板100以及在基板100上依次形成的栅极101、栅极绝缘层102、包括第一半导体层103和第二半导体层104的有源层、源极105、漏极106和钝化层107。在该实施例中，有源层包括依次叠置的第一半导体层103、第二半导体层104和第三半导体层108，第二半导体层104设置在第一半导体层103的远离栅极101的一侧，而第三半导体层108设置在第二半导体层104的远离栅极101的一侧。
与图2所示的实施例相同，在该实施例中，第一半导体层103作为有源层 中主要用于形成沟道的部分，其通常采用高迁移率的氧化物材料；第二半导体层104采用高导带底的氧化物材料。例如，第一半导体层103的第一氧化物材料Oxide1为常规沟道材料，如IGZO、IGTO、IZO、ITZO、IGZTO等，第二半导体层104的第二氧化物材料Oxide2为GZO、Pr-GZO等。与图2所示的实施例不同，该实施例的薄膜晶体管的有源层还包括了设置在主要用作刻蚀阻挡层的第二半导体层104的远离栅极101一侧的第三半导体层108。第三半导体层108的材料可以为第三氧化物材料Oxide3。例如，第三氧化物材料可以为结晶氧化物材料，如IGZO(136)等。在该实施例中，有源层的第一氧化物材料Oxide1、第二氧化物材料Oxide2和第三氧化物材料Oxide3的导带底E CBM的能级关系可以设置为：|E CBMOxide1-E CBMOxide2|>0.2eV，为了进一步提升薄膜晶体管的性能，可以使得|E CBMOxide1-E CBMOxide2|>0.3eV；而第二氧化物材料Oxide2和第三氧化物材料Oxide3的导带底的能级关系可以设置为：
|E CBMOxide3|>|E CBMOxide2|(即，第三氧化物材料的导带底的绝对值大于第二氧化物材料的导带底的绝对值)。
图6A所示的实施例的薄膜晶体管在有源层的远离栅极101的一侧又增设了一层结晶氧化物层，用以提升物理阻挡特性防止临近的膜层或工艺中的H和O影响半导体层。通过该种叠层沟道设计，可以显著提升高迁移率氧化物薄膜晶体管稳定性。
图6B示出了根据本公开实施例的薄膜晶体管的示意图。该薄膜晶体管可以包括基板100以及在基板100上依次形成的栅极101、栅极绝缘层102、包括第一半导体层103、第二半导体层104和第四半导体层110的有源层、源极105、漏极106和钝化层107。在该实施例中，有源层包括依次叠置在栅极绝缘层102上的第四半导体层110、第一半导体层103和第二半导体层104，第二半导体层104设置在第一半导体层103的远离栅极101的一侧，而第四半导体层110设置在第一半导体层103的靠近栅极101的一侧。
与图2所示的实施例相同，在该实施例中，第一半导体层103作为有源层中主要用于形成沟道的部分，其通常采用高迁移率的氧化物材料；第二半导体 层104采用高导带底的氧化物材料。例如，第一半导体层103的第一氧化物材料Oxide1为常规沟道材料，如IGZO、IGTO、IZO、ITZO、IGZTO等，第二半导体层104的第二氧化物材料Oxide2为GZO、Pr-GZO等。与图2所示的实施例不同，该实施例的薄膜晶体管的有源层还包括了设置在主要用作载流子通道的第一半导体层103的靠近栅极101一侧的第四半导体层110，即，在该实施例中，有源层包括了分别设置在第一半导体层103两侧的第二半导体层104和第四半导体层110。第四半导体层110的材料可以与第二半导体层104的材料相同，为第二氧化物材料Oxide2。例如，在该实施例中，有源层的第一氧化物材料Oxide1和第二氧化物材料Oxide2的导带底E CBM的能级关系可以设置为：|E CBMOxide1-E CBMOxide2|>0.2eV，为了进一步提升薄膜晶体管的性能，可以使得|E CBMOxide1-E CBMOxide2|>0.3eV。
类似地，为了进一步提升器件性能，还可以在图6B所示的薄膜晶体管的有源层的第二半导体层104上进一步设置第三半导体层108，如图6C所示，如上所述，在该实施例中，第三半导体层108的材料可以为第三氧化物材料Oxide3。例如，第三氧化物材料可以为结晶氧化物材料，如IGZO(136)等。在该实施例中，有源层的第一氧化物材料Oxide1、第二氧化物材料Oxide2和第三氧化物材料Oxide3的导带底E CBM的能级关系可以设置为：|E CBMOxide1-E CBMOxide2|>0.2eV，为了进一步提升薄膜晶体管的性能，可以使得|E CBMOxide1-E CBMOxide2|>0.3eV；而第二氧化物材料Oxide2和第三氧化物材料Oxide3的导带底的能级关系可以设置为：
|E CBMOxide3|>|E CBMOxide2|。
以上实施例以薄膜晶体管为底栅型晶体管对本公开进行了描述，本公开不限于此。图7示出了根据本公开实施例的薄膜晶体管为顶栅型薄膜晶体管的结构示意图。
图7所示的薄膜晶体管包括例如由玻璃制备的基板100以及在基板100上依次形成的缓冲层200、第二半导体层104、第一半导体层103、栅极绝缘层102、栅极101、层间介电层109、源极105、漏极106和钝化层107。
在该顶栅型薄膜晶体管中，与图2所示的实施例类似，有源层包括第一半导体层103和第二半导体层104，第二半导体层104设置在第一半导体层103的远离栅极101一侧。与图2所示的实施例相同，第一半导体层103作为有源层中主要用于形成沟道承载载流子从而实现薄膜晶体管导通的部分，其通常采用高迁移率氧化物的材料，其设置在栅极绝缘层102和第二半导体层104之间，例如，可以采用IGZO形成第一半导体层103，其导带底E CBM范围为4.4eV至5.2eV，带隙Eg在2.0eV至3.2eV，载流子浓度在5*E19数量级以内。第二半导体层104设置在第一半导体层103的远离栅极101一侧。在本实施例的薄膜晶体管中，如上所述，期望载流子处于第一半导体层103中，使得在薄膜晶体管工作时第一半导体层103作为沟道来在源极105和漏极106之间传输载流子；而第二半导体层104的主要作用为界面匹配和刻蚀保护，起到蚀刻阻挡层的作用。
具体地,在本公开中，所述第一半导体层103的第一材料的导带底与所述第二半导体层104的第二材料的导带底的差值的绝对值大于0.2eV。
在一个实施例中，第一半导体层103和第二半导体层104均为氧化物半导体层。第一半导体层103的第一氧化物材料Oxide1和第二半导体层104的第二氧化物材料Oxide2应当满足(E CBMOxide1-E CBMOxide2)的绝对值>0.2eV，进一步可以大于0.3eV。
第一半导体层103的材料例如可以为相关技术中作为半导体层材料的IGZO，而第二半导体层104的材料例如可以采用GZO,其主要作用为刻蚀阻挡层。在这种情况下，可以确保(E CBMOxide1-E CBMOxide2)的差值的绝对值大于0.4eV，此时可以使得第一半导体层103中的绝大部分载流子被阻挡而无法迁移至背沟道，进而无法被背沟道所俘获，提高了薄膜晶体管的稳定性。
具体地，所述第一半导体层103的材料可以包括IGZO，IZO，IGTO和IGZTO中的至少一种，这些材料均具有较高的电子迁移率；所述第二半导体层104的材料可以包括GZO和Pr-GZO(GZO中掺入一定量Pr(镨元素))中的至少一种，这些材料均具有较高的导带底。具体地,这些材料的导带底E CBM如下：：IGZO (111)＝4.48eV，IZO(31)＝5.2eV，IZO(11)＝4.9eV，GZO(73)＝4.05eV，GZO(37)＝4.08eV。
在该实施例中，源极105和漏极106分别通过延伸穿过层间介电层109的两个过孔与第一半导体层103的未被栅极101和栅极绝缘层102覆盖的两端电连接。在该实施例中，可以采用单个构图工艺同时形成第二半导体层104和第一半导体层103的图案。例如，可以在基板100上的缓冲层200上依次形成第二氧化物材料层和第一氧化物材料层，然后通过利用同一个掩膜版的同一构图工艺(包括涂覆光刻胶、曝光、显影、刻蚀)来同时形成第二半导体层104和第一半导体层103的图案，如此形成的第一半导体层103和第二半导体层104的图案在基板100上的正投影大致完全重叠。类似地，也可以利用同一掩膜版通过同一构图工艺同时形成栅极101和栅极绝缘层102的图案。
本公开的另一方面还提供了制备薄膜晶体管的方法。图8示出了根据本公开的薄膜晶体管的制备方法的各个步骤所形成的结构的流程图。具体地，如图9所示，本公开的薄膜晶体管的制备方法的流程图包括步骤S101至S104。
在步骤S101，如图8的(a)，在例如玻璃的基板100上形成栅极101的图案；然后在形成的栅极101的图案上形成栅极绝缘层102。
在步骤S102，如图8的(b)，在栅极绝缘层102上形成第一半导体层103和第二半导体层104的图案。例如，首先在栅极绝缘层102上依次形成第一氧化物材料层和第二氧化物材料层，然后利用同一掩膜通过同一构图工艺同时形成第一半导体层103和第二半导体层104的图案，具体地，例如在第二氧化物材料层上涂覆光刻胶，然后曝光、显影和蚀刻，同时形成第一半导体层103和第二半导体层104。本公开对此不进行限定，只要所形成的第一半导体层103的第一氧化物材料Oxide1和第二半导体层104的第二氧化物材料Oxide2满足(E CBMOxide1-E CBMOxide2)的绝对值>0.2eV即可，从而使得第一半导体层103中的绝大部分载流子被阻挡而无法迁移至背沟道，进而无法被背沟道所俘获，提高了薄膜晶体管的稳定性。在该步骤中，采用了同一掩膜通过同一构图工艺同时形成了第一半导体层103和第二半导体层104的图案，因此可以在不增加 掩膜的情况下提高器件的稳定性。
如上所述，所述第一半导体层103的材料可以包括IGZO，IZO，IGTO和IGZTO中的至少一种，这些材料均具有较高的电子迁移率；所述第二半导体层104的材料可以包括GZO和Pr-GZO(GZO中掺入一定量Pr(镨元素))中的至少一种，这些材料均具有较高的导带底。具体地,这些材料的导带底E CBM如下：：IGZO(111)＝4.48eV，IZO(31)＝5.2eV，IZO(11)＝4.9eV，GZO(73)＝4.05eV，GZO(37)＝4.08eV。
在步骤S103，在栅极绝缘层102上第一半导体层103和第二半导体层104的图案上形成源漏材料层，利用蚀刻液对源漏材料层进行湿法蚀刻以在第一半导体层103两侧分别形成源极105和漏极106。作为刻蚀阻挡层的第二半导体层104此步骤中可以保护第一半导体层103的材料不会受到蚀刻液的损伤。
如图8的(c)所示，在该步骤中形成的源极105和漏极106同时覆盖了第一半导体层103和第二半导体层104的两端，但是如上所述，在本公开中，在薄膜晶体管工作时，只有第一半导体层103作为有效的载流子通道使得薄膜晶体管导通，而第二半导体层104主要用作蚀刻阻挡层，并且起到界面匹配的作用，以将有效载流子尽量限制在第一半导体层103中，阻挡载流子迁移到第二半导体层104中。
在步骤S104，在所形成的结构上形成钝化层107对薄膜晶体管进行保护。
在本公开的一个实施例中，对于图6所示的有源层包括第一半导体层103、第二半导体层104和第三半导体层108的薄膜晶体管，制备方法包括步骤S201至S204。
在步骤S201，在例如玻璃的基板100上形成栅极101的图案；然后在形成的栅极101的图案上形成栅极绝缘层102。
在步骤S202，在栅极绝缘层102上形成第一半导体层103、第二半导体层104和第三半导体层108的图案。例如，首先在栅极绝缘层102上依次形成第一氧化物材料层、第二氧化物材料层和第三氧化物材料层，然后利用同一掩膜通过同一构图工艺同时形成第一半导体层103、第二半导体层104和第三半导体层 108的图案，具体地，例如在第三氧化物材料层上涂覆光刻胶，然后曝光、显影和蚀刻，同时形成第一半导体层103、第二半导体层104和第三半导体层108。如上所述，第三半导体层108的材料可以为第三氧化物材料Oxide3。例如，第三氧化物材料可以为结晶氧化物材料，如IGZO(136)等。在该实施例中，有源层的第一氧化物材料Oxide1、第二氧化物材料Oxide2和第三氧化物材料Oxide3的导带底E CBM的能级关系可以设置为：|E CBMOxide1-E CBMOxide2|>0.2eV，为了进一步提升薄膜晶体管的性能，可以使得|E CBMOxide1-E CBMOxide2|>0.3eV；而第二氧化物材料Oxide2和第三氧化物材料Oxide3的导带底的能级关系可以设置为：|E CBMOxide3|>|E CBMOxide2|。通过这些设置，可以使得第一半导体层103中的绝大部分载流子被阻挡而无法迁移至背沟道，进而无法被背沟道所俘获，提高了薄膜晶体管的稳定性。在该步骤中，采用了同一掩膜通过同一构图工艺同时形成了第一半导体层103、第二半导体层104和第三半导体层108的图案，因此可以在不增加掩膜的情况下提高器件的稳定性。
在步骤S203，在栅极绝缘层102上第一半导体层103、第二半导体层104和第三半导体层108的图案上形成源漏材料层，利用蚀刻液对源漏材料层进行湿法蚀刻以在第一半导体层103两侧分别形成源极105和漏极106。作为刻蚀阻挡层的第二半导体层104此步骤中可以保护第一半导体层103的材料不会受到蚀刻液的损伤。
在步骤S204，在所形成的结构上形成钝化层107对薄膜晶体管进行保护。
在本公开的一个实施例中，对于图7所示的有源层包括第一半导体层103和第二半导体层104的顶栅型薄膜晶体管而言，制备方法包括步骤S301至S305。
在步骤S301，在基板100上依次形成缓冲层200、第二材料层、第一材料层、栅极绝缘材料层和栅极材料层；利用同一第一掩膜板通过同一构图工艺形成栅极101和栅极绝缘层102的图案；然后利用同一第二掩膜板通过同一构图工艺形成第一半导体层103和第二半导体层104。如图7所示，为了保留对源极105和漏极106接触位置，第一半导体层103和第二半导体层104在基板100上的正投影面积大于栅极101和栅极绝缘层102在基板100上的正投影面积。
在步骤S302，在栅极101的远离基板100的一侧形成层间介电层109。
在步骤S303，在层间介电层109中对应于第一半导体层103的两端位置分别形成第一通孔和第二通孔。
在步骤S304，在第一通孔和第二通孔中分别填充源漏极材料，从而分别形成源极和漏极。
在步骤S305，在源极和漏极上形成钝化层。
在本公开的薄膜晶体管中，有源层包括第一半导体层103和第二半导体层104，第一半导体层103和第二半导体层104均为氧化物半导体层。第一半导体层103的第一氧化物材料Oxide1和第二半导体层104的第二氧化物材料Oxide2应当满足(E CBMOxide1-E CBMOxide2)的绝对值>0.2eV，进一步可以大于0.3eV。第一半导体层103的材料例如可以为相关技术中作为半导体层材料的IGZO，而第二半导体层104的材料例如可以采用GZO,其主要作用为刻蚀阻挡层。在这种情况下，可以确保(E CBMOxide1-E CBMOxide2)的差值的绝对值大于0.4eV，此时可以使得第一半导体层103中的绝大部分载流子被阻挡而无法迁移至背沟道，进而无法被背沟道所俘获，提高了薄膜晶体管的稳定性。
本公开实施例还提供一种阵列基板，包括上述的薄膜晶体管。
具体的，阵列基板包括驱动电路。阵列基板驱动发光器件时，一个发光器件的驱动电路可以包括多个薄膜晶体管，例如包括开关晶体管、驱动晶体管等，这些晶体管中的至少一个晶体管可以为本公开实施例提供的薄膜晶体管。
本公开实施例还提供一种显示面板，包括上述阵列基板。
可选地，显示面板可以包括各种类型的显示面板，例如液晶显示面板，有源矩阵有机发光二极管(Active-matrix OLED，AMOLED)显示面板，无源矩阵有机电激发光二极管(Passive matrix OLED，PMOLED)显示面板，也可以是微发光二极管(Micro LED)显示面板。
虽然本申请所揭露的实施方式如上，但所述的内容仅为便于理解本申请而采用的实施方式，并非用以限定本申请。任何本申请所属领域内的技术人员，在不脱离本申请所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (17)

  1. 一种薄膜晶体管，包括：
    基板；以及
    设置在基板上的栅极、栅极绝缘层、有源层、源极和漏极，其中，
    所述有源层包括沿着垂直于所述基板的方向依次设置的第一半导体层和第二半导体层，
    所述第二半导体层设置在第一半导体层的远离所述栅极的一侧；
    所述第一半导体层包括第一氧化物材料，所述第二半导体层包括第二氧化物材料；
    所述第一氧化物材料的电子迁移率高于所述第二氧化物材料的电子迁移率；以及
    所述第一氧化物材料的导带底低于所述第二氧化物材料的导带底，并且所述第一氧化物材料的导带底与所述第二氧化物材料的导带底的差值的绝对值大于0.2eV。
  2. 根据权利要求1所述的薄膜晶体管，其中，
    所述有源层还包括设置在所述第二半导体层的远离所述栅极一侧的第三半导体层，以及
    所述第三半导体层包括结晶氧化物材料。
  3. 根据权利要求2所述的薄膜晶体管，其中，
    所述结晶氧化物材料包括结晶IGZO。
  4. 根据权利要求1至3中任一项所述的薄膜晶体管，其中，
    所述有源层还包括设置在所述第一半导体层的靠近所述栅极一侧的第四半导体层；
    所述第四半导体层包括第四氧化物材料；以及
    所述第四氧化物材料的电子迁移率小于所述第一氧化物材料的电子迁移率。
  5. 根据权利要求4所述的薄膜晶体管，其中，
    所述第四氧化物材料与所述第二氧化物材料相同。
  6. 根据权利要求1至5中任一项所述的薄膜晶体管，其中，
    所述第一氧化物材料包括IGZO，IZO，IGTO，ITZO和IGZTO中的至少一种；以及
    所述第二氧化物材料包括GZO和Pr-GZO中的至少一种。
  7. 根据权利要求1至6中任一项所述的薄膜晶体管，其中，
    所述栅极绝缘层处于所述栅极的远离所述基板的一侧；
    所述有源层处于所述栅极的远离所述基板的一侧；
    所述第一半导体层和所述第二半导体层在所述基板上的正投影面积大致相同；以及
    所述源极和所述漏极分别与所述栅极绝缘层上所述第一半导体层和所述第二半导体层的相对的两端接触。
  8. 根据权利要求1至6中任一项所述的薄膜晶体管，还包括设置在基板上的缓冲层和层间介电层，其中，
    所述第二半导体层设置在所述缓冲层的远离所述基板的一侧；
    所述第一半导体层设置在所述第二半导体层的远离所述基板的一侧；
    所述栅极绝缘层设置在所述第一半导体层的远离所述基板的一侧；
    所述栅极设置在所述栅极绝缘层的远离所述基板的一侧；
    所述层间介电层设置在所述栅极的远离所述基板的一侧；
    所述第一半导体层和所述第二半导体层在所述基板上的正投影面积大致相同；以及
    所述源极和所述漏极分别通过所述层间介电层中的第一过孔和第二过孔与所述第一半导体层相对的两端接触。
  9. 一种薄膜晶体管的制备方法，包括：
    在基板上形成栅极、栅极绝缘层、有源层、源极和漏极，使得所述有源层包括沿着垂直于所述基板的方向依次设置的第一半导体层和第二半导体层，所述第二半导体层设置在第一半导体层的远离所述栅极的一侧，所述第一半导体层包括第一氧化物材料，所述第二半导体层包括第二氧化物材料；所述第一氧化物材料的电子迁移率高于所述第二氧化物材料的电子迁移率；以及所述第一氧化物材料的导带底低于所述第二氧化物材料的导带底，并且所述第一氧化物材料的导带底与所述第二氧化物材料的导带底的差值的绝对值大于0.2eV。
  10. 根据权利要求9所述的制备方法，其中，
    所述第一氧化物材料包括IGZO，ITZO，IZO，IGTO和IGZTO中的至少一种；以及
    所述第二氧化物材料包括GZO和Pr-GZO中的至少一种。
  11. 根据权利要求9或10所述的制备方法，其中，在基板上形成栅极、栅极绝缘层、有源层、源极和漏极包括：
    在基板上形成栅极的图案；
    在栅极的图案上形成栅极绝缘层；
    在栅极绝缘层上依次形成第一氧化物材料层和第二氧化物材料层，并且利用第一掩膜通过一次构图工艺在栅极绝缘层上形成第一半导体层和第二半导体层的图案；
    在栅极绝缘层上第一半导体层和第二半导体层的图案上形成源漏材料层， 对源漏材料层进行蚀刻以在第一半导体层的相对的两端分别形成源极和漏极；以及
    在源极和漏极上形成钝化层。
  12. 根据权利要求9或10所述的制备方法，其中，在基板上形成栅极、栅极绝缘层、有源层、源极和漏极包括：
    在所述基板上形成栅极的图案；
    在栅极的图案上形成栅极绝缘层；
    在栅极绝缘层上依次形成第一氧化物材料层、第二氧化物材料层和第三氧化物材料层，并且利用第一掩膜通过一次构图工艺在栅极绝缘层上形成第一半导体层、第二半导体层和第三半导体层的图案；
    在栅极绝缘层上第一半导体层、第二半导体层和第三半导体层的图案上形成源漏材料层，对源漏材料层进行蚀刻以在第一半导体层的相对的两端分别形成源极和漏极；以及
    在源极和漏极上形成钝化层。
  13. 根据权利要求12所述的制备方法，其中，所述第三半导体层包括结晶氧化物材料。
  14. 根据权利要求9至13中任一项所述的制备方法，其中，在基板上形成栅极、栅极绝缘层、有源层、源极和漏极包括：
    在基板上形成栅极的图案；
    在栅极的图案上形成栅极绝缘层；
    在栅极绝缘层上依次形成第四氧化物材料层、第一氧化物材料层和第二氧化物材料层，并且利用第一掩膜通过一次构图工艺在栅极绝缘层上形成第四半导体层、第一半导体层和第二半导体层的图案；
    在栅极绝缘层上第四半导体层、第一半导体层和第二半导体层的图案上形 成源漏材料层，对源漏材料层进行蚀刻以在第一半导体层的相对的两端分别形成源极和漏极；以及
    在源极和漏极上形成钝化层。
  15. 根据权利要求9或10所述的制备方法，其中，在基板上形成栅极、栅极绝缘层、有源层、源极和漏极包括：
    在基板上依次形成缓冲层、第二氧化物材料层、第一氧化物材料层、栅极绝缘材料层和栅极材料层；
    利用第一掩膜板通过一次构图工艺形成栅极和栅极绝缘层的图案；
    利用第二掩膜板通过一次构图工艺形成第一半导体层和第二半导体层的图案；
    在栅极的远离所述基板的一侧形成层间介电层；
    在层间介电层中对应于第一半导体层相对的两端位置分别形成第一通孔和第二通孔；
    在第一通孔和第二通孔中分别填充源漏极材料，形成源极和漏极；以及
    在源极和漏极上形成钝化层。
  16. 一种阵列基板，包括发光器件和用于驱动发光器件发光的驱动电路，其中，所述驱动电路包括根据权利要求1至8中任一项所述的薄膜晶体管。
  17. 一种显示面板，包括根据权利要求16所述的阵列基板。
PCT/CN2021/133997 2021-11-29 2021-11-29 薄膜晶体管及其制备方法、阵列基板和显示面板 WO2023092554A1 (zh)

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