WO2023082324A1 - 显示装置及电子设备 - Google Patents

显示装置及电子设备 Download PDF

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Publication number
WO2023082324A1
WO2023082324A1 PCT/CN2021/132418 CN2021132418W WO2023082324A1 WO 2023082324 A1 WO2023082324 A1 WO 2023082324A1 CN 2021132418 W CN2021132418 W CN 2021132418W WO 2023082324 A1 WO2023082324 A1 WO 2023082324A1
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WO
WIPO (PCT)
Prior art keywords
transistor
output
current source
electrically connected
adjustable current
Prior art date
Application number
PCT/CN2021/132418
Other languages
English (en)
French (fr)
Inventor
刘金风
蔡淼荣
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/617,583 priority Critical patent/US20240005837A1/en
Publication of WO2023082324A1 publication Critical patent/WO2023082324A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of display technology, in particular to a display device and electronic equipment.
  • Energy Star which is a government program jointly implemented by the U.S. Department of Energy and the U.S. Environmental Protection Agency, aims to better protect the living environment and save energy. It is mainly used in computers, office equipment, and household appliances. . Display products also need to meet the power consumption requirements of Energy Star before they can be sold on the market normally, and energy efficiency standards are also evolving and tightening year by year (ES7.0 ⁇ ES8.0 ⁇ ES9.0).
  • the present application provides a display device and electronic equipment to improve the display quality and reduce the technical problems of display power consumption.
  • the present application provides a display device, which includes a display panel and a data driver.
  • the display panel includes a plurality of data lines; the output end of the data driver is electrically connected to the plurality of data lines respectively, and the data driver includes an output amplifier.
  • the output amplifier is used to output the corresponding data signal to the display panel, and a pulse duration of the data signal includes a start time period, a sustain time period and an end time period; wherein, in the start time period, the output amplifier has a first bias current; during the sustain period, the output amplifier has a second bias current; during the end period, the output amplifier has a third bias current; and the current value of the first bias current is greater than the current value of the second bias current , and/or, the current value of the third bias current is greater than the current value of the second bias current.
  • the current value of the first bias current is equal to or greater than the current value of the third bias current.
  • the duration of the start time period is less than or equal to the duration of the maintenance period; and/or, the duration of the end period is less than or equal to the duration of the maintenance period.
  • the time length of the start time period is equal to the time length of the end time period.
  • the output amplifier includes an input stage, an amplification stage, and an output stage, and the input stage is used to access and differentially process the first input signal and the second input signal; the input end of the amplification stage is electrically connected to the output end of the input stage The electrical connection is used to amplify the differential result of the first input signal and the second input signal; the input end of the output stage is electrically connected to the output end of the amplification stage, and the output end of the output stage is used to output the corresponding data signal.
  • the input stage includes a transistor MN1, a transistor MN2, a transistor MN3, a transistor MP3, a transistor MP2, and a transistor MP1, the gate of the transistor MN1 is used to access the first input signal, and the transistor MN1 is an N-channel transistor
  • the gate of the transistor MN2 is used to access the second input signal, and the transistor MN2 is an N-channel transistor;
  • the drain of the transistor MN3 is electrically connected to the source of the transistor MN1 and the source of the transistor MN2, and the gate of the transistor MN3
  • the source of the transistor MN3 is used for connecting the negative power supply signal, and the transistor MN3 is an N-channel transistor;
  • the source of the transistor MP3 is used for connecting the positive power supply signal, and the gate of the transistor MP3 is used for
  • the second control signal is connected, the transistor MP3 is a P-channel transistor;
  • the source of the transistor MP2 is electrically connected to the drain of the transistor MP3, the gate of the transistor MP
  • the amplification stage includes an adjustable current source IP5, an adjustable current source I7, an adjustable current source IN5, an adjustable current source IP6, an adjustable current source I8, and an adjustable current source IN6, and the adjustable current source
  • the input end of IP5 is used to access the positive power supply signal, the output end of the adjustable current source IP5 is electrically connected to the drain of the transistor MN2; the input end of the adjustable current source I7 is electrically connected to the output end of the adjustable current source IP5 ;
  • the input terminal of the adjustable current source IN5 is electrically connected with the output terminal of the adjustable current source I7 and the drain of the transistor MP2, and the output terminal of the adjustable current source IN5 is used to connect the negative power supply signal, the negative power supply signal and the positive power supply signal It is used to form a DC power supply; the input terminal of the adjustable current source IP6 is used to access the positive power supply signal, the output terminal of the adjustable current source IP6 is electrically connected with the drain of the transistor MN1, and the output current value of the adjustable current source IP6
  • the output stage includes a transistor MP9 and a transistor MN9, the gate of the transistor MP9 is electrically connected to the output terminal of the adjustable current source IP6, the source of the transistor MP9 is used to access the positive power supply signal, and the transistor MP9 The drain is used to output data signals, and the transistor MP9 is a P-channel transistor; the gate of the transistor MN9 is electrically connected to the output terminal of the adjustable current source I8, and the drain of the transistor MN9 is electrically connected to the drain of the transistor MP9.
  • the source of transistor MN9 is used to connect the negative power supply signal.
  • the output stage further includes a capacitor CM1 and a capacitor CM2, one end of the capacitor CM1 is electrically connected to the gate of the transistor MP9, and the other end of the capacitor CM1 is electrically connected to the drain of the transistor MP9; one end of the capacitor CM2 It is electrically connected to the other end of the capacitor CM1, and the other end of the capacitor CM2 is electrically connected to the gate of the transistor MN9.
  • the display device further includes a timing controller, and the timing controller includes at least one register, and the at least one register is used for storing the current of the start time period, the maintenance time period, the end time period, and the first bias current value, the current value of the second bias current, and the configuration data corresponding to the current value of the third bias current; wherein, the output end of the timing controller is electrically connected to the input end of the data driver, and the data driver is based on the received configuration data The output amplifier is controlled to output a corresponding data signal.
  • the present application provides an electronic device, which includes a mobile terminal and the display device in any one of the foregoing implementation manners; the mobile terminal is combined with the display device.
  • the first bias current, the second bias current, and the third bias current corresponding to the output amplifier are respectively configured in the start time period, the maintenance time period, and the end time period.
  • the current value of the first bias current is greater than the current value of the second bias current
  • the current value of the third bias current is greater than the current value of the second bias current, which can effectively shorten the pulse edge of the data signal.
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a timing controller provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a driver chip provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an output amplifier provided by an embodiment of the present application.
  • FIG. 5 is a circuit schematic diagram of the output amplifier in FIG. 4 .
  • FIG. 6 is a schematic diagram of the variation of the pulse edge transition time of the data signal with the bias current.
  • FIG. 7 is a schematic diagram of comparing waveforms of data signals corresponding to two different bias currents.
  • FIG. 8 is a comparison diagram of power consumption corresponding to various display situations.
  • this embodiment provides a display device, which includes a display panel 100 and a data driver 200, the display panel 100 includes a plurality of data lines DL; the data driver 200 The output terminals of the data driver 200 are respectively electrically connected to a plurality of data lines DL.
  • the data driver 200 includes at least one driver chip 210. Each driver chip 210 may include at least one output amplifier 211. The output amplifier 211 is used to output the corresponding data signal to the display. Panel 100.
  • the display device may also include a timing controller 300, and the timing controller 300 includes at least one register 310, and at least one register 310 is used for storing and starting time period, maintaining time period, ending Configuration data corresponding to the time period, the current value of the first bias current, the current value of the second bias current, and the current value of the third bias current; wherein, the output terminal of the timing controller 300 is connected to the input terminal of the data driver 200 Electrically connected, the data driver 200 controls the output amplifier 211 to output corresponding data signals based on the received configuration data.
  • the inverting input terminal of the output amplifier 211 can be electrically connected with its output terminal to form a corresponding inverting voltage follower, which can be used to amplify the current value of the data signal.
  • the output amplifier 211 includes an input stage 2111, an amplification stage 2112, and an output stage 2113.
  • the input stage 2111 is used to access and differentially process the first input signal AVP, the second Input signal AVO;
  • the input terminal of the amplifier stage 2112 is electrically connected to the output terminal of the input stage 2111, and is used to amplify the differential result of the first input signal AVP and the second input signal AVO;
  • the input terminal of the output stage 2113 is connected to the output terminal of the amplifier stage 2112
  • the output terminals are electrically connected, and the output terminals of the output stage 2113 are used to output corresponding data signals.
  • the first input signal AVP can be connected to the non-inverting input terminal of the output amplifier 211
  • the second input signal AVO can be connected to the inverting input terminal of the output amplifier 211 .
  • the input stage 2111 includes a transistor MN1, a transistor MN2, a transistor MN3, a transistor MP3, a transistor MP2, and a transistor MP1.
  • the gate of the transistor MN1 is used to access the first input signal AVP,
  • the transistor MN1 is an N-channel transistor;
  • the gate of the transistor MN2 is used to access the second input signal AVO, and the transistor MN2 is an N-channel transistor;
  • the drain of the transistor MN3 is connected to the source of the transistor MN1 and the source of the transistor MN2 Electrically connected, the gate of the transistor MN3 is used to access the first control signal VBN1, the source of the transistor MN3 is used to connect to the negative power supply signal VSS, the transistor MN3 is an N-channel transistor;
  • the source of the transistor MP3 is used to access The positive power supply signal VDD, the gate of the transistor MP3 is used to access the second control signal VBP1, the transistor MP3 is a P-channel transistor;
  • I-bias represents the bias current of the output amplifier 211 .
  • the amplification stage 2112 includes a multi-channel current source connected between the input stage 2111 and the output stage 2113, the multi-channel current source includes an adjustable current source IP5, an adjustable current source I7, adjustable current source IN5, adjustable current source IP6, adjustable current source I8 and adjustable current source IN6, the input terminal of the adjustable current source IP5 is used to access the positive power supply signal VDD, the output of the adjustable current source IP5 terminal is electrically connected to the drain of the transistor MN2; the input terminal of the adjustable current source I7 is electrically connected to the output terminal of the adjustable current source IP5; the input terminal of the adjustable current source IN5 is connected to the output terminal of the adjustable current source I7, The drain of the transistor MP2 is electrically connected, the output terminal of the adjustable current source IN5 is used to connect the negative power supply signal VSS, and the negative power supply signal VSS and the positive power supply signal VDD are used to form a DC power supply; the input terminal of the adjustable current source IP6 is used for When the positive power
  • the output stage 2113 includes a transistor MP9 and a transistor MN9, the gate of the transistor MP9 is electrically connected to the output terminal of the adjustable current source IP6, the source of the transistor MP9 is used to access the positive power supply signal VDD, and the transistor MP9
  • the drain of MP9 is used to output data signals, and the transistor MP9 is a P-channel transistor; the gate of the transistor MN9 is electrically connected to the output terminal of the adjustable current source I8, and the drain of the transistor MN9 is electrically connected to the drain of the transistor MP9 connection, the source of the transistor MN9 is used to connect the negative power supply signal VSS.
  • the output stage 2113 further includes a capacitor CM1 and a capacitor CM2, one end of the capacitor CM1 is electrically connected to the gate of the transistor MP9, and the other end of the capacitor CM1 is electrically connected to the drain of the transistor MP9; the capacitor CM2 One end is electrically connected to the other end of the capacitor CM1 , and the other end of the capacitor CM2 is electrically connected to the gate of the transistor MN9 . It can be understood that the capacitors CM1 and CM2 can be used to improve the working stability of the output amplifier 211 .
  • the output stage 2113 is composed of the transistor MP9 and the transistor MN9
  • the output stage 2113 is composed of a transistor MN9 to form a common source amplifier circuit, and the PMOS transistor MP9 provides a bias current for the transistor MN9 and acts as an active load of the transistor MN9.
  • the voltage change curve S1, voltage change curve S2, and voltage change curve S3 of the data signal output by the output amplifier 211 jump from a low potential to a target high potential in sequence corresponding to 0.25 times the bias current of the output amplifier 211, 0.5 times the bias current and 1 times the bias current, and the time for the voltage change curve S1, the voltage change curve S2 and the voltage change curve S3 to jump from the low potential to the target high potential is getting shorter and shorter, that is, With the increase of the bias current of the output amplifier 211 provided in the present application, the time required for the pulse edge transition of the data signal becomes shorter and shorter, correspondingly, the charging efficiency/capability of the data signal is also higher and higher.
  • the charging time that can be provided is shorter, so in this shorter charging time, the waveform of the data signal can be closer to the ideal standard square wave signal , can improve the defect of insufficient charging of the pixel, and then can improve the display quality.
  • the bias current of the output amplifier 211 for example, 0.5 times or 1 times the bias current, remains unchanged in a pulse duration T, and the potential change of the data signal output by the output amplifier 211 is shown in the waveform curve S20.
  • the bias current of the output amplifier 211 is configured with different current values in the start time period T1, the maintenance time period T2 and the end time period T3, for example, in the start time period T1, the output amplifier 211 has a first bias current; in the maintenance period T2, the output amplifier 211 has a second bias current; in the end period T3, the output amplifier 211 has a third bias current; and the current value of the first bias current is greater than the second bias current.
  • the potential change of the data signal output by the output amplifier 211 is shown in the waveform curve S10 .
  • the first bias current is 1 times the bias current
  • the second bias current is 0.5 times the bias current
  • the third bias current is 1 times the bias current
  • the current value of the first bias current is equal to or greater than the current value of the third bias current. It can be understood that, in this embodiment, the rising slope of the data signal can be made larger than the falling slope while keeping the second bias current constant, so that the required high potential can be reached faster.
  • the duration of the start period T1 is less than or equal to the duration of the maintenance period T2; and/or, the duration of the end period T3 is less than or equal to the duration of the maintenance period T2.
  • the time length of the start time period T1 is equal to the time length of the end time period T3.
  • the bias current of the conventional output amplifier 211 remains unchanged to achieve the same display quality, its bias current needs to be kept at the first bias current or the third bias current. current, in this way, the second bias current in the maintenance period T2 will generate a long time waste of power consumption, therefore, in general comparison, under the same display quality, the dynamically changing bias current needs lower power consumption.
  • Figure 8 shows the power consumption comparison data of different display situations, where Pattern is used to represent the corresponding screen; 0white is used to represent the 0th white screen; 1Black is used to represent the first black screen; 3Green is used to represent the first black screen.
  • 5Gray191 is used to represent the fifth 191 grayscale picture
  • 7chess is used to represent the seventh checkerboard picture
  • 9H gray Bar is used to represent the ninth horizontal gradient grayscale picture
  • 14colorbar is used to represent the first 14 color bar screens
  • 21Pixel on/off is used to represent the 21st screen with one pixel bright and one pixel dark
  • 22Window shutdown is used to represent the 22nd window screen
  • 23H_strip is used to represent the 23rd horizontal screen where one line is bright and one line is off
  • 32 Sub v-line is used to represent the 32nd vertical screen where one column is bright and one column is dark.
  • SDR ON is used to indicate that the SDR function is turned on, that is, the bias current of the output amplifier 211 can change dynamically.
  • SDR OFF is used to indicate that the SDR function is off, that is, the bias current of the output amplifier 211 remains unchanged.
  • ⁇ P refers to the power consumption, the unit is Mw.
  • Power down refers to the reduced power consumption ratio.
  • the static power consumption in the SDR ON state is generally smaller than that in the SDR OFF state.
  • VAA, HVAA and VDD respectively represent three DC voltages of different specifications required by the display device, and the sum of the power consumption of the three DC voltages of different specifications is the static power consumption of the display device.
  • this application effectively reduces the display power consumption by configuring three stages of dynamically changing bias current for the output amplifier 211 .
  • this embodiment provides an electronic device, which includes a mobile terminal and the display device in any one of the above embodiments; the mobile terminal is combined with the display device.
  • the first bias current, the second bias current and the Three bias currents, and the current value of the first bias current is greater than the current value of the second bias current, and/or, the current value of the third bias current is greater than the current value of the second bias current, which can effectively shorten the data
  • the time required for the pulse edge jump of the signal improves the charging capacity of the data signal, thereby improving the display quality; at the same time, under the same display quality, compared with the bias current that remains unchanged in the traditional technical solution, the present application
  • the output amplifier 211 By configuring the output amplifier 211 with three stages of dynamically changing bias currents, the display power consumption is effectively reduced.
  • the electronic device in the above embodiments may be one of a mobile phone, a tablet computer, a notebook computer, an all-in-one computer, and a smart watch.
  • the mobile phone when the electronic device is a mobile phone, the mobile phone may include a display device and
  • the display device may be installed on the mobile terminal, and the display device may also execute a video signal from the mobile terminal to display a corresponding picture.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

本申请公开了一种显示装置及电子设备，该显示装置通过在起始时间段、维持时间段以及结束时间段中依次配置对应的第一偏置电流、第二偏置电流以及第三偏置电流，且第一偏置电流的电流值大于第二偏置电流的电流值，和/或，第三偏置电流的电流值大于第二偏置电流的电流值，提高了显示品质，降低了显示功耗。

Description

显示装置及电子设备 技术领域
本申请涉及显示技术领域，具体涉及一种显示装置及电子设备。
 背景技术
随着电子产品的普及以及资源问题的日益突出，对消费电子产品的低功耗要求也越来越高。例如能源之星（Energy Star），其是美国能源部和美国环保署共同推行的一项政府计划，旨在更好地保护生存环境，节约能源，主要应用在计算机及办公设备、家用电器等领域。显示产品也需要满足能源之星的功耗要求，才能正常在市面上销售，而且能效标准也在逐年的演变加严（ES7.0→ES8.0→ES9.0）。
因此，不断开发更加节能且更高品质的显示技术是非常有必要的。
 技术问题
本申请提供一种显示装置及电子设备，以改善显示品质并降低显示功耗的技术问题。
 技术解决方案
第一方面，本申请提供一种显示装置，其包括显示面板和数据驱动器，显示面板包括多条数据线；数据驱动器的输出端与多条数据线分别对应电性连接，数据驱动器包括输出放大器，输出放大器用于输出对应的数据信号至显示面板，数据信号的一个脉冲持续时间包括起始时间段、维持时间段以及结束时间段；其中，在起始时间段中，输出放大器具有第一偏置电流；在维持时间段中，输出放大器具有第二偏置电流；在结束时间段中，输出放大器具有第三偏置电流；且第一偏置电流的电流值大于第二偏置电流的电流值，和/或，第三偏置电流的电流值大于第二偏置电流的电流值。
在其中一些实施方式中，第一偏置电流的电流值等于或者大于第三偏置电流的电流值。
在其中一些实施方式中，起始时间段的时间长度小于或者等于维持时间段的时间长度；和/或，结束时间段的时间长度小于或者等于维持时间段的时间长度。
在其中一些实施方式中，起始时间段的时间长度等于结束时间段的时间长度。
在其中一些实施方式中，输出放大器包括输入级、放大级以及输出级，输入级用于接入并差分处理第一输入信号、第二输入信号；放大级的输入端与输入级的输出端电性连接，用于放大第一输入信号与第二输入信号的差分结果；输出级的输入端与放大级的输出端电性连接，输出级的输出端用于输出对应的数据信号。
在其中一些实施方式中，输入级包括晶体管MN1、晶体管MN2、晶体管MN3、晶体管MP3、晶体管MP2以及晶体管MP1，晶体管MN1的栅极用于接入第一输入信号，晶体管MN1为N沟道型晶体管；晶体管MN2的栅极用于接入第二输入信号，晶体管MN2为N沟道型晶体管；晶体管MN3的漏极与晶体管MN1的源极、晶体管MN2的源极电性连接，晶体管MN3的栅极用于接入第一控制信号，晶体管MN3的源极用于连接负电源信号，晶体管MN3为N沟道型晶体管；晶体管MP3的源极用于接入正电源信号，晶体管MP3的栅极用于接入第二控制信号，晶体管MP3为P沟道型晶体管；晶体管MP2的源极与晶体管MP3的漏极电性连接，晶体管MP2的栅极用于接入第二输入信号，晶体管MP2为P沟道型晶体管；晶体管MP1的源极与晶体管MP3的漏极电性连接，晶体管MP1的栅极用于接入第一输入信号，晶体管MP1为P沟道型晶体管。
在其中一些实施方式中，放大级包括可调电流源IP5、可调电流源I7、可调电流源IN5、可调电流源IP6、可调电流源I8以及可调电流源IN6，可调电流源IP5的输入端用于接入正电源信号，可调电流源IP5的输出端与晶体管MN2的漏极电性连接；可调电流源I7的输入端与可调电流源IP5的输出端电性连接；可调电流源IN5的输入端与可调电流源I7的输出端、晶体管MP2的漏极电性连接，可调电流源IN5的输出端用于连接负电源信号，负电源信号与正电源信号用于构成一直流电源；可调电流源IP6的输入端用于接入正电源信号，可调电流源IP6的输出端与晶体管MN1的漏极电性连接，可调电流源IP6的输出电流值与可调电流源IP5的输出电流值相同；可调电流源I8的输入端与可调电流源IP6的输出端电性连接，可调电流源I8的输出电流值与可调电流源I7的输出电流值相同；可调电流源IN6的输入端与可调电流源I8的输出端、晶体管MP1的漏极电性连接，可调电流源IN6的输出端用于连接负电源信号，可调电流源IN6的输出电流值与可调电流源IN5的输出电流值相同。
在其中一些实施方式中，输出级包括晶体管MP9和晶体管MN9，晶体管MP9的栅极与可调电流源IP6的输出端电性连接，晶体管MP9的源极用于接入正电源信号，晶体管MP9的漏极用于输出数据信号，晶体管MP9为P沟道型晶体管；晶体管MN9的栅极与可调电流源I8的输出端电性连接，晶体管MN9的漏极与晶体管MP9的漏极电性连接，晶体管MN9的源极用于连接负电源信号。
在其中一些实施方式中，输出级还包括电容CM1和电容CM2，电容CM1的一端与晶体管MP9的栅极电性连接，电容CM1的另一端与晶体管MP9的漏极电性连接；电容CM2的一端与电容CM1的另一端电性连接，电容CM2的另一端与晶体管MN9的栅极电性连接。
在其中一些实施方式中，显示装置还包括时序控制器，时序控制器包括至少一个寄存器，至少一个寄存器用于存储与起始时间段、维持时间段、结束时间段、第一偏置电流的电流值、第二偏置电流的电流值以及第三偏置电流的电流值对应的配置数据；其中，时序控制器的输出端与数据驱动器的输入端电性连接，数据驱动器基于接收到的配置数据控制输出放大器输出对应的数据信号。
第二方面，本申请提供一种电子设备，其包括移动终端和上述任一实施方式中的显示装置；移动终端与显示装置结合。
 有益效果
本申请提供的显示装置及电子设备，通过在起始时间段、维持时间段以及结束时间段中分别给输出放大器配置依次对应的第一偏置电流、第二偏置电流以及第三偏置电流，且第一偏置电流的电流值大于第二偏置电流的电流值，和/或，第三偏置电流的电流值大于第二偏置电流的电流值，可以有效缩短数据信号的脉冲沿跳变所需时间，提高了数据信号的充电能力，进而提高了显示品质；同时，在相同的显示品质下，与传统技术方案中保持不变的偏置电流相比，本申请通过给输出放大器配置三段动态变化的偏置电流，有效降低了显示功耗。
 附图说明
图1为本申请实施例提供的显示装置的结构示意图。
图2为本申请实施例提供的时序控制器的结构示意图。
图3为本申请实施例提供的驱动芯片的结构示意图。
图4为本申请实施例提供的输出放大器的结构示意图。
图5为图4中输出放大器的电路原理图。
图6为数据信号的脉冲沿跳变时间随偏置电流变化的示意图。
图7为两种不同偏置电流对应的数据信号的波形对比示意图。
图8为多种不同显示情况对应的功耗对比图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
请参阅图1至图8，如图1和图3所示，本实施例提供了一种显示装置，其包括显示面板100和数据驱动器200，显示面板100包括多条数据线DL；数据驱动器200的输出端与多条数据线DL分别对应电性连接，数据驱动器200包括至少一个驱动芯片210，每个驱动芯片210可以包括至少一个输出放大器211，输出放大器211用于输出对应的数据信号至显示面板100。
其中，如图1和图2所示，该显示装置还可以包括时序控制器300，时序控制器300包括至少一个寄存器310，至少一个寄存器310用于存储与起始时间段、维持时间段、结束时间段、第一偏置电流的电流值、第二偏置电流的电流值以及第三偏置电流的电流值对应的配置数据；其中，时序控制器300的输出端与数据驱动器200的输入端电性连接，数据驱动器200基于接收到的配置数据控制输出放大器211输出对应的数据信号。
如图4所示，输出放大器211的反相输入端可以与其输出端电性连接，以形成对应的反相电压跟随器，可以用于放大数据信号的电流值。
如图4和图5所示，在其中一个实施例中，输出放大器211包括输入级2111、放大级2112以及输出级2113，输入级2111用于接入并差分处理第一输入信号AVP、第二输入信号AVO；放大级2112的输入端与输入级2111的输出端电性连接，用于放大第一输入信号AVP与第二输入信号AVO的差分结果；输出级2113的输入端与放大级2112的输出端电性连接，输出级2113的输出端用于输出对应的数据信号。
其中，第一输入信号AVP可以接入至输出放大器211的同相输入端，第二输入信号AVO可以接入至输出放大器211的反相输入端。
如图5所示，在其中一个实施例中，输入级2111包括晶体管MN1、晶体管MN2、晶体管MN3、晶体管MP3、晶体管MP2以及晶体管MP1，晶体管MN1的栅极用于接入第一输入信号AVP，晶体管MN1为N沟道型晶体管；晶体管MN2的栅极用于接入第二输入信号AVO，晶体管MN2为N沟道型晶体管；晶体管MN3的漏极与晶体管MN1的源极、晶体管MN2的源极电性连接，晶体管MN3的栅极用于接入第一控制信号VBN1，晶体管MN3的源极用于连接负电源信号VSS，晶体管MN3为N沟道型晶体管；晶体管MP3的源极用于接入正电源信号VDD，晶体管MP3的栅极用于接入第二控制信号VBP1，晶体管MP3为P沟道型晶体管；晶体管MP2的源极与晶体管MP3的漏极电性连接，晶体管MP2的栅极用于接入第二输入信号AVO，晶体管MP2为P沟道型晶体管；晶体管MP1的源极与晶体管MP3的漏极电性连接，晶体管MP1的栅极用于接入第一输入信号AVP，晶体管MP1为P沟道型晶体管。
其中，I-bias表征输出放大器211的偏置电流。
如图5所示，在其中一个实施例中，放大级2112包括连接于输入级2111与输出级2113之间的多路电流源，该多路电流源包括可调电流源IP5、可调电流源I7、可调电流源IN5、可调电流源IP6、可调电流源I8以及可调电流源IN6，可调电流源IP5的输入端用于接入正电源信号VDD，可调电流源IP5的输出端与晶体管MN2的漏极电性连接；可调电流源I7的输入端与可调电流源IP5的输出端电性连接；可调电流源IN5的输入端与可调电流源I7的输出端、晶体管MP2的漏极电性连接，可调电流源IN5的输出端用于连接负电源信号VSS，负电源信号VSS与正电源信号VDD用于构成一直流电源；可调电流源IP6的输入端用于接入正电源信号VDD，可调电流源IP6的输出端与晶体管MN1的漏极电性连接，可调电流源IP6的输出电流值与可调电流源IP5的输出电流值相同；可调电流源I8的输入端与可调电流源IP6的输出端电性连接，可调电流源I8的输出电流值与可调电流源I7的输出电流值相同；可调电流源IN6的输入端与可调电流源I8的输出端、晶体管MP1的漏极电性连接，可调电流源IN6的输出端用于连接负电源信号VSS，可调电流源IN6的输出电流值与可调电流源IN5的输出电流值相同。
在其中一个实施例中，输出级2113包括晶体管MP9和晶体管MN9，晶体管MP9的栅极与可调电流源IP6的输出端电性连接，晶体管MP9的源极用于接入正电源信号VDD，晶体管MP9的漏极用于输出数据信号，晶体管MP9为P沟道型晶体管；晶体管MN9的栅极与可调电流源I8的输出端电性连接，晶体管MN9的漏极与晶体管MP9的漏极电性连接，晶体管MN9的源极用于连接负电源信号VSS。
在其中一个实施例中，输出级2113还包括电容CM1和电容CM2，电容CM1的一端与晶体管MP9的栅极电性连接，电容CM1的另一端与晶体管MP9的漏极电性连接；电容CM2的一端与电容CM1的另一端电性连接，电容CM2的另一端与晶体管MN9的栅极电性连接。可以理解的是，电容CM1、电容CM2可以用于提高输出放大器211的工作稳定性。
第一输入信号AVP、第二输入信号AVO经过输入级2111与放大级2112差分放大后，通过晶体管MN1和晶体管MP1的漏极输出，用以驱动输出级2113，输出级2113由晶体管MP9和晶体管MN9组成，输出级2113由晶体管MN9组成共源放大电路，PMOS型晶体管MP9为晶体管MN9提供偏置电流，并作为晶体管MN9的有源负载。
如图6所示，输出放大器211输出的数据信号由低电位跳变至目标高电位的电压变化曲线S1、电压变化曲线S2以及电压变化曲线S3依次对应输出放大器211的0.25倍的偏置电流、0.5倍的偏置电流以及1倍的偏置电流，而电压变化曲线S1、电压变化曲线S2以及电压变化曲线S3由低电位跳变至目标高电位的所用时间越来越短，也就是说，本申请提供的输出放大器211随着其偏置电流的增加，数据信号的脉冲沿跳变所需时间越来越短，对应地，数据信号的充电效率/充电能力也越来越高。
特别是对于高频和/或高分辨率的显示装置而言，能够提供的充电时间更短，因此，在这更短的充电时间中，数据信号的波形可以更接近于理想的标准方波信号，可以改善像素充电不足的缺陷，进而可以改善显示品质。
如图7所示，输出放大器211的偏置电流，例如，0.5倍或者1倍的偏置电流，在一个脉冲持续时间T中保持不变，输出放大器211输出的数据信号的电位变化如波形曲线S20。输出放大器211的偏置电流在起始时间段T1、维持时间段T2以及结束时间段T3中分别配置不同的电流值时，例如，在起始时间段T1中，输出放大器211具有第一偏置电流；在维持时间段T2中，输出放大器211具有第二偏置电流；在结束时间段T3中，输出放大器211具有第三偏置电流；且第一偏置电流的电流值大于第二偏置电流的电流值和/或第三偏置电流的电流值大于第二偏置电流的电流值的情况下，输出放大器211输出的数据信号的电位变化如波形曲线S10。例如，第一偏置电流为1倍的偏置电流，第二偏置电流为0.5倍的偏置电流，第三偏置电流为1倍的偏置电流时，通过对比容易发现，波形曲线S10的脉冲沿跳变所用时间明显短于波形曲线S20的脉冲沿跳变所用时间，也就是说，波形曲线S10的脉冲沿更接近于直角即理想的标准方波信号，对于充电不足的改善更具优越性。
在其中一些实施例中，第一偏置电流的电流值等于或者大于第三偏置电流的电流值。可以理解的是，在本实施例中，能够在保持第二偏置电流不变的情况下，使得数据信号的上升坡度大于其下降坡度，可以更快地达到所需的高电位。
在其中一些实施例中，起始时间段T1的时间长度小于或者等于维持时间段T2的时间长度；和/或，结束时间段T3的时间长度小于或者等于维持时间段T2的时间长度。
在其中一些实施例中，起始时间段T1的时间长度等于结束时间段T3的时间长度。
如图8所示，若要达到相同的显示品质的情况下，相对于传统输出放大器211的偏置电流保持不变的话，其偏置电流需要一直保持于第一偏置电流或者第三偏置电流，如此，则在维持时间段T2中的第二偏置电流将会产生时间较长的功耗浪费，因此，总体相比的话，相同的显示品质情况下，动态变化的偏置电流所需的功耗更低。
基于此，图8给出了不同显示情况的功耗对比数据，其中，Pattern用于表征对应的画面；0white用于表征第0个白画面；1Black用于表征第1个黑画面；3Green用于表征第3个绿画面；5Gray191用于表征第5个191灰阶画面；7chess用于表征第7个棋盘格画面；9H gray Bar用于表征第9个水平渐变灰阶画面；14colorbar用于表征第14个彩条画面；21Pixel on/off用于表征第21个一像素亮一像素暗的画面；22Window shutdown用于表征第22个窗口画面；23H_strip用于表征第23个水平一行亮一行灭的画面；32 Sub v-line用于表征第32个垂直一列亮一列暗的画面。SDR ON用于表征SDR功能开启，即输出放大器211的偏置电流可以动态变化。SDR OFF用于表征SDR功能关闭，即输出放大器211的偏置电流保持不变。△P是指功耗，单位是Mw。Power down是指降低的功耗比例。
在对应画面下，SDR ON状态下的静态功耗普遍小于SDR OFF状态下的静态功耗。
其中，VAA、HVAA以及VDD分别代表显示装置所需的三种不同规格的直流电压，该三种不同规格的直流电压的功耗之和为显示装置的静态功耗。
综上所述，在相同的显示品质下，与传统技术方案中保持不变的偏置电流相比，本申请通过给输出放大器211配置三段动态变化的偏置电流，有效降低了显示功耗。
在其中一个实施例中，本实施例提供一种电子设备，其包括移动终端和上述任一实施例中的显示装置；移动终端与显示装置结合。
可以理解的是，本实施例提供的电子设备，通过在起始时间段、维持时间段以及结束时间段中分别给输出放大器211配置依次对应的第一偏置电流、第二偏置电流以及第三偏置电流，且第一偏置电流的电流值大于第二偏置电流的电流值，和/或，第三偏置电流的电流值大于第二偏置电流的电流值，可以有效缩短数据信号的脉冲沿跳变所需时间，提高了数据信号的充电能力，进而提高了显示品质；同时，在相同的显示品质下，与传统技术方案中保持不变的偏置电流相比，本申请通过给输出放大器211配置三段动态变化的偏置电流，有效降低了显示功耗。
需要进行说明的是，上述实施例中的电子设备可以为手机、平板电脑、笔记本电脑、一体式电脑以及智能手表中的一种，例如，当该电子设备为手机时，手机可以包括显示装置和移动终端，该显示装置可以安装于该移动终端上，该显示装置还可以执行源于该移动终端的视频信号以显示对应的画面。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示装置，所述显示装置包括：
    显示面板，所述显示面板包括多条数据线；和
    数据驱动器，所述数据驱动器的输出端与所述多条数据线分别对应电性连接，所述数据驱动器包括输出放大器，所述输出放大器用于输出对应的数据信号至所述显示面板，所述数据信号的一个脉冲持续时间包括起始时间段、维持时间段以及结束时间段；
    其中，在所述起始时间段中，所述输出放大器具有第一偏置电流；在所述维持时间段中，所述输出放大器具有第二偏置电流；在所述结束时间段中，所述输出放大器具有第三偏置电流；且所述第一偏置电流的电流值大于所述第二偏置电流的电流值，和/或，所述第三偏置电流的电流值大于所述第二偏置电流的电流值。
  2. 根据权利要求1所述的显示装置，其中，所述第一偏置电流的电流值等于或者大于所述第三偏置电流的电流值。
  3. 根据权利要求1所述的显示装置，其中，所述起始时间段的时间长度小于或者等于所述维持时间段的时间长度；和/或，所述结束时间段的时间长度小于或者等于所述维持时间段的时间长度。
  4. 根据权利要求3所述的显示装置，其中，所述起始时间段的时间长度等于所述结束时间段的时间长度。
  5. 根据权利要求1所述的显示装置，其中，所述输出放大器包括：
    输入级，用于接入并差分处理第一输入信号、第二输入信号；
    放大级，所述放大级的输入端与所述输入级的输出端电性连接，用于放大所述第一输入信号与所述第二输入信号的差分结果；以及
    输出级，所述输出级的输入端与所述放大级的输出端电性连接，所述输出级的输出端用于输出对应的所述数据信号。
  6. 根据权利要求5所述的显示装置，其中，所述输入级包括：
    晶体管MN1，所述晶体管MN1的栅极用于接入所述第一输入信号，所述晶体管MN1为N沟道型晶体管；
    晶体管MN2，所述晶体管MN2的栅极用于接入所述第二输入信号，所述晶体管MN2为N沟道型晶体管；
    晶体管MN3，所述晶体管MN3的漏极与所述晶体管MN1的源极、所述晶体管MN2的源极电性连接，所述晶体管MN3的栅极用于接入第一控制信号，所述晶体管MN3的源极用于连接负电源信号，所述晶体管MN3为N沟道型晶体管；
    晶体管MP3，所述晶体管MP3的源极用于接入正电源信号，所述晶体管MP3的栅极用于接入第二控制信号，所述晶体管MP3为P沟道型晶体管；
    晶体管MP2，所述晶体管MP2的源极与所述晶体管MP3的漏极电性连接，所述晶体管MP2的栅极用于接入所述第二输入信号，所述晶体管MP2为P沟道型晶体管；以及
    晶体管MP1，所述晶体管MP1的源极与所述晶体管MP3的漏极电性连接，所述晶体管MP1的栅极用于接入所述第一输入信号，所述晶体管MP1为P沟道型晶体管。
  7. 根据权利要求6所述的显示装置，其中，所述放大级包括：
    可调电流源IP5，所述可调电流源IP5的输入端用于接入所述正电源信号，所述可调电流源IP5的输出端与所述晶体管MN2的漏极电性连接；
    可调电流源I7，所述可调电流源I7的输入端与所述可调电流源IP5的输出端电性连接；
    可调电流源IN5，所述可调电流源IN5的输入端与所述可调电流源I7的输出端、所述晶体管MP2的漏极电性连接，所述可调电流源IN5的输出端用于连接所述负电源信号，所述负电源信号与所述正电源信号用于构成一直流电源；
    可调电流源IP6，所述可调电流源IP6的输入端用于接入所述正电源信号，所述可调电流源IP6的输出端与所述晶体管MN1的漏极电性连接，所述可调电流源IP6的输出电流值与所述可调电流源IP5的输出电流值相同；
    可调电流源I8，所述可调电流源I8的输入端与所述可调电流源IP6的输出端电性连接，所述可调电流源I8的输出电流值与所述可调电流源I7的输出电流值相同；以及
    可调电流源IN6，所述可调电流源IN6的输入端与所述可调电流源I8的输出端、所述晶体管MP1的漏极电性连接，所述可调电流源IN6的输出端用于连接所述负电源信号，所述可调电流源IN6的输出电流值与所述可调电流源IN5的输出电流值相同。
  8. 根据权利要求7所述的显示装置，其中，所述输出级包括：
    晶体管MP9，所述晶体管MP9的栅极与所述可调电流源IP6的输出端电性连接，所述晶体管MP9的源极用于接入所述正电源信号，所述晶体管MP9的漏极用于输出所述数据信号，所述晶体管MP9为P沟道型晶体管；和
    晶体管MN9，所述晶体管MN9的栅极与所述可调电流源I8的输出端电性连接，所述晶体管MN9的漏极与所述晶体管MP9的漏极电性连接，所述晶体管MN9的源极用于连接所述负电源信号。
  9. 根据权利要求8所述的显示装置，其中，所述输出级还包括：
    电容CM1，所述电容CM1的一端与所述晶体管MP9的栅极电性连接，所述电容CM1的另一端与所述晶体管MP9的漏极电性连接；和
    电容CM2，所述电容CM2的一端与所述电容CM1的另一端电性连接，所述电容CM2的另一端与所述晶体管MN9的栅极电性连接。
  10. 根据权利要求1所述的显示装置，其中，所述显示装置还包括：
    时序控制器，所述时序控制器包括至少一个寄存器，所述至少一个寄存器用于存储与所述起始时间段、所述维持时间段、所述结束时间段、所述第一偏置电流的电流值、所述第二偏置电流的电流值以及所述第三偏置电流的电流值对应的配置数据；
    其中，所述时序控制器的输出端与所述数据驱动器的输入端电性连接，所述数据驱动器基于接收到的所述配置数据控制所述输出放大器输出对应的所述数据信号。
  11. 一种电子设备，包括：
    如权利要求1所述的显示装置；和
    移动终端，与所述显示装置结合。
  12. 根据权利要求11所述的电子设备，其中，所述第一偏置电流的电流值等于或者大于所述第三偏置电流的电流值。
  13. 根据权利要求11所述的电子设备，其中，所述起始时间段的时间长度小于或者等于所述维持时间段的时间长度；和/或，所述结束时间段的时间长度小于或者等于所述维持时间段的时间长度。
  14. 根据权利要求13所述的电子设备，其中，所述起始时间段的时间长度等于所述结束时间段的时间长度。
  15. 根据权利要求11所述的电子设备，其中，所述输出放大器包括：
    输入级，用于接入并差分处理第一输入信号、第二输入信号；
    放大级，所述放大级的输入端与所述输入级的输出端电性连接，用于放大所述第一输入信号与所述第二输入信号的差分结果；以及
    输出级，所述输出级的输入端与所述放大级的输出端电性连接，所述输出级的输出端用于输出对应的所述数据信号。
  16. 根据权利要求15所述的电子设备，其中，所述输入级包括：
    晶体管MN1，所述晶体管MN1的栅极用于接入所述第一输入信号，所述晶体管MN1为N沟道型晶体管；
    晶体管MN2，所述晶体管MN2的栅极用于接入所述第二输入信号，所述晶体管MN2为N沟道型晶体管；
    晶体管MN3，所述晶体管MN3的漏极与所述晶体管MN1的源极、所述晶体管MN2的源极电性连接，所述晶体管MN3的栅极用于接入第一控制信号，所述晶体管MN3的源极用于连接负电源信号，所述晶体管MN3为N沟道型晶体管；
    晶体管MP3，所述晶体管MP3的源极用于接入正电源信号，所述晶体管MP3的栅极用于接入第二控制信号，所述晶体管MP3为P沟道型晶体管；
    晶体管MP2，所述晶体管MP2的源极与所述晶体管MP3的漏极电性连接，所述晶体管MP2的栅极用于接入所述第二输入信号，所述晶体管MP2为P沟道型晶体管；以及
    晶体管MP1，所述晶体管MP1的源极与所述晶体管MP3的漏极电性连接，所述晶体管MP1的栅极用于接入所述第一输入信号，所述晶体管MP1为P沟道型晶体管。
  17. 根据权利要求16所述的电子设备，其中，所述放大级包括：
    可调电流源IP5，所述可调电流源IP5的输入端用于接入所述正电源信号，所述可调电流源IP5的输出端与所述晶体管MN2的漏极电性连接；
    可调电流源I7，所述可调电流源I7的输入端与所述可调电流源IP5的输出端电性连接；
    可调电流源IN5，所述可调电流源IN5的输入端与所述可调电流源I7的输出端、所述晶体管MP2的漏极电性连接，所述可调电流源IN5的输出端用于连接所述负电源信号，所述负电源信号与所述正电源信号用于构成一直流电源；
    可调电流源IP6，所述可调电流源IP6的输入端用于接入所述正电源信号，所述可调电流源IP6的输出端与所述晶体管MN1的漏极电性连接，所述可调电流源IP6的输出电流值与所述可调电流源IP5的输出电流值相同；
    可调电流源I8，所述可调电流源I8的输入端与所述可调电流源IP6的输出端电性连接，所述可调电流源I8的输出电流值与所述可调电流源I7的输出电流值相同；以及
    可调电流源IN6，所述可调电流源IN6的输入端与所述可调电流源I8的输出端、所述晶体管MP1的漏极电性连接，所述可调电流源IN6的输出端用于连接所述负电源信号，所述可调电流源IN6的输出电流值与所述可调电流源IN5的输出电流值相同。
  18. 根据权利要求17所述的电子设备，其中，所述输出级包括：
    晶体管MP9，所述晶体管MP9的栅极与所述可调电流源IP6的输出端电性连接，所述晶体管MP9的源极用于接入所述正电源信号，所述晶体管MP9的漏极用于输出所述数据信号，所述晶体管MP9为P沟道型晶体管；和
    晶体管MN9，所述晶体管MN9的栅极与所述可调电流源I8的输出端电性连接，所述晶体管MN9的漏极与所述晶体管MP9的漏极电性连接，所述晶体管MN9的源极用于连接所述负电源信号。
  19. 根据权利要求18所述的电子设备，其中，所述输出级还包括：
    电容CM1，所述电容CM1的一端与所述晶体管MP9的栅极电性连接，所述电容CM1的另一端与所述晶体管MP9的漏极电性连接；和
    电容CM2，所述电容CM2的一端与所述电容CM1的另一端电性连接，所述电容CM2的另一端与所述晶体管MN9的栅极电性连接。
  20. 根据权利要求11所述的电子设备，其中，所述显示装置还包括：
    时序控制器，所述时序控制器包括至少一个寄存器，所述至少一个寄存器用于存储与所述起始时间段、所述维持时间段、所述结束时间段、所述第一偏置电流的电流值、所述第二偏置电流的电流值以及所述第三偏置电流的电流值对应的配置数据；
    其中，所述时序控制器的输出端与所述数据驱动器的输入端电性连接，所述数据驱动器基于接收到的所述配置数据控制所述输出放大器输出对应的所述数据信号。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110205193A1 (en) * 2010-02-19 2011-08-25 Renesas Electronics Corporation Operational amplifier with decreased through current, and display panel driver and display device incorporating the same
CN102347011A (zh) * 2010-07-21 2012-02-08 瑞萨电子株式会社 用于液晶显示装置的源极驱动器和使用其的液晶显示装置
CN103474015A (zh) * 2013-08-20 2013-12-25 北京大学深圳研究生院 输出放大器、数模转换器、数据驱动电路和显示装置
CN106257580A (zh) * 2015-06-22 2016-12-28 三星显示有限公司 显示设备和驱动该显示设备的方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3666423B2 (ja) * 2001-07-06 2005-06-29 日本電気株式会社 駆動回路
US6670941B2 (en) * 2001-10-22 2003-12-30 Koninklijke Philips Electronics N.V. Slow rate controlled ramp and its use in liquid crystal displays
KR100486254B1 (ko) * 2002-08-20 2005-05-03 삼성전자주식회사 액정 표시 장치를 저 전력으로 구동하는 회로 및 그 방법
JP2009303121A (ja) * 2008-06-17 2009-12-24 Nec Electronics Corp 演算増幅器回路、その演算増幅器回路を用いた液晶表示装置の駆動方法
TWI408638B (zh) * 2008-10-20 2013-09-11 Raydium Semiconductor Corp 驅動電路系統以及運算放大器迴轉率提高方法
JP5328461B2 (ja) * 2009-04-21 2013-10-30 ルネサスエレクトロニクス株式会社 演算増幅器
JP2011019115A (ja) * 2009-07-09 2011-01-27 Renesas Electronics Corp 差動ａｂ級増幅回路、駆動回路および表示装置
US8466908B2 (en) * 2010-07-13 2013-06-18 Himax Technologies Limited Display device having a bias control unit for dynamically biasing a buffer and method thereof
KR101147354B1 (ko) * 2010-07-19 2012-05-23 매그나칩 반도체 유한회사 출력 버퍼용 슬루율 부스트 회로 및 이를 구비한 출력 버퍼
TWI428880B (zh) * 2010-08-03 2014-03-01 Himax Tech Ltd 動態偏壓驅動裝置及其方法
KR102055841B1 (ko) * 2013-03-05 2019-12-13 삼성전자주식회사 출력 버퍼 회로 및 이를 포함하는 소스 구동 회로
KR20160020650A (ko) * 2014-08-13 2016-02-24 삼성디스플레이 주식회사 데이터 드라이버 및 이의 구동 방법
KR102159257B1 (ko) * 2014-09-26 2020-09-23 삼성전자 주식회사 디스플레이 구동 회로 및 디스플레이 구동 방법
JP2019144548A (ja) * 2018-02-22 2019-08-29 シナプティクス インコーポレイテッド 表示ドライバ、表示装置及び表示パネルの駆動方法
KR102574314B1 (ko) * 2018-08-09 2023-09-04 삼성전자주식회사 휘도에 기반하여 소스 드라이버의 전압 슬루율을 제어하는 전자 장치
KR20200091527A (ko) * 2019-01-22 2020-07-31 삼성디스플레이 주식회사 표시 장치 및 이를 이용한 표시 패널의 구동 방법
KR20210133358A (ko) * 2020-04-28 2021-11-08 삼성디스플레이 주식회사 데이터 구동부, 이를 포함하는 표시 장치 및 이를 이용한 표시 패널의 구동 방법
KR20230060781A (ko) * 2021-10-28 2023-05-08 엘지디스플레이 주식회사 표시 장치 및 그의 구동 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110205193A1 (en) * 2010-02-19 2011-08-25 Renesas Electronics Corporation Operational amplifier with decreased through current, and display panel driver and display device incorporating the same
CN102347011A (zh) * 2010-07-21 2012-02-08 瑞萨电子株式会社 用于液晶显示装置的源极驱动器和使用其的液晶显示装置
CN103474015A (zh) * 2013-08-20 2013-12-25 北京大学深圳研究生院 输出放大器、数模转换器、数据驱动电路和显示装置
CN106257580A (zh) * 2015-06-22 2016-12-28 三星显示有限公司 显示设备和驱动该显示设备的方法

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