WO2023080206A1 - Pitch conversion unit and method for manufacturing same - Google Patents

Pitch conversion unit and method for manufacturing same Download PDF

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Publication number
WO2023080206A1
WO2023080206A1 PCT/JP2022/041213 JP2022041213W WO2023080206A1 WO 2023080206 A1 WO2023080206 A1 WO 2023080206A1 JP 2022041213 W JP2022041213 W JP 2022041213W WO 2023080206 A1 WO2023080206 A1 WO 2023080206A1
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WO
WIPO (PCT)
Prior art keywords
conductive
conversion unit
pitch conversion
conductive layer
thickness direction
Prior art date
Application number
PCT/JP2022/041213
Other languages
French (fr)
Japanese (ja)
Inventor
滋樹 坂井
賀津雄 木村
正展 八木
Original Assignee
ニデックアドバンステクノロジー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ニデックアドバンステクノロジー株式会社 filed Critical ニデックアドバンステクノロジー株式会社
Priority to KR1020247018016A priority Critical patent/KR20240110589A/en
Priority to JP2023558079A priority patent/JPWO2023080206A1/ja
Priority to CN202280073810.2A priority patent/CN118202252A/en
Publication of WO2023080206A1 publication Critical patent/WO2023080206A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/073Multiple probes
    • G01R1/07307Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07364Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/073Multiple probes
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/073Multiple probes
    • G01R1/07307Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07314Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Definitions

  • the present invention relates to a pitch conversion unit and its manufacturing method.
  • a pitch conversion unit for converting the pitch of the plurality of contact terminal side electrodes into the pitch of the plurality of device side electrodes.
  • a pitch conversion unit for example, a space transformer including a ceramic substrate, a wiring layer, and a thin film layer is known, as disclosed in Patent Document 1.
  • the ceramic substrate includes at least one wiring layer inside the ceramic substrate.
  • a conductive path is provided in the ceramic substrate so as to penetrate the wiring layer in the ceramic substrate. Wiring layers connected to the conductive path are provided on one surface and the opposite surface of the ceramic substrate.
  • the wiring layer located on one surface of the ceramic substrate has a wiring pattern corresponding to the arrangement pattern of the probes.
  • the wiring layer located on the opposite side of the ceramic substrate is connected to the printed circuit board via an extendable pogo pin unit.
  • the printed circuit board has printed wiring that can be connected to test circuitry on the inspection machine.
  • Such a conductive path is generally formed by forming a via hole in the substrate in the thickness direction and filling the via hole with a conductive material to electrically connect the conductive layer constituting the wiring layer. Methods are known for forming conductive vias connected to the .
  • the conductive layer is exposed by processing a part of the insulating layer using a laser beam or the like. form a hole.
  • part of the insulating layer may remain on the bottom surface of the hole formed by the laser beam. That is, the conductive layer may not be exposed at the bottom surface of the via hole. In such a case, there is a possibility that sufficient bonding strength cannot be obtained between the conductive via formed by filling the via hole with a conductive material and the conductive layer.
  • An object of the present invention is to improve the bonding strength between a conductive via penetrating an insulating layer in the thickness direction and a conductive layer in a pitch conversion unit that converts the pitch of a plurality of contact terminal side electrodes to the pitch of a plurality of device side electrodes. It is to provide a possible configuration.
  • a pitch conversion unit includes: a plurality of contact terminal side electrodes electrically connected to a plurality of contact terminals for transmitting and receiving electric signals to and from an inspection point to be inspected; and a plurality of device-side electrodes connected to each other, the pitch conversion unit converting the pitch of the plurality of contact terminal-side electrodes into the pitch of the plurality of device-side electrodes.
  • This pitch conversion unit includes: a plurality of resin layers laminated in a thickness direction; a plurality of through conductors penetrating through at least one resin layer among the plurality of resin layers in the thickness direction; The through conductor located on the opposite side to the two resin layers adjacent in the thickness direction among the plurality of through conductors and penetrating the two adjacent resin layers in the thickness direction respectively. a pair of conductive layers to be connected; an insulating layer positioned between the pair of conductive layers; and a via.
  • One conductive layer of the pair of conductive layers has a recess recessed in the thickness direction in at least a portion of a joint portion with the conductive via.
  • a method of manufacturing a pitch conversion unit is a method of manufacturing a pitch conversion unit having the above configuration.
  • This manufacturing method includes a via hole forming step of forming a via hole forming a part of the conductive via in the insulating layer, and a step of forming the via hole in the insulating layer; a recess forming step of forming the recess in a portion of the conductive layer overlapping the via hole; and a conductive via forming the conductive via by filling a conductive material in the via hole. and a forming step.
  • the pitch conversion unit in the pitch conversion unit for converting the pitch of the plurality of contact terminal side electrodes to the pitch of the plurality of device side electrodes, the conductive vias penetrating the insulating layer in the thickness direction It is possible to realize a configuration capable of improving the bonding strength between the substrate and the conductive layer.
  • FIG. 1 is a conceptual diagram showing a schematic configuration of a semiconductor inspection device provided with a pitch conversion unit according to an embodiment.
  • FIG. 2 is a partial cross-sectional view showing the schematic configuration of the inspection unit and showing the inspection jig in cross section.
  • FIG. 3 is a cross-sectional view schematically showing an example of the configuration of the pitch conversion unit.
  • 4A is a partially enlarged sectional view showing an enlarged part of the pitch conversion unit shown in FIG. 3.
  • FIG. FIG. 4B is an enlarged portion showing a part of the pitch conversion unit, in which the conductive layer is formed with a concave portion forming a cylindrical space whose bottom radius is smaller than the radius of the opening formed in the conductive layer; It is an expanded sectional view.
  • FIG. 1 is a conceptual diagram showing a schematic configuration of a semiconductor inspection device provided with a pitch conversion unit according to an embodiment.
  • FIG. 2 is a partial cross-sectional view showing the schematic configuration of the inspection unit and showing the inspection jig
  • FIG. 5 is a cross-sectional view showing an example of a method of manufacturing the pitch conversion unit.
  • FIG. 6 is a cross-sectional view showing an example of a method of manufacturing the pitch conversion unit.
  • FIG. 7 is a cross-sectional view showing an example of a method of manufacturing the pitch conversion unit.
  • FIG. 8 is a cross-sectional view showing an example of a method of manufacturing the pitch conversion unit.
  • FIG. 9 is a cross-sectional view showing an example of a method of manufacturing the pitch conversion unit.
  • FIG. 10 is a cross-sectional view showing an example of a method of manufacturing the pitch conversion unit.
  • the pitch conversion unit according to the present invention can be used in an inspection device that electrically inspects an object to be inspected by bringing a probe into contact with the object to be inspected and causing a current to flow.
  • an inspection device that electrically inspects an object to be inspected by bringing a probe into contact with the object to be inspected and causing a current to flow.
  • a semiconductor inspection apparatus for electrically inspecting a semiconductor wafer to be inspected will be described as an example.
  • FIG. 1 is a perspective view showing a schematic configuration of a semiconductor inspection apparatus 100 having a pitch conversion unit 1 according to an embodiment of the invention.
  • a semiconductor inspection apparatus 100 is an inspection apparatus for inspecting a circuit formed on a semiconductor wafer DUT, which is an example of an object to be inspected.
  • circuits corresponding to a plurality of semiconductor chips are formed on a semiconductor substrate such as silicon.
  • the inspection target is, for example, an electronic component such as a semiconductor chip, a CSP (Chip size package), or a semiconductor element (IC: Integrated Circuit).
  • the semiconductor inspection apparatus 100 shown in FIG. 1 The semiconductor inspection apparatus 100 shown in FIG. 1
  • the sample table 106 has a mounting portion 106a on which the semiconductor wafer DUT is mounted on its upper surface.
  • the sample table 106 can fix the semiconductor wafer DUT to be inspected at a predetermined position.
  • the mounting portion 106a can be raised and lowered.
  • the mounting section 106 a can raise the semiconductor wafer DUT accommodated in the sample stage 106 to the inspection position, and store the inspected semiconductor wafer DUT in the sample stage 106 .
  • the mounting section 106a can rotate the semiconductor wafer DUT, for example, to orient the orientation flat in a predetermined direction.
  • the inspection processing unit 108 has, for example, a power supply circuit, a voltage source, an ammeter, a microcomputer, and the like.
  • the inspection processing unit 108 moves and positions the inspection unit 104 by controlling a driving mechanism (not shown), and brings each probe 121 of the inspection unit 104 into contact with each inspection point of the semiconductor wafer DUT. Thereby, each inspection point and the inspection section 104 are electrically connected.
  • the inspection processing unit 108 supplies an alternating current or voltage for inspection to each inspection point of the semiconductor wafer DUT via each probe 121 in the above-described state, and the voltage signal or current signal obtained from each probe 121 Based on this, the semiconductor wafer DUT is inspected for, for example, circuit pattern breaks and short circuits.
  • the test processing unit 108 may measure the impedance of the test object based on the voltage signal or current signal obtained from each probe 121 by supplying alternating current or voltage to each test point.
  • FIG. 2 is a partial cross-sectional view showing a schematic configuration of the inspection unit 104. As shown in FIG. In FIG. 2, the inspection jig 2 of the inspection unit 104 is shown in cross section for explanation. Note that the configuration shown in FIG. 2 is an example of the inspection unit 104 . The configuration of the inspection unit 104 is not limited to the configuration shown in FIG.
  • the inspection unit 104 has an inspection jig 2 and a connection plate 3 .
  • the inspection jig 2 is a jig for inspecting the semiconductor wafer DUT by bringing a plurality of probes 121 into contact therewith.
  • the inspection unit 104 is, for example, a so-called probe card.
  • the inspection jig 2 has a pitch conversion unit 1, a plurality of probes 121 (contact terminals), and a penetrating member 122 that holds the plurality of probes 121 with their tips directed toward the semiconductor wafer DUT.
  • the inspection jig 2 includes a plurality of probes 121 corresponding to inspection points within a partial area (for example, the hatched area in FIG. 1, hereinafter referred to as an inspection area) of the plurality of chips formed on the semiconductor wafer DUT. have The probe 121 penetrates through the penetrating member 122 . Since the structures of the probe 121 and the penetrating member 122 are the same as those of the conventional art, detailed description thereof will be omitted.
  • connection plate 3 is detachable with the pitch conversion unit 1 .
  • the connection plate 3 has a plurality of electrodes (not shown) electrically connected to the pitch conversion unit 1 .
  • Each electrode of the connection plate 3 is electrically connected to the inspection processing section 108 by, for example, a cable 131, a connection terminal 132, and the like.
  • the pitch conversion unit 1 is a pitch conversion member for converting the spacing between the probes 121 to the electrode pitch of the connection plate 3 .
  • the pitch conversion unit 1 has, on one surface, a plurality of contact terminal side electrodes 21 that are in contact with and conduct with a plurality of probes 121 of the inspection jig 2 .
  • the pitch conversion unit 1 has a plurality of device-side electrodes 22 on the other surface that are electrically connected to electrodes (not shown) of the connection plate 3 via the connection member 4 . A detailed configuration of the pitch conversion unit 1 will be described later.
  • connection member 4 is positioned between the device-side electrode 22 of the pitch conversion unit 1 and the electrode of the connection plate 3 and is in elastic contact with both.
  • the connection member 4 electrically connects the device-side electrode 22 of the pitch conversion unit 1 and the electrode of the connection plate 3 .
  • the connection member 4 is a so-called pogo pin unit.
  • FIG. 1 is an explanatory diagram schematically and conceptually showing an example of the configuration of the semiconductor inspection apparatus 100, and FIG. It is an explanatory view schematically and conceptually shown.
  • FIGS. 1 and 2 the number, density and arrangement of the probes 121, the shape of the inspection section 104, the size ratio, etc. are also illustrated in a simplified and conceptualized manner.
  • the inspection area is emphasized more than that of a general semiconductor inspection apparatus. The inspection area may be smaller than the area shown in FIG. 1 or larger than the area shown in FIG.
  • FIG. 3 is a cross-sectional view schematically showing the configuration of the pitch conversion unit 1.
  • FIG. 4A is a partially enlarged sectional view showing an enlarged part of the pitch conversion unit 1.
  • the pitch conversion unit 1 has a substrate 11 made of resin, a contact terminal side electrode 21, a device side electrode 22, and a conductor 31 positioned inside the substrate 11.
  • the substrate 11 has multiple resin layers 12 and multiple insulating layers 13 .
  • the resin layer 12 is made of epoxy resin such as prepreg, polyimide resin, or the like.
  • the insulating layer 13 is made of, for example, a prepreg, a bonding sheet, or the like.
  • the multiple resin layers 12 and the multiple insulating layers 13 are laminated in the thickness direction. More specifically, as shown in FIG. 3, insulating layers 13 are positioned between resin blocks B composed of a plurality of resin layers 12 laminated in the thickness direction.
  • each resin block B is formed by laminating a plurality of resin layers 12 .
  • the resin blocks B are bonded to each other via the insulating layer 13 .
  • the conductor 31 includes multiple metal layers 32 , multiple through conductors 33 , and multiple conductive vias 34 .
  • a plurality of metal layers 32 are formed planarly along the resin layer 12 in each resin block B.
  • the plurality of through conductors 33 penetrate the resin layer 12 in the thickness direction and electrically connect the metal layers 32 in the thickness direction. That is, the metal layer 32 and the penetrating conductor 33 are electrically connected within each resin block B.
  • the metal layer 32 and the penetrating conductor 33 are made of copper, for example.
  • the metal layer 32 and the penetrating conductor 33 are formed by plating, for example.
  • the plurality of metal layers 32 have conductive layers 36 located at the ends of the resin blocks B in the stacking direction of the resin layers 12 .
  • the conductive layer 36 is electrically connected to the penetrating conductor 33 penetrating the resin layer 12 .
  • the surface of the conductive layer 36 located at the end of the resin block B is covered with the insulating layer 13 . Therefore, the insulating layer 13 is positioned between the conductive layers 36 positioned at the ends in the stacking direction of the adjacent resin blocks B. As shown in FIG. That is, the insulating layer 13 connects the conductive layers 36 located at the ends of the adjacent resin blocks B to each other.
  • the conductive layer 36 of the adjacent resin block B is located on the opposite side to the two resin layers 12 adjacent in the thickness direction of the conductive layer 36 among the plurality of resin layers 12, and the plurality of through conductors 33 They are a pair of conductive layers electrically connected to the penetrating conductors 33 penetrating the two adjacent resin layers 12 in the thickness direction.
  • the insulating layer 13 is positioned between the pair of conductive layers 36 .
  • the conductive layer 36 has fine uneven portions 36a on the surface where the insulating layer 13 is located, that is, the surface on the insulating layer 13 side.
  • the uneven portion 36a is formed on the surface of the conductive layer 36 on the insulating layer 13 side by texturing or the like. Since the conductive layer 36 has uneven portions 36 a on its surface, the adhesion of the insulating layer 13 to the conductive layer 36 can be improved.
  • the through conductor 33 is also electrically connected to the contact terminal side electrode 21 formed on the surface of the pitch conversion unit 1 on the inspection jig 2 side.
  • the penetrating conductors 33 are also electrically connected to device-side electrodes 22 formed on the surface of the pitch conversion unit 1 on the side of the inspection device, that is, on the side of the connection plate 3 .
  • the conductive vias 34 are electrically connected to the conductive layers 36 of the adjacent resin blocks B through the insulating layer 13 in the thickness direction. That is, the conductive vias 34 electrically connect the conductive layers 36 of the resin blocks B adjacent to each other. As a result, the conductive layers 36 of the adjacent resin blocks B are electrically connected to form an electric circuit within the pitch conversion unit 1 .
  • the insulating layer 13 provided on one of the adjacent resin blocks B is heated and fused to the other resin block B. Thereby, the adjacent resin blocks B are integrated through the insulating layer 13 .
  • the conductive via 34 is positioned within the via hole 13a penetrating the insulating layer 13 in the thickness direction.
  • the conductive vias 34 are made of a conductive paste filled in the via holes 13a.
  • This conductive paste contains metal particles as a filler and an organic substance as a binder.
  • the metal particles of the conductive paste contain, for example, tin.
  • the conductive paste becomes the conductive vias 34 by, for example, heat treatment.
  • the conductive vias 34 are joined to the conductive layers 36 of the adjacent resin blocks B. Although not shown, a reaction layer of copper and tin is formed at the junction between the conductive via 34 and the conductive layer 36 . Since the conductive via 34 and the conductive layer 36 are metal-bonded by this reaction layer, sufficient bonding strength between the conductive via 34 and the conductive layer 36 can be secured.
  • One conductive layer 36 of the conductive layers 36 of the adjacent resin blocks B has a concave portion 40 at the joint portion with the conductive via 34 .
  • the recess 40 has a shape in which the entire joint portion is recessed in the thickness direction of the conductive layer 36 . At least a part of the joint portion of the recess 40 may have a shape recessed in the thickness direction.
  • the recess 40 has a shape in which the entire joining portion of the conductive layer 36 with the conductive via 34 is recessed in the thickness direction.
  • the conductive layer 36 can be exposed over the entire joint portion of the conductive layer 36 with the conductive via 34 . Therefore, it is possible to more reliably prevent the surface of the conductive layer 36 from being covered with an insulating layer or the like at the joint portion. Therefore, since the conductive layer 36 and the conductive via 34 can be metal-bonded more firmly at the bonding portion, the bonding strength between the conductive layer 36 and the conductive via 34 can be further improved.
  • the recessed portion 40 has, for example, a circular shape when the conductive layer 36 is viewed in the stacking direction of the conductive layer 36 and the insulating layer 13 .
  • the concave portion 40 may have a shape other than a circular shape, such as an elliptical shape, a rectangular shape, or a polygonal shape, when the conductive layer 36 is viewed in the stacking direction.
  • the concave portion 40 may have the same shape and size as the via hole portion 13a of the conductive via 34 when the conductive layer 36 is viewed in the stacking direction, or may be different from the via hole portion 13a of the conductive via 34. It may have the same shape as the via hole 13a of the conductive via 34 and may be smaller than the via hole 13a.
  • the recess 40 includes a bottom surface 41 and side surfaces 42 .
  • the bottom surface 41 is, for example, a circular flat surface when the conductive layer 36 is viewed in the stacking direction.
  • the bottom surface 41 may have a shape other than a circular shape such as an elliptical shape, a rectangular shape, or a polygonal shape when the conductive layer 36 is viewed in the stacking direction.
  • the bottom surface 41 may be a curved surface, or may have a stepped deep groove, a spiral or annular groove, unevenness, or the like.
  • the side surface 42 extends in the direction normal to the surface of the conductive layer 36 on which the opening of the recess 40 is formed.
  • the side surfaces 42 may extend obliquely with respect to said surface.
  • the recess 40 has, for example, a cylindrical or truncated conical space inside.
  • the recess 40 has a cylindrical space inside, the radius of the bottom surface 41 of which is equal to the radius of the opening formed in the conductive layer 36 .
  • the recess 140 may have a cylindrical or frusto-conical space inside, the radius of the bottom surface 141 of which is smaller than the radius of the opening formed in the conductive layer 36 .
  • reference numeral 142 denotes the side surface of the recess 140
  • reference numeral 141a denotes the recessed portion of the bottom surface of the recess 140.
  • the thickness T1 of the conductive layer 36 at the bottom surface 41 of the recess 40 is smaller than the thickness of the conductive layer 36 other than the recess 40 .
  • the thickness T1 of the conductive layer 36 at the bottom surface 41 is smaller than the thickness T2 of the conductive layer 36 at the lowest portion of the uneven portion 36a of the conductive layer 36 .
  • a thickness T1 of the conductive layer 36 at the bottom surface 41 is the thickness of the conductive layer 36 at a portion of the bottom surface 41 where the recess 40 has the smallest depth.
  • the bottom surface 41 of the recess 40 is positioned inward in the thickness direction of the conductive layer 36 from the lowermost portion of the uneven portion 36a formed on the surface of the conductive layer 36 on the insulating layer 13 side.
  • the lowermost portion is a concave portion positioned most inward in the thickness direction of the uneven portion 36 a in the thickness direction of the conductive layer 36 .
  • the conductive layer 36 has the uneven portion 36 a on the surface located on the insulating layer 13 side for improving the adhesion with the insulating layer 13 .
  • the bottom surface 41 of the concave portion 40 is located inside the conductive layer 36 in the thickness direction of the lowermost portion of the concave/convex portion 36a.
  • the conductive layer 36 can be exposed on the bottom surface 41 of the recess 40 . Therefore, since the conductive layer 36 and the conductive via 34 can be metal-bonded more firmly in the concave portion 40, the bonding strength between the conductive layer 36 and the conductive via 34 can be further improved.
  • the bottom surface 41 has a bottom recessed portion 41a in the central portion when the conductive layer 36 is viewed in the stacking direction.
  • the bottom recessed portion 41 a is recessed in the thickness direction of the conductive layer 36 compared to other portions of the bottom surface 41 . That is, the recessed portion 40 has a bottom recessed portion 41 a that is recessed in the thickness direction more than other portions of the recessed portion 40 on the bottom surface 41 .
  • the amount of depression of the bottom surface depression portion 41 a is the largest at the central portion of the bottom surface 41 when the conductive layer 36 is viewed in the stacking direction, and decreases toward the outer periphery of the bottom surface 41 .
  • the thickness T3 of the conductive layer 36 at the central position of the bottom surface 41 as viewed in the stacking direction of the conductive layer 36 is the smallest among the thicknesses of the conductive layer 36 in the recess 40 .
  • the conductive vias 34 are formed by filling the via holes 13a of the insulating layer 13 with a metal paste or the like, the metal paste enters the bottom recessed portions 41a of the recesses 40 of the conductive layer 36. . Therefore, the conductive via 34 can be more strongly bonded to the bottom surface 41 of the conductive layer 36 . Further, since the bottom surface 41 has the bottom recessed portion 41a, the metal paste can be easily filled in the bottom recessed portion 41a. Therefore, with the above configuration, the conductive via 34 that is more strongly bonded to the bottom surface 41 of the conductive layer 36 can be easily formed.
  • the bottom recessed portion 41a is located in the central portion of the joint portion of the conductive layer 36 with the conductive via 34 when the conductive layer 36 is viewed in the stacking direction.
  • a side surface 42 of the recess 40 is a cylindrical surface in which the opening side of the recess 40 coincides with the bottom surface 41 when the conductive layer 36 is viewed in the stacking direction.
  • the side surface 42 has, for example, an annular shape when viewed in the stacking direction of the resin layers 12 .
  • the side surface 42 may have a shape other than an annular shape, such as an elliptical annular shape, a rectangular annular shape, or a polygonal annular shape when viewed in the stacking direction of the resin layers 12 .
  • the pitch conversion unit 1 includes a plurality of contact terminal side electrodes 21 electrically connected to a plurality of probes 121 that transmit and receive electrical signals to and from an inspection point to be inspected, and a semiconductor inspection device 100 that is electrically connected to the semiconductor inspection device 100 . It is a pitch conversion unit that has a plurality of device-side electrodes 22 that are physically connected, and converts the pitch of the plurality of contact terminal-side electrodes 21 into the pitch of the plurality of device-side electrodes.
  • the pitch conversion unit 1 includes a plurality of resin layers 12 laminated in the thickness direction, a plurality of through conductors 33 penetrating at least one resin layer 12 of the plurality of resin layers 12 in the thickness direction, and a plurality of resin layers 12 .
  • a penetrating conductor located on the opposite side of two resin layers 12 adjacent in the thickness direction among the layers 12 and penetrating the two adjacent resin layers 12 among the plurality of penetrating conductors 33 in the thickness direction.
  • a pair of conductive layers 36 electrically connected to the body 33, an insulating layer 13 positioned between the pair of conductive layers 36, and a pair of conductive layers penetrating through the insulating layer 13 in the thickness direction. and a conductive via 34 that is bonded to the layer 36 .
  • One conductive layer 36 of the pair of conductive layers 36 has a recess 40 recessed in the thickness direction in at least a part of the joint portion with the conductive via 34 .
  • the conductive layer 36 can be exposed in the portion where the concave portion 40 is formed in the joint portion of the conductive layer 36 with the conductive via 34 . Therefore, it is possible to prevent the surface of the conductive layer 36 from being covered with the insulating layer 13 or the like in the concave portion 40 . Therefore, since the conductive layer 36 and the conductive via 34 can be metal-bonded within the recess 40, the bonding strength between the conductive layer 36 and the conductive via 34 can be improved.
  • Resin block B has a plurality of resin layers 12 , a plurality of metal layers 32 , and a plurality of through conductors 33 . Therefore, when forming the resin block B, while laminating the plurality of resin layers 12 in the thickness direction, the plurality of metal layers 32 are formed between the resin layers 12, and the resin layers 12 are penetrated in the thickness direction. to form a plurality of through conductors 33 bonded to the metal layer 32 .
  • the method of forming the resin layer 12, the metal layer 32 and the penetrating conductor 33 in the resin block B is the same as the conventional method, so detailed description thereof will be omitted.
  • the conductive layer 36 which is part of the metal layer 32, is exposed on the joint side of the resin block B that is joined as described later.
  • the contact terminal side electrode 21 is exposed to the resin block B positioned at one end in the stacking direction among the plurality of resin blocks B constituting the pitch conversion unit 1 .
  • the device-side electrode 22 is exposed to the resin block B positioned at the other end in the stacking direction among the plurality of resin blocks B constituting the pitch conversion unit 1 .
  • an uneven portion 36a is formed on the surface of the exposed portion of the conductive layer 36 in the resin block B by texturing or the like.
  • the uneven portion 36a is formed on the surface of the exposed portion of the conductive layer 36, the adhesion of the insulating layer 13 to the conductive layer 36 is improved when the insulating layer 13 is formed on the resin block B as described later. can be done.
  • the insulating layer 13 is formed on the surface of the resin block B where the conductive layer 36 is exposed, and the PET layer 14 is formed on the insulating layer 13 .
  • the portions of the insulating layer 13 and the PET layer 14 located on the conductive layer 36 are irradiated with laser light ⁇ to form the holes 15 by laser processing.
  • Holes 15 include via holes 13 a formed in insulating layer 13 .
  • the step of forming the via holes 13a in the insulating layer 13 is the via hole forming step.
  • the laser light ⁇ is, for example, CO 2 laser light or UV laser light.
  • the inside of the hole 15 is irradiated with a laser beam ⁇ to partially remove the insulating layer 13 remaining at the bottom of the hole 15 .
  • the laser beam ⁇ has a power density sufficient to partially remove the conductive layer 36 .
  • recesses 40 are formed in the conductive layer 36 .
  • the recessed portion 40 is formed in a portion of the conductive layer 36 that overlaps the via hole portion 13a when the conductive layer 36 is viewed in the stacking direction. Since the shape of the concave portion 40 is as described above, detailed description thereof will be omitted.
  • the laser beam ⁇ is, for example, a green laser beam, a UV laser beam, an excimer laser beam, or the like.
  • a conductive via 34 is formed in which the via hole 13a of the insulating layer 13 is filled with the conductive paste.
  • the step of forming the conductive via 34 by filling the via hole 13a with a conductive paste, which is a conductive material, is the conductive via forming step.
  • another resin block B is superimposed on the insulating layer 13, and by heating the two resin blocks B to a temperature at which the insulating layer 13 is fused, It is possible to join the resin blocks B to each other. Also, the conductive vias 34 are metal-bonded to the conductive layers 36 of the two resin blocks B, respectively.
  • the pitch conversion unit 1 composed of a plurality of resin blocks B is formed.
  • the manufacturing method of the pitch conversion unit 1 of the present embodiment includes a via hole forming step of forming a via hole 13a constituting a part of the conductive via 34 in the insulating layer 13, and a step of forming the conductive layer 36 in the stacking direction.
  • a recess forming step of forming a recess 40 in a portion of the conductive layer 36 overlapping the via hole 13a and a conductive material filling the via hole 13a with a conductive material to form the conductive via 34 are performed. and a conductive via formation step.
  • the via hole 13a formed in the insulating layer 13 is filled with the conductive paste to form the conductive via 34 joined to the conductive layer 36, and the conductive layer 36 is viewed in the stacking direction.
  • the pitch conversion unit 1 is obtained in which the recesses 40 are formed in the portions of the conductive layer 36 overlapping the via holes 13a.
  • the conductive layer 36 can be exposed in the portion where the concave portion 40 is formed in the joint portion of the conductive layer 36 with the conductive via 34 . Therefore, it is possible to prevent the surface of the conductive layer 36 from being covered with the insulating layer 13 or the like in the concave portion 40 . Therefore, since the conductive layer 36 and the conductive via 34 can be metal-bonded within the recess 40, the bonding strength between the conductive layer 36 and the conductive via 34 can be improved.
  • the recess 40 is formed by irradiating a portion of the conductive layer 36 that overlaps the via hole 13a with the laser beam ⁇ when the conductive layer 36 is viewed in the stacking direction.
  • the concave portion 40 can be easily formed in the conductive layer 36 in the via hole forming step. Therefore, the pitch conversion unit 1 having the configuration of this embodiment can be easily obtained.
  • the pitch conversion unit is not limited to the semiconductor inspection device, and may be used, for example, in a substrate inspection device that inspects a substrate.
  • the board to be inspected by the board inspection apparatus may be a ceramic multilayer wiring board, a glass epoxy board, a flexible board, a ceramic multilayer wiring board, a package board for a semiconductor package, an interposer board, a film carrier, or the like. It may be an electrode plate for a display such as a liquid crystal display, an EL (Electric-Luminescence) display, a touch panel display, an electrode plate for a touch panel, or the like, or it may be another type of substrate. good.
  • the pitch conversion unit 1 is formed by bonding a plurality of resin blocks B via the insulating layer 13 .
  • the pitch conversion unit may be formed by laminating a plurality of resin layers as long as it has a configuration having conductive vias.
  • the pitch conversion unit may include an insulating layer. In this case, the configuration of this embodiment may be applied to the junction between the conductive via and the conductive layer.
  • the resin block B has three resin layers 12 in the example shown in FIG.
  • the insulating block may have two or less resin layers, or may have four or more resin layers.
  • the pitch conversion unit 1 has three resin blocks B in the example shown in FIG.
  • the pitch conversion unit may have two or less resin blocks, or four or more resin blocks.
  • the bottom surfaces 41 and 141 of the recesses 40 and 140 have bottom recess portions 41a and 141a in the central portion when the conductive layer 36 is viewed in the stacking direction.
  • the bottom surface may have a recessed portion on the bottom surface other than the central portion when viewed in the stacking direction of the conductive layers.
  • the bottom recessed portion may be provided at any position of the joint portion of the conductive layer with the conductive via when the conductive layer is viewed in the stacking direction.
  • the bottom surface may not have a bottom surface recess.
  • the bottom surface may have a convex portion.
  • the recess amount of the bottom recess portion 41a is the largest at the central portion of the bottom surface 41 when the conductive layer 36 is viewed in the stacking direction, and becomes smaller toward the outer peripheral side of the bottom surface 41.
  • the shape of the bottom recessed portion may be any shape as long as it is recessed in the thickness direction compared to other portions of the bottom surface of the recess.
  • the side surface 42 of the recess 40 is a cylindrical surface in which the opening side of the recess 40 is the same as the bottom surface 41 when the conductive layer 36 is viewed in the stacking direction.
  • the side surface of the recess may be a tapered surface in which the opening side of the recess is positioned radially outward or radially inward from the bottom surface when the conductive layers are viewed in the stacking direction.
  • the side surface of the recess may be polygonal when the conductive layers are viewed in the stacking direction.
  • a side surface of the recess may include a plurality of flat surfaces.
  • the laser beam ⁇ is used when forming the recesses 40 in the conductive layer 36 .
  • the recesses may be formed mechanically in the conductive layer using a tool or the like. That is, any processing method other than laser processing may be used as long as the processing method is capable of removing the insulating layer on the conductive layer and exposing the conductive layer at the bottom surface of the via hole.
  • the conductive layer 36 has fine uneven portions 36a on the surface on the insulating layer 13 side.
  • the conductive layer does not have to have unevenness on the surface on the insulating layer side.
  • the present invention includes a plurality of contact terminal side electrodes electrically connected to a plurality of contact terminals for transmitting and receiving electric signals to and from an inspection point to be inspected, and a plurality of device side electrodes electrically connected to an inspection device. and a pitch conversion unit that converts the pitch of the plurality of contact terminal side electrodes into the pitch of the plurality of device side electrodes.
  • connection plate 1 pitch conversion unit 2 inspection jig 3 connection plate 4 connection member 11 substrate 12 resin layer 13 insulation layer 13a via hole 14 PET layer 21 contact terminal side electrode 22 device side electrode 31 conductor 32 metal layer 33 through conductor 34 Conductive via 36 Conductive layer 36a Uneven portions 40, 140 Concave portions 41, 141 Bottom surfaces 41a, 141a Bottom recessed portions 42, 142 Side surface 100 Semiconductor inspection device 104 Inspection unit 106 Sample table 106a Mounting unit 108 Inspection processing unit 121 Probe 122 Penetrating member 131 cable 132 connection terminal B resin block DUT semiconductor wafer

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Abstract

Provided is a pitch conversion unit for converting the pitch of a plurality of contact-terminal-side electrodes to the pitch of a plurality of device-side electrodes, the pitch conversion unit being configured such that the joining strength between an electroconductive layer and an electroconductive via penetrating through an insulation layer in a thickness direction can be improved. This pitch conversion unit 1 has: a plurality of resin layers 12 laminated in a thickness direction; a plurality of penetrating electroconductive bodies 33 that penetrate through the resin layers 12 in the thickness direction; a pair of electroconductive layers 36 positioned on facing sides of two resin layers 12 that are adjacent in the thickness direction, the electroconductive layers 36 being electrically connected to the penetrating electroconductive bodies 33 that penetrate through each of the two adjacent resin layers in the thickness direction, among the plurality of penetrating electroconductive bodies 33; an insulation layer 13 positioned between the pair of electroconductive layers 36; and an electroconductive via 34 penetrating through the insulation layer 13 in the thickness direction, end sections of the electroconductive via 34 being joined to the pair of electroconductive layers 36. One of the pair of electroconductive layers 36 has, in at least one section of the portion joined to the electroconductive via 34, a recess 40 that is sunken in the thickness direction.

Description

ピッチ変換ユニット及びその製造方法Pitch conversion unit and manufacturing method thereof
 本発明は、ピッチ変換ユニット及びその製造方法に関する。 The present invention relates to a pitch conversion unit and its manufacturing method.
 検査対象の検査点に対して電気信号を授受する複数の接触端子に電気的に接続される複数の接触端子側電極と、検査装置に電気的に接続される複数の装置側電極とを有し、前記複数の接触端子側電極のピッチを前記複数の装置側電極のピッチに変換するピッチ変換ユニットが知れている。このようなピッチ変換ユニットとして、例えば、特許文献1に開示されているように、セラミックス基板と、配線層と、薄膜層とを備えたスペーストランスフォーマが知られている。 It has a plurality of contact terminal-side electrodes electrically connected to a plurality of contact terminals for transmitting and receiving electric signals to and from an inspection point to be inspected, and a plurality of device-side electrodes electrically connected to an inspection device. , a pitch conversion unit for converting the pitch of the plurality of contact terminal side electrodes into the pitch of the plurality of device side electrodes. As such a pitch conversion unit, for example, a space transformer including a ceramic substrate, a wiring layer, and a thin film layer is known, as disclosed in Patent Document 1.
 前記セラミックス基板は、少なくとも一層のセラミックス基板内配線層を内包している。前記セラミックス基板には、導電路が前記セラミックス基板内配線層を貫通するように設けられている。前記セラミックス基板の一面及び反対面には、前記導電路に接続される配線層が設けられている。 The ceramic substrate includes at least one wiring layer inside the ceramic substrate. A conductive path is provided in the ceramic substrate so as to penetrate the wiring layer in the ceramic substrate. Wiring layers connected to the conductive path are provided on one surface and the opposite surface of the ceramic substrate.
 前記セラミックス基板の一面に位置する前記配線層は、プローブの配置パターンに対応した配線パターンを有する。前記セラミックス基板の反対面に位置する前記配線層は、伸縮可能なポゴピンユニットを介して、プリント回路基板と接続されている。このプリント回路基板は、検査機側の試験回路に接続可能なプリント配線を有する。 The wiring layer located on one surface of the ceramic substrate has a wiring pattern corresponding to the arrangement pattern of the probes. The wiring layer located on the opposite side of the ceramic substrate is connected to the printed circuit board via an extendable pogo pin unit. The printed circuit board has printed wiring that can be connected to test circuitry on the inspection machine.
特開2019-178961号公報JP 2019-178961 A
 上述の特許文献1に開示されるようなスペーストランスフォーマでは、セラミック基板に、その厚み方向に貫通して配線層同士を電気的に接続する導電路等を形成する必要がある。このような導電路として、一般的に、基板に厚み方向のビア用穴部を形成して該ビア用穴部内に導電性材料を充填することにより、前記配線層を構成する導電層に電気的に接続される導電性ビアを形成する方法が知られている。 In the space transformer disclosed in the above-mentioned Patent Document 1, it is necessary to form a conductive path or the like that penetrates the ceramic substrate in the thickness direction and electrically connects the wiring layers. Such a conductive path is generally formed by forming a via hole in the substrate in the thickness direction and filling the via hole with a conductive material to electrically connect the conductive layer constituting the wiring layer. Methods are known for forming conductive vias connected to the .
 ところで、一般的には、基板などの絶縁層に前記ビア用穴部を形成する際には、レーザ光等を用いて、前記絶縁層の一部を加工することにより、前記導電層を露出させる穴を形成する。この場合、前記レーザ光によって形成された穴の底面等に、前記絶縁層の一部が残る場合がある。すなわち、前記ビア用穴部の底面では、前記導電層が露出していない場合がある。このような場合には、前記ビア用穴部内に導電性材料を充填して形成された前記導電性ビアと前記導電層との接合強度が十分に得られない可能性がある。 By the way, generally, when forming the via holes in an insulating layer such as a substrate, the conductive layer is exposed by processing a part of the insulating layer using a laser beam or the like. form a hole. In this case, part of the insulating layer may remain on the bottom surface of the hole formed by the laser beam. That is, the conductive layer may not be exposed at the bottom surface of the via hole. In such a case, there is a possibility that sufficient bonding strength cannot be obtained between the conductive via formed by filling the via hole with a conductive material and the conductive layer.
 本発明の目的は、複数の接触端子側電極のピッチを複数の装置側電極のピッチに変換するピッチ変換ユニットにおいて、絶縁層を厚み方向に貫通する導電性ビアと導電層との接合強度を向上可能な構成を提供することにある。 An object of the present invention is to improve the bonding strength between a conductive via penetrating an insulating layer in the thickness direction and a conductive layer in a pitch conversion unit that converts the pitch of a plurality of contact terminal side electrodes to the pitch of a plurality of device side electrodes. It is to provide a possible configuration.
 本発明の一実施形態に係るピッチ変換ユニットは、検査対象の検査点に対して電気信号を授受する複数の接触端子に電気的に接続される複数の接触端子側電極と、検査装置に電気的に接続される複数の装置側電極とを有し、前記複数の接触端子側電極のピッチを前記複数の装置側電極のピッチに変換するピッチ変換ユニットである。このピッチ変換ユニットは、厚み方向に積層される複数の樹脂層と、前記複数の樹脂層のうち少なくとも一つの樹脂層を前記厚み方向に貫通する複数の貫通導電体と、前記複数の樹脂層のうち前記厚み方向に隣り合う2つの樹脂層に対して対向側に位置し、前記複数の貫通導電体のうち前記隣り合う2つの樹脂層をそれぞれ前記厚み方向に貫通する貫通導電体に電気的に接続される一対の導電層と、前記一対の導電層の間に位置する絶縁層と、前記絶縁層を前記厚み方向に貫通して、端部が前記一対の導電層に接合されている導電性ビアと、を有する。前記一対の導電層のうち一方の導電層は、前記導電性ビアとの接合部分の少なくとも一部に、前記厚み方向に窪んだ凹部を有する。 A pitch conversion unit according to an embodiment of the present invention includes: a plurality of contact terminal side electrodes electrically connected to a plurality of contact terminals for transmitting and receiving electric signals to and from an inspection point to be inspected; and a plurality of device-side electrodes connected to each other, the pitch conversion unit converting the pitch of the plurality of contact terminal-side electrodes into the pitch of the plurality of device-side electrodes. This pitch conversion unit includes: a plurality of resin layers laminated in a thickness direction; a plurality of through conductors penetrating through at least one resin layer among the plurality of resin layers in the thickness direction; The through conductor located on the opposite side to the two resin layers adjacent in the thickness direction among the plurality of through conductors and penetrating the two adjacent resin layers in the thickness direction respectively. a pair of conductive layers to be connected; an insulating layer positioned between the pair of conductive layers; and a via. One conductive layer of the pair of conductive layers has a recess recessed in the thickness direction in at least a portion of a joint portion with the conductive via.
 本発明の一実施形態に係るピッチ変換ユニットの製造方法は、上述の構成を有するピッチ変換ユニットの製造方法である。この製造方法は、前記絶縁層に前記導電性ビアの一部を構成するビア用穴部を形成するビア用穴部形成工程と、前記導電層を前記導電層及び前記絶縁層の積層方向に見て、前記導電層において前記ビア用穴部と重なる部分に、前記凹部を形成する凹部形成工程と、前記ビア用穴部内に導電材料を充填することにより、前記導電性ビアを形成する導電性ビア形成工程と、を有する。 A method of manufacturing a pitch conversion unit according to an embodiment of the present invention is a method of manufacturing a pitch conversion unit having the above configuration. This manufacturing method includes a via hole forming step of forming a via hole forming a part of the conductive via in the insulating layer, and a step of forming the via hole in the insulating layer; a recess forming step of forming the recess in a portion of the conductive layer overlapping the via hole; and a conductive via forming the conductive via by filling a conductive material in the via hole. and a forming step.
 本発明の一実施形態に係るピッチ変換ユニットによれば、複数の接触端子側電極のピッチを複数の装置側電極のピッチに変換するピッチ変換ユニットにおいて、絶縁層を厚み方向に貫通する導電性ビアと導電層との接合強度を向上可能な構成を実現することができる。 According to the pitch conversion unit according to one embodiment of the present invention, in the pitch conversion unit for converting the pitch of the plurality of contact terminal side electrodes to the pitch of the plurality of device side electrodes, the conductive vias penetrating the insulating layer in the thickness direction It is possible to realize a configuration capable of improving the bonding strength between the substrate and the conductive layer.
図1は、実施形態に係るピッチ変換ユニットを備えた半導体検査装置の概略構成を示す概念図である。FIG. 1 is a conceptual diagram showing a schematic configuration of a semiconductor inspection device provided with a pitch conversion unit according to an embodiment. 図2は、検査部の概略構成を示すとともに、検査治具を断面で示す部分断面図である。FIG. 2 is a partial cross-sectional view showing the schematic configuration of the inspection unit and showing the inspection jig in cross section. 図3は、ピッチ変換ユニットの構成の一例を模式的に示す断面図である。FIG. 3 is a cross-sectional view schematically showing an example of the configuration of the pitch conversion unit. 図4Aは、図3に示すピッチ変換ユニットの一部を拡大して示す部分拡大断面図である。4A is a partially enlarged sectional view showing an enlarged part of the pitch conversion unit shown in FIG. 3. FIG. 図4Bは、導電層に、底面の半径が前記導電層に形成された開口の半径よりも小さい円柱状の空間を形成する凹部が形成された、ピッチ変換ユニットの一部を拡大して示す部分拡大断面図である。FIG. 4B is an enlarged portion showing a part of the pitch conversion unit, in which the conductive layer is formed with a concave portion forming a cylindrical space whose bottom radius is smaller than the radius of the opening formed in the conductive layer; It is an expanded sectional view. 図5は、ピッチ変換ユニットの製造方法の一例を示す断面図である。FIG. 5 is a cross-sectional view showing an example of a method of manufacturing the pitch conversion unit. 図6は、ピッチ変換ユニットの製造方法の一例を示す断面図である。FIG. 6 is a cross-sectional view showing an example of a method of manufacturing the pitch conversion unit. 図7は、ピッチ変換ユニットの製造方法の一例を示す断面図である。FIG. 7 is a cross-sectional view showing an example of a method of manufacturing the pitch conversion unit. 図8は、ピッチ変換ユニットの製造方法の一例を示す断面図である。FIG. 8 is a cross-sectional view showing an example of a method of manufacturing the pitch conversion unit. 図9は、ピッチ変換ユニットの製造方法の一例を示す断面図である。FIG. 9 is a cross-sectional view showing an example of a method of manufacturing the pitch conversion unit. 図10は、ピッチ変換ユニットの製造方法の一例を示す断面図である。FIG. 10 is a cross-sectional view showing an example of a method of manufacturing the pitch conversion unit.
 以下、図面を参照し、本発明の実施の形態を詳しく説明する。なお、図中の同一または相当部分については同一の符号を付してその説明は繰り返さない。また、各図中の構成部材の寸法は、実際の構成部材の寸法及び各構成部材の寸法比率等を忠実に表したものではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated. Also, the dimensions of the constituent members in each drawing do not faithfully represent the actual dimensions of the constituent members, the dimensional ratios of the respective constituent members, and the like.
 なお、以下の説明において、“固定”、“接続”及び“取り付ける”等(以下、固定等)の表現は、部材同士が直接、固定等されている場合だけでなく、他の部材を介して固定等されている場合も含む。すなわち、以下の説明において、固定等の表現には、部材同士の直接的及び間接的な固定等の意味が含まれる。 In the following description, expressions such as "fixed", "connected", and "attached" (hereinafter referred to as "fixed") are used not only when members are directly fixed to each other, but also when other members are used. It also includes cases where it is fixed. That is, in the following description, expressions such as fixing include meanings such as direct and indirect fixing between members.
 本発明に係るピッチ変換ユニットは、検査対象にプローブを当接させて電流を流すことにより、検査対象の電気的検査を行う検査装置に用いることができる。以下で説明する実施形態では、検査対象としての半導体ウェハの電気的検査を行う半導体検査装置を例に挙げて説明する。 The pitch conversion unit according to the present invention can be used in an inspection device that electrically inspects an object to be inspected by bringing a probe into contact with the object to be inspected and causing a current to flow. In the embodiments described below, a semiconductor inspection apparatus for electrically inspecting a semiconductor wafer to be inspected will be described as an example.
(半導体検査装置)
 図1は、本発明の実施形態に係るピッチ変換ユニット1を有する半導体検査装置100の概略構成を示す斜視図である。半導体検査装置100は、検査対象の一例である半導体ウェハDUTに形成された回路を検査するための検査装置である。
(Semiconductor inspection equipment)
FIG. 1 is a perspective view showing a schematic configuration of a semiconductor inspection apparatus 100 having a pitch conversion unit 1 according to an embodiment of the invention. A semiconductor inspection apparatus 100 is an inspection apparatus for inspecting a circuit formed on a semiconductor wafer DUT, which is an example of an object to be inspected.
 半導体ウェハDUTでは、例えばシリコンなどの半導体基板に、複数の半導体チップに対応する回路が形成されている。なお、前記検査対象は、例えば、半導体チップ、CSP(Chip size package)、半導体素子(IC:Integrated Circuit)等の電子部品である。 In the semiconductor wafer DUT, circuits corresponding to a plurality of semiconductor chips are formed on a semiconductor substrate such as silicon. The inspection target is, for example, an electronic component such as a semiconductor chip, a CSP (Chip size package), or a semiconductor element (IC: Integrated Circuit).
 図1に示す半導体検査装置100は、検査部104と、試料台106と、検査処理部108とを備えている。  The semiconductor inspection apparatus 100 shown in FIG.
 試料台106は、上面に、半導体ウェハDUTが搭載される載置部106aを有する。試料台106は、検査対象の半導体ウェハDUTを所定位置に固定可能である。載置部106aは、昇降可能である。具体的には、載置部106aは、試料台106内に収容された半導体ウェハDUTを検査位置に上昇可能であり、検査済みの半導体ウェハDUTを試料台106内に格納可能である。また、載置部106aは、例えば半導体ウェハDUTを回転させて、オリエンテーション・フラットを所定の方向に向けることができる。 The sample table 106 has a mounting portion 106a on which the semiconductor wafer DUT is mounted on its upper surface. The sample table 106 can fix the semiconductor wafer DUT to be inspected at a predetermined position. The mounting portion 106a can be raised and lowered. Specifically, the mounting section 106 a can raise the semiconductor wafer DUT accommodated in the sample stage 106 to the inspection position, and store the inspected semiconductor wafer DUT in the sample stage 106 . Further, the mounting section 106a can rotate the semiconductor wafer DUT, for example, to orient the orientation flat in a predetermined direction.
 検査処理部108は、特に図示しないが、例えば、電源回路、電圧形、電流計及びマイクロコンピュータ等を有する。検査処理部108は、図示しない駆動機構を制御することにより検査部104を移動させて位置決めし、半導体ウェハDUTの各検査点に、検査部104の各プローブ121を接触させる。これにより、各検査点と検査部104とが電気的に接続される。 Although not shown, the inspection processing unit 108 has, for example, a power supply circuit, a voltage source, an ammeter, a microcomputer, and the like. The inspection processing unit 108 moves and positions the inspection unit 104 by controlling a driving mechanism (not shown), and brings each probe 121 of the inspection unit 104 into contact with each inspection point of the semiconductor wafer DUT. Thereby, each inspection point and the inspection section 104 are electrically connected.
 検査処理部108は、上述の状態で各プローブ121を介して半導体ウェハDUTの各検査点に、検査用の交流の電流または電圧を供給し、各プローブ121から得られた電圧信号または電流信号に基づいて、例えば回路パターンの断線及び短絡等の半導体ウェハDUTの検査を実行する。検査処理部108は、交流の電流または電圧を各検査点に供給することによって、各プローブ121から得られた電圧信号または電流信号に基づいて、検査対象のインピーダンスを測定してもよい。 The inspection processing unit 108 supplies an alternating current or voltage for inspection to each inspection point of the semiconductor wafer DUT via each probe 121 in the above-described state, and the voltage signal or current signal obtained from each probe 121 Based on this, the semiconductor wafer DUT is inspected for, for example, circuit pattern breaks and short circuits. The test processing unit 108 may measure the impedance of the test object based on the voltage signal or current signal obtained from each probe 121 by supplying alternating current or voltage to each test point.
(検査部)
 図2は、検査部104の概略構成を示す部分断面図である。図2では、説明のために、検査部104のうち検査治具2を断面で示す。なお、図2に示す構成は、検査部104の一例である。検査部104の構成は、図2に示す構成に限定されない。
(Inspection unit)
FIG. 2 is a partial cross-sectional view showing a schematic configuration of the inspection unit 104. As shown in FIG. In FIG. 2, the inspection jig 2 of the inspection unit 104 is shown in cross section for explanation. Note that the configuration shown in FIG. 2 is an example of the inspection unit 104 . The configuration of the inspection unit 104 is not limited to the configuration shown in FIG.
 検査部104は、検査治具2と、接続プレート3とを有する。検査治具2は、半導体ウェハDUTに複数のプローブ121を接触させて検査するための治具である。検査部104は、例えば、いわゆるプローブカードである。 The inspection unit 104 has an inspection jig 2 and a connection plate 3 . The inspection jig 2 is a jig for inspecting the semiconductor wafer DUT by bringing a plurality of probes 121 into contact therewith. The inspection unit 104 is, for example, a so-called probe card.
 検査治具2は、ピッチ変換ユニット1と、複数のプローブ121(接触端子)と、複数のプローブ121を、先端部を半導体ウェハDUTへ向けた状態で保持する貫通部材122とを有する。 The inspection jig 2 has a pitch conversion unit 1, a plurality of probes 121 (contact terminals), and a penetrating member 122 that holds the plurality of probes 121 with their tips directed toward the semiconductor wafer DUT.
 半導体ウェハDUTには、複数のチップが形成されている。各チップには、複数のパッド及びバンプ等が形成されている。前記複数のパッド及びバンプ等は、検査点として設定されている。検査治具2は、半導体ウェハDUTに形成された複数のチップのうち一部の領域(例えば図1にハッチングで示す領域、以下、検査領域と称する)内の検査点に対応する複数のプローブ121を有する。プローブ121は、貫通部材122を貫通している。プローブ121及び貫通部材122の構成は、従来と同様であるため、詳しい説明を省
略する。
A plurality of chips are formed on the semiconductor wafer DUT. A plurality of pads, bumps, and the like are formed on each chip. The plurality of pads, bumps, etc. are set as inspection points. The inspection jig 2 includes a plurality of probes 121 corresponding to inspection points within a partial area (for example, the hatched area in FIG. 1, hereinafter referred to as an inspection area) of the plurality of chips formed on the semiconductor wafer DUT. have The probe 121 penetrates through the penetrating member 122 . Since the structures of the probe 121 and the penetrating member 122 are the same as those of the conventional art, detailed description thereof will be omitted.
 接続プレート3は、ピッチ変換ユニット1を着脱可能である。接続プレート3は、ピッチ変換ユニット1と電気的に接続される図示しない複数の電極を有する。接続プレート3の各電極は、例えば、ケーブル131及び接続端子132等によって、検査処理部108と電気的に接続されている。 The connection plate 3 is detachable with the pitch conversion unit 1 . The connection plate 3 has a plurality of electrodes (not shown) electrically connected to the pitch conversion unit 1 . Each electrode of the connection plate 3 is electrically connected to the inspection processing section 108 by, for example, a cable 131, a connection terminal 132, and the like.
 ピッチ変換ユニット1は、プローブ121相互間の間隔を、接続プレート3の電極ピッチに変換するためのピッチ変換部材である。ピッチ変換ユニット1は、一方の面に、検査治具2の複数のプローブ121と接触して導通する複数の接触端子側電極21を有する。ピッチ変換ユニット1は、他方の面に、接続部材4を介して接続プレート3の図示しない電極と接続されて導通する複数の装置側電極22を有する。ピッチ変換ユニット1の詳しい構成は、後述する。 The pitch conversion unit 1 is a pitch conversion member for converting the spacing between the probes 121 to the electrode pitch of the connection plate 3 . The pitch conversion unit 1 has, on one surface, a plurality of contact terminal side electrodes 21 that are in contact with and conduct with a plurality of probes 121 of the inspection jig 2 . The pitch conversion unit 1 has a plurality of device-side electrodes 22 on the other surface that are electrically connected to electrodes (not shown) of the connection plate 3 via the connection member 4 . A detailed configuration of the pitch conversion unit 1 will be described later.
 接続部材4は、ピッチ変換ユニット1の装置側電極22と接続プレート3の電極との間に位置し、両者に対して弾性接触している。接続部材4は、ピッチ変換ユニット1の装置側電極22と接続プレート3の電極とを電気的に接続する。接続部材4は、いわゆるポゴピンユニットである。 The connection member 4 is positioned between the device-side electrode 22 of the pitch conversion unit 1 and the electrode of the connection plate 3 and is in elastic contact with both. The connection member 4 electrically connects the device-side electrode 22 of the pitch conversion unit 1 and the electrode of the connection plate 3 . The connection member 4 is a so-called pogo pin unit.
 なお、発明の理解を容易にする観点から、図1は、半導体検査装置100の構成の一例を概略的及び概念的に示した説明図であり、図2は、検査部104の構成の一例を概略的及び概念的に示した説明図である。図1及び図2では、プローブ121の本数、密度及び配置、検査部104の形状、大きさの比率等についても、簡略化及び概念化して記載している。また、図1では、例えば、プローブ121の配置の理解を容易にする観点で、一般的な半導体検査装置よりも検査領域を大きく強調して記載している。前記検査領域は、図1に示す領域よりも小さくてもよいし、図1に示す領域よりも大きくてもよい。 From the viewpoint of facilitating understanding of the invention, FIG. 1 is an explanatory diagram schematically and conceptually showing an example of the configuration of the semiconductor inspection apparatus 100, and FIG. It is an explanatory view schematically and conceptually shown. In FIGS. 1 and 2, the number, density and arrangement of the probes 121, the shape of the inspection section 104, the size ratio, etc. are also illustrated in a simplified and conceptualized manner. In addition, in FIG. 1, for example, from the viewpoint of facilitating understanding of the arrangement of the probes 121, the inspection area is emphasized more than that of a general semiconductor inspection apparatus. The inspection area may be smaller than the area shown in FIG. 1 or larger than the area shown in FIG.
(ピッチ変換ユニット)
 次に、ピッチ変換ユニット1の構成について、図2から図4Aを用いて説明する。図3は、ピッチ変換ユニット1の構成を模式的に示す断面図である。図4Aは、ピッチ変換ユニット1の一部を拡大して示す部分拡大断面図である。
(pitch conversion unit)
Next, the configuration of the pitch conversion unit 1 will be described with reference to FIGS. 2 to 4A. FIG. 3 is a cross-sectional view schematically showing the configuration of the pitch conversion unit 1. As shown in FIG. FIG. 4A is a partially enlarged sectional view showing an enlarged part of the pitch conversion unit 1. FIG.
 図2及び図3に示すように、ピッチ変換ユニット1は、樹脂製の基板11と、接触端子側電極21と、装置側電極22と、基板11内に位置する導電体31とを有する。 As shown in FIGS. 2 and 3, the pitch conversion unit 1 has a substrate 11 made of resin, a contact terminal side electrode 21, a device side electrode 22, and a conductor 31 positioned inside the substrate 11.
 基板11は、複数の樹脂層12と、複数の絶縁層13とを有する。樹脂層12は、プリプレグ等のエポキシ系樹脂、ポリイミド系樹脂などによって構成されている。絶縁層13は、例えば、プリプレグ、ボンディングシートなどによって構成されている。例えば、複数の樹脂層12及び複数の絶縁層13は、厚み方向に積層されている。詳しくは、図3に示すように、厚み方向に積層された複数の樹脂層12からなる樹脂ブロックB同士の間に、絶縁層13が位置する。 The substrate 11 has multiple resin layers 12 and multiple insulating layers 13 . The resin layer 12 is made of epoxy resin such as prepreg, polyimide resin, or the like. The insulating layer 13 is made of, for example, a prepreg, a bonding sheet, or the like. For example, the multiple resin layers 12 and the multiple insulating layers 13 are laminated in the thickness direction. More specifically, as shown in FIG. 3, insulating layers 13 are positioned between resin blocks B composed of a plurality of resin layers 12 laminated in the thickness direction.
 詳しくは後述するが、各樹脂ブロックBは、複数の樹脂層12を積層形成することによって形成される。樹脂ブロックB同士は、絶縁層13を介して接合されている。 Although details will be described later, each resin block B is formed by laminating a plurality of resin layers 12 . The resin blocks B are bonded to each other via the insulating layer 13 .
 各樹脂ブロックBを構成する樹脂層12内及び樹脂ブロックB同士を接合する絶縁層13内には、導電性を有する導電体31が形成されている。導電体31は、複数の金属層32と、複数の貫通導電体33と、複数の導電性ビア34とを含む。 Inside the resin layer 12 forming each resin block B and inside the insulating layer 13 joining the resin blocks B together, a conductor 31 having conductivity is formed. The conductor 31 includes multiple metal layers 32 , multiple through conductors 33 , and multiple conductive vias 34 .
 複数の金属層32は、各樹脂ブロックB内に、樹脂層12に沿って面状に形成されている。複数の貫通導電体33は、各樹脂ブロックB内で、樹脂層12を厚み方向に貫通して金属層32同士を厚み方向に電気的に接続する。すなわち、金属層32と貫通導電体33とは、各樹脂ブロックB内で電気的に接続されている。金属層32及び貫通導電体33は、例えば、銅によって構成されている。金属層32及び貫通導電体33は、例えば、メッキ処理によって形成される。 A plurality of metal layers 32 are formed planarly along the resin layer 12 in each resin block B. In each resin block B, the plurality of through conductors 33 penetrate the resin layer 12 in the thickness direction and electrically connect the metal layers 32 in the thickness direction. That is, the metal layer 32 and the penetrating conductor 33 are electrically connected within each resin block B. As shown in FIG. The metal layer 32 and the penetrating conductor 33 are made of copper, for example. The metal layer 32 and the penetrating conductor 33 are formed by plating, for example.
 複数の金属層32は、樹脂層12の積層方向において樹脂ブロックBの端部に位置する導電層36を有する。導電層36は、樹脂層12を貫通する貫通導電体33と電気的に接続されている。導電層36において樹脂ブロックBの端部に位置する面は、絶縁層13によって覆われている。よって、隣り合う樹脂ブロックBにおいて前記積層方向の端部に位置する導電層36の間には、絶縁層13が位置する。すなわち、絶縁層13は、隣り合う樹脂ブロックBの端部に位置する導電層36同士を接続している。なお、隣り合う樹脂ブロックBの導電層36が、複数の樹脂層12のうち導電層36の厚み方向に隣り合う2つの樹脂層12に対して対向側に位置し、複数の貫通導電体33のうち前記隣り合う2つの樹脂層12をそれぞれ前記厚み方向に貫通する貫通導電体33に電気的に接続される一対の導電層である。よって、絶縁層13は、一対の導電層36の間に位置する。 The plurality of metal layers 32 have conductive layers 36 located at the ends of the resin blocks B in the stacking direction of the resin layers 12 . The conductive layer 36 is electrically connected to the penetrating conductor 33 penetrating the resin layer 12 . The surface of the conductive layer 36 located at the end of the resin block B is covered with the insulating layer 13 . Therefore, the insulating layer 13 is positioned between the conductive layers 36 positioned at the ends in the stacking direction of the adjacent resin blocks B. As shown in FIG. That is, the insulating layer 13 connects the conductive layers 36 located at the ends of the adjacent resin blocks B to each other. Note that the conductive layer 36 of the adjacent resin block B is located on the opposite side to the two resin layers 12 adjacent in the thickness direction of the conductive layer 36 among the plurality of resin layers 12, and the plurality of through conductors 33 They are a pair of conductive layers electrically connected to the penetrating conductors 33 penetrating the two adjacent resin layers 12 in the thickness direction. Thus, the insulating layer 13 is positioned between the pair of conductive layers 36 .
 図4Aに示すように、導電層36は、絶縁層13が位置する面、すなわち絶縁層13側の面に、微小な凹凸部36aを有する。凹凸部36aは、テクスチャリング等によって、導電層36の絶縁層13側の面に形成される。導電層36が表面に凹凸部36aを有することにより、導電層36に対する絶縁層13の密着性を向上することができる。 As shown in FIG. 4A, the conductive layer 36 has fine uneven portions 36a on the surface where the insulating layer 13 is located, that is, the surface on the insulating layer 13 side. The uneven portion 36a is formed on the surface of the conductive layer 36 on the insulating layer 13 side by texturing or the like. Since the conductive layer 36 has uneven portions 36 a on its surface, the adhesion of the insulating layer 13 to the conductive layer 36 can be improved.
 図3に示すように、貫通導電体33は、ピッチ変換ユニット1の検査治具2側の面に形成された接触端子側電極21にも電気的に接続されている。また、貫通導電体33は、ピッチ変換ユニット1の検査装置側、すなわち接続プレート3側の面に形成された装置側電極22にも電気的に接続されている。 As shown in FIG. 3, the through conductor 33 is also electrically connected to the contact terminal side electrode 21 formed on the surface of the pitch conversion unit 1 on the inspection jig 2 side. The penetrating conductors 33 are also electrically connected to device-side electrodes 22 formed on the surface of the pitch conversion unit 1 on the side of the inspection device, that is, on the side of the connection plate 3 .
 図3及び図4Aに示すように、導電性ビア34は、絶縁層13を厚み方向に貫通して、隣り合う樹脂ブロックBの導電層36に電気的に接続されている。すなわち、導電性ビア34は、隣り合う樹脂ブロックBの導電層36同士を電気的に接続する。これにより、隣り合う樹脂ブロックBにおいて、導電層36が電気的に接続されてピッチ変換ユニット1内に電気回路が形成される。 As shown in FIGS. 3 and 4A, the conductive vias 34 are electrically connected to the conductive layers 36 of the adjacent resin blocks B through the insulating layer 13 in the thickness direction. That is, the conductive vias 34 electrically connect the conductive layers 36 of the resin blocks B adjacent to each other. As a result, the conductive layers 36 of the adjacent resin blocks B are electrically connected to form an electric circuit within the pitch conversion unit 1 .
 なお、後述するように、隣り合う樹脂ブロックBのうち一方の樹脂ブロックBに設けられた絶縁層13は、加熱されて他方の樹脂ブロックBに融着される。これにより、隣り合う樹脂ブロックBは、絶縁層13を介して一体化されている。 As will be described later, the insulating layer 13 provided on one of the adjacent resin blocks B is heated and fused to the other resin block B. Thereby, the adjacent resin blocks B are integrated through the insulating layer 13 .
 図4Aに示すように、導電性ビア34は、絶縁層13を厚み方向に貫通するビア用穴部13a内に位置する。導電性ビア34は、ビア用穴部13a内に充填された導電性ペーストによって構成されている。この導電性ペーストは、フィラーである金属粒子と、バインダである有機物とを含む。前記導電性ペーストの金属粒子は、例えば、錫などを含む。前記導電性ペーストは、ビア用穴部13a内に充填された後に、例えば熱処理されることにより、導電性ビア34となる。 As shown in FIG. 4A, the conductive via 34 is positioned within the via hole 13a penetrating the insulating layer 13 in the thickness direction. The conductive vias 34 are made of a conductive paste filled in the via holes 13a. This conductive paste contains metal particles as a filler and an organic substance as a binder. The metal particles of the conductive paste contain, for example, tin. After filling the via holes 13a, the conductive paste becomes the conductive vias 34 by, for example, heat treatment.
 導電性ビア34は、隣り合う樹脂ブロックBの導電層36に接合されている。特に図示しないが、導電性ビア34と導電層36との接合部分には、銅及び錫の反応層が形成されている。この反応層によって導電性ビア34と導電層36とが金属結合されるため、導電性ビア34と導電層36との十分な接合強度を確保することができる。 The conductive vias 34 are joined to the conductive layers 36 of the adjacent resin blocks B. Although not shown, a reaction layer of copper and tin is formed at the junction between the conductive via 34 and the conductive layer 36 . Since the conductive via 34 and the conductive layer 36 are metal-bonded by this reaction layer, sufficient bonding strength between the conductive via 34 and the conductive layer 36 can be secured.
 隣り合う樹脂ブロックBの導電層36のうち一方の導電層36は、導電性ビア34との接合部分に、凹部40を有する。本実施形態では、凹部40は、前記接合部分全体が導電層36の厚み方向に凹んだ形状を有する。なお、凹部40は、前記接合部分の少なくとも一部が前記厚み方向に凹んだ形状を有していてもよい。 One conductive layer 36 of the conductive layers 36 of the adjacent resin blocks B has a concave portion 40 at the joint portion with the conductive via 34 . In this embodiment, the recess 40 has a shape in which the entire joint portion is recessed in the thickness direction of the conductive layer 36 . At least a part of the joint portion of the recess 40 may have a shape recessed in the thickness direction.
 このように、本実施形態では、凹部40は、導電層36における導電性ビア34との接合部分全体が前記厚み方向に窪んだ形状を有する。これにより、導電層36における導電性ビア34との接合部分全体において、導電層36を露出させることができる。よって、前記接合部分において、導電層36の表面が、絶縁層等により覆われるのをより確実に防止できる。したがって、前記接合部分において導電層36と導電性ビア34とをより強固に金属接合させることができるため、導電層36と導電性ビア34との接合強度をより向上することができる。 As described above, in the present embodiment, the recess 40 has a shape in which the entire joining portion of the conductive layer 36 with the conductive via 34 is recessed in the thickness direction. As a result, the conductive layer 36 can be exposed over the entire joint portion of the conductive layer 36 with the conductive via 34 . Therefore, it is possible to more reliably prevent the surface of the conductive layer 36 from being covered with an insulating layer or the like at the joint portion. Therefore, since the conductive layer 36 and the conductive via 34 can be metal-bonded more firmly at the bonding portion, the bonding strength between the conductive layer 36 and the conductive via 34 can be further improved.
 凹部40は、導電層36を導電層36及び絶縁層13の積層方向に見て、例えば、円形状である。凹部40は、導電層36を前記積層方向に見て、例えば、楕円状、矩形状、多角形状などの円形状以外の形状であってもよい。凹部40は、導電層36を前記積層方向に見て、導電性ビア34のビア用穴部13aと同じ形状及び大きさであってもよいし、導電性ビア34のビア用穴部13aと異なる形状であってもよいし、導電性ビア34のビア用穴部13aと同じ形状で且つビア用穴部13aよりも小さくてもよい。 The recessed portion 40 has, for example, a circular shape when the conductive layer 36 is viewed in the stacking direction of the conductive layer 36 and the insulating layer 13 . The concave portion 40 may have a shape other than a circular shape, such as an elliptical shape, a rectangular shape, or a polygonal shape, when the conductive layer 36 is viewed in the stacking direction. The concave portion 40 may have the same shape and size as the via hole portion 13a of the conductive via 34 when the conductive layer 36 is viewed in the stacking direction, or may be different from the via hole portion 13a of the conductive via 34. It may have the same shape as the via hole 13a of the conductive via 34 and may be smaller than the via hole 13a.
 凹部40は、底面41と、側面42とを含む。底面41は、導電層36を前記積層方向に見て例えば円形状の平面である。なお、底面41は、導電層36を前記積層方向に見て例えば楕円状、矩形状、多角形状などの円形状以外の形状であってもよい。また、底面41は、曲面であってもよいし、階段状に深くなる溝、螺旋状または円環状の溝、凹凸などを有していてもよい。側面42は、導電層36において凹部40の開口が形成された面に対して、法線方向に延びている。側面42は、前記面に対して斜めに延びていていてもよい。 The recess 40 includes a bottom surface 41 and side surfaces 42 . The bottom surface 41 is, for example, a circular flat surface when the conductive layer 36 is viewed in the stacking direction. Note that the bottom surface 41 may have a shape other than a circular shape such as an elliptical shape, a rectangular shape, or a polygonal shape when the conductive layer 36 is viewed in the stacking direction. In addition, the bottom surface 41 may be a curved surface, or may have a stepped deep groove, a spiral or annular groove, unevenness, or the like. The side surface 42 extends in the direction normal to the surface of the conductive layer 36 on which the opening of the recess 40 is formed. The side surfaces 42 may extend obliquely with respect to said surface.
 凹部40は、内方に、例えば円柱状または円錐台状の空間を有する。図4Aに示す例では、凹部40は、内方に、底面41の半径が導電層36に形成された開口の半径と等しい円柱状の空間を有する。図4Bに示すように、凹部140は、内方に、底面141の半径が導電層36に形成された開口の半径よりも小さい円柱状または円錐台状の空間を有していてもよい。なお、図4Bにおいて、符号142は凹部140の側面であり、符号141aは凹部140の底面窪み部である。 The recess 40 has, for example, a cylindrical or truncated conical space inside. In the example shown in FIG. 4A , the recess 40 has a cylindrical space inside, the radius of the bottom surface 41 of which is equal to the radius of the opening formed in the conductive layer 36 . As shown in FIG. 4B, the recess 140 may have a cylindrical or frusto-conical space inside, the radius of the bottom surface 141 of which is smaller than the radius of the opening formed in the conductive layer 36 . In FIG. 4B, reference numeral 142 denotes the side surface of the recess 140, and reference numeral 141a denotes the recessed portion of the bottom surface of the recess 140. As shown in FIG.
 図4Aに示すように、凹部40の底面41における導電層36の厚みT1は、凹部40以外の導電層36の厚みよりも小さい。具体的には、底面41における導電層36の厚みT1は、導電層36の凹凸部36aの最下部における導電層36の厚みT2よりも小さい。底面41における導電層36の厚みT1は、底面41のうち凹部40の深さが最も小さい部分における導電層36の厚みである。これにより、凹部40の底面41は、導電層36において絶縁層13側の面に形成された凹凸部36aの最下部よりも導電層36の厚み方向内方に位置する。前記最下部は、導電層36の厚み方向において、凹凸部36aのうち最も厚み方向内方に位置する凹部分である。 As shown in FIG. 4A , the thickness T1 of the conductive layer 36 at the bottom surface 41 of the recess 40 is smaller than the thickness of the conductive layer 36 other than the recess 40 . Specifically, the thickness T1 of the conductive layer 36 at the bottom surface 41 is smaller than the thickness T2 of the conductive layer 36 at the lowest portion of the uneven portion 36a of the conductive layer 36 . A thickness T1 of the conductive layer 36 at the bottom surface 41 is the thickness of the conductive layer 36 at a portion of the bottom surface 41 where the recess 40 has the smallest depth. As a result, the bottom surface 41 of the recess 40 is positioned inward in the thickness direction of the conductive layer 36 from the lowermost portion of the uneven portion 36a formed on the surface of the conductive layer 36 on the insulating layer 13 side. The lowermost portion is a concave portion positioned most inward in the thickness direction of the uneven portion 36 a in the thickness direction of the conductive layer 36 .
 このように、本実施形態では、導電層36は、絶縁層13側に位置する面に、絶縁層13との密着性を向上するための凹凸部36aを有する。凹部40の底面41は、凹凸部36aの最下部よりも導電層36の厚み方向内方に位置する。 As described above, in the present embodiment, the conductive layer 36 has the uneven portion 36 a on the surface located on the insulating layer 13 side for improving the adhesion with the insulating layer 13 . The bottom surface 41 of the concave portion 40 is located inside the conductive layer 36 in the thickness direction of the lowermost portion of the concave/convex portion 36a.
 これにより、導電層36の凹部40では、表面の凹凸部36aに付着している絶縁層13が除去されているため、凹部40の底面41に導電層36を露出させることができる。したがって、凹部40において、導電層36と導電性ビア34とをより強固に金属接合させることができるため、導電層36と導電性ビア34との接合強度をより向上することができる。 As a result, since the insulating layer 13 adhering to the irregularities 36 a on the surface of the recess 40 of the conductive layer 36 is removed, the conductive layer 36 can be exposed on the bottom surface 41 of the recess 40 . Therefore, since the conductive layer 36 and the conductive via 34 can be metal-bonded more firmly in the concave portion 40, the bonding strength between the conductive layer 36 and the conductive via 34 can be further improved.
 底面41は、導電層36を積層方向に見て中央部分に、底面窪み部41aを有する。底面窪み部41aは、底面41の他の部分に比べて、導電層36の厚み方向に窪んでいる。すなわち、凹部40は、底面41に、凹部40の他の部分よりも前記厚み方向に窪んだ底面窪み部41aを有する。底面窪み部41aの窪み量は、導電層36を積層方向に見て底面41の中央に位置する部分で最も大きく、底面41の外周側に向かうほど小さい。これにより、底面41のうち導電層36を積層方向に見て中央の位置における導電層36の厚みT3が、凹部40における導電層36の厚みの中で最も小さい。 The bottom surface 41 has a bottom recessed portion 41a in the central portion when the conductive layer 36 is viewed in the stacking direction. The bottom recessed portion 41 a is recessed in the thickness direction of the conductive layer 36 compared to other portions of the bottom surface 41 . That is, the recessed portion 40 has a bottom recessed portion 41 a that is recessed in the thickness direction more than other portions of the recessed portion 40 on the bottom surface 41 . The amount of depression of the bottom surface depression portion 41 a is the largest at the central portion of the bottom surface 41 when the conductive layer 36 is viewed in the stacking direction, and decreases toward the outer periphery of the bottom surface 41 . As a result, the thickness T3 of the conductive layer 36 at the central position of the bottom surface 41 as viewed in the stacking direction of the conductive layer 36 is the smallest among the thicknesses of the conductive layer 36 in the recess 40 .
 これにより、絶縁層13のビア用穴部13a内に金属ペースト等を充填することにより導電性ビア34を形成する際に、導電層36の凹部40の底面窪み部41a内に前記金属ペーストが入り込む。よって、導電層36の底面41に対して導電性ビア34をより強固に接合することができる。また、底面41が底面窪み部41aを有することにより、底面窪み部41a内に前記金属ペーストを容易に充填することができる。したがって、上述の構成により、導電層36の底面41に対してより強固に接合される導電性ビア34を、容易に形成することができる。 As a result, when the conductive vias 34 are formed by filling the via holes 13a of the insulating layer 13 with a metal paste or the like, the metal paste enters the bottom recessed portions 41a of the recesses 40 of the conductive layer 36. . Therefore, the conductive via 34 can be more strongly bonded to the bottom surface 41 of the conductive layer 36 . Further, since the bottom surface 41 has the bottom recessed portion 41a, the metal paste can be easily filled in the bottom recessed portion 41a. Therefore, with the above configuration, the conductive via 34 that is more strongly bonded to the bottom surface 41 of the conductive layer 36 can be easily formed.
 底面窪み部41aは、導電層36を積層方向に見て、導電層36における導電性ビア34との接合部分の中央部に位置する。これにより、導電層36の凹部40内に導電ペーストを充填する際に、底面窪み部41a内に前記金属ペーストを容易に充填することができる。したがって、上述の構成により、導電層36の底面41に対してより強固に接合される導電性ビア34を、より容易に形成することができる。 The bottom recessed portion 41a is located in the central portion of the joint portion of the conductive layer 36 with the conductive via 34 when the conductive layer 36 is viewed in the stacking direction. As a result, when filling the conductive paste into the recess 40 of the conductive layer 36, the metal paste can be easily filled into the bottom recessed portion 41a. Therefore, the above configuration makes it possible to more easily form the conductive via 34 that is more strongly bonded to the bottom surface 41 of the conductive layer 36 .
 凹部40の側面42は、導電層36を積層方向に見て、凹部40の開口側が底面41と一致する円筒状の面である。側面42は、樹脂層12の積層方向に見て例えば円環状である。なお、側面42は、樹脂層12の積層方向に見て例えば楕円環状、矩形環状、多角形環状などの円環状以外の形状であってもよい。 A side surface 42 of the recess 40 is a cylindrical surface in which the opening side of the recess 40 coincides with the bottom surface 41 when the conductive layer 36 is viewed in the stacking direction. The side surface 42 has, for example, an annular shape when viewed in the stacking direction of the resin layers 12 . Note that the side surface 42 may have a shape other than an annular shape, such as an elliptical annular shape, a rectangular annular shape, or a polygonal annular shape when viewed in the stacking direction of the resin layers 12 .
 本実施形態では、ピッチ変換ユニット1は、検査対象の検査点に対して電気信号を授受する複数のプローブ121に電気的に接続される複数の接触端子側電極21と、半導体検査装置100に電気的に接続される複数の装置側電極22とを有し、複数の接触端子側電極21のピッチを複数の装置側電極のピッチに変換するピッチ変換ユニットである。ピッチ変換ユニット1は、厚み方向に積層される複数の樹脂層12と、複数の樹脂層12のうち少なくとも一つの樹脂層12を前記厚み方向に貫通する複数の貫通導電体33と、複数の樹脂層12のうち前記厚み方向に隣り合う2つの樹脂層12に対して対向側に位置し、複数の貫通導電体33のうち前記隣り合う2つの樹脂層12をそれぞれ前記厚み方向に貫通する貫通導電体33に電気的に接続される一対の導電層36と、前記一対の導電層36の間に位置する絶縁層13と、絶縁層13を前記厚み方向に貫通して、端部が一対の導電層36に接合されている導電性ビア34と、を有する。一対の導電層36のうち一方の導電層36は、導電性ビア34との接合部分の少なくとも一部に、前記厚み方向に窪んだ凹部40を有する。 In the present embodiment, the pitch conversion unit 1 includes a plurality of contact terminal side electrodes 21 electrically connected to a plurality of probes 121 that transmit and receive electrical signals to and from an inspection point to be inspected, and a semiconductor inspection device 100 that is electrically connected to the semiconductor inspection device 100 . It is a pitch conversion unit that has a plurality of device-side electrodes 22 that are physically connected, and converts the pitch of the plurality of contact terminal-side electrodes 21 into the pitch of the plurality of device-side electrodes. The pitch conversion unit 1 includes a plurality of resin layers 12 laminated in the thickness direction, a plurality of through conductors 33 penetrating at least one resin layer 12 of the plurality of resin layers 12 in the thickness direction, and a plurality of resin layers 12 . A penetrating conductor located on the opposite side of two resin layers 12 adjacent in the thickness direction among the layers 12 and penetrating the two adjacent resin layers 12 among the plurality of penetrating conductors 33 in the thickness direction. A pair of conductive layers 36 electrically connected to the body 33, an insulating layer 13 positioned between the pair of conductive layers 36, and a pair of conductive layers penetrating through the insulating layer 13 in the thickness direction. and a conductive via 34 that is bonded to the layer 36 . One conductive layer 36 of the pair of conductive layers 36 has a recess 40 recessed in the thickness direction in at least a part of the joint portion with the conductive via 34 .
 これにより、導電層36における導電性ビア34との接合部分のうち、凹部40が形成されている部分において、導電層36を露出させることができる。よって、凹部40において、導電層36の表面が、絶縁層13等により覆われるのを防止できる。したがって、凹部40内で導電層36と導電性ビア34とを金属接合させることができるため、導電層36と導電性ビア34との接合強度を向上することができる。 As a result, the conductive layer 36 can be exposed in the portion where the concave portion 40 is formed in the joint portion of the conductive layer 36 with the conductive via 34 . Therefore, it is possible to prevent the surface of the conductive layer 36 from being covered with the insulating layer 13 or the like in the concave portion 40 . Therefore, since the conductive layer 36 and the conductive via 34 can be metal-bonded within the recess 40, the bonding strength between the conductive layer 36 and the conductive via 34 can be improved.
(ピッチ変換ユニットの製造方法)
 次に、上述の構成を有するピッチ変換ユニット1の製造方法を、図5から10を用いて説明する。
(Manufacturing method of pitch conversion unit)
Next, a method of manufacturing the pitch conversion unit 1 having the above configuration will be described with reference to FIGS.
 まず、図5に示すように、ピッチ変換ユニット1を構成する複数の樹脂ブロックBを形成する。樹脂ブロックBは、複数の樹脂層12と、複数の金属層32と、複数の貫通導電体33とを有する。よって、樹脂ブロックBを形成する際に、複数の樹脂層12を厚み方向に積層しつつ、樹脂層12同士の間に複数の金属層32を形成し、樹脂層12を前記厚み方向に貫通して金属層32に接合される複数の貫通導電体33を形成する。樹脂ブロックBにおいて、樹脂層12、金属層32及び貫通導電体33を形成する方法は、従来の方法と同様であるため、詳しい説明を省略する。 First, as shown in FIG. 5, a plurality of resin blocks B constituting the pitch conversion unit 1 are formed. Resin block B has a plurality of resin layers 12 , a plurality of metal layers 32 , and a plurality of through conductors 33 . Therefore, when forming the resin block B, while laminating the plurality of resin layers 12 in the thickness direction, the plurality of metal layers 32 are formed between the resin layers 12, and the resin layers 12 are penetrated in the thickness direction. to form a plurality of through conductors 33 bonded to the metal layer 32 . The method of forming the resin layer 12, the metal layer 32 and the penetrating conductor 33 in the resin block B is the same as the conventional method, so detailed description thereof will be omitted.
 上述のように形成された複数の樹脂ブロックBのうち、後述するように接合される樹脂ブロックBには、接合側に金属層32の一部である導電層36が露出している。なお、ピッチ変換ユニット1を構成する複数の樹脂ブロックBのうち、積層方向の一方の端部に位置する樹脂ブロックBには、接触端子側電極21が露出している。また、ピッチ変換ユニット1を構成する複数の樹脂ブロックBのうち、積層方向の他方の端部に位置する樹脂ブロックBには、装置側電極22が露出している。 Among the plurality of resin blocks B formed as described above, the conductive layer 36, which is part of the metal layer 32, is exposed on the joint side of the resin block B that is joined as described later. The contact terminal side electrode 21 is exposed to the resin block B positioned at one end in the stacking direction among the plurality of resin blocks B constituting the pitch conversion unit 1 . Further, the device-side electrode 22 is exposed to the resin block B positioned at the other end in the stacking direction among the plurality of resin blocks B constituting the pitch conversion unit 1 .
 なお、図5以降の図には特に図示しないが、樹脂ブロックBにおいて導電層36の露出部分の表面には、テクスチャリング等によって凹凸部36aが形成される。導電層36の露出部分の表面に凹凸部36aを形成することによって、後述するように樹脂ブロックB上に絶縁層13を形成する際に、導電層36に対する絶縁層13の密着性を向上することができる。 Although not particularly shown in the figures after FIG. 5, an uneven portion 36a is formed on the surface of the exposed portion of the conductive layer 36 in the resin block B by texturing or the like. By forming the uneven portion 36a on the surface of the exposed portion of the conductive layer 36, the adhesion of the insulating layer 13 to the conductive layer 36 is improved when the insulating layer 13 is formed on the resin block B as described later. can be done.
 次に、図6に示すように、樹脂ブロックBにおいて導電層36が露出している面上に、絶縁層13を形成するとともに、絶縁層13上にPET層14を形成する。その後、図7に示すように、絶縁層13及びPET層14において導電層36上に位置する部分に、レーザ光αを照射して、レーザ加工により穴部15を形成する。穴部15は、絶縁層13に形成されたビア用穴部13aを含む。絶縁層13にビア用穴部13aを形成する工程が、ビア用穴部形成工程である。レーザ光αは、例えば、COレーザ光またはUVレーザ光などである。 Next, as shown in FIG. 6, the insulating layer 13 is formed on the surface of the resin block B where the conductive layer 36 is exposed, and the PET layer 14 is formed on the insulating layer 13 . After that, as shown in FIG. 7, the portions of the insulating layer 13 and the PET layer 14 located on the conductive layer 36 are irradiated with laser light α to form the holes 15 by laser processing. Holes 15 include via holes 13 a formed in insulating layer 13 . The step of forming the via holes 13a in the insulating layer 13 is the via hole forming step. The laser light α is, for example, CO 2 laser light or UV laser light.
 上述のレーザ加工によって、絶縁層13及びPET層14のそれぞれ一部は除去されるが、穴部15の底面に、絶縁層13の一部が残存する場合がある。そのため、図8に示すように、穴部15内にレーザ光βを照射して、穴部15の底部に残っている絶縁層13の一部を除去する。この際、レーザ光βは、導電層36の一部を除去するパワー密度を有する。よって、導電層36には、凹部40が形成される。凹部40は、導電層36を積層方向に見て、導電層36においてビア用穴部13aと重なる部分に形成される。凹部40の形状は、既述のとおりであるため、詳しい説明を省略する。なお、レーザ光βは、例えば、グリーンレーザ光、UVレーザ光、エキシマレーザ光などである。 Although the insulating layer 13 and the PET layer 14 are partially removed by the laser processing described above, a portion of the insulating layer 13 may remain on the bottom surface of the hole 15 . Therefore, as shown in FIG. 8, the inside of the hole 15 is irradiated with a laser beam β to partially remove the insulating layer 13 remaining at the bottom of the hole 15 . At this time, the laser beam β has a power density sufficient to partially remove the conductive layer 36 . Accordingly, recesses 40 are formed in the conductive layer 36 . The recessed portion 40 is formed in a portion of the conductive layer 36 that overlaps the via hole portion 13a when the conductive layer 36 is viewed in the stacking direction. Since the shape of the concave portion 40 is as described above, detailed description thereof will be omitted. Note that the laser beam β is, for example, a green laser beam, a UV laser beam, an excimer laser beam, or the like.
 次に、穴部15内に導電材料である導電性ペーストを充填した後、PET層14を除去する。これにより、図9に示すように、絶縁層13のビア用穴部13a内に導電性ペーストが充填された導電性ビア34が形成される。ビア用穴部13a内に導電材料である導電性ペーストを充填することにより、導電性ビア34を形成する工程が、導電性ビア形成工程である。 Next, after filling the holes 15 with a conductive paste, which is a conductive material, the PET layer 14 is removed. As a result, as shown in FIG. 9, a conductive via 34 is formed in which the via hole 13a of the insulating layer 13 is filled with the conductive paste. The step of forming the conductive via 34 by filling the via hole 13a with a conductive paste, which is a conductive material, is the conductive via forming step.
 そして、図10に示すように、絶縁層13上に別の樹脂ブロックBを重ねた状態で、2つの樹脂ブロックBを絶縁層13が融着する温度まで加熱することにより、絶縁層13を介して樹脂ブロックB同士を接合することができる。また、導電性ビア34は、2つの樹脂ブロックBの導電層36にそれぞれ金属接合される。 Then, as shown in FIG. 10, another resin block B is superimposed on the insulating layer 13, and by heating the two resin blocks B to a temperature at which the insulating layer 13 is fused, It is possible to join the resin blocks B to each other. Also, the conductive vias 34 are metal-bonded to the conductive layers 36 of the two resin blocks B, respectively.
 以上のような工程を、積層する樹脂ブロックBの数に応じて繰り返すことにより、複数の樹脂ブロックBによって構成されるピッチ変換ユニット1が形成される。 By repeating the above steps according to the number of resin blocks B to be laminated, the pitch conversion unit 1 composed of a plurality of resin blocks B is formed.
 本実施形態のピッチ変換ユニット1の製造方法は、絶縁層13に導電性ビア34の一部を構成するビア用穴部13aを形成するビア用穴部形成工程と、導電層36を積層方向に見て、導電層36においてビア用穴部13aと重なる部分に、凹部40を形成する凹部形成工程と、ビア用穴部13a内に導電材料を充填することにより、導電性ビア34を形成する導電性ビア形成工程と、を有する。 The manufacturing method of the pitch conversion unit 1 of the present embodiment includes a via hole forming step of forming a via hole 13a constituting a part of the conductive via 34 in the insulating layer 13, and a step of forming the conductive layer 36 in the stacking direction. As can be seen, a recess forming step of forming a recess 40 in a portion of the conductive layer 36 overlapping the via hole 13a and a conductive material filling the via hole 13a with a conductive material to form the conductive via 34 are performed. and a conductive via formation step.
 これにより、絶縁層13に形成されたビア用穴部13a内に導電性ペーストが充填されて導電層36と接合された導電性ビア34が構成されるとともに、導電層36を前記積層方向に見て、導電層36においてビア用穴部13aと重なる部分に、凹部40が形成されたピッチ変換ユニット1が得られる。 As a result, the via hole 13a formed in the insulating layer 13 is filled with the conductive paste to form the conductive via 34 joined to the conductive layer 36, and the conductive layer 36 is viewed in the stacking direction. Thus, the pitch conversion unit 1 is obtained in which the recesses 40 are formed in the portions of the conductive layer 36 overlapping the via holes 13a.
 このように形成されたピッチ変換ユニット1では、導電層36における導電性ビア34との接合部分のうち、凹部40が形成されている部分において、導電層36を露出させることができる。よって、凹部40において、導電層36の表面が、絶縁層13等により覆われるのを防止できる。したがって、凹部40内で導電層36と導電性ビア34とを金属接合させることができるため、導電層36と導電性ビア34との接合強度を向上することができる。 In the pitch conversion unit 1 formed in this manner, the conductive layer 36 can be exposed in the portion where the concave portion 40 is formed in the joint portion of the conductive layer 36 with the conductive via 34 . Therefore, it is possible to prevent the surface of the conductive layer 36 from being covered with the insulating layer 13 or the like in the concave portion 40 . Therefore, since the conductive layer 36 and the conductive via 34 can be metal-bonded within the recess 40, the bonding strength between the conductive layer 36 and the conductive via 34 can be improved.
 また、前記ビア用凹部形成工程では、導電層36を前記積層方向に見て、導電層36においてビア用穴部13aと重なる部分に、レーザ光βを照射することにより、凹部40を形成する。 Further, in the via recess forming step, the recess 40 is formed by irradiating a portion of the conductive layer 36 that overlaps the via hole 13a with the laser beam β when the conductive layer 36 is viewed in the stacking direction.
 これにより、ビア用穴部形成工程において、導電層36に凹部40を容易に形成することができる。よって、本実施形態の構成を有するピッチ変換ユニット1を容易に得ることができる。 Thereby, the concave portion 40 can be easily formed in the conductive layer 36 in the via hole forming step. Therefore, the pitch conversion unit 1 having the configuration of this embodiment can be easily obtained.
 (その他の実施形態)
 以上、本発明の実施の形態を説明したが、上述した実施の形態は本発明を実施するための例示に過ぎない。よって、上述した実施の形態に限定されることなく、その趣旨を逸脱しない範囲内で上述した実施の形態を適宜変形して実施することが可能である。
(Other embodiments)
Although the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the present invention. Therefore, without being limited to the above-described embodiment, it is possible to modify the above-described embodiment as appropriate without departing from the spirit thereof.
 前記実施形態では、電気検査装置として半導体検査装置を例に挙げて説明した。しかしながら、ピッチ変換ユニットは、半導体検査装置に限らず、例えば基板を検査する基板検査装置に用いてもよい。この場合には、前記基板検査装置の検査対象である基板は、セラミック多層配線基板、ガラスエポキシ基板、フレキシブル基板、セラミック多層配線基板、半導体パッケージ用のパッケージ基板、インターポーザ基板、フィルムキャリア等の基板であってもよいし、液晶ディスプレイ、EL(Electtric-Luminescence)ディスプレイ、タッチパネルディスプレイ等のディスプレイ用の電極板、タッチパネル用等の電極板等であってもよいし、他の種類の基板であってもよい。 In the above embodiment, a semiconductor inspection device was taken as an example of an electrical inspection device. However, the pitch conversion unit is not limited to the semiconductor inspection device, and may be used, for example, in a substrate inspection device that inspects a substrate. In this case, the board to be inspected by the board inspection apparatus may be a ceramic multilayer wiring board, a glass epoxy board, a flexible board, a ceramic multilayer wiring board, a package board for a semiconductor package, an interposer board, a film carrier, or the like. It may be an electrode plate for a display such as a liquid crystal display, an EL (Electric-Luminescence) display, a touch panel display, an electrode plate for a touch panel, or the like, or it may be another type of substrate. good.
 前記実施形態では、ピッチ変換ユニット1は、絶縁層13を介して、複数の樹脂ブロックBを接合することによって形成されている。しかしながら、ピッチ変換ユニットは、導電性ビアを有する構成であれば、複数の樹脂層を積層することによって形成されてもよい。ピッチ変換ユニットは、絶縁層を含んでいてもよい。この場合、導電性ビアと導電層との接合部分に、本実施形態の構成を適用すればよい。 In the above embodiment, the pitch conversion unit 1 is formed by bonding a plurality of resin blocks B via the insulating layer 13 . However, the pitch conversion unit may be formed by laminating a plurality of resin layers as long as it has a configuration having conductive vias. The pitch conversion unit may include an insulating layer. In this case, the configuration of this embodiment may be applied to the junction between the conductive via and the conductive layer.
 前記実施形態では、図3に示す例において、樹脂ブロックBは、3層の樹脂層12を有する。しかしながら、絶縁ブロックは、2層以下の樹脂層を有していてもよいし、4層以上の樹脂層を有していてもよい。また、前記実施形態では、図3に示す例において、ピッチ変換ユニット1は、3つの樹脂ブロックBを有する。しかしながら、ピッチ変換ユニットは、2つ以下の樹脂ブロックを有していてもよいし、4つ以上の樹脂ブロックを有していてもよい。 In the above embodiment, the resin block B has three resin layers 12 in the example shown in FIG. However, the insulating block may have two or less resin layers, or may have four or more resin layers. In the above embodiment, the pitch conversion unit 1 has three resin blocks B in the example shown in FIG. However, the pitch conversion unit may have two or less resin blocks, or four or more resin blocks.
 前記実施形態では、凹部40,140の底面41,141は、導電層36を積層方向に見て中央部分に、底面窪み部41a,141aを有する。しかしながら、底面は、導電層を積層方向に見て中央部分以外に、底面窪み部を有していてもよい。底面窪み部は、導電層を積層方向に見て、導電層における導電性ビアとの接合部分のどの位置に設けられていてもよい。底面は、底面窪み部を有していなくてもよい。底面は、凸部を有していてもよい。 In the above-described embodiments, the bottom surfaces 41 and 141 of the recesses 40 and 140 have bottom recess portions 41a and 141a in the central portion when the conductive layer 36 is viewed in the stacking direction. However, the bottom surface may have a recessed portion on the bottom surface other than the central portion when viewed in the stacking direction of the conductive layers. The bottom recessed portion may be provided at any position of the joint portion of the conductive layer with the conductive via when the conductive layer is viewed in the stacking direction. The bottom surface may not have a bottom surface recess. The bottom surface may have a convex portion.
 前記実施形態では、底面窪み部41aの窪み量は、導電層36を積層方向に見て底面41の中央に位置する部分で最も大きく、底面41の外周側に向かうほど小さい。しかしながら、底面窪み部の形状は、凹部の底面の他の部分に比べて前記厚み方向に窪んでいれば、どのような形状であってもよい。 In the above-described embodiment, the recess amount of the bottom recess portion 41a is the largest at the central portion of the bottom surface 41 when the conductive layer 36 is viewed in the stacking direction, and becomes smaller toward the outer peripheral side of the bottom surface 41. However, the shape of the bottom recessed portion may be any shape as long as it is recessed in the thickness direction compared to other portions of the bottom surface of the recess.
 前記実施形態では、凹部40の側面42は、導電層36を積層方向に見て、凹部40の開口側が底面41と同じである円筒状の面である。しかしながら、凹部の側面は、導電層を積層方向に見て、凹部の開口側が底面よりも径方向外方または径方向内方に位置するテーパ状の面であってもよい。また、凹部の側面は、導電層を積層方向に見て、多角形状であってもよい。凹部の側面は、複数の平面を含んでいてもよい。 In the above embodiment, the side surface 42 of the recess 40 is a cylindrical surface in which the opening side of the recess 40 is the same as the bottom surface 41 when the conductive layer 36 is viewed in the stacking direction. However, the side surface of the recess may be a tapered surface in which the opening side of the recess is positioned radially outward or radially inward from the bottom surface when the conductive layers are viewed in the stacking direction. Moreover, the side surface of the recess may be polygonal when the conductive layers are viewed in the stacking direction. A side surface of the recess may include a plurality of flat surfaces.
 前記実施形態では、導電層36に凹部40を形成する際に、レーザ光βを用いている。しかしながら、工具等を用いて導電層に機械的に凹部を形成してもよい。すなわち、ビア用穴部の底面で、前記導電層上の絶縁層を除去して前記導電層を露出させることが可能な加工方法であれば、レーザ加工以外の方法であってもよい。 In the above embodiment, the laser beam β is used when forming the recesses 40 in the conductive layer 36 . However, the recesses may be formed mechanically in the conductive layer using a tool or the like. That is, any processing method other than laser processing may be used as long as the processing method is capable of removing the insulating layer on the conductive layer and exposing the conductive layer at the bottom surface of the via hole.
 前記実施形態では、導電層36は、絶縁層13側の面に、微小な凹凸部36aを有する。しかしながら、導電層は、絶縁層側の面に凹凸部を有していなくてもよい。 In the above-described embodiment, the conductive layer 36 has fine uneven portions 36a on the surface on the insulating layer 13 side. However, the conductive layer does not have to have unevenness on the surface on the insulating layer side.
 本発明は、検査対象の検査点に対して電気信号を授受する複数の接触端子に電気的に接続される複数の接触端子側電極と、検査装置に電気的に接続される複数の装置側電極とを有し、前記複数の接触端子側電極のピッチを前記複数の装置側電極のピッチに変換するピッチ変換ユニットに利用可能である。 The present invention includes a plurality of contact terminal side electrodes electrically connected to a plurality of contact terminals for transmitting and receiving electric signals to and from an inspection point to be inspected, and a plurality of device side electrodes electrically connected to an inspection device. and a pitch conversion unit that converts the pitch of the plurality of contact terminal side electrodes into the pitch of the plurality of device side electrodes.
1 ピッチ変換ユニット
2 検査治具
3 接続プレート
4 接続部材
11 基板
12 樹脂層
13 絶縁層
13a ビア用穴部
14 PET層
21 接触端子側電極
22 装置側電極
31 導電体
32 金属層
33 貫通導電体
34 導電性ビア
36 導電層
36a 凹凸部
40、140 凹部
41、141 底面
41a、141a 底面窪み部
42、142 側面
100 半導体検査装置
104 検査部
106 試料台
106a 載置部
108 検査処理部
121 プローブ
122 貫通部材
131 ケーブル
132 接続端子
B 樹脂ブロック
DUT 半導体ウェハ
1 pitch conversion unit 2 inspection jig 3 connection plate 4 connection member 11 substrate 12 resin layer 13 insulation layer 13a via hole 14 PET layer 21 contact terminal side electrode 22 device side electrode 31 conductor 32 metal layer 33 through conductor 34 Conductive via 36 Conductive layer 36a Uneven portions 40, 140 Concave portions 41, 141 Bottom surfaces 41a, 141a Bottom recessed portions 42, 142 Side surface 100 Semiconductor inspection device 104 Inspection unit 106 Sample table 106a Mounting unit 108 Inspection processing unit 121 Probe 122 Penetrating member 131 cable 132 connection terminal B resin block DUT semiconductor wafer

Claims (7)

  1.  検査対象の検査点に対して電気信号を授受する複数の接触端子に電気的に接続される複数の接触端子側電極と、検査装置に電気的に接続される複数の装置側電極とを有し、前記複数の接触端子側電極のピッチを前記複数の装置側電極のピッチに変換するピッチ変換ユニットであって、
     厚み方向に積層される複数の樹脂層と、
     前記複数の樹脂層のうち少なくとも一つの樹脂層を前記厚み方向に貫通する複数の貫通導電体と、
     前記複数の樹脂層のうち前記厚み方向に隣り合う2つの樹脂層に対して対向側に位置し、前記複数の貫通導電体のうち前記隣り合う2つの樹脂層をそれぞれ前記厚み方向に貫通する貫通導電体に電気的に接続される一対の導電層と、
     前記一対の導電層の間に位置する絶縁層と、
     前記絶縁層を前記厚み方向に貫通して、端部が前記一対の導電層に接合されている導電性ビアと、
    を有し、
     前記一対の導電層のうち一方の導電層は、前記導電性ビアとの接合部分の少なくとも一部に、前記厚み方向に窪んだ凹部を有する、ピッチ変換ユニット。
    It has a plurality of contact terminal-side electrodes electrically connected to a plurality of contact terminals for transmitting and receiving electric signals to and from an inspection point to be inspected, and a plurality of device-side electrodes electrically connected to an inspection device. , a pitch conversion unit for converting the pitch of the plurality of contact terminal side electrodes to the pitch of the plurality of device side electrodes,
    a plurality of resin layers laminated in the thickness direction;
    a plurality of penetrating conductors penetrating through at least one resin layer of the plurality of resin layers in the thickness direction;
    A through-hole positioned on the opposite side of two resin layers adjacent in the thickness direction among the plurality of resin layers and penetrating the two adjacent resin layers among the plurality of through conductors in the thickness direction. a pair of conductive layers electrically connected to the conductor;
    an insulating layer positioned between the pair of conductive layers;
    a conductive via penetrating the insulating layer in the thickness direction and having ends joined to the pair of conductive layers;
    has
    The pitch conversion unit, wherein one of the pair of conductive layers has a recess recessed in the thickness direction in at least a part of a joint portion with the conductive via.
  2.  請求項1に記載のピッチ変換ユニットにおいて、
     前記凹部は、前記導電層における前記導電性ビアとの接合部分全体が前記厚み方向に窪んだ形状を有する、
    ピッチ変換ユニット。
    A pitch conversion unit according to claim 1, wherein
    The recess has a shape in which the entire joint portion with the conductive via in the conductive layer is recessed in the thickness direction,
    Pitch conversion unit.
  3.  請求項1または2に記載のピッチ変換ユニットにおいて、
     前記凹部は、底面に、前記凹部の他の部分よりも前記厚み方向に窪んだ底面窪み部を有する、
    ピッチ変換ユニット。
    A pitch conversion unit according to claim 1 or 2,
    The recess has, on its bottom surface, a recessed bottom surface that is recessed in the thickness direction more than other portions of the recess,
    Pitch conversion unit.
  4.  請求項3に記載のピッチ変換ユニットにおいて、
     前記底面窪み部は、前記導電層を前記導電層及び前記絶縁層の積層方向に見て、前記導電層における前記導電性ビアとの接合部分の中央部に位置する、ピッチ変換ユニット。
    A pitch conversion unit according to claim 3, wherein
    The pitch conversion unit, wherein the bottom recessed portion is positioned at a central portion of a joint portion of the conductive layer with the conductive via when the conductive layer is viewed in a stacking direction of the conductive layer and the insulating layer.
  5.  請求項1から4のいずれか一つに記載のピッチ変換ユニットにおいて、
     前記導電層は、絶縁層側に位置する面に、前記絶縁層との密着性を向上するための凹凸部を有し、
     前記凹部の底面は、前記凹凸部の最下部よりも前記導電層の厚み方向内方に位置する、ピッチ変換ユニット。
    A pitch conversion unit according to any one of claims 1 to 4,
    The conductive layer has an uneven portion for improving adhesion with the insulating layer on a surface located on the insulating layer side,
    The pitch conversion unit, wherein the bottom surface of the concave portion is located inside the lowermost portion of the uneven portion in the thickness direction of the conductive layer.
  6.  請求項1から5のいずれか一つに記載のピッチ変換ユニットの製造方法であって、
     前記絶縁層に前記導電性ビアの一部を構成するビア用穴部を形成するビア用穴部形成工程と、
     前記導電層を前記導電層及び前記絶縁層の積層方向に見て、前記導電層において前記ビア用穴部と重なる部分に、前記凹部を形成する凹部形成工程と、
     前記ビア用穴部内に導電材料を充填することにより、前記導電性ビアを形成する導電性ビア形成工程と、
    を有する、
    ピッチ変換ユニットの製造方法。
    A method for manufacturing the pitch conversion unit according to any one of claims 1 to 5,
    a via hole forming step of forming a via hole forming part of the conductive via in the insulating layer;
    a recess forming step of forming the recess in a portion of the conductive layer that overlaps the via hole when viewed from the direction in which the conductive layer and the insulating layer are laminated;
    a conductive via forming step of forming the conductive via by filling the via hole with a conductive material;
    having
    A method for manufacturing a pitch conversion unit.
  7.  請求項6に記載のピッチ変換ユニットの製造方法において、
     前記凹部形成工程では、前記導電層を前記積層方向に見て、前記導電層において前記ビア用穴部と重なる部分に、レーザ光を照射することにより、前記凹部を形成する、ピッチ変換ユニットの製造方法。
    In the manufacturing method of the pitch conversion unit according to claim 6,
    In the step of forming a recess, the recess is formed by irradiating a laser beam to a portion of the conductive layer overlapping the via hole when viewed in the stacking direction of the conductive layer, thereby forming the recess. Method.
PCT/JP2022/041213 2021-11-08 2022-11-04 Pitch conversion unit and method for manufacturing same WO2023080206A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007115952A (en) * 2005-10-21 2007-05-10 Matsushita Electric Ind Co Ltd Interposer substrate and manufacturing method thereof
JP2009236639A (en) * 2008-03-26 2009-10-15 Kyocera Corp Substrate and substrate for probe card assembly
JP2009236721A (en) * 2008-03-27 2009-10-15 Kyocera Corp Substrate, substrate for probe card assembly, manufacturing method of substrate
JP2011023694A (en) * 2009-06-19 2011-02-03 Kyocera Corp Wiring board, probe card, and electronic device
WO2013031822A1 (en) * 2011-08-29 2013-03-07 京セラ株式会社 Thin-film wiring substrate and substrate for probe card

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019178961A (en) 2018-03-30 2019-10-17 株式会社ヨコオ Space transformer, ceramic substrate for probe card, manufacturing method of space transformer, and forming method of ceramic substrate for probe card

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007115952A (en) * 2005-10-21 2007-05-10 Matsushita Electric Ind Co Ltd Interposer substrate and manufacturing method thereof
JP2009236639A (en) * 2008-03-26 2009-10-15 Kyocera Corp Substrate and substrate for probe card assembly
JP2009236721A (en) * 2008-03-27 2009-10-15 Kyocera Corp Substrate, substrate for probe card assembly, manufacturing method of substrate
JP2011023694A (en) * 2009-06-19 2011-02-03 Kyocera Corp Wiring board, probe card, and electronic device
WO2013031822A1 (en) * 2011-08-29 2013-03-07 京セラ株式会社 Thin-film wiring substrate and substrate for probe card

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