TW201929629A - Multi-DUT testing interposer module and manufacturing method thereof - Google Patents

Abstract

The present invention provides a multi-DUT testing interposer module and a manufacturing method thereof. The testing interposer module includes a rigid substrate; a plurality of package carriers, each package carrier being embedded in a through hole of the rigid substrate; at least one dielectric layer covering opposite surfaces of the rigid substrate and the through hole; connection holes forming at the dielectric layer; at least one conductive plating layer covering the dielectric layer and the connection holes; and line conductors formed on the conductive plating and corresponding to the positions of the connection holes, wherein the line conductors are electrically connected to the package carriers via the connection holes. The present invention can reduce the thickness of the testing interposer module and the transmission path of the test signal thereof, and thus provide a more efficient measurement technology.

Description

Multi-die test interface module and manufacturing method thereof

The invention relates to a test medium panel and a manufacturing method thereof, in particular to a multi-die test interface module and a manufacturing method thereof.

Generally, unpackaged semiconductor semi-finished products, such as die yield test, use a test interface panel as a conversion interface between the die and the test machine. For the yield test of the packaged semiconductor finished product, as shown in Fig. 1, it is a conventional die test structure for a single die, including a printed circuit board (not shown) connected to the test equipment, and connection printing. The test board 10A of the board. The test carrier 10A can be connected with a plurality of die test probes 11A of the die test probes 11A for testing the die 14A on the mobile carrier 13A, and a test interface motherboard 15A for positioning the test carrier 10A. . The test interface mother board 15A is provided with a connection pad 151A for connecting and fixing the conductive bumps 101A on the test carrier 10A. This figure is shown as a single die test, so the test carrier 10A is a single die test interface panel. This prior art only provides one die test at a time, and the test efficiency is not good.

There are vertical probe cards in the market that usually have a Space Transformer (ST), or test interface panel. The test interface panel (also known as ST) is generally tested with a single die (Single DUT) or a pair of die (Dual DUT), but when there are too many I/O points or multiple die ( Multi DUT) When testing, the design of the test interface panel ST is complicated, and the circuit must be dispersed by increasing the number of layers. The finished product is also relatively thick and is not conducive to high-speed testing. The demand for signal and power integrity has also increased costs and delivery has become longer.

Referring to FIG. 2, another conventional example is applied to a die test structure for a plurality of crystal grains, including a printed circuit board (not shown) connected to a test device, and a plurality of test carriers 10A connected to the printed circuit board. A probe test stand 11A, a die 14A, a test moving stage (not shown) carrying the die 14A, and a test interface mother board 15A are connected to the test carrier 10A. The test is carried out for carrying a plurality of dies, and the plurality of test carriers 10A further includes a carrier interface 16A. A metal connection pad 161A is formed on the upper and lower sides of the load-bearing interface seat 16A, and is soldered by a solder ball (not shown). The test carrier 10A can be fixed to the load-bearing interface seat 16A through a soldered connection. The conductive bumps 101A on the test carrier 10A are corresponding to the metal connection pads 161A on the carrier interface 16A. The solder ball soldering method is used to construct the electrical contact between the test carrier 10A and the carrier interface 16A, thereby designing the signal interconnection between the tested die 14A and the test device. However, such die test connection structures and manufacturing methods have the following drawbacks:

1. The transmission performance deteriorates: Since the solder ball is required to conduct heat through the heating plate and heat transfer from the other side to the carrier interface 16A, especially lead-free solder, the process time is longer and the process temperature is higher. Damage to the test carrier 10A. Furthermore, it is necessary to connect through a load-bearing interface seat 16A, and the load-bearing interface seat must first have a certain level of flatness, which is beneficial to the subsequent test carrier welding, and serves as a support for the several test carriers. In the reflow soldering step, the overall thickness of the carrier interface is bound to become relatively thicker, which will lead to an increase in the transmission path. As the thickness of the product increases, the increase in the inductance is increased, which tends to result in High-frequency signal distortion problems occur, which in turn leads to poor transmission performance.

2. Risk of failure of assembly: In response to the demand for high-precision wafer design and multi-DUT testing, the number of test I/O points has increased, and the number of test I/O points has increased by a thousand. Therefore, the size of the test panel/test carrier must be increased, and the number of solder balls (BGA solder joints) will increase. Thus, regardless of whether several test carriers are soldered simultaneously or non-simultaneously on the same carrier interface, the flatness, air soldering, short circuit, etc. are not easily controlled, and the assembly success rate is reduced. In addition, each of the test carriers is easily displaced from the predetermined position during the reflow, so that the relative positions of the test carriers after welding cannot correspond to the bearing interface, or cannot correspond to the waiting object (such as probe testing). The relative position of the electrical contacts of the probe on the seat 11A; if the probe test seat 11A 勉 emphasizes the displacement of the test carrier during the welding, it is bound to cause the probe of the connected probe The height of the measuring end is uneven. In this way, when the probe is disposed, the space converter must further adjust the position and flatness of the probe by using the adjustment mechanism, thereby increasing the complexity of the process of the probe card/probe test socket.

3. The process is complicated and difficult to control: mainly in the welding method to construct the electrical contact between the test carrier 10A and the load-bearing interface seat 16A, so that the test carrier, the load-bearing interface seat and the probe test seat must be in the process. Control the corresponding flatness, increase the complexity of process rework, and control the difficulty. Even, it is conventional to form a test panel formed by soldering, resulting in a reduction in the area of the connection point between the layers. When there is a drop in the position of the test panel seat and the actual die point, if the re-reflow is removed, the problem of desoldering is caused. Specifically, the solder ball material will be inconsistent due to the high temperature of the soldering, and then the ball must be re-planted after the tin is sucked, so that there will be another thermal shock problem.

Therefore, in the era of precision, speed and meager profit, in order to reduce the test cost, it is necessary to propose a test interface device that can apply multiple die tests, and improve the quality and performance of electrical transmission, reduce the problem of signal interference, and is easy. In order to become the mainstream multi-die test interface module and its manufacturing method, it can be established and controlled.

An object of the present invention is to provide a multi-die test interface module and a method of fabricating the same, and more particularly to integrating a plurality of carrier boards into a thin test interface module to solve the problem of affecting high-frequency signal transmission in the prior art. technical problem. And through the fan-out wiring process of the test interface module, the thickness of the signal fan is reduced, and the transmission path is shortened, so as to provide a test of a plurality of crystal grains at a time (in one test, a single crystal is expanded into a multi-die) , providing efficient test results.

Another object of the present invention is to provide a multi-die test interface module and a method for fabricating the same, which solves the technical problems in the prior art that the soldering is connected, affecting the probe test suite assembly and the process is complicated and difficult to control.

In order to achieve the above object, an aspect of the present invention provides a method for manufacturing a multi-die test interface module, comprising the steps of: providing a substrate; forming a through hole penetrating the surface of the substrate; and inserting a package carrier in the through hole of the substrate Forming a dielectric layer on the surface of the substrate and the through hole, the dielectric layer covering the package carrier; forming a connection hole at the dielectric layer; forming a conductive plating layer in the dielectric layer and the connection hole And brushing the conductive plating layer to at least retain a conductive plating layer corresponding to the position of the connecting hole to form a line conductor, and the line conductor is electrically connected to the package carrier through the connecting hole.

Another aspect of the present invention provides a method of fabricating a multi-die test interface module, comprising the steps of: providing a substrate; forming a through hole penetrating the first surface and the second surface of the substrate; and inserting the through hole in the substrate Forming a carrier layer; forming a first dielectric layer covering the first surface of the substrate, and forming a second dielectric layer covering the second surface of the substrate, and the through hole is filled with a dielectric layer, the dielectric layer package Overlying the package carrier; and depending on the wiring or pattern on the package carrier, Forming a connection hole in the first dielectric layer and the second dielectric layer; forming a conductive plating layer in the first dielectric layer and the second dielectric layer and the connection hole; brushing the conductive plating layer, at least retaining a first conductive plating layer corresponding to a position of the connection hole of the first dielectric layer, and a second conductive plating layer corresponding to a position of the connection hole of the second dielectric layer; and forming a first line conductor corresponding to the first conductive plating layer, and A second line conductor having a size larger than the first line conductor is formed corresponding to the second conductive plating layer.

In accordance with the above-described embodiments of the present invention, the substrate is made of a rigid material, including fiberglass, glass, ceramic, rigid particles, tantalum carbide or sapphire substrates. The through holes are made by etching or machining or electric discharge machining, and are plural, in order to assemble the package carrier.

According to the above embodiment of the present invention, in the step of forming a dielectric layer on the surface of the substrate and the through hole, the height of the dielectric layer on the surface of the substrate is higher than the metal measurement point on the package carrier. The package covers the package.

According to the above embodiment of the present invention, the top surface and the bottom of the package carrier in the substrate are provided with metal measuring points, and the dielectric layer is higher than the height of the metal measuring point or the bottom metal measuring point of the top surface of the package carrier. Its system is 50um.

According to the above embodiment of the present invention, in the step of performing the brushing of the conductive plating layer, the conductive plating layer formed on the outer surface of the substrate is subjected to a brushing and leveling process, and the brushing and leveling process can be brushed and finished according to actual needs. The thickness required for the multi-die test interface module.

According to the above embodiment of the present invention, the line guiding system is obtained by an additive method, and can be made of different sizes according to actual needs, so that the die to be tested is filled with the conductive plating layer through the connecting hole through the line conductor. The metal measuring points of the package carrier form an electrical connection.

A further aspect of the present invention provides a structural design of a multi-die test interface module, comprising: a substrate provided with a through hole; and a plurality of package carrier plates embedded in the through hole of the substrate; a dielectric layer is disposed on the surface of the substrate and the through hole; a connection hole is disposed on the dielectric layer; at least one conductive plating layer is disposed on the dielectric layer and the connection hole; and the line conductor And disposed at a position corresponding to the connection hole, the line conductor is electrically connected to the package carrier through the connection hole.

According to still another aspect of the present invention, a structural design of a multi-die test interface module includes: a substrate having a through hole extending through the first surface and the second surface of the substrate; and a plurality of package carriers mounted on the substrate The first dielectric layer is disposed on the first surface of the substrate, the second dielectric layer covers the second surface of the substrate, and the first dielectric layer and the second dielectric layer are correspondingly The through hole covers the package carrier; the connection holes are respectively disposed at the first dielectric layer and the second dielectric layer; the first conductive plating layer is disposed on the first dielectric layer corresponding to the position of the connection hole, a second conductive plating layer disposed on the second dielectric layer corresponding to the position of the connection hole; and a first line conductor disposed on the first conductive plating layer and corresponding to the connection hole position, and the second line conductor disposed on the second conductive plating layer And corresponding to the location of the connection hole, the second line conductor size is larger than the first line conductor size.

According to the above embodiments of the present invention, the dielectric layer comprises more than two dielectric layers, and further comprises an extended size line conductor between the two dielectric layers.

The multi-die test interface module of the present invention has the following effects; a plurality of through-holes are formed in the rigid substrate, and the through-holes can be used to embed a plurality of package carriers, and then through the dielectric layer and the cloth holes Steps such as conductive plating, brushing, and fan-out wiring of the signal are integrated into a thin test interface module, which reduces the thickness of the signal fan and shortens the transmission path, thereby solving the problem that the test interface panel needs to be soldered in the prior art. The technical problem that the thickness of the finished product becomes thick and the high-frequency signal transmission performance is deteriorated. Moreover, the present invention can improve the electrical performance of Signal Integration (SI) and Power Integration (PI) on the test interface panel, and is suitable for applications of high frequency and high speed testing. Furthermore, the present invention can improve the bonding strength of the line and the reliability of the line. In addition, it can also improve the flatness of the test interface module, which is beneficial to the probe test set assembly, and also contributes to the improvement of the yield of the product process.

Furthermore, in the embodiment of the present invention, by extending the wiring process of the line conductor of the test interface module, the position of the measuring point can be made to conform to the position of the actual grain measuring point, and the connection is not required by welding, and the conventional influence can be solved. Thermal shock resistance of assembly. Therefore, the present invention can be manufactured by the above-mentioned manufacturing as long as it has a plurality of carrier boards or package carrier boards, and each of the carrier boards is provided with a metal measuring point or a circuit having a circuit or a pattern as a measuring point. The method (process) integrates a plurality of carrier boards into a thin test interface module or a space conversion module, which facilitates the fan-out wiring process of the test interface module, thereby reducing the thickness of the signal fan opening, thereby shortening the transmission path. In order to provide a test of many grains at a time, it is possible to expand a single crystal into a multi-grain in one test, providing high-efficiency test efficiency.

10A‧‧‧ test carrier

101A‧‧‧conductive bumps

11A‧‧‧ probe test seat

111A‧‧‧Probe

13A‧‧‧Test mobile stage

14A‧‧‧ grain

141A‧‧‧Measurement points

15A‧‧‧Test Interface Motherboard

151A‧‧‧ connection pad

16A‧‧‧ Carrying interface seat

161A‧‧‧Metal connection pad

2, 2'‧‧‧ test interface module

20‧‧‧Rigid substrate

21‧‧‧through holes

22‧‧‧Configure the groove

30‧‧‧Package carrier

31‧‧‧Metal measuring points

40‧‧‧ dielectric layer

41‧‧‧First dielectric layer

42‧‧‧Second dielectric layer

44‧‧‧connection hole

45‧‧‧First connection hole

46‧‧‧Second connection hole

45'‧‧‧ first connection hole filled with conductive plating

46'‧‧‧Second connection hole filled with conductive plating

50‧‧‧ Conductive coating

51‧‧‧First conductive coating

52‧‧‧Second conductive coating

51'‧‧‧First conductive coating (such as the bottom conductive trace pattern)

52'‧‧‧Second conductive coating (such as top conductive trace pattern)

71, 71'‧‧‧ First line conductor

72‧‧‧Second line conductor

Figure 1 shows a schematic diagram of a conventional single-die test architecture.

Figure 2 shows a schematic of a conventional multi-die test architecture.

3A-3H are schematic flow charts showing the manufacturing method of the multi-die test interface module of the present invention.

Figure 4 is a block diagram showing the structure of the multi-die test interface module of the present invention.

Figure 5 is a top plan view of the multi-die test interface module of the present invention.

Figure 6 is a partial cross-sectional view showing the multi-die test interface module and the die set in the present invention.

Figure 7 shows the multi-die test interface module as a vertical detection structure and more in the present invention. A schematic diagram of the formation of individual grains.

The present invention will be further described in detail below with reference to the drawings and embodiments. The article "a" or "an" is used in the claims Also, in the figures, elements that are structurally, functionally similar or identical are denoted by the same reference numerals.

First, the present invention is fabricated on a rigid and flat substrate material through a plurality of through holes for embedding a plurality of package carriers. When the size of the carrier is to be packaged, a plurality of through holes are first formed by etching or machining or electrical discharge machining. There are many ways for the package carrier to be disposed in the through hole. Specifically, after the carrier is loaded with a rigid substrate and the plurality of package carriers are aligned correctly, the package carrier can be buried and positioned. Throughout the hole, it is advantageous to carry out the subsequent step of adding the dielectric material and the like, but the above configuration is not limited. Furthermore, the height of the rigid substrate, in particular, is the same as the height of the exposed metal measuring points on the package carrier, or slightly higher, but is not limited to the aforementioned height design.

In addition, in the present invention, the package carrier can be a single-die carrier, and the number and spacing of the metal measuring points on the bottom and top surfaces of the package carrier are only convenient for the description of the present invention, and are not limited, as long as A plurality of carrier boards are provided, and each of the carrier boards is provided with a metal measuring point or a circuit with a circuit or a pattern as a measuring point, and the plurality of carrier boards can be integrated and integrated by the manufacturing method (process) of the present invention. Forming a thin test interface module or a space conversion module facilitates the fan-out wiring process of the test interface module. Moreover, after the plurality of package carriers 30 are configured in the final process step, the two sides of the package are supported by a rigid substrate, wherein only thickness control of the layering step is required, that is, effective control The thickness of the integrated system is reduced to reduce the thickness of the signal, thereby shortening the transmission path to provide a test of many grains at a time, providing high efficiency test efficiency.

Please refer to FIGS. 3A-3H for a schematic flow chart showing a method of manufacturing the test interface module of the present invention.

First, as shown in FIG. 3A, a substrate 20 is provided. The substrate 20 is a hard (rigid) and flat material. In this embodiment, an organic substrate of glass fiber, glass, and silicon carbide can be used. SiC), ceramic (Ceramic), sapphire substrate (Sapphire) and the like.

As shown in FIG. 3B, one or a plurality of through holes 21 are formed, and the through holes 21 penetrate the first surface (the surface) and the second surface (the upper surface) of the rigid substrate 20. According to the characteristics of the material, the through hole 21 can be formed by wet drilling or dry drilling to achieve the upper and lower conduction results. Wet drilling can be performed, for example, by chemical etch, sensitization, etc.; dry drilling can be performed, for example, mechanical drilling, laser drilling, plasma drilling, sand blasting, ultrasonic drilling, and discharging. Processing and so on. The foregoing is illustrative only, but not limiting.

As shown in FIG. 3C, the package carrier 30 is built in the through hole 21 of the rigid substrate 20. Specifically, the packaged carrier 30 is completed in the through hole 21, and the height of the metal measuring point 31 exposed by the package carrier 30 can be the same as that of the rigid substrate 20, but is not limited. In this step, the package carrier can be a single die carrier, or other carrier, as long as each carrier is exposed with a metal measuring point or a circuit with a line or a pattern can be used as a measuring point. The interior has a fine wiring design that is sufficient to transmit signals.

As shown in FIG. 3D, it is a build-up step; forming a build-up layer 40 on the first surface (such as the surface) and the second surface (such as the surface) of the rigid substrate 20, respectively, to form a first layer on the first surface. The dielectric layer 41 forms a second dielectric layer 42 on the second surface. Dielectric produced by the layering method The layer 40 is also filled in the through holes 21 and covers the package carrier 30. Specifically, the dielectric layer produced by the build-up method in the present invention can be produced by thermal compression bonding, coating, sputtering, or atomic layer deposition (ALD) of the PCB. The insulating material may be a solid (such as a dry dielectric material, a target), or a liquid material (such as a wet dielectric material). In the step of forming a dielectric layer mainly on the surface of the rigid substrate and the through hole, the height of the dielectric layer on the surface of the rigid substrate is higher than the metal measuring point on the package carrier to cover The package carrier.

In this step, the first dielectric layer 41 covers the first surface, and after the second dielectric layer 42 covers the second surface, the dielectric layer 40 is slightly higher than the height of the metal measuring point 31 of the top surface of the package carrier 30 ( Or the height of the metal measuring point 31 on the bottom surface, generally no more than 50um (ie, ≦50um). Therefore, the first dielectric layer 41 and the second dielectric layer 42 covered by the lower and upper surfaces of the rigid substrate 20 are only increased by about 100 um to the metal measuring points 31 of the bottom and top surfaces of the package carrier 30. In other words, the arrangement of the plurality of package carriers 30 is mainly supported by the rigid substrate 20 on both sides thereof, and only the thickness control of the layering step is required, that is, the thickness after integration is effectively controlled.

As shown in FIG. 3E, it is a cloth hole step; a connection hole is formed at the first dielectric layer 41 and the second dielectric layer 42. In this step, the first connection hole 45 (located on the bottom surface) and the second connection hole 46 (located on the top surface) are mainly used to respectively serve the first dielectric layer 41 and the second dielectric layer 42. The metal measuring points 31 are connected to the bottom surface and the top surface of the package carrier 30. The first and second connecting holes 45, 46 are formed by a wet etching (such as chemical etch) or dry etching (such as laser, plasma, sand blasting, ultrasonic, electric discharge machining, etc.). Made by the way.

As shown in FIG. 3F, it is a conductive plating step; the first dielectric layer 41 and the second dielectric layer 42 are covered with a conductive plating layer 50, and conductive layers are formed in the first and second connection holes 45, 46, respectively. The plating layer 50, that is, the first and second connection holes 45', 46' filled with the conductive material (see the 3G) FIG.) is mainly used to electrically connect the conductive plating layer 50 with the metal measuring points 31 (see FIG. 3G) on the package carrier 30. In the foregoing case, the first and second conductive-filled connection holes 45', 46' can also be electrically connected to the metal line conductor or metal layer on the conductive plating layer 50, and can also be used to connect the metal layer and be located at the most Metal pad on the outer layer. In this step, the conductive plating layer 50 is formed on the exposed surface of the dielectric layer 40 and in the first and second connection holes 45, 46. A possible fabrication method of the conductive coating 50 is to first deposit a thin electrode layer on the wall surface of the dielectric layer 40 and the connection holes 45, 46 by sputtering, and then place the rigid substrate 40 in the electrolyte for oxidation. The electrolysis is reduced to form the electroconductive plating layer 50. Regarding the production of the conductive plating layer 50, an ion plating film, an electroless plating film, or a general chemical displacement deposition method may be employed.

As shown in FIG. 3G, the brushing and flattening step is performed on the first surface and the second surface of the rigid substrate 40, that is, the first surface and the second surface are referenced to be higher than the first surface. The conductive coating 50 on the second surface is brushed to a thin layer and flattened to its flatness. In this way, the flatness of the board surface can be better controlled, which will be more helpful for the assembly effect of subsequent test applications. In this step, for example, the first conductive via 51' corresponding to the first dielectric layer 41 is left to form a first conductive plating layer 51' (such as a bottom conductive trace pattern), and a second connection corresponding to the second dielectric layer 42 is formed. The location of the aperture 46 forms a second conductive coating 52' (e.g., a top conductive trace pattern). The first conductive plating layer 51' and the second conductive plating layer 52' respectively correspond to the positions of the metal measuring points 31 of the bottom and top surfaces of the package carrier 30 in the rigid substrate 20, and are electrically connected to each other.

As shown in FIG. 3H, it is a wiring step; the first line conductor 71 is formed at a position corresponding to the first conductive plating layer 51', and the size is formed larger than the first line conductor 71 at a position corresponding to the second conductive plating layer 52'. The second line conductor 72, wherein the spacing between the first line conductors 71 is also less than the spacing between the second line conductors 72. Therefore, as shown in Figure 5, the aforementioned process steps A plurality of carrier boards can be integrated to form a thin test interface module 2. In this step, the first line conductor 71 can also be fabricated by an additive method (or subtraction method), and can be made of different sizes according to actual needs. In addition, when the line conductor is located between the two dielectric layers 41, 41, the size of the line conductor can be increased according to actual needs. The above-mentioned addition method (or subtraction method) is a conventional production method, and therefore will not be further described herein.

As shown in FIG. 4, the first line conductor 71 of the test interface module 2 has a small size and pitch for connection to the probe 111A on the probe test stand 11A. The second line conductor 72 has a large size and spacing for connection to a contact of a printed circuit board (not shown), thereby achieving a space conversion effect by the thin test interface module 2. In addition, the package carrier of the present invention is a single-grain carrier, and may also be a carrier having an exposed metal measuring point or a circuit having a line or a pattern as a measuring point (with a fine circuit design inside). The plurality of carrier boards can be integrated into a thin test interface module 2 by the manufacturing method of the present invention, which facilitates testing the fan-out wiring process of the interface module 2, thereby reducing the thickness of the signal fan opening, thereby shortening the transmission path. Provides testing of many grains at a time, which can be expanded into multiple grains by testing a single grain at a time, providing high efficiency test efficiency.

The number of layers for the build-up step described above is described by making the upper and lower layers, that is, the number of the first dielectric layer 41 and the second dielectric layer 42 is exemplified by one layer. It can be understood that the first dielectric layer 41 and the second dielectric layer 42 can each comprise more than one dielectric layer. Generally, the number of the second dielectric layers 42 only needs one to two dielectric layers, and when the first dielectric layer 41 needs to be converted into a small size to a large size (or a large size to a small size) The number of dielectric layers is relatively large, and a plurality of dielectric layers can be disposed according to actual needs. As shown in FIG. 6 and FIG. 7, the first line conductor can be connected between the adjacent upper and lower dielectric layers 41, 41 in the above wiring step. The 71' is extended in size to form a metal-like or metal-like line as part of the circuit (as shown in Figures 6 and 7). However, if there are other application requirements (such as adding signal path measurement points or tuning circuits) when actually testing, it is possible to increase the number of layers or modify the circuit design to meet the demand. That is, for the above-mentioned layering step, the cloth hole step, and the wiring step, the number of layers is increased correspondingly (the number of the layer-adding steps is increased), the number, position and mode of the adjacent upper and lower layers are modified, and the phase is modified. The number of adjacent upper and lower electrical wirings is designed in relation to the position and the like, but basically does not deviate from the steps of the above manufacturing method.

That is, in the above wiring step, when the position of the metal measuring point 31 of the package carrier 30 is different from the position of the measuring point 141A of the actual die 14A, the line conductor is located between the two dielectric layers 41, 41. The size can be increased according to actual needs. Referring to FIG. 6, when the position of the measuring point of the first line conductor is different from the position of the measuring point 141A of the actual die 14A, the first line conductor 71' extended to a large size may be performed in the wiring step, that is, The electrical contact can be smoothly achieved by smoothly meeting the position of the measuring point 141A of the actual die 14A.

As described above, the present invention is described by forming the line conductors (i.e., the first line conductor 71 and the second line conductor 72) on both the bottom and the top of the rigid substrate 20, but it is also possible only for the first of the small scales. The line conductor 71 is modified into a second line conductor of a large size in the above-described wiring step, and the first line conductor is omitted. The second line guidance system can be used to construct the line or fan-out line required for space conversion. That is to say, some parts of the first line conductor and the second line conductor are used to construct a line or fan-out line required for space conversion, so that the bottom and top sides of the rigid substrate 20 can be fully utilized. The line conductor is used as the line Fan-out, which can also greatly reduce the number of layers and effectively reduce the thickness of the board.

Furthermore, as shown in FIG. 7, when the test interface module of the present invention is used as a vertical probe When the measuring structure and the plurality of crystal grains are assembled, the position of the metal measuring point 31 of the package carrier 30 and the position of the measuring point 141A of the actual die 14A fall, and only the top surface of the test interface module 2 is to be tested in the wiring step. A line conductor 71' is made to be elongated and large-sized, and then sequentially added with a step of adding a layer to form another first dielectric layer 41, and a step of forming a hole to form another first connecting hole 45' filled with a conductive substance, A conductive plating and brushing flattening step forms another first conductive plating layer 51', and a wiring step forms another first line conductor 71, thus rapidly forming a vertical multi-die detecting test interface module 2'. Finally, the test performance of the electrical contact is achieved by smoothly matching the position of the plurality of measuring points 141A of the actual multi-die 14A with the uppermost first line conductor 71 (as shown in FIG. 7).

The present invention also provides a structural design of the test interface module 2 that can be made using the method described above. As shown in FIG. 4 and FIG. 5 , the test interface module 2 of the present invention comprises: a rigid substrate 20 , one or more through holes 21 provided with a plurality of package carriers 30 , and at least one first dielectric The layer 41, the second dielectric layer 42, the plurality of connection holes 44, the at least one conductive plating layer 50' subjected to the conductive plating and the brushing and flattening step, the first line conductor 71 and the second line conductor 72.

The through hole 21 is provided with one or more, and each through hole 21 penetrates through a first surface (such as a bottom surface) of the rigid substrate 20 and a second surface (such as a top surface). The depth of the through holes 21 is sufficient for the package carrier 30 to be located therein, and the plurality of package carriers 30 are placed in the through holes of the rigid substrate (as shown in FIG. 5) to expose the metal points of the package carrier 30. The height of 31 may be the same as or slightly lower than the rigid substrate 20.

The first dielectric layer 41 is disposed on the first surface of the rigid substrate 20, and the second dielectric layer 42 is disposed on the second surface of the rigid substrate 20, and the first dielectric layer 41 and the second dielectric layer 42 are Corresponding to the through hole 21 and covering the metal measuring points 31 on the bottom and top surfaces of the package carrier 30, the first dielectric layer 41 (or the second dielectric layer 42) is slightly higher than the metal surface of the package carrier 30. Point 31 height (or top surface) The height of the metal measuring point 31), that is, no more than 50um (ie, 50um), therefore, the first dielectric layer 41 and the second dielectric layer 42 only have metal points on the bottom/top surface of the package carrier 30. 31 is only about 100um in total. That is, after the plurality of package carriers 30 are placed in the through holes 21 and the first and second dielectric layers 41 and 42 are added, the package carrier 30 is mainly rigidly supported by the rigid substrate 20. And the first dielectric layer 41 and the second dielectric layer 42 are respectively provided with a first connection hole 45 (located on the bottom surface) and a second connection hole 46 (located on the top surface) for respectively serving the first dielectric layer The layer 41 and the second dielectric layer 42 penetrate and communicate with the metal measuring points 31 of the bottom surface and the top surface of the package carrier 30.

The at least one conductive plating layer 50' that has undergone the conductive plating and the brushing and flattening step is provided with a first conductive plating layer 51' on the first dielectric layer 41 and the second dielectric layer 42 as shown in FIG. 3G. (such as the bottom conductive trace pattern), the second conductive plating 52' (such as the top conductive trace pattern), and the first conductive plating 51' (such as the bottom conductive trace pattern), the second conductive plating 52' (such as the top conductive The line patterns respectively correspond to the positions of the first connection hole 45' filled with the conductive material and the second connection hole 46' filled with the conductive material. The first conductive plating layer 51' and the second conductive plating layer 52' also correspond to the positions of the metal measuring points 31 of the bottom and top surfaces of the package carrier 30 in the rigid substrate 20, and can respectively pass through the first filled conductive material. The connection hole 45' is located at the second connection with the conductive substance connection hole 46' and is electrically connected to the metal measuring point 31 of the bottom and top surfaces of the package carrier 30.

For the cooperation, as shown in FIG. 3G and FIG. 3H, the first line conductor 71 is formed on the first conductive plating layer 51' (such as the bottom conductive circuit pattern) and corresponds to the first filling hole 45' filled with the conductive material. The second line conductor 72 is formed on the second conductive plating 52' (such as the top conductive wiring pattern) and corresponds to the position of the second insulating material-filled connection hole 46'. The size of the second line conductor 52 is larger than the size of the first line conductor 51, and the spacing between the second line conductors 52 is also greater than the spacing between the first line conductors 51. The first line conductor 51 is used for the probe test seat 11A (with probe 111A) is connected and second line conductor 52 is used to connect to a contact of a printed circuit board (not shown). The test interface module 2 is made to achieve space conversion efficiency as a test. The test interface module 2 of the present invention integrates a plurality of package carrier boards into a thin test interface module through the above structure, thereby reducing the thickness of the fan-opening, thereby shortening the transmission path, and providing a test of a plurality of crystal grains at a time. It can be expanded into multiple grains by testing a single grain at a time, providing a highly efficient test effect.

In one embodiment, the package carrier 30 disposed on the test interface module 2 should be a single die carrier, or a carrier or board with exposed metal dots 31 having a line or a pattern. The carrier board can be used as a measuring point (with a fine circuit design inside), and a plurality of carrier boards can be integrated into a thin test interface module 2 (or a space conversion module) through the manufacturing method (process) of the present invention.

In one embodiment, as shown in FIG. 6, it shows a partial cross-sectional view of the test interface module and the die assembly in the present invention. When the position of the metal measuring point 31 of the package carrier 30 and the position of the measuring point 141A of the actual die 14A are dropped, that is, the measuring position of the first line conductor 71 of the test interface module 2 and the actual die 14A are measured. When the position of the point 141A is different, the first line conductor 71' can be designed to be extended by the above-mentioned wiring step (that is, the different sizes are extended according to actual needs), and the position of the measuring point 141A of the actual crystal grain 14A can be smoothly matched to achieve electric power. Sexual contact.

In an embodiment, as shown in FIG. 7, it shows a schematic diagram of the test interface module of the present invention as a vertical detection structure and a plurality of crystal grains. When the position of the metal measuring point 31 of the package carrier 30 and the position of the measuring point 141A of the actual die 14A fall, the at least one first dielectric layer 41 of the test interface module 2 further includes two first dielectrics. The layers 41, 41 and the test interface module are disposed between the two first dielectric layers 41, 41 to extend the large-sized first line conductor 71'. The body is similar to a metal layer or a metal line as part of the circuit. In the figure, in order to match the actual positions of the plurality of measuring points 141A of the plurality of die 14A, a plurality of first lines extending in different sizes are provided between the two first dielectric layers 41. The conductor 71' (ie, different sizes are extended according to actual needs), and another first dielectric layer 41 filled with a conductive material is sequentially disposed on the uppermost first dielectric layer 41, and a conductive plating layer and a brush are provided. Another first conductive plating layer 51' and another first line conductor 71 are grounded, so that the test interface module 2' (or space conversion module) integrated into a vertical multi-die detection can be quickly constructed. Finally, the first line conductor 71 at the top is smoothly matched with the actual positions of the plurality of measuring points 141A of the plurality of crystal grains 14A to achieve electrical contact, thereby providing high test efficiency.

That is, as described above, for the vertical detecting structure, the present invention is mainly to embed a plurality of package carriers in a rigid substrate configuration, and in this manner, the plurality of package carriers 30 are disposed with the two ends thereof The rigid substrate 20 is supported as a support, and the thickness thereof can be reduced, and then designed by means of a dielectric layer and a cloth hole, a conductive plating layer, a brushing flattening, and a wiring of a line conductor, through which the line conductor passes. The package carrier is electrically connected to form a basic thin test interface module 2. If there are other application requirements (such as adding signal path measurement points, or tuning circuit) in actual testing, it is possible to increase the number of layers or modify the circuit design to meet the demand. That is, for the above-mentioned layering step, the cloth hole step, and the wiring step, the number of layers is increased correspondingly (the number of the layer-adding steps is increased), the number, position and mode of the adjacent upper and lower layers are modified, and the phase is modified. The number of adjacent upper and lower electrical wirings is designed in relation to the position and the like, but basically does not deviate from the steps of the above manufacturing method. Referring to FIG. 7, the structural design is such that when the number of layers is increased, the basic type thin test interface module 2 is required to extend the top line of the first line conductor 71 in the wiring step, and then Add another thin first dielectric layer 41 (controllable thickness) a first connection hole 45' filled with a conductive material, another first conductive plating layer 51', and another first line conductor 71, thus rapidly forming a test interface mode for vertical multi-die detection Group 2'. Finally, the test performance of the electrical contact is achieved by smoothly matching the position of the plurality of measuring points 141A of the actual multi-die 14A with the uppermost first line conductor 71 (as shown in FIG. 7). By analogy, it is possible to add multiple layers. In this way, the overall thickness can be effectively controlled to construct a test interface module 2' (or space conversion module).

The present invention has the following advantages: the multi-die test interface module of the present invention has a plurality of package carrier plates embedded in a rigid substrate, and in this manner, the plurality of package carrier plates 30 are disposed, and the two sides thereof are made by the rigid substrate 20 For the support, the dielectric layer is electrically connected to the package carrier through the connection hole through the dielectric layer and the hole, the conductive coating, the brushing and the line conductor, wherein only the thickness adjustment step is performed. That is, it can effectively control the thickness of the integrated integrated body, so that it can be integrated into a thin test interface module (or space conversion module), thereby reducing the thickness of the signal fan, thereby shortening the transmission path to provide a plurality of times. The test of the crystal grains can be expanded into a single crystal by a single crystal in one test, providing a high-efficiency test effect. Even better, improve the signal integrity (SI) and power integrity (PI) electrical performance on the multi-die test interface module under the path of shortening the signal transmission, providing better performance. Electrical quality is also in line with high-frequency high-speed test applications. The invention effectively reduces the overall thickness and thickness, reduces the inductance response, and improves the electrical performance, thereby being able to solve the problem that the high-inductance of the test interface panel in the prior art or the influence of the conventional reflow is performed to interfere with the high-frequency signal transmission. technical problem. Moreover, since the transmission path of the power source is shortened, the need to place a capacitor in a long path can be reduced, and the problem of placing a capacitor to increase the number of layers and causing high inductance is avoided, and further, the conventional feedback can be reduced. The impact of welding also avoids problems such as complicated process and difficult to control.

Furthermore, the present invention integrates a plurality of package carrier structures into a test interface module in an embedded arrangement manner, which can solve the conventional problem of multiple solder joints, and the processing time is shorter. In addition to improving the bonding strength of the line and the reliability of the line, it also contributes to the convenience and yield improvement of the product, and is more capable of improving the competitiveness in response to the rapidly developing semiconductor testing needs.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention. Those skilled in the art can make various changes without departing from the spirit and scope of the present invention. And the replacement, equivalent replacement, still fall within the scope of the patent protection of the present invention.

Claims (22)

A method for manufacturing a multi-die test interface module includes the steps of: providing a substrate; forming a through hole penetrating the surface of the substrate; placing a package carrier on the through hole of the substrate; and a surface of the substrate and the through hole Forming a dielectric layer, the dielectric layer covering the package carrier; forming a connection hole at the dielectric layer; forming a conductive plating layer in the dielectric layer and the connection hole; and brushing the conductive plating layer, At least the conductive plating layer corresponding to the position of the connecting hole is formed to form a line conductor, and the line conductor is electrically connected to the package carrier through the connecting hole. The method of manufacturing a multi-die test interface module according to claim 1, wherein the substrate is made of a rigid material, including glass fiber, glass, ceramic, rigid particles, tantalum carbide fiber or sapphire substrate. The method for manufacturing a multi-die test interface module according to claim 1, wherein the through-holes are formed by etching or machining or electrical discharge machining, and are plural, to facilitate assembly of the package carrier. . The method for manufacturing a multi-die test interface module according to claim 1, wherein in the step of forming a dielectric layer on the surface of the substrate and the through hole, the dielectric is located on a surface of the substrate The height of the layer is higher than the metal measuring points on the package carrier to cover the package carrier. The method for manufacturing a multi-die test interface module according to claim 1, wherein a metal measuring point is disposed on a top surface and a bottom portion of the package carrier in the substrate, and the dielectric layer is slightly high. The height of the metal measuring point of the package carrier is um50um. The method for manufacturing a multi-die test interface module according to claim 1, wherein in the step of performing the brushing of the conductive plating layer, the conductive plating layer formed on the outer surface of the substrate is brushed and leveled. And the brushing and leveling process can be brushed and leveled according to actual requirements to the thickness of the multi-die test interface module. The method for manufacturing a multi-die test interface module according to claim 1, wherein the line guiding system is obtained by subtractive or additive method, and can be made according to actual needs. The die to be tested is electrically connected to the metal measuring points of the package carrier through the connection hole through the connection hole to fill the conductive plating layer. The method of fabricating a multi-die test interface module according to claim 1, wherein the dielectric layer comprises two or more dielectric layers, and the line conductor is formed on two adjacent dielectric layers. In the meantime, the system can be increased in size according to actual needs. A method for manufacturing a multi-die test interface module, comprising the steps of: providing a substrate; forming a through hole penetrating the first surface and the second surface of the substrate; inserting a package carrier in the through hole of the substrate; forming a The first dielectric layer covers the first surface of the substrate, and the second dielectric layer covers the second surface of the substrate, and the through hole is filled with a dielectric layer, and the dielectric layer covers the package carrier; Forming a connection hole in the first dielectric layer and the second dielectric layer; forming a conductive plating layer on the first dielectric layer and the second dielectric layer; and the connection layer; the first dielectric layer and the second dielectric layer The conductive plating layer on the electric layer is brushed to at least retain a first conductive plating layer corresponding to the position of the connecting hole of the first dielectric layer, and a connection corresponding to the second dielectric layer a second conductive plating layer at the hole position; and forming a first line conductor corresponding to the first conductive plating layer and a second line conductor having a size larger than the first line conductor corresponding to the second conductive plating layer. The method of manufacturing a multi-die test interface module according to claim 9, wherein the substrate is made of a rigid material, including glass fiber, glass, ceramic, rigid particles, tantalum carbide fiber or sapphire substrate. The method for manufacturing a multi-die test interface module according to claim 9, wherein the through-hole is formed by etching or machining or electrical discharge machining, and is plural, to facilitate assembly of the package carrier . The method for manufacturing a multi-die test interface module according to claim 9, wherein in the step of forming a dielectric layer on the surface of the substrate and the through hole, the dielectric is located on a surface of the substrate The height of the layer is higher than the metal measuring points on the package carrier to cover the package carrier. The method for manufacturing a multi-die test interface module according to claim 9, wherein a metal measuring point is disposed on a top surface and a bottom portion of the package carrier in the substrate, and the dielectric layer is slightly higher than The height of the metal measuring point of the package carrier is um50um. The method for manufacturing a multi-die test interface module according to claim 9, wherein in the step of brushing the conductive plating layer, the conductive plating layer formed on the outer surface of the substrate is brushed and leveled. And the brushing and leveling process can be brushed and leveled according to actual requirements to the thickness of the multi-die test interface module. The method for manufacturing a multi-die test interface module according to claim 9, wherein the first line conductor and the second line conductor system are obtained by subtractive or additive methods, and the second line conductor is obtained. The process steps of extending the size according to actual needs to facilitate the first line conductor and the second line The road conductors are filled with the conductive plating through the connection holes to form an electrical connection with the metal measuring points of the package carrier. The method of fabricating a multi-die test interface module according to any one of claims 1 to 15, wherein the package carrier can be a carrier having a circuit or a pattern as a measuring point on the board. A multi-die test interface module includes: a substrate provided with a through hole; a plurality of package carrier plates embedded in the through holes of the substrate; at least one dielectric layer disposed on the surface of the substrate and the through hole a hole, a connection hole disposed on the dielectric layer; at least one conductive plating layer disposed on the dielectric layer and the connection hole; and a line conductor disposed at the conductive plating layer and corresponding to the position of the connection hole The line conductor is electrically connected to the package carrier through the connection hole. The multi-die test interface module of claim 17, wherein the substrate is made of a rigid material, including glass fiber, glass, ceramic, rigid particles, tantalum carbide fiber or sapphire substrate. The multi-die test interface module of claim 17, wherein the at least one dielectric layer comprises two or more dielectric layers, and the line conductor is disposed between the adjacent two dielectric layers. The system can be designed to increase the size according to actual needs. A multi-die test interface module includes: a substrate, a through hole penetrating through the first surface and the second surface of the substrate; and a plurality of package carrier plates embedded in the through holes of the substrate; a first dielectric layer is disposed on the first surface of the substrate, and a second dielectric layer is disposed on the second surface of the substrate, and the first dielectric layer and the second dielectric layer are opposite to each other Covering the package carrier; the connection holes are respectively disposed at the first dielectric layer and the second dielectric layer; the first conductive plating layer is disposed on the first dielectric layer corresponding to the position of the connection hole, and the second conductive a plating layer disposed on the second dielectric layer corresponding to the location of the connection hole; and a first line conductor disposed on the first conductive plating layer and corresponding to the connection hole position, and a second line conductor disposed on the second conductive plating layer And corresponding to the location of the connection hole, the second line conductor size is larger than the first line conductor size. The multi-die test interface module of claim 20, wherein the substrate is made of a rigid material, including glass fiber, glass, ceramic, rigid particles, tantalum carbide fiber or sapphire substrate. The multi-die test interface module according to any one of claims 17 to 21, wherein the package carrier has an exposed metal measuring point, or the board has a line or a pattern as a measuring point. Carrier board.