TWI606770B - Ultra-fine pitch testing interposer and manufacturing method thereof - Google Patents

Description

Ultra-fine pitch test interface panel and manufacturing method thereof

The present invention relates to a probe card, and more particularly to an ultra-fine pitch (Ultra-Fine Pitch) test panel in a probe card and a method of fabricating the same.

The integrated circuit test is divided into Chip Probing (CP) and Final Test (FT), where CP is wafer level test and FT is package level test. It is difficult to test with CP. In particular, as the processing capability of semiconductors continues to increase, the reduction in wafer size or the increase in the density of metal pads on the wafers reduces the pitch of the metal pads, so the pitch of the probes must be further reduced in accordance with the spacing of the metal pads. In addition to the increase in measuring point density, the vertical probe card (Vertical Probe Card) is mainly used in the market.

The vertical probe card generally has a space transformer (ST), or a test interface panel, and a conductive contact with a large spacing on one side of the ST is electrically connected to a printed circuit board (PCB); ST On the other side, a conductive pad with a small pitch is connected to the probe, and the ST bit is between the wafer and the printed circuit board. The probe is in contact with the contact on the wafer, and the metal pad on the wafer can be arranged at a small pitch. Switch to a printed circuit board with a large pitch configuration.

The test interface panel (ie, ST) can be classified into a multilayer ceramic substrate (MLC) and a multilayer organic substrate (Multi-Layer Organic, MLO). In testing, it is generally tested with a single die (Single DUT) or a pair of die (Dual DUT), but when there are too many I/O points or multiple die (Multi DUT) test, ST The design becomes complicated, and the lines must be dispersed by increasing the number of layers. Multi-layer ceramic substrates (MLC) usually have a very high number of layers, and the finished product is relatively thick, and it is also disadvantageous for the signal and power integrity requirements of high-speed testing. Of course, it is expensive, so in the era of low profit, Reduce the cost of testing. At present, the test panel for micro-pitch/high-measurement points and multi-grain test is the mainstream of Thin Film Multi-Layer Organic (TF-MLO) test panels.

Figure 1 shows a schematic diagram of the architecture of a conventional TF-MLO test interface panel. The conventional TF-MLO test interface panel has a double-sided core substrate 10, which may be a multi-laminated core substrate having through holes 11 penetrating the upper and lower surfaces. The upper and lower surfaces of the core substrate 10 respectively form a build-up structure 12, 13 by a build-up method, and the contact holes 14 are formed by laser drilling in the build-up structures 12 and 13, and the contact holes 14 are filled with a conductive substance. The contact holes 14 in the build-up structures 12 and 13 on the upper and lower sides are electrically connected to each other through the conductive material formed in the through holes 11. The build-up structure 12 corresponding to the lower side is formed with a metal pad 15 which is connectable to the above mentioned printed circuit board through a solder ball. A thin film layer structure 16 is formed on the upper layer buildup structure 13. The thin film layer structure 16 includes a plurality of dielectric layers 17 and a metal layer 18 and a contact hole 19 formed by lithography, electroplating, etching, and the corresponding contact holes 19 are The surface of the film layer structure 16 is formed with a metal pad 20, which is fixed to the probe Connect to electrically test the wafer. As can be seen from Fig. 1, the element dimension of the film layer structure 16 is much smaller than that of the layered structures 12, 13, and the size and spacing of the metal pad 20 and the metal pad 15 are greatly different, thereby achieving space conversion. purpose.

The conventional TF-MLO test panel has the following drawbacks: In high frequency applications, the quality of the signal is greatly affected by the inductance. Due to the limitation of line width/pitch and micro-blind hole production, in order to multi-grain test, more layers are needed to divide the signal (Fan-out) in the circuit design. As the thickness of the product increases, more is generated. Inductance problem. Specifically, the calculation formula of the inductance is: Where L is the inductance, h is the plate thickness, and d is the aperture of the contact hole. It can be seen from the above formula that the influence on the inductance is dominated by the thickness of the board. The thicker the product, the larger the inductance, which may cause high-frequency signal distortion.

The micro-pitch is usually less than 80 μm. In the current line width/pitch fabrication capability, the number of lines that can pass between the micro-spacings is limited, which also results in the need for more layers to shunt signals, which also creates inductance problems. As shown in Figure 2, the line must span to another layer. On the other hand, in order to solve the problem of common electricity, a large number of capacitors are arranged, which also leads to an increase in the number of layers and an inductance problem.

In addition, in the evolution of line production, the wide line is subtracted and produced, and the fine line is made by addition, but to the fine line, in addition to reducing the line width (<15um), there must be a certain copper cross-sectional area. Since the current is carried, the bonding area (width) of the substrate is often reduced, which tends to cause peeling of the line, and relatively affects the reliability and yield of the product. As shown in Fig. 3, the joint surface of the line B and the substrate surface S The product is smaller than the joint area of the line A and the substrate surface S, and the line B is easily peeled off from the substrate surface S.

An object of the present invention is to provide an ultra-fine pitch (Ultra-Fine Pitch) test interface panel and a method for fabricating the same to solve the technical problem that the test interposer generates high inductance and affects high-frequency signal transmission in the prior art.

Another object of the present invention is to provide an ultrafine pitch test interface panel and a method of fabricating the same to solve the technical problem of easy stripping of narrow line width lines in the prior art.

In order to achieve the above object, an aspect of the present invention provides a method for fabricating an ultrafine pitch test interface panel, comprising the steps of: providing a rigid substrate; forming a through hole penetrating a surface of the rigid substrate; and forming a groove on the surface of the rigid substrate Forming a groove pattern; forming a conductive plating layer in the through hole and the groove; grinding the surface of the rigid substrate to remove a portion of the conductive plating layer formed on the groove, and forming a remaining conductive plating layer in the groove a wiring pattern; forming a dielectric layer covering the wiring pattern; forming a contact hole at the dielectric layer; and forming a metal pad at a position corresponding to the contact hole by exposure, development, and plating, and the metal pad passes through the contact hole The line pattern is electrically connected.

Another aspect of the present invention provides a method for fabricating an ultrafine pitch test interface panel, comprising the steps of: providing a rigid substrate; forming a through hole penetrating the first surface and the second surface of the rigid substrate; Forming a groove on the surface and the second surface, forming a first groove pattern on the first surface, forming a second groove pattern on the second surface; forming a conductive plating in the through hole and the groove a layer; a first surface and a second surface of the rigid substrate are ground to remove a portion of the conductive plating layer formed in the recess, and the remaining conductive plating layer forms a first line pattern in the first groove pattern, Forming a second line pattern in the second groove pattern; forming a first dielectric layer covering the first line pattern, and forming a second dielectric layer covering the second line pattern; at the first dielectric layer Forming a contact hole at the second dielectric layer; forming a first metal pad at a position corresponding to the contact hole of the first dielectric layer; and using a contact hole corresponding to the second dielectric layer by exposure, development, and plating The location forms a second metal pad that is smaller in size than the first metal pad.

A further aspect of the present invention provides an ultrafine pitch test interface panel comprising: a rigid substrate; a circuit pattern embedded under the surface of the rigid substrate, the exposed surface of the circuit pattern being on the same surface as the surface of the rigid substrate; a dielectric layer covering the circuit pattern; a contact hole formed at the dielectric layer; and a metal pad formed at a position corresponding to the contact hole, the metal pad being electrically connected to the circuit pattern through the contact hole.

According to still another aspect of the present invention, an ultrafine pitch test interface panel includes: a rigid substrate; a through hole penetrating through the first surface and the second surface of the rigid substrate, filled with a conductive plating layer; and a first circuit pattern embedded in the rigidity The exposed surface of the first line pattern is on the same surface as the first surface of the rigid substrate under the first surface of the substrate; the second line pattern is embedded under the second surface of the rigid substrate, the second line pattern The exposed surface is on the same surface as the second surface of the rigid substrate, and the second circuit pattern is electrically connected to the first line pattern through the conductive plating layer in the through hole; a first dielectric layer covers the first line a pattern; at least one second dielectric layer, Covering the second line pattern; a contact hole formed at the first dielectric layer and the second dielectric layer; a first metal pad formed at a position corresponding to the contact hole of the first dielectric layer; and a second metal The pad is formed at a position corresponding to the contact hole of the second dielectric layer, and the size of the second metal pad is smaller than the size of the first metal pad.

The ultra-fine pitch test interface panel of the present invention is provided with an embedded circuit pattern on a rigid substrate, and the circuit pattern can be used to construct a fan-out line of the signal, thereby reducing the number of layers to be fanned out, the thickness of the board is thinned, and the inductance is reduced. Therefore, it is possible to solve the technical problem that the high-inductance of the test interface panel in the prior art affects the transmission of high-frequency signals. Moreover, the present invention improves the electrical performance of Signal Integration (SI) and Power Integration (PI) on the test interface panel, and is suitable for high-frequency high-speed test applications. Furthermore, the present invention not only improves the bonding strength of the line and the reliability of the line, but also contributes to the improvement of the yield of the product. In addition, in the embodiment of the present invention, since the Pitch is continuously reduced, the area of the connection point between the layers is reduced, which has affected the thermal shock resistance of the subsequent assembly. Therefore, the conductive bump is used instead of the solder ball to eliminate the need for the tin ball. The thermal shock problem caused by heat fusion.

10‧‧‧ core substrate

11‧‧‧through holes

12‧‧‧Additional structure

13‧‧‧Additional structure

14‧‧‧Contact hole

15‧‧‧Metal pad

16‧‧‧film layer structure

17‧‧‧Dielectric layer

18‧‧‧metal layer

19‧‧‧Contact hole

20‧‧‧Metal pad

40‧‧‧Rigid substrate

41‧‧‧through holes

42‧‧‧ Groove

43‧‧‧ Conductive coating

44‧‧‧through holes filled with conductive coating

45‧‧‧ line pattern

46‧‧‧First dielectric layer

47‧‧‧Second dielectric layer

48‧‧‧Contact hole

49‧‧‧First metal mat

50‧‧‧Second metal mat

51‧‧‧Anti-oxidation coating

52‧‧‧metal layer

60‧‧‧Superfine pitch test panel

61‧‧‧Electrical bumps

70‧‧‧Printed circuit board

71‧‧‧ solder mask

72‧‧‧Contacts

73‧‧‧ solder paste

81‧‧‧Support materials

82‧‧‧ screws

A, B‧‧‧ lines

S‧‧‧Substrate surface

Figure 1 shows a schematic diagram of the architecture of a conventional TF-MLO test interface panel.

Figure 2 shows a schematic diagram of fanning out signals to another layer in the prior art.

Figure 3 shows a schematic diagram of the relationship between line width and joint area.

4A to 4H are views showing a flow chart of a method of manufacturing the ultrafine pitch test interface panel of the present invention.

Fig. 5 is a view showing the structure of the ultrafine pitch test interface panel of the present invention.

6A and 6B are views showing the assembly of the ultrafine pitch test interface panel and the printed circuit board in the present invention.

The present invention will be further described in detail below with reference to the drawings and embodiments. The article "a" or "an" is used in the claims Also, in the figures, elements that are structurally, functionally similar or identical are denoted by the same reference numerals.

The invention is to make a buried circuit in a rigid and flat substrate material (Core), and to increase the thickness of the metal pad according to the requirement of the width and the narrow pitch of the metal pad, and to make the ultra-fine pitch in this way (Ultra) -Fine Pitch) Test panel or Space Transformer (ST). The buried circuit can perform finer circuit design and increase wiring density, thereby reducing the number of layers that need to fan-out the fan and reducing the thickness of the board, thereby solving the problem that the test panel is high in the prior art. Inductance affects the technical problem of high-frequency signal transmission.

Please refer to FIGS. 4A-4H for a schematic flow chart showing a method of manufacturing the ultrafine pitch test interface panel of the present invention.

First, as shown in FIG. 4A, a rigid substrate 40 is provided. The rigid substrate 40 is a hard and flat material, and may be made of glass, wafer, ceramic, or sapphire. Photosensitive glass (Photosensitivity Glass) and so on.

As shown in FIG. 4B, one or a plurality of through holes 41 are formed, and the through holes 41 penetrate the first surface (the surface) and the second surface (the upper surface) of the rigid substrate 40. The through hole 41 can be formed by wet drilling or dry drilling according to the characteristics of the material, and the result of the upper and lower conduction can be achieved. Wet drilling such as chemical etch can be used; dry drilling such as mechanical drilling, laser drilling, plasma drilling, sand blasting, ultrasonic drilling, electrical discharge machining, and photosensitive holes can be used. Wait.

As shown in FIG. 4C, grooves 42 are formed on the first surface and the second surface of the rigid substrate 40, and the grooves 42 constitute a first groove pattern on the first surface of the rigid substrate 40 and a second groove on the rigid substrate 40. The surface constitutes a second groove pattern, and the first groove pattern and the second groove pattern subsequently form a line pattern. The first surface and the recess 42 at the second surface may be formed by wet etching or dry etching, such as chemical etching, dry etching such as laser, plasma, sand blasting, ultrasonic, and discharge. Processing and photo-forming process, etc.

As shown in FIG. 4D, a conductive plating layer 43 is formed in the through holes 41 and the grooves 42, and in this step, the conductive plating layer 43 is formed on the exposed surface of the rigid substrate 40. A feasible method is to first deposit a thin electrode layer on the wall surface of the through hole 41 and the groove 42 by sputtering, and then put the rigid substrate 40 into the electrolyte to perform redox electrolysis to form the conductive plating layer 43. . Regarding the production of the conductive plating layer 43, an ion plating film, an electroless plating film, or a general chemical displacement deposition method may be employed.

As shown in FIG. 4E, flat grinding is performed on the first surface and the second surface of the rigid substrate 40, for example, based on the first surface and the second surface, The conductive plating layer 43 of the first surface and the second surface is removed by grinding, so that a part of the conductive plating layer formed on the groove 42 is removed, that is, the conductive plating layer 43 formed on the top of the groove 42 is removed by grinding, and the groove 42 is removed. The remaining conductive plating layer 43 forms a first line pattern 45 (such as a side conductive line) in the first groove pattern, and a second line pattern 45 (such as a side conductive line) is formed in the second groove pattern, first The line pattern 45 and the second line pattern 45 are embedded conductive lines. At this time, the first circuit pattern is embedded under the first surface of the rigid substrate 40, and the exposed surface of the first circuit pattern is on the same surface as the first surface (lower surface) of the rigid substrate 40; the second circuit pattern is embedded. Under the second surface (upper side surface) of the rigid substrate 40, the exposed surface of the second line pattern is on the same surface as the second surface of the rigid substrate 40. Further, as can be seen from FIG. 4E, the first line pattern and the second line pattern are electrically connected to each other through the conductive plating layer 43 in the through hole 41.

Next, as shown in FIG. 4F, layer formation is performed on the first line pattern and the second line pattern, a first dielectric layer 46 is formed on the first line pattern, and a second dielectric is formed on the second line pattern. Layer 47. The dielectric layers 46, 47 produced by the build-up method can be produced by thermal compression bonding, coating, evaporation, sputtering or atomic layer deposition (ALD) of the PCB, and the raw material can be gas ( Such as acetylene), solids (such as dry dielectric materials, targets) or liquids (such as wet dielectric materials).

As shown in FIG. 4G, a contact hole 48 is formed at the first dielectric layer 46 and the second dielectric layer 47. The contact hole 48 is filled with a conductive material, which is mainly used for connecting the upper and lower layers. The first line pattern and/or the second line pattern are electrically connected. In the case where the dielectric layer is a plurality of layers, the contact hole 48 can also be electrically connected to the dielectric layer. A metal layer or a metal line may also be used to connect the metal layer to the metal pad on the outermost layer. The hole-forming means of the contact hole 48 can be formed, for example, by wet etching (such as chemical etch) or dry etching (such as laser, plasma, sand blasting, ultrasonic, electric discharge machining, etc.).

As shown in FIG. 4H, a first metal pad 49 is formed at a position corresponding to the contact hole 48 of the first dielectric layer 46, and a first metal pad 49 is formed at a position corresponding to the contact hole 48 of the second dielectric layer 47. The spacing between the second metal pads 50 and the second metal pads 50 is also smaller than the spacing between the first metal pads 49. The second metal pad 50 can be formed by an additive method. Specifically, an electrode layer is first deposited on the exposed surface of the second dielectric layer 47 and the contact hole 48 by ion plating, electroless plating or general chemical displacement deposition; then a photoresist layer is coated on the electrode layer. Removing the photoresist corresponding to the predetermined position of the second metal pad 50 by exposure development, and leaving the remaining photoresist as a barrier layer; using Ferrari's law, placing the object to be plated on the cathode and plating in the acidic liquid chemical system Forming a plating layer on the electrode layer, which is a component of the second metal pad 50. The plating solution may include an additive composed of sulfuric acid, hydrochloric acid, copper metal, and organic substances; after that, the plating layer is ground and passed through a wet grinding method. In a manner, the grinding is performed by grinding particles having a smaller particle diameter, and a better coplanarity can be obtained. Finally, the remaining photoresist and the excess electrode layer (ie, the electrode not corresponding to the position of the second metal pad 50 are removed). Layer), that is, a second metal pad 50 is produced. The first metal pad 49 can also be fabricated in the same or similar manner, but with less precision requirements.

The second metal pad 50 has a small size and spacing for connection with the probe, and the first metal pad 49 has a large size and spacing for contact with the printed circuit board. The connection makes the test interface panel achieve the effect of space conversion.

The step shown in FIG. 4H further includes a surface treatment step of forming an oxidation resistant coating 51 on the first metal pad 49 and the second metal pad 50 to prevent the first metal pad 49 and the second metal pad 50 from being included. Oxidation in an oxygen atmosphere, this surface treatment step can be performed after the step of removing the remaining photoresist and the excess electrode layer, such as electroplating gold, chemical immersion gold, nickel-palladium gold, and electroplating ruthenium.

The number of layers in the above description is described above in layers, that is, the number of the first dielectric layer 46 and the second dielectric layer 47 is illustrated by one layer each. However, it will be appreciated that the first dielectric layer 46 and the second dielectric layer 47 may each comprise more than one dielectric layer. Generally, the number of the first dielectric layers 46 only needs one to two dielectric layers, and the second dielectric layer 47 has a relatively large number of dielectric layers due to the large-to-small size conversion. A multilayer dielectric layer may be disposed as needed, and a metal layer or a metal line may be formed between the two dielectric layers as part of the circuit.

Furthermore, in the above description, the circuit pattern (ie, the first line pattern and the second line pattern) is formed on both sides of the rigid substrate 40, but the second metal pad 50 may be formed only for the small ruler. The line pattern is omitted, and the first line pattern is omitted. The second line pattern can be used to construct a line or a Fan-out line required for space conversion, and of course, it can also extend through the through hole 44 to the first line pattern. That is to say, some portions of the first line pattern and the second line pattern are used to construct a line or a Fan-out line required for space conversion, so that the line pattern on both sides of the rigid substrate 40 can be fully utilized as the line Fan. -out, will be originally made between the dielectric layers The fan-out line is transferred to the line patterns on both sides of the rigid substrate 40, so that the number of layers can be greatly reduced, and the board thickness can be effectively reduced.

The present invention also provides an ultrafine pitch test interface panel that can be fabricated using the methods described above. As shown in FIG. 5, the ultrafine pitch test interface panel of the present invention comprises: a rigid substrate 40, one or more through holes 44 filled with a conductive material, a first line pattern, a second line pattern, and a first dielectric layer. 46. At least a second dielectric layer 47, a contact hole 48, a first metal pad 49, and a second metal pad 50. The through hole 44 penetrates the first surface (the side surface as below) and the second surface (the upper side surface) of the rigid substrate 40. The first line pattern and the second line pattern are embedded conductive lines, and the first line pattern is embedded under the first surface of the rigid substrate 40, and the exposed surface of the first line pattern is located on the first surface of the rigid substrate 40. On the same side, the second circuit pattern is embedded under the second surface of the rigid substrate 40, and the exposed surface of the second circuit pattern is on the same surface as the second surface of the rigid substrate 40. The first line pattern and the second line pattern are electrically connected to each other through the conductive material in the through hole 41. The first dielectric layer 46 and the second dielectric layer 47 respectively cover the first line pattern and the second line pattern, and the first dielectric layer 46 and the second dielectric layer 47 are formed with contact holes 48, contact holes. The 48 is filled with a conductive material, which is mainly used to connect the upper and lower layers, and is electrically connected to the first line pattern and/or the second line pattern. The first metal pad 49 is formed at a position corresponding to the contact hole 48 of the first dielectric layer 46; the second metal pad 50 is formed at a position corresponding to the contact hole 48 of the second dielectric layer 47. The size of the second metal pad 50 is smaller than the size of the first metal pad 49, and the spacing between the second metal pads 50 is also smaller than the spacing between the first metal pads 49. The second metal pad 50 is used to connect with the probe, and the first metal pad 49 is used for the printed circuit board. The joint connection makes the test interface panel achieve the effect of space conversion.

In one embodiment, the at least one second dielectric layer 47 of the test panel comprises at least two second dielectric layers 47. The test interface further comprises a metal layer or a metal line 52 formed on the two second layers. Between the electrical layers 47, it is used as part of the circuit.

The present invention has the following advantages: the ultra-fine pitch test interface panel of the present invention is configured with an embedded circuit pattern on a rigid substrate. In this way, the line pattern can be constructed with a narrower line width and a smaller blind hole aperture, thereby increasing The wiring density, this line pattern can be used to build the fan-out line of the signal, which can reduce the number of layers that need to be fanned out. As the number of layers becomes smaller, that is, the thickness of the board is thinner and the inductance is lowered, so that the technical problem that the high inductance of the test interposer generates high-frequency signal transmission in the prior art can be solved. Moreover, since the transmission path of the power supply is shortened, the requirement of placing a capacitor in a long path can be reduced, and the problem of placing a capacitor to increase the number of layers and causing high inductance is also avoided.

The invention can construct a fine line (Fine Line) and a micro blind hole structure on the line pattern on both sides of the rigid substrate, thereby providing higher wiring density, reducing the number of layers for fanning the signal, thereby shortening the path of signal transmission and improving the path. The electrical performance of Signal Integration (SI) and Power Integration (PI) on the ultra-fine pitch test panel provides better electrical quality and is also suitable for high-frequency high-speed test applications.

Furthermore, the embedded circuit structure can provide a joint area of at least 2 surfaces (inclusive), which not only improves the bonding strength of the line and the reliability of the line, but also contributes to the improvement of the yield of the product. In addition, due to the reduced number of layers, relative process time Shorter, it is more able to meet the needs of fast-growing semiconductor testing and enhance competitiveness.

In the ultra-fine pitch test interface panel of the present invention, since the test pitch (Pitch) is continuously reduced, the area of the connection point between the layers is reduced, which has affected the thermal shock resistance of the subsequent assembly, so the conductive bump is used instead of the solder ball to eliminate the implant. For the thermal shock caused by the hot melt of the solder ball, please refer to the following.

Please refer to FIG. 6A and FIG. 6B, which are schematic diagrams showing the assembly of the ultra-fine pitch test interface panel and the printed circuit board in the present invention. In the present invention, conductive bumps 61, such as copper bumps, may be disposed on the ultrafine pitch test interface panel 60. Specifically, conductive bumps 61 are formed on the outer surface of the first metal pad 49 of the ultrafine pitch test interface panel 60. The printed circuit board 70 has a solder resist layer 71 thereon, and the solder resist layer 71 has an opening that exposes the contacts 72. Solder paste 73 is applied to the contacts 72 of the printed circuit board 70. When the ultra-fine pitch test interface panel 60 is assembled with the printed circuit board 70, the ultra-fine pitch test interface panel 60 is heated. At this time, the conductive bumps 61 on the first metal pad 49 are soldered to the contacts 72 through the solder paste 73. together. During the process, the screw 82 and the screw hole are used for the positioning and fixing of the test panel 60 and the printed circuit board 70, and the physical change of the heat expansion and contraction occurs due to the heating or cooling of the material, so that the material can be softened by the support material 81. The opportunity to deform downwards to increase the success rate of welding.

In the embodiment of the invention, the conductive bump 61 is used instead of the solder ball, which can eliminate the thermal shock problem caused by the heat fusion of the solder ball. The solder ball needs to be heated by the solder ball to about 200 ° C, and the solder is cured after three minutes. When the conductive bump 61 is used, the substrate is heated by about 260 ° C, but after 20 seconds, the soldering is completed, and the substrate receives heat for a short time. The heat energy is lower, so it can solve the problem of deriving the interlayer due to the reduction of the blind hole diameter. The point at which the joint is deteriorated by thermal shock. In addition, this aspect of the invention can also control the coplanarity of the bump junctions, increasing the probability of successful assembly, especially on high pin count joints. In the ultra-fine pitch test panel of the present invention, for other materials requiring solder balls, the bump process can be used if the impact of high temperature is considered.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

40‧‧‧Rigid substrate

44‧‧‧through holes filled with conductive coating

45‧‧‧ line pattern

46‧‧‧First dielectric layer

47‧‧‧Second dielectric layer

48‧‧‧Contact hole

49‧‧‧First metal mat

50‧‧‧Second metal mat

52‧‧‧metal layer

Claims (17)

A method for manufacturing an ultra-fine pitch (Ultra-Fine Pitch) test interface panel, comprising the steps of: providing a rigid substrate; forming a through hole penetrating a surface of the rigid substrate; forming a groove on the surface of the rigid substrate to form a concave a conductive pattern is formed in the through hole and the groove; grinding is performed on the surface of the rigid substrate to remove a portion of the conductive plating layer formed on the groove, and the remaining conductive plating layer in the groove forms a line pattern; Forming a dielectric layer covering the circuit pattern; forming a contact hole at the dielectric layer; and forming a metal pad at a position corresponding to the contact hole by exposure, development, and plating, the metal pad is formed through the contact hole and the line pattern Electrical connection. The method for manufacturing an ultrafine pitch test panel according to claim 1, wherein the material of the rigid substrate is selected from the group consisting of glass, germanium wafer, ceramic, photosensitive glass, and sapphire substrate. The manufacturing method of the ultrafine pitch test interface panel according to the first aspect of the invention, wherein the groove is formed by etching, machining or electric discharge machining. The method for manufacturing an ultrafine pitch test interface panel according to claim 1, wherein in the step of polishing the surface of the rigid substrate, the conductive plating layer formed on the top of the groove is ground and removed. The method for manufacturing an ultrafine pitch test interface panel according to claim 1, wherein the metal pad is obtained by an additive method. A method for manufacturing an ultra-fine pitch (Ultra-Fine Pitch) test interface panel, comprising the steps of: providing a rigid substrate; forming a through hole penetrating the first surface and the second surface of the rigid substrate; first in the rigid substrate Forming a groove on the surface and the second surface, forming a first groove pattern on the first surface, forming a second groove pattern on the second surface; forming a conductive plating layer in the through hole and the groove; The first surface and the second surface of the rigid substrate are ground to remove a portion of the conductive plating formed on the groove, and the remaining conductive plating forms a first line pattern in the first groove pattern, in the second concave Forming a second line pattern in the groove pattern; forming a first dielectric layer covering the first line pattern, and forming a second dielectric layer covering the second line pattern; at the first dielectric layer and the second dielectric layer Forming a contact hole at the electrical layer; forming a first metal pad at a position corresponding to the contact hole of the first dielectric layer; and forming a size at a position corresponding to the contact hole of the second dielectric layer by exposure, development, and plating A first metal pad smaller second metal pad. The method for manufacturing an ultrafine pitch test interface panel according to claim 6, wherein the material of the rigid substrate is selected from the group consisting of glass, germanium wafer, ceramic, photosensitive glass, and sapphire substrate. The manufacturing method of the ultrafine pitch test interface panel according to claim 6, wherein the groove is formed by etching, mechanical or electrical discharge machining. The method for manufacturing an ultrafine pitch test interface panel according to claim 6, wherein in the step of grinding the surface of the rigid substrate, the conductive plating formed on the top of the groove is ground and removed. The method for manufacturing an ultrafine pitch test panel according to claim 6, wherein the second metal pad is obtained by an additive method. The manufacturing method of the ultrafine pitch test interface panel according to claim 6, further comprising the step of forming conductive bumps on the outer surface of the second metal pad. The manufacturing method of the ultrafine pitch test interface panel according to claim 6, wherein the distance between the second metal pads is smaller than the distance between the first metal pads. An ultra-fine pitch (Ultra-Fine Pitch) test interface panel comprising: a rigid substrate; a through hole penetrating through the first surface and the second surface of the rigid substrate, filled with a conductive plating layer; a first circuit pattern embedded in the rigidity The exposed surface of the first line pattern is on the same surface as the first surface of the rigid substrate under the first surface of the substrate; the second line pattern is embedded under the second surface of the rigid substrate, the second line pattern The exposed surface is on the same surface as the second surface of the rigid substrate, and the second circuit pattern is electrically connected to the first line pattern through the conductive plating layer in the through hole; a first dielectric layer covering the first line pattern; at least one second dielectric layer covering the second line pattern; contact holes formed at the first dielectric layer and the second dielectric layer; a metal pad formed at a position corresponding to the contact hole of the first dielectric layer; and a second metal pad formed at a position corresponding to the contact hole of the second dielectric layer, the second metal pad having a size smaller than the first The size of the metal pad. The ultrafine pitch test interface panel of claim 13, wherein the material of the rigid substrate is selected from the group consisting of glass, germanium wafer, ceramic, photosensitive glass, and sapphire substrate. The ultrafine pitch test interface panel of claim 13, wherein the at least one second dielectric layer comprises two or more second dielectric layers, and the ultrafine pitch test interface panel further comprises a metal A layer is formed between the two second dielectric layers. The ultrafine pitch test interface panel of claim 13 further comprising a conductive bump formed on an outer surface of the first metal pad. The ultrafine pitch test interface panel of claim 13, wherein the distance between the second metal pads is less than the distance between the first metal pads.