TWI444632B - A method of fabricating a testing board - Google Patents
A method of fabricating a testing board Download PDFInfo
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- TWI444632B TWI444632B TW101134638A TW101134638A TWI444632B TW I444632 B TWI444632 B TW I444632B TW 101134638 A TW101134638 A TW 101134638A TW 101134638 A TW101134638 A TW 101134638A TW I444632 B TWI444632 B TW I444632B
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本發明有關於一種測試載板結構之製法,尤指一種用於積體電路上或封裝後用以測試的微小間距測試載板結構之製法。The invention relates to a method for manufacturing a test carrier structure, in particular to a method for testing a micro-pitch test carrier structure for testing on an integrated circuit or after packaging.
請參考圖1至圖3所示,一般的垂直式晶圓測試結構包含有連接測試設備的印刷電路板2A、及連接印刷電路板2A的測試載板1A,該測試載板1A連接有多個晶圓測試探針11A,以供測試移動載台3A上的晶圓4A,其中測試載板1A可區分為(1)多層陶瓷基板1B(Multi Layer Ceramic,MLC),如圖2所示;(2)多層有機基板1C(Multi Layer Organic,MLO),如圖3所示。但是兩者製程差異頗大,如多層陶瓷基板(MLC)必須採用低溫共燒多層陶瓷(LTCC)製程製作,使用生胚材料(Green Tape),搭配印刷製程及高溫的燒結,才可以製程成品,通常層數很高,價格很高。而多層有機基板(MLO)則是利用印刷電路板(PCB)製程就可完成,其線路微細化雖可透過投資微影設備以達成,但盲孔的加工仍採用雷射鑽孔加工,在材料及加工能力將會有所限制。Referring to FIG. 1 to FIG. 3, a general vertical wafer test structure includes a printed circuit board 2A connected to a test device, and a test carrier 1A connected to the printed circuit board 2A. The test carrier 1A is connected to a plurality of Wafer test probe 11A for testing wafer 4A on mobile stage 3A, wherein test carrier 1A can be divided into (1) multilayer ceramic substrate 1B (Multi Layer Ceramic, MLC), as shown in FIG. 2; 2) Multi-layer organic substrate 1C (Multi Layer Organic, MLO), as shown in FIG. However, the process of the two processes is quite different. For example, the multilayer ceramic substrate (MLC) must be fabricated by a low temperature co-fired multilayer ceramic (LTCC) process. The green tape can be processed with a green process and a high temperature sintering process. Usually the number of floors is high and the price is very high. The multilayer organic substrate (MLO) can be completed by using a printed circuit board (PCB) process. Although the circuit miniaturization can be achieved by investing in lithography equipment, the blind hole processing is still performed by laser drilling. And processing capacity will be limited.
就測試用的MLC載板而言,一般設計多採用單一顆晶粒(Single DUT)或一對晶粒(Dual DUT)做測試,當I/O測點過多或是多顆晶粒(Multi DUT)測試,設計變相對複雜,且採用印刷方式的線寬最小為100微米,導致佈線密度有限,必須以增加層數來分散線路的佈排密度,所以層數有可能高達50層以上。加上每層都必須用雷射加工打孔,並用銀 膏塞孔及印製線路,故相對成本高,交期也長。For the MLC carrier board used for testing, the general design uses a single die (Single DUT) or a pair of die (Dual DUT) for testing. When there are too many I/O points or multiple grains (Multi DUT) Test, the design becomes relatively complicated, and the line width of the printing method is at least 100 micrometers, resulting in a limited wiring density. It is necessary to increase the number of layers to disperse the density of the wiring, so the number of layers may be as high as 50 or more. Plus each layer must be laser-punched and silver-coated Paste plugs and printed circuits, so the relative cost is high and the delivery time is long.
而測試用的MLO載板可採用PCB製程及材料,但對於微小間距加工,增層材料有所限制。當採用含玻璃纖維的材料經過雷射鑽孔,往往導致電鍍後會產生燈蕊效應而短路報廢。若採用量產封裝用的覆晶載板材料(Ajinomoto Build-up Film,ABF),其並無玻璃纖維,但採用該材料必須投資昂貴的壓合設備、昂貴的化銅設備及藥水,並非一般樣品廠(如:測試用載板廠)可負擔。The test MLO carrier board can be used in PCB process and materials, but for small pitch processing, the build-up material is limited. When a glass fiber-containing material is subjected to laser drilling, it often causes a lamp core effect after the plating and a short circuit is discarded. If Ajinomoto Build-up Film (ABF) is used for mass production, it has no glass fiber, but it must be invested in expensive press equipment, expensive copper equipment and potion. Sample plants (eg, test carrier plants) are affordable.
當封裝的發展趨向覆晶式封裝(Flip Chip Package),其I/O的排列方式呈球型陣列式(Ball Grid Array),因此要對應達到具微小間距測試能力的製程重點是開孔要微小化,並呈陣列式排列,但無玻璃纖維材料經過二氧化碳(CO2)雷射或紫外光(UV)雷射鑽孔加工後,需再經去膠渣(Desmear)流程,嚴重造成開孔孔徑擴大問題,成品的間距約只能達到140微米。或許雷射加工的參數可再優化,讓孔徑再縮小,甚至不需作去膠渣,但材料的玻璃轉移溫度(Tg)不夠高(約150℃),且熱膨脹係數太大(CTE約250ppm/℃),對於後續產品組裝品質的可靠度將是很大的疑慮。When the development of packaging tends to Flip Chip Package, the arrangement of I/O is in the form of Ball Grid Array. Therefore, the key to the process of testing with small pitch is that the opening is small. And arranged in an array, but after the glass fiber material is subjected to carbon dioxide (CO2) laser or ultraviolet (UV) laser drilling, it needs to go through the desmear process, which seriously causes the aperture to be enlarged. The problem is that the finished product can only reach a pitch of about 140 microns. Perhaps the parameters of the laser processing can be re-optimized, so that the pore size is further reduced, and even the desmear is not required, but the glass transition temperature (Tg) of the material is not high enough (about 150 ° C), and the coefficient of thermal expansion is too large (CTE about 250 ppm / °C), there will be great doubts about the reliability of subsequent product assembly quality.
緣是,本發明人有感上述問題之可改善,乃潛心研究並配合學理之運用,而提出一種設計合理且有效改善上述問題之本發明。The reason is that the present inventors have felt that the above problems can be improved, and that the present invention has been deliberately studied and used in conjunction with the theory, and a present invention which is reasonable in design and effective in improving the above problems has been proposed.
本發明在於提供一種微小間距測試載板結構之製法,能有效縮小介電層開孔之孔徑,以進一步達到具微小間距測試能力。The invention provides a method for manufacturing a micro-pitch test carrier structure, which can effectively reduce the aperture of the dielectric layer opening to further achieve the test capability with a small pitch.
為達上面所描述的,本發明提供一種微小間距測試 載板結構之製法,係包括:提供一核心基板,其相對表面分別形成一第一線路層及一第二線路層,該第一線路層電性連接於該第二線路層;形成一感光性介電層覆蓋於該核心基板及該第一線路層之表面;利用曝光顯影方式形成多個呈等間距排列的開孔於該第一感光性介電層中,以顯露部分第一線路層;透過濺鍍方式形成一導電層覆蓋於該感光性介電層表面及該些開孔內;透過電鍍方式形成一金屬層填充於該些開孔內;移除顯露於該感光性介電層表面之該導電層;研磨顯露於該第一感光性介電層表面之該金屬層,以形成多個第一導電盲孔,該些第一導電盲孔分別具有一接觸墊,且電性連接於該第一線路層;以及於該第一感光性介電層上形成有增層結構,該增層結構包含至少一第二感光性介電層、形成於該第二感光性介電層中的多個第二導電盲孔且該些第二導電盲孔係分別疊設於該些第一導電盲孔且電性連接於該第一線路層。In order to achieve the above, the present invention provides a micro pitch test The method of manufacturing the carrier structure comprises: providing a core substrate, wherein the opposite surfaces respectively form a first circuit layer and a second circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer; forming a photosensitive property a dielectric layer covering the surface of the core substrate and the first circuit layer; forming a plurality of openings arranged at equal intervals in the first photosensitive dielectric layer by exposure and development to expose a portion of the first circuit layer; Forming a conductive layer over the surface of the photosensitive dielectric layer and the openings through a sputtering method; forming a metal layer filled in the openings through electroplating; removing the surface exposed on the photosensitive dielectric layer The conductive layer is formed by polishing the metal layer exposed on the surface of the first photosensitive dielectric layer to form a plurality of first conductive via holes, wherein the first conductive blind vias respectively have a contact pad and are electrically connected to a first wiring layer; and a build-up structure formed on the first photosensitive dielectric layer, the build-up structure comprising at least one second photosensitive dielectric layer formed in the second photosensitive dielectric layer a plurality of second conductive blind holes and the The second line are stacked conductive vias disposed in the first conductive blind hole and electrically connected to the first circuit layer.
本發明復提供一種微小間距測試載板結構之製法,係包括:提供一核心基板,其相對表面分別形成一第一線路層及一第二線路層,該第一線路層電性連接於該第二線路層;形成一感光性介電層覆蓋於該核心基板及該第一線路層之表面;利用曝光顯影方式形成多個呈等間距排列的開孔於該第一感光性介電層中,以顯露部分第一線路層;透過濺鍍方式形成一導電層覆蓋於該感光性介電層表面及該些開孔內;透過電鍍方式形成一金屬層覆蓋於該第一感光性介電層的整個表面及充佈於該些開孔內;一併移除該第一感光性介電層表面之部分該金屬層及該 導電層;研磨顯露於該第一感光性介電層表面之部分該金屬層,以形成多個第一導電盲孔,該些第一導電盲孔分別具有一接觸墊,且電性連接於該第一線路層;以及於該第一感光性介電層上形成有增層結構,該增層結構包含至少一第二感光性介電層、形成於該第二感光性介電層中的多個第二導電盲孔,且該些第二導電盲孔係分別疊設於該些第一導電盲孔且電性連接於該第一線路層。The invention provides a method for fabricating a micro-pitch test carrier structure, comprising: providing a core substrate, wherein a first circuit layer and a second circuit layer are respectively formed on opposite surfaces thereof, wherein the first circuit layer is electrically connected to the first circuit layer a second circuit layer; a photosensitive dielectric layer is formed on the surface of the core substrate and the first circuit layer; and a plurality of openings arranged at equal intervals are formed in the first photosensitive dielectric layer by exposure and development. Forming a portion of the first circuit layer; forming a conductive layer over the surface of the photosensitive dielectric layer and the openings through sputtering; forming a metal layer over the first photosensitive dielectric layer by electroplating And the entire surface is filled in the openings; and the metal layer and the portion of the surface of the first photosensitive dielectric layer are removed together a conductive layer; a portion of the metal layer exposed on the surface of the first photosensitive dielectric layer to form a plurality of first conductive vias, each of the first conductive vias having a contact pad and electrically connected thereto a first circuit layer; and a build-up structure formed on the first photosensitive dielectric layer, the build-up structure comprising at least one second photosensitive dielectric layer, formed in the second photosensitive dielectric layer And a second conductive via hole, wherein the second conductive via holes are respectively stacked on the first conductive blind via holes and electrically connected to the first circuit layer.
承上所述,藉由本發明之微小間距測試載板結構之製法,有效縮小開孔之孔徑,以使該些導電盲孔呈微小間距排列,以進一步達到具微小間距測試能力。According to the method for fabricating the micro-pitch test carrier structure of the present invention, the aperture of the opening is effectively reduced, so that the conductive blind holes are arranged at a fine pitch to further achieve the capability of testing with a small pitch.
為了能更進一步瞭解本發明為達成既定目的所採取之技術、方法及功效,請參閱以下有關本發明之詳細說明、圖式,相信本發明之目的、特徵與特點,當可由此得以深入且具體之瞭解,然而所附圖式均為簡化之示意圖僅提供參考與說明用,其數目、形狀、佈局並非用來對本創作加以限制者。In order to further understand the technology, method and effect of the present invention in order to achieve the intended purpose, reference should be made to the detailed description and drawings of the present invention. The drawings are to be considered in a simplified form, and are not intended to limit the scope of the present invention.
請參閱圖4A至4G,此為本發明之微小間距測試載板結構製法第一實施例之流程示意圖。Please refer to FIG. 4A to FIG. 4G, which are schematic diagrams showing the flow of the first embodiment of the method for manufacturing the micro pitch test carrier structure of the present invention.
如圖4A所示,首先提供一核心基板10,其上、下表面分別形成一第一線路層101及一第二線路層102,該第一線路層101藉由導電通孔103電性連接於該第二線路層102。本實施例中,提供的核心基板10為雙面的核心基板, 但其層數及線路的佈局並不限制於此,如圖9A至9D所示,可依據設計需求而決定為另一種雙面的核心基板10a;結合多層壓合的核心基板10b;另一種結合多層壓合的核心基板10c;或結合多次多層壓合的的核心基板10d。As shown in FIG. 4A, a core substrate 10 is provided. A first circuit layer 101 and a second circuit layer 102 are formed on the upper and lower surfaces. The first circuit layer 101 is electrically connected to the via hole 103. The second circuit layer 102. In this embodiment, the core substrate 10 is provided as a double-sided core substrate. However, the number of layers and the layout of the circuit are not limited thereto. As shown in FIGS. 9A to 9D, it may be determined as another double-sided core substrate 10a according to design requirements; combined with the multi-laminated core substrate 10b; another combination The multi-laminated core substrate 10c; or a core substrate 10d combined with a plurality of layers.
如圖4B所示,形成一第一感光性介電層21覆蓋於該核心基板10及該第一線路層101之表面。詳細來說,該第一感光性介電層21是透過印刷或塗佈方式所形成,且該第一感光性介電層21為具有高阻值之感光介電材料。As shown in FIG. 4B, a first photosensitive dielectric layer 21 is formed to cover the surface of the core substrate 10 and the first wiring layer 101. In detail, the first photosensitive dielectric layer 21 is formed by printing or coating, and the first photosensitive dielectric layer 21 is a photosensitive dielectric material having a high resistance.
如圖4C所示,利用曝光顯影方式形成多個呈微小間距排列的第一開孔211於第一感光性介電層中21,以顯露部分第一線路層101。更詳細的說,經由感光介電材料的感光效果並透過曝光顯影方式形成具有62.5微米以下孔徑d的第一開孔211,且該些第一開孔211可為陣列式排列。換言之,本發明利用曝光顯影方式可使第一開孔211微小化,而孔徑d可依據感光材料膜厚薄進行孔徑d的增減,在實務上,最終取決於曝光設備的曝光能力,優點為無需以雷射加工形成開孔,不會造成第一開孔211之孔徑d擴大問題,且不會因形成膠渣而影響可靠度,能通過斷短路電性測試,並且省下雷射鑽孔的時間,可提昇生產效率與生產品質。As shown in FIG. 4C, a plurality of first openings 211 arranged at a fine pitch are formed in the first photosensitive dielectric layer 21 by exposure development to expose a portion of the first wiring layer 101. In more detail, the first opening 211 having a pore diameter d of 62.5 μm or less is formed through the photosensitive effect of the photosensitive dielectric material and by exposure development, and the first openings 211 may be arranged in an array. In other words, the first opening 211 can be miniaturized by the exposure and development method, and the aperture d can increase or decrease the aperture d according to the film thickness of the photosensitive material. In practice, it ultimately depends on the exposure capability of the exposure device, and the advantage is that it is unnecessary. The laser hole is formed by the laser processing, and the hole diameter d of the first opening 211 is not enlarged, and the reliability is not affected by the formation of the glue. The short circuit electrical test can be passed, and the laser drilling is saved. Time can improve production efficiency and production quality.
如圖4D所示,透過濺鍍方式形成一導電層212覆蓋於該第一感光性介電層21表面及該些第一開孔211內。需說明的是,由於第一感光性介電層21本身是光滑面,沒有導電物質存在,因此本發明以直流電濺鍍方式形 成導電層212以增強結合力,該導電層212為具有導電性的金屬薄膜。As shown in FIG. 4D, a conductive layer 212 is formed on the surface of the first photosensitive dielectric layer 21 and the first openings 211 by sputtering. It should be noted that since the first photosensitive dielectric layer 21 itself is a smooth surface and no conductive material exists, the present invention is formed by direct current sputtering. The conductive layer 212 is formed to enhance the bonding force, and the conductive layer 212 is a metal thin film having conductivity.
如圖4E所示,先依據一預定之線路圖騰(圖略)進行曝光顯影,並將光阻213覆蓋於第一感光性介電層21表面上非線路圖騰的區域,做為之後電鍍時的遮蔽,再透過電鍍方式形成一第一金屬層22,並填充於第一開孔211內。需說明的是,藉由導電層212的傳導電流,電鍍沉積銅於第一開孔211內以形成第一金屬層22,上述導電層212的材質係選自鉻合金、銅、鈦及鎢所組成的群組,但不加以限定。此外電鍍之材料,較佳為銅,但不限於此,可為金、銀、及錫等金屬材料或合金材料。As shown in FIG. 4E, exposure development is performed according to a predetermined line totem (not shown), and the photoresist 213 is overlaid on the surface of the first photosensitive dielectric layer 21 on the surface of the non-line totem, as after plating. A first metal layer 22 is formed by masking and then electroplating, and is filled in the first opening 211. It should be noted that, by conducting current of the conductive layer 212, copper is deposited in the first opening 211 to form the first metal layer 22, and the material of the conductive layer 212 is selected from the group consisting of chromium alloy, copper, titanium and tungsten. A group of groups, but not limited. Further, the material to be plated is preferably copper, but is not limited thereto, and may be a metal material or an alloy material such as gold, silver or tin.
如圖4F、圖4G所示,移除顯露於第一感光性介電層21表面之光阻213、導電層212,並研磨顯露於該第一感光性介電層21表面之第一金屬層22,以形成多個第一導電盲孔221,該些第一導電盲孔分別具有一第一連接墊222,且電性連接於第一線路層101。As shown in FIG. 4F and FIG. 4G, the photoresist 213 and the conductive layer 212 exposed on the surface of the first photosensitive dielectric layer 21 are removed, and the first metal layer exposed on the surface of the first photosensitive dielectric layer 21 is polished. 22, to form a plurality of first conductive blind vias 221, each of the first conductive vias 222 having a first connection pad 222 and electrically connected to the first circuit layer 101.
請參閱圖5A至5G,此為本發明之微小間距測試載板結構製法第二實施例之流程示意圖。與上述第一實施例的差異在於,如圖5E至圖5G所示,透過電鍍方式形成一第一金屬層22覆蓋於第一感光性介電層21的整個表面及充佈於該些第一開孔211內,並透過蝕刻方式一併移除該第一感光性介電層21表面之部分第一金屬層22及導電層212,並研磨部分顯露於該第一感光性介電層21表面之第一金屬層22,以形成多個第一導電盲孔221,該些第一導電盲孔221分別具有一連接墊222,且電性 連接於第一線路層101。需說明的是,導電層212主要是採濺鍍薄膜加工,依據電阻公式R=ρ(L/A),當厚度(A)變薄,將產生較大的DC電阻,因藉由導電層212電阻變高,使其電鍍沉積速率會變慢,進而使第一金屬層22厚度的均勻性變好,對線路蝕刻更有幫助。Please refer to FIG. 5A to FIG. 5G, which are schematic diagrams of the second embodiment of the method for manufacturing the micro pitch test carrier structure of the present invention. The difference from the first embodiment is that, as shown in FIG. 5E to FIG. 5G, a first metal layer 22 is formed on the entire surface of the first photosensitive dielectric layer 21 and is filled on the first surface by electroplating. a portion of the first metal layer 22 and the conductive layer 212 on the surface of the first photosensitive dielectric layer 21 are removed by etching, and the polished portion is exposed on the surface of the first photosensitive dielectric layer 21. The first metal layer 22 is formed to form a plurality of first conductive blind holes 221, and the first conductive blind holes 221 respectively have a connection pad 222, and the electrical Connected to the first circuit layer 101. It should be noted that the conductive layer 212 is mainly processed by sputtering film. According to the resistance formula R=ρ(L/A), when the thickness (A) is thin, a large DC resistance will be generated due to the conductive layer 212. The resistance becomes higher, so that the plating deposition rate becomes slower, thereby making the uniformity of the thickness of the first metal layer 22 better, which is more helpful for line etching.
至此,可依設計需求重複上述第一實施例圖4B至圖4G或第二實施例圖5B至圖5G之流程,製作出增層結構,以完成本發明之雙面或多層板雙面增層與雙面或多層板單面增層。At this point, the process of FIG. 4B to FIG. 4G of the first embodiment or the process of FIG. 5B to FIG. 5G of the second embodiment may be repeated according to design requirements, and a layer-added structure may be formed to complete the double-sided or multi-layer plate double-layer layering of the present invention. Add layers on one side with double-sided or multi-layer boards.
請參閱圖6A至6F,此為依上述第一或第二實施例之製法延伸形成本發明第三實施例之微小間距測試載板結構之雙面板雙面增層的製法。Referring to Figures 6A through 6F, there is shown a method of fabricating a double-panel double-sided buildup of the micro pitch test carrier structure of the third embodiment of the present invention in accordance with the method of the first or second embodiment.
如圖6A所示,提供一核心基板10,該核心基板10為雙面核心基板,其上、下表面分別形成一第一線路層101及一第二線路層102,該第一線路層101藉由導電通孔103電性連接於該第二線路層102。As shown in FIG. 6A, a core substrate 10 is provided. The core substrate 10 is a double-sided core substrate, and a first circuit layer 101 and a second circuit layer 102 are formed on the upper and lower surfaces, respectively. The conductive vias 103 are electrically connected to the second circuit layer 102.
如圖6B所示,形成一第一感光性介電層21及一第二感光性介電層31分別覆蓋於核心基板10的上、下表面及第一、第二線路層101、102之表面。As shown in FIG. 6B, a first photosensitive dielectric layer 21 and a second photosensitive dielectric layer 31 are formed on the upper and lower surfaces of the core substrate 10 and the surfaces of the first and second circuit layers 101 and 102, respectively. .
如圖6C所示,於第一感光性介電層21中及第二感光性介電層31中分別形成多個第一開孔211及多個第二開孔311,以分別顯露部分第一線路層101及第二線路層102,且該些第一、第二開孔211、311之孔徑d小於62.5微米。As shown in FIG. 6C , a plurality of first openings 211 and a plurality of second openings 311 are respectively formed in the first photosensitive dielectric layer 21 and the second photosensitive dielectric layer 31 to respectively expose the first portion The circuit layer 101 and the second circuit layer 102, and the apertures d of the first and second openings 211 and 311 are less than 62.5 micrometers.
如圖6D所示,於該些第一開孔211及該些第二開 孔311分別形成多個第一導電盲孔221及多個第二導電盲孔321。每一第一導電盲孔221及每一第二導電盲孔321分別具有一第一連接墊222及一第二連接墊322。As shown in FIG. 6D, the first openings 211 and the second openings The holes 311 respectively form a plurality of first conductive blind holes 221 and a plurality of second conductive blind holes 321 . Each of the first conductive vias 221 and each of the second conductive vias 321 has a first connection pad 222 and a second connection pad 322 .
如圖6E所示,於第一感光性介電層21上及第二感光性介電層31上分別形成有增層之結構100、200。增層之結構100包含一第三感光性介電層41、一最外層之第五感光性介電層61、形成於該第三感光性介電層41中的多個第三導電盲孔421、及形成於該最外層之第五感光性介電層61中的多個第五導電盲孔621。覆蓋第三感光性介電層41於第一感光性介電層21,覆蓋最外層之第五感光性介電層61於第三感光性介電層41。其中,該些第三導電盲孔421係分別疊設於該些第一導電盲孔221,該些第五導電盲孔621係分別疊設於該些第三導電盲孔421。As shown in FIG. 6E, structures 10 and 200 are formed on the first photosensitive dielectric layer 21 and the second photosensitive dielectric layer 31, respectively. The layered structure 100 includes a third photosensitive dielectric layer 41, an outermost fifth photosensitive dielectric layer 61, and a plurality of third conductive blind vias 421 formed in the third photosensitive dielectric layer 41. And a plurality of fifth conductive blind vias 621 formed in the fifth photosensitive dielectric layer 61 of the outermost layer. The third photosensitive dielectric layer 41 is covered on the first photosensitive dielectric layer 21, and the fifth photosensitive dielectric layer 61 on the outermost layer is covered on the third photosensitive dielectric layer 41. The third conductive vias 421 are respectively stacked on the first conductive vias 221 , and the fifth conductive vias 621 are respectively stacked on the third conductive vias 421 .
增層之結構200包含一第四感光性介電層51、一另一最外層之第六感光性介電層71、形成於該第四感光性介電層51中的多個第四導電盲孔521、及形成於另一最外層之第六感光性介電層71中的多個第六導電盲孔721。覆蓋第四感光性介電層51於第二感光性介電層31,覆蓋另一最外層之第六感光性介電層71於第四感光性介電層51。其中,該些第四導電盲孔521係分別疊設於該些第二導電盲孔321,該些第六導電盲孔721係分別疊設於該些第四導電盲孔521。The layered structure 200 includes a fourth photosensitive dielectric layer 51, a sixth outermost photosensitive layer 71, and a plurality of fourth conductive blinds formed in the fourth photosensitive dielectric layer 51. a hole 521 and a plurality of sixth conductive blind holes 721 formed in the sixth photosensitive dielectric layer 71 of the other outermost layer. The fourth photosensitive dielectric layer 51 is covered on the second photosensitive dielectric layer 31 and covers the other outermost sixth photosensitive dielectric layer 71 on the fourth photosensitive dielectric layer 51. The fourth conductive blind vias 521 are respectively stacked on the second conductive vias 321 , and the sixth conductive vias 721 are respectively stacked on the fourth conductive vias 521 .
最外層之第五感光性介電層61為本實施例之微小間距測試載板之測試端(亦即測試載板之C4面),形成有多個測試端連接墊622,以供多個晶圓測試探針11A(如圖1)電 性連接於該些測試端連接墊622的中央處,該些測試端連接墊622呈矩陣式排列(如圖6F),或為環繞式排列(如圖6G)且每一測試端連接墊622的中央與每一相鄰之測試端連接墊622的中央之間的間距D小於等於140微米,藉由此晶圓測試探針之間距D,可達到具微小間距測試能力。The fifth outer photosensitive dielectric layer 61 of the outermost layer is the test end of the micro pitch test carrier of the embodiment (that is, the C4 side of the test carrier), and a plurality of test end connection pads 622 are formed for the plurality of crystals. Round test probe 11A (Figure 1) Connected to the center of the test terminal connection pads 622, the test terminal connection pads 622 are arranged in a matrix (as shown in FIG. 6F), or in a wraparound arrangement (as shown in FIG. 6G) and each test end is connected to the pad 622. The distance D between the center and the center of each adjacent test terminal connection pad 622 is less than or equal to 140 micrometers, whereby the distance D between the probes can be tested to achieve a fine pitch test capability.
另一最外層之第六感光性介電層71為本實施例之微小間距測試載板之植球端(亦即測試載板之BGA面),形成有多個植球端連接墊722,且覆蓋有一防焊層80,該些植球端連接墊722各植設有錫球81,以供電性接至測試設備的印刷電路板2A(如圖1),而電性接至測試設備的方式並不以焊接方式為限。The other outermost sixth photosensitive dielectric layer 71 is the ball-grating end of the micro-pitch test carrier of the embodiment (that is, the BGA surface of the test carrier), and a plurality of ball-end connection pads 722 are formed, and Covered with a solder resist layer 80, each of the ball end connection pads 722 is provided with a solder ball 81, which is electrically connected to the printed circuit board 2A of the test equipment (as shown in FIG. 1), and electrically connected to the test equipment. It is not limited by the welding method.
請參閱圖7A至7E,此為依上述第一或第二實施例之製法延伸形成本發明之微小間距測試載板結構之多層板單面增層的製法。Referring to Figures 7A through 7E, there is shown a method of forming a single-sided buildup of a multilayer board of the micro pitch test carrier structure of the present invention by the method of the first or second embodiment described above.
如圖7A所示,提供一核心基板10”,該核心基板10”為多層核心基板,其上、下表面分別形成一第一線路層101”及一第二線路層102”,該第一線路層101”電性連接於該第二線路層102”。更進一步說明的是,透過多層核心基板的設計,可將一般線路較寬的信號層、電源層、及接地層,利用傳統PCB製程(如蝕刻),形成圖形化信號層(未圖示)、圖形化電源層(未圖示)、及圖形化接地層(未圖示),並做整體性的壓合形成多層核心基板,且使圖形化信號層、圖形化電源層、及圖形化接地層電性連接於第一、第二線路層101”、102”。As shown in FIG. 7A, a core substrate 10" is provided. The core substrate 10" is a multi-layer core substrate, and a first circuit layer 101" and a second circuit layer 102" are formed on the upper and lower surfaces, respectively. The layer 101" is electrically connected to the second circuit layer 102". Furthermore, through the design of the multi-layer core substrate, a signal layer, a power layer, and a ground layer having a wider general line can be formed into a patterned signal layer (not shown) by using a conventional PCB process (such as etching). A patterned power layer (not shown) and a patterned ground plane (not shown) are integrally bonded to form a multilayer core substrate with a patterned signal layer, a patterned power plane, and a patterned ground plane Electrically connected to the first and second circuit layers 101", 102".
如圖7B所示,形成有一第一感光性介電層21”覆蓋 於核心基板10”表面及第一線路層101”之表面。As shown in FIG. 7B, a first photosensitive dielectric layer 21" is formed to be covered. The surface of the core substrate 10" and the surface of the first wiring layer 101".
如圖7C所示,於第一感光性介電層21”中形成多個第一開孔211”,以顯露部分第一線路層101”,且每一開孔211”之孔徑d小於62.5微米。As shown in FIG. 7C, a plurality of first openings 211" are formed in the first photosensitive dielectric layer 21" to expose a portion of the first wiring layer 101", and the aperture d of each of the openings 211" is less than 62.5 microns. .
如圖7D所示,於該些第一開孔211”形成多個第一導電盲孔221”,且每一第一導電盲孔221”具有一第一連接墊222”。As shown in FIG. 7D, a plurality of first conductive vias 221" are formed in the first openings 211", and each of the first conductive vias 221" has a first connection pad 222".
如圖7E所示,於第一感光性介電層21”上,形成有增層結構100”,該增層結構100”包含一第二感光性介電層31”、一最外層之第三感光性介電層41”、形成於該第二感光性介電層31”中的多個第二導電盲孔321”、及形成於最外層之第三感光性介電層41”中的多個第三導電盲孔421”。覆蓋第二感光性介電層31”於第一感光性介電層21”,覆蓋最外層之第三感光性介電層41”於第二感光性介電層31”。其中,該些第二導電盲孔321”係分別疊設於該些第一導電盲孔221”,該些第三導電盲孔421”係分別疊設於該些第二導電盲孔321”。As shown in FIG. 7E, on the first photosensitive dielectric layer 21", a build-up structure 100" is formed. The build-up structure 100" includes a second photosensitive dielectric layer 31" and a third outermost layer. The photosensitive dielectric layer 41", the plurality of second conductive blind vias 321" formed in the second photosensitive dielectric layer 31", and the plurality of third photosensitive dielectric layers 41" formed in the outermost layer a third conductive blind via 421" covering the second photosensitive dielectric layer 31" on the first photosensitive dielectric layer 21", covering the outermost third photosensitive dielectric layer 41" on the second photosensitive dielectric The second conductive blind holes 321 ′′ are respectively stacked on the first conductive blind holes 221 ′′, and the third conductive blind holes 421 ′′ are respectively stacked on the second conductive blinds Hole 321".
最外層之第三感光性介電層41”為本實施例之微小間距測試載板之測試端,形成有多個測試端連接墊422”。以供電性連接多個晶圓測試探針11A(如圖1),且每一測試端連接墊422”的中央與每一相鄰之測試端連接墊422的中央之間的間距D小於等於140微米,在實務上,取決於待測晶圓而定,藉由此晶圓測試探針之間距D,可達到具微小間距測試能力。The outermost third photosensitive dielectric layer 41" is the test end of the micro pitch test carrier of the embodiment, and a plurality of test end connection pads 422" are formed. The plurality of wafer test probes 11A (FIG. 1) are electrically connected, and the distance D between the center of each test terminal connection pad 422" and the center of each adjacent test terminal connection pad 422 is less than or equal to 140. Micron, in practice, depending on the wafer to be tested, by means of the wafer test probe spacing D, a small pitch test capability can be achieved.
第二線路層102”為本實施例之微小間距測試載板之植球端,且覆蓋有一防焊層80”,該第二線路層102”植設 有多個錫球81”,以供電性接至測試設備的印刷電路板2A(如圖1),而電性接至測試設備的方式並不以焊接方式為限。The second circuit layer 102" is the ball-grating end of the micro-pitch test carrier of the embodiment, and is covered with a solder resist layer 80", and the second circuit layer 102" is implanted There are a plurality of solder balls 81", which are electrically connected to the printed circuit board 2A of the test equipment (as shown in Fig. 1), and the manner of electrically connecting to the test equipment is not limited to the soldering method.
請參閱圖8及圖8A,此為本實施例之微小間距測試載板之部分增層結構之製法的示意圖。與上述實施例的差異在於,增層結構100a包含一內層感光性介電層31a、一外層感光性介電層41a,利用曝光顯影方式在增層結構100a之外層感光性介電層41a形成有一凹槽43a,該凹槽43a顯露由部分內層導電盲孔321a之內層連接墊322a延伸形成的內層線路層3221a,以供嵌入電子元件,如電阻、電容或電感等,且該凹槽43a形成位置接近待測試物(DUT)的內層線路層3221a,藉由縮短路徑,有助於電性品質之提升,並依據嵌入各種電子元件之特性,可達到射頻(RF)調協、濾波、電源完整性(Power Integration)等各項功能的設計需求。Please refer to FIG. 8 and FIG. 8A , which are schematic diagrams showing the manufacturing method of a part of the layered structure of the micro pitch test carrier of the embodiment. The difference from the above embodiment is that the build-up structure 100a includes an inner photosensitive dielectric layer 31a and an outer photosensitive dielectric layer 41a, which are formed by the exposure and development method on the photosensitive dielectric layer 41a outside the build-up structure 100a. There is a recess 43a which exposes an inner layer circuit layer 3221a formed by an inner layer connection pad 322a of a portion of the inner conductive via 321a for embedding electronic components such as resistors, capacitors or inductors, and the recess The groove 43a forms an inner layer circuit layer 3221a located close to the object to be tested (DUT), which contributes to an improvement in electrical quality by shortening the path, and can achieve radio frequency (RF) tuning according to the characteristics of embedding various electronic components. Design requirements for various functions such as filtering and power integration.
綜合以上所述,本發明的優點至少在於:In summary, the advantages of the present invention are at least:
(1)降低成本及工時:本發明採用曝光顯影製程,可同時省下多層有機載板(MLO)製程中的黑化、壓合及雷射鑽孔的時間,並可結合線路加成法製作,亦有助於縮減整體線寬/線距,可提高佈線的密度,也可省下多層陶瓷載板(MLC)銀膏印製線路的成本及工時,並有效降低層數的安排。(1) Cost reduction and working hours: The invention adopts the exposure and development process, and can simultaneously save the blackening, pressing and laser drilling time in the multilayer organic carrier (MLO) process, and can be combined with the line addition method. The production also helps to reduce the overall line width / line spacing, can increase the density of the wiring, can also save the cost and working hours of the multilayer ceramic carrier (MLC) silver paste printed circuit, and effectively reduce the number of layers.
(2)縮小孔徑且不需去膠渣:本發明採用感光性材料做為介電層,不需經過機械加工,並採用曝光顯影製程來加工,不需經過去膠渣流程,可解決孔徑擴大問題,另外盲孔的加工作業時間也可縮短。(2) Reducing the aperture and eliminating the need for desmear: The invention adopts a photosensitive material as a dielectric layer, does not need to be mechanically processed, and is processed by an exposure and development process, and does not need to go through a desmear process to solve the aperture expansion. The problem, in addition, the processing time of blind holes can also be shortened.
(3)增加待測物(Device Under Test)的測試數量:縮小孔徑使間距更小,有助於呈微小間距之線路安排,可提高各層線路設計的密度,並有助於多個待測物(Multi DUT)設計之佈局。(3) Increase the number of tests of the Device Under Test: reduce the aperture to make the spacing smaller, help the arrangement of the wiring with a small pitch, increase the density of the design of each layer, and contribute to multiple objects to be tested. (Multi DUT) design layout.
(4)電源優化:本發明利用感光性介電材料之特性,在接近待測物(DUT)端,透過曝光顯影形成一個凹槽,以將電子元件內嵌在線路層上,可比一般的佈局更佳化,以提升電源完整性。(4) Power supply optimization: The present invention utilizes the characteristics of the photosensitive dielectric material to form a groove through the exposure and development near the DUT end to embed the electronic component on the circuit layer, which is comparable to the general layout. Better to improve power integrity.
(5)增加產品應用範圍:利用感光性介電材料的玻璃轉移溫度(Tg)約200℃,因此對於選用的板材將不會有太多限制,可採用陶瓷材料或印刷電路板材料,故多層陶瓷基板(MLC)或多層有機基板(MLO)產品都可以應用本發明之製法。(5) Increase the application range of the product: the glass transition temperature (Tg) of the photosensitive dielectric material is about 200 ° C, so there will be no restrictions on the selected plate, ceramic materials or printed circuit board materials can be used, so multiple layers The method of the present invention can be applied to both a ceramic substrate (MLC) or a multilayer organic substrate (MLO) product.
1A‧‧‧測試載板1A‧‧‧ test carrier
11A‧‧‧晶圓測試探針11A‧‧‧ wafer test probe
1B‧‧‧多層陶瓷基板1B‧‧‧Multilayer ceramic substrate
1C‧‧‧多層有機基板1C‧‧‧Multilayer organic substrate
2A‧‧‧印刷電路板2A‧‧‧Printed circuit board
3A‧‧‧移動載台3A‧‧‧Mobile stage
4A‧‧‧晶圓4A‧‧‧ wafer
10、10”、10a、10b、10c、10d‧‧‧核心基板10, 10", 10a, 10b, 10c, 10d‧‧‧ core substrate
101、101”‧‧‧第一線路層101, 101”‧‧‧First circuit layer
102、102”‧‧‧第二線路層102, 102"‧‧‧second circuit layer
103、103”‧‧‧導電通孔103, 103"‧‧‧ conductive through holes
21、21”‧‧‧第一感光性介電層21, 21" ‧ ‧ first photosensitive dielectric layer
211、211”‧‧‧第一開孔211, 211" ‧ ‧ first opening
212‧‧‧導電層212‧‧‧ Conductive layer
213‧‧‧光阻213‧‧‧Light resistance
22、22”‧‧‧第一金屬層22, 22" ‧ ‧ first metal layer
221、221”‧‧‧第一導電盲孔221, 221"‧‧‧ first conductive blind hole
222、222”‧‧‧第一連接墊222, 222" ‧ ‧ first connection pad
31、31”‧‧‧第二感光性介電層31, 31"‧‧‧Second photosensitive dielectric layer
311‧‧‧第二開孔311‧‧‧Second opening
32‧‧‧第二金屬層32‧‧‧Second metal layer
321、321”‧‧‧第二導電盲孔321,321"‧‧‧Second conductive blind hole
322‧‧‧第二連接墊322‧‧‧Second connection pad
100、100”、100a、200‧‧‧增層結構100, 100”, 100a, 200‧‧‧ layered structure
41、41”‧‧‧第三感光性介電層41, 41"‧‧‧ Third photosensitive dielectric layer
421、421”‧‧‧第三導電盲孔421, 421"‧‧‧ Third conductive blind hole
51‧‧‧第四感光性介電層51‧‧‧The fourth photosensitive dielectric layer
521‧‧‧第四導電盲孔521‧‧‧4th conductive blind hole
61‧‧‧第五感光性介電層61‧‧‧ Fifth photosensitive dielectric layer
621‧‧‧第五導電盲孔621‧‧‧5th conductive blind hole
622‧‧‧測試端連接墊622‧‧‧Test terminal connection pad
71‧‧‧第六感光性介電層71‧‧‧ Sixth photosensitive dielectric layer
721‧‧‧第六導電盲孔721‧‧‧6th conductive blind hole
722、422”‧‧‧植球端連接墊722, 422" ‧ ‧ ball end connection pads
80、80”‧‧‧防焊層80, 80" ‧ ‧ solder mask
81、81”‧‧‧錫球81, 81"‧‧‧ solder balls
d‧‧‧孔徑D‧‧‧ aperture
D‧‧‧間距D‧‧‧ spacing
31a‧‧‧內層感光性介電層31a‧‧‧Inner photosensitive dielectric layer
321a‧‧‧內層導電盲孔321a‧‧‧Inner conductive blind hole
322a‧‧‧內層連接墊322a‧‧‧ Inner connection pad
3221a‧‧‧內層線路層3221a‧‧‧ Inner layer
41a‧‧‧外層感光性介電層41a‧‧‧Outer photosensitive dielectric layer
422a‧‧‧測試端連接墊422a‧‧‧Test end connection pad
43a‧‧‧凹槽43a‧‧‧ Groove
圖1,為習知技術之垂直式晶圓測試結構的側視示意圖。1 is a side elevational view of a vertical wafer test structure of the prior art.
圖2,為習知技術之測試載板為多層陶瓷基板的剖面示意圖。2 is a schematic cross-sectional view showing a test carrier of the prior art as a multilayer ceramic substrate.
圖3,為習知技術之測試載板為多層有機基板的剖面示意圖。3 is a schematic cross-sectional view showing a test carrier of the prior art as a multilayer organic substrate.
圖4A至4G,為本發明之微小間距測試載板結構之製法第一實施例的流程示意圖。4A to 4G are schematic flow charts showing the first embodiment of the method for manufacturing the micro pitch test carrier structure of the present invention.
圖5A至5G,為本發明之微小間距測試載板結構之製法第二實施例的流程示意圖。5A to 5G are schematic flow charts showing a second embodiment of a method for manufacturing a micro pitch test carrier structure according to the present invention.
圖6A至6G,為本發明之微小間距測試載板結構之雙面增層之製法的流程示意圖。6A to 6G are schematic flow charts showing the manufacturing method of the double-sided layering of the micro-pitch test carrier structure of the present invention.
圖7A至7E,為本發明之微小間距測試載板結構之單面增 層之製法的流程示意圖。7A to 7E show a single-sided increase of the micro-pitch test carrier structure of the present invention Schematic diagram of the process of layer production.
圖8,為本發明之微小間距測試載板之局部的增層結構之製法的示意圖。Fig. 8 is a schematic view showing the method of manufacturing the partial buildup structure of the micro pitch test carrier of the present invention.
圖8A,為本發明之微小間距測試載板之局部的增層結構之製法的俯視示意圖。Fig. 8A is a top plan view showing the method of manufacturing the partial buildup structure of the micro pitch test carrier of the present invention.
圖9A,為本發明之微小間距測試載板之核心基板為另一種雙面的核心基板的剖面示意圖。9A is a cross-sectional view showing the core substrate of the micro pitch test carrier of the present invention as another double-sided core substrate.
圖9B,為本發明之微小間距測試載板之核心基板為結合多層壓合的核心基板的剖面示意圖。9B is a schematic cross-sectional view showing the core substrate of the micro pitch test carrier of the present invention in combination with a multi-laminated core substrate.
圖9C,為本發明之微小間距測試載板之核心基板為另一種結合多層壓合的核心基板的剖面示意圖。9C is a cross-sectional view showing the core substrate of the micro pitch test carrier of the present invention as another core substrate combined with a multi-laminate.
圖9D,為本發明之微小間距測試載板之核心基板為結合多次多層壓合的的核心基板的剖面示意圖。FIG. 9D is a cross-sectional view showing the core substrate of the micro pitch test carrier of the present invention as a core substrate combined with multiple times of lamination.
10‧‧‧核心基板10‧‧‧ core substrate
101‧‧‧第一線路層101‧‧‧First circuit layer
102‧‧‧第二線路層102‧‧‧Second circuit layer
103‧‧‧導電通孔103‧‧‧ conductive through hole
21‧‧‧第一感光性介電層21‧‧‧First photosensitive dielectric layer
22‧‧‧第一金屬層22‧‧‧First metal layer
211‧‧‧第一開孔211‧‧‧ first opening
221‧‧‧第一導電盲孔221‧‧‧First conductive blind hole
222‧‧‧第一連接墊222‧‧‧First connection pad
31‧‧‧第二感光性介電層31‧‧‧Second photosensitive dielectric layer
32‧‧‧第二金屬層32‧‧‧Second metal layer
311‧‧‧第二開孔311‧‧‧Second opening
321‧‧‧第二導電盲孔321‧‧‧Second conductive blind hole
322‧‧‧第二連接墊322‧‧‧Second connection pad
Claims (10)
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TW101134638A TWI444632B (en) | 2012-09-21 | 2012-09-21 | A method of fabricating a testing board |
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TW101134638A TWI444632B (en) | 2012-09-21 | 2012-09-21 | A method of fabricating a testing board |
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TWI444632B true TWI444632B (en) | 2014-07-11 |
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CN112002684A (en) * | 2020-08-17 | 2020-11-27 | 北京蓝智芯科技中心(有限合伙) | Space conversion substrate based on rewiring circuit layer and preparation method thereof |
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