TW201413261A - A method of fabricating a testing board - Google Patents

Abstract

A method of fabricating a testing board, in the following steps of: providing a core substrate; forming a first circuit layer and a second circuit layer; to form a dielectric layer; forming holes arranged in the dielectric layer; forming a conductive layer; forming a metal layer distributed in the holes; removing the conductive layer; grinding the metal layer for forming a plurality of first conductive pillars; forming the build-up layer, wherein the build-up layer includes at least one second dielectric layer, second conductive pillars formed in the second dielectric layer, and the second conductive pillars stack the first conductive pillars.

Description

Method for manufacturing micro-pitch test carrier structure

The invention relates to a method for manufacturing a test carrier structure, in particular to a method for testing a micro-pitch test carrier structure for testing on an integrated circuit or after packaging.

Referring to FIG. 1 to FIG. 3, a general vertical wafer test structure includes a printed circuit board 2A connected to a test device, and a test carrier 1A connected to the printed circuit board 2A. The test carrier 1A is connected to a plurality of Wafer test probe 11A for testing wafer 4A on mobile stage 3A, wherein test carrier 1A can be divided into (1) multilayer ceramic substrate 1B (Multi Layer Ceramic, MLC), as shown in FIG. 2; 2) Multi-layer organic substrate 1C (Multi Layer Organic, MLO), as shown in FIG. However, the process of the two processes is quite different. For example, the multilayer ceramic substrate (MLC) must be fabricated by a low temperature co-fired multilayer ceramic (LTCC) process. The green tape can be processed with a green process and a high temperature sintering process. Usually the number of floors is high and the price is very high. The multilayer organic substrate (MLO) can be completed by using a printed circuit board (PCB) process. Although the circuit miniaturization can be achieved by investing in lithography equipment, the blind hole processing is still performed by laser drilling. And processing capacity will be limited.

For the MLC carrier board used for testing, the general design uses a single die (Single DUT) or a pair of die (Dual DUT) for testing. When there are too many I/O points or multiple grains (Multi DUT) Test, the design becomes relatively complicated, and the line width of the printing method is at least 100 micrometers, resulting in a limited wiring density. It is necessary to increase the number of layers to disperse the density of the wiring, so the number of layers may be as high as 50 or more. Plus each layer must be laser-punched and silver-coated Paste plugs and printed circuits, so the relative cost is high and the delivery time is long.

The test MLO carrier board can be used in PCB process and materials, but for small pitch processing, the build-up material is limited. When a glass fiber-containing material is subjected to laser drilling, it often causes a lamp core effect after the plating and a short circuit is discarded. If Ajinomoto Build-up Film (ABF) is used for mass production, it has no glass fiber, but it must be invested in expensive press equipment, expensive copper equipment and potion. Sample plants (eg, test carrier plants) are affordable.

When the development of packaging tends to Flip Chip Package, the arrangement of I/O is in the form of Ball Grid Array. Therefore, the key to the process of testing with small pitch is that the opening is small. And arranged in an array, but after the glass fiber material is subjected to carbon dioxide (CO2) laser or ultraviolet (UV) laser drilling, it needs to go through the desmear process, which seriously causes the aperture to be enlarged. The problem is that the finished product can only reach a pitch of about 140 microns. Perhaps the parameters of the laser processing can be re-optimized, so that the pore size is further reduced, and even the desmear is not required, but the glass transition temperature (Tg) of the material is not high enough (about 150 ° C), and the coefficient of thermal expansion is too large (CTE about 250 ppm / °C), there will be great doubts about the reliability of subsequent product assembly quality.

The reason is that the present inventors have felt that the above problems can be improved, and that the present invention has been deliberately studied and used in conjunction with the theory, and a present invention which is reasonable in design and effective in improving the above problems has been proposed.

The invention provides a method for manufacturing a micro-pitch test carrier structure, which can effectively reduce the aperture of the dielectric layer opening to further achieve the test capability with a small pitch.

In order to achieve the above, the present invention provides a micro pitch test The method of manufacturing the carrier structure comprises: providing a core substrate, wherein the opposite surfaces respectively form a first circuit layer and a second circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer; forming a photosensitive property a dielectric layer covering the surface of the core substrate and the first circuit layer; forming a plurality of openings arranged at equal intervals in the first photosensitive dielectric layer by exposure and development to expose a portion of the first circuit layer; Forming a conductive layer over the surface of the photosensitive dielectric layer and the openings through a sputtering method; forming a metal layer filled in the openings through electroplating; removing the surface exposed on the photosensitive dielectric layer The conductive layer is formed by polishing the metal layer exposed on the surface of the first photosensitive dielectric layer to form a plurality of first conductive via holes, wherein the first conductive blind vias respectively have a contact pad and are electrically connected to a first wiring layer; and a build-up structure formed on the first photosensitive dielectric layer, the build-up structure comprising at least one second photosensitive dielectric layer formed in the second photosensitive dielectric layer a plurality of second conductive blind holes and the The second line are stacked conductive vias disposed in the first conductive blind hole and electrically connected to the first circuit layer.

The invention provides a method for fabricating a micro-pitch test carrier structure, comprising: providing a core substrate, wherein a first circuit layer and a second circuit layer are respectively formed on opposite surfaces thereof, wherein the first circuit layer is electrically connected to the first circuit layer a second circuit layer; a photosensitive dielectric layer is formed on the surface of the core substrate and the first circuit layer; and a plurality of openings arranged at equal intervals are formed in the first photosensitive dielectric layer by exposure and development. Forming a portion of the first circuit layer; forming a conductive layer over the surface of the photosensitive dielectric layer and the openings through sputtering; forming a metal layer over the first photosensitive dielectric layer by electroplating And the entire surface is filled in the openings; and the metal layer and the portion of the surface of the first photosensitive dielectric layer are removed together a conductive layer; a portion of the metal layer exposed on the surface of the first photosensitive dielectric layer to form a plurality of first conductive vias, each of the first conductive vias having a contact pad and electrically connected thereto a first circuit layer; and a build-up structure formed on the first photosensitive dielectric layer, the build-up structure comprising at least one second photosensitive dielectric layer, formed in the second photosensitive dielectric layer And a second conductive via hole, wherein the second conductive via holes are respectively stacked on the first conductive blind via holes and electrically connected to the first circuit layer.

According to the method for fabricating the micro-pitch test carrier structure of the present invention, the aperture of the opening is effectively reduced, so that the conductive blind holes are arranged at a fine pitch to further achieve the capability of testing with a small pitch.

In order to further understand the technology, method and effect of the present invention in order to achieve the intended purpose, reference should be made to the detailed description and drawings of the present invention. The drawings are to be considered in a simplified form, and are not intended to limit the scope of the present invention.

[First Embodiment]

Please refer to FIG. 4A to FIG. 4G, which are schematic diagrams showing the flow of the first embodiment of the method for manufacturing the micro pitch test carrier structure of the present invention.

As shown in FIG. 4A, a core substrate 10 is provided. A first circuit layer 101 and a second circuit layer 102 are formed on the upper and lower surfaces. The first circuit layer 101 is electrically connected to the via hole 103. The second circuit layer 102. In this embodiment, the core substrate 10 is provided as a double-sided core substrate. However, the number of layers and the layout of the circuit are not limited thereto. As shown in FIGS. 9A to 9D, it may be determined as another double-sided core substrate 10a according to design requirements; combined with the multi-laminated core substrate 10b; another combination The multi-laminated core substrate 10c; or a core substrate 10d combined with a plurality of layers.

As shown in FIG. 4B, a first photosensitive dielectric layer 21 is formed to cover the surface of the core substrate 10 and the first wiring layer 101. In detail, the first photosensitive dielectric layer 21 is formed by printing or coating, and the first photosensitive dielectric layer 21 is a photosensitive dielectric material having a high resistance.

As shown in FIG. 4C, a plurality of first openings 211 arranged at a fine pitch are formed in the first photosensitive dielectric layer 21 by exposure development to expose a portion of the first wiring layer 101. In more detail, the first opening 211 having a pore diameter d of 62.5 μm or less is formed through the photosensitive effect of the photosensitive dielectric material and by exposure development, and the first openings 211 may be arranged in an array. In other words, the first opening 211 can be miniaturized by the exposure and development method, and the aperture d can increase or decrease the aperture d according to the film thickness of the photosensitive material. In practice, it ultimately depends on the exposure capability of the exposure device, and the advantage is that it is unnecessary. The laser hole is formed by the laser processing, and the hole diameter d of the first opening 211 is not enlarged, and the reliability is not affected by the formation of the glue. The short circuit electrical test can be passed, and the laser drilling is saved. Time can improve production efficiency and production quality.

As shown in FIG. 4D, a conductive layer 212 is formed on the surface of the first photosensitive dielectric layer 21 and the first openings 211 by sputtering. It should be noted that since the first photosensitive dielectric layer 21 itself is a smooth surface and no conductive material exists, the present invention is formed by direct current sputtering. The conductive layer 212 is formed to enhance the bonding force, and the conductive layer 212 is a metal thin film having conductivity.

As shown in FIG. 4E, exposure development is performed according to a predetermined line totem (not shown), and the photoresist 213 is overlaid on the surface of the first photosensitive dielectric layer 21 on the surface of the non-line totem, as after plating. A first metal layer 22 is formed by masking and then electroplating, and is filled in the opening 211. It should be noted that, by conducting current of the conductive layer 212, copper is deposited in the first opening 211 to form the first metal layer 22, and the material of the conductive layer 212 is selected from the group consisting of chromium alloy, copper, titanium and tungsten. A group of groups, but not limited. Further, the material to be plated is preferably copper, but is not limited thereto, and may be a metal material or an alloy material such as gold, silver or tin.

As shown in FIG. 4F and FIG. 4G, the photoresist 213 and the conductive layer 212 exposed on the surface of the first photosensitive dielectric layer 21 are removed, and the first metal layer exposed on the surface of the first photosensitive dielectric layer 21 is polished. 22, to form a plurality of first conductive blind vias 221, each of the first conductive vias 222 having a first connection pad 222 and electrically connected to the first circuit layer 101.

[Second embodiment]

Please refer to FIG. 5A to FIG. 5G, which are schematic diagrams of the second embodiment of the method for manufacturing the micro pitch test carrier structure of the present invention. The difference from the first embodiment is that, as shown in FIG. 5E to FIG. 5G, a first metal layer 22 is formed on the entire surface of the first photosensitive dielectric layer 21 and is filled on the first surface by electroplating. a portion of the first metal layer 22 and the conductive layer 212 on the surface of the first photosensitive dielectric layer 21 are removed by etching, and the polished portion is exposed on the surface of the first photosensitive dielectric layer 21. The first metal layer 22 is formed to form a plurality of first conductive blind holes 221, and the first conductive blind holes 221 respectively have a connection pad 222, and the electrical Connected to the first circuit layer 101. It should be noted that the conductive layer 212 is mainly processed by sputtering film. According to the resistance formula R=ρ(L/A), when the thickness (A) is thin, a large DC resistance will be generated due to the conductive layer 212. The resistance becomes higher, so that the plating deposition rate becomes slower, thereby making the uniformity of the thickness of the first metal layer 22 better, which is more helpful for line etching.

At this point, the process of FIG. 4B to FIG. 4G of the first embodiment or the process of FIG. 5B to FIG. 5G of the second embodiment may be repeated according to design requirements, and a layer-added structure may be formed to complete the double-sided or multi-layer plate double-layer layering of the present invention. Add layers on one side with double-sided or multi-layer boards.

[Third embodiment]

Referring to Figures 6A through 6F, there is shown a method of fabricating a double-panel double-sided buildup of the micro pitch test carrier structure of the third embodiment of the present invention in accordance with the method of the first or second embodiment.

As shown in FIG. 6A, a core substrate 10 is provided. The core substrate 10 is a double-sided core substrate, and a first circuit layer 101 and a second circuit layer 102 are formed on the upper and lower surfaces, respectively. The conductive vias 103 are electrically connected to the second circuit layer 102.

As shown in FIG. 6B, a first photosensitive dielectric layer 21 and a second photosensitive dielectric layer 31 are formed on the upper and lower surfaces of the core substrate 10 and the surfaces of the first and second circuit layers 101 and 102, respectively. .

As shown in FIG. 6C , a plurality of first openings 211 and a plurality of second openings 311 are respectively formed in the first photosensitive dielectric layer 21 and the second photosensitive dielectric layer 31 to respectively expose the first portion The circuit layer 101 and the second circuit layer 102, and the apertures d of the first and second openings 211 and 311 are less than 62.5 micrometers.

As shown in FIG. 6D, the first openings 211 and the second openings The holes 311 respectively form a plurality of first conductive blind holes 221 and a plurality of second conductive blind holes 321 . Each of the first conductive vias 221 and each of the second conductive vias 321 has a first connection pad 222 and a second connection pad 322 .

As shown in FIG. 6E, structures 10 and 200 are formed on the first photosensitive dielectric layer 21 and the second photosensitive dielectric layer 31, respectively. The layered structure 100 includes a third photosensitive dielectric layer 41, an outermost photosensitive dielectric layer 61, a plurality of third conductive blind vias 421 formed in the third photosensitive dielectric layer 41, and A plurality of fifth conductive via holes 621 formed in the photosensitive dielectric layer 61 of the outermost layer. The third photosensitive dielectric layer 41 is covered on the first photosensitive dielectric layer 21, and the outermost photosensitive dielectric layer 61 is covered on the third photosensitive dielectric layer 41. The third conductive vias 421 are respectively stacked on the first conductive vias 221 , and the fifth conductive vias 621 are respectively stacked on the third conductive vias 421 .

The layered structure 200 includes a fourth photosensitive dielectric layer 51, a further outermost photosensitive dielectric layer 71, and a plurality of fourth conductive blind vias 521 formed in the fourth photosensitive dielectric layer 51. And a plurality of sixth conductive blind vias 721 formed in the other outermost photosensitive dielectric layer 71. The fourth photosensitive dielectric layer 51 is covered on the second photosensitive dielectric layer 31, and the other outermost photosensitive dielectric layer 71 is covered on the fourth photosensitive dielectric layer 51. The fourth conductive blind vias 521 are respectively stacked on the second conductive vias 321 , and the sixth conductive vias 721 are respectively stacked on the fourth conductive vias 521 .

The outermost photosensitive dielectric layer 61 is the test end of the micro pitch test carrier of the embodiment, and a plurality of test end connection pads 622 are formed for the plurality of wafer test probes 11A (FIG. 1). Connected to the center of the test terminal connection pads 622, the test terminal connection pads 622 are arranged in a matrix (as shown in the figure). 6F), or in a wraparound arrangement (as shown in FIG. 6G) and the spacing D between the center of each test end connection pad 622 and the center of each adjacent test end connection pad 622 is less than or equal to 140 microns, thereby The distance D between the round test probes can be tested with a small pitch.

The other outermost photosensitive dielectric layer 71 is the ball-grating end of the micro-pitch test carrier of the embodiment, and a plurality of ball-end connection pads 722 are formed and covered with a solder resist layer 80. The connection pads 722 are each provided with a solder ball 81 to be electrically connected to the printed circuit board 2A of the test equipment (see FIG. 1), and the manner of electrically connecting to the test equipment is not limited to the soldering method.

[Fourth embodiment]

Referring to Figures 7A through 7F, there is shown a method of forming a single-sided buildup of a multilayer board of the micro pitch test carrier structure of the present invention in accordance with the method of the first or second embodiment described above.

As shown in FIG. 7A, a core substrate 10" is provided. The core substrate 10" is a multi-layer core substrate, and a first circuit layer 101" and a second circuit layer 102" are formed on the upper and lower surfaces, respectively. The layer 101" is electrically connected to the second circuit layer 102". Furthermore, through the design of the multi-layer core substrate, a signal layer, a power layer, and a ground layer having a wider general line can be formed into a patterned signal layer (not shown) by using a conventional PCB process (such as etching). A patterned power layer (not shown) and a patterned ground plane (not shown) are integrally bonded to form a multilayer core substrate with a patterned signal layer, a patterned power plane, and a patterned ground plane Electrically connected to the first and second circuit layers 101", 102".

As shown in FIG. 7B, a first photosensitive dielectric layer 21" is formed to cover the surface of the core substrate 10" and the surface of the first wiring layer 101".

As shown in FIG. 7C, a plurality of layers are formed in the first photosensitive dielectric layer 21" The first opening 211" is to expose a portion of the first wiring layer 101", and the aperture d of each of the openings 211" is less than 62.5 microns.

As shown in FIG. 7D, a plurality of first conductive vias 221" are formed in the first openings 211", and each of the first conductive vias 221" has a first connection pad 222".

As shown in FIG. 7E, on the first photosensitive dielectric layer 21", a build-up structure 100" is formed. The build-up structure 100" includes a second photosensitive dielectric layer 31", and an outermost layer is photosensitive. a dielectric layer 41", a plurality of second conductive blind vias 321" formed in the second photosensitive dielectric layer 31", and a plurality of third conductive layers formed in the photosensitive dielectric layer 41" of the outermost layer a blind via 421" covering the second photosensitive dielectric layer 31" on the first photosensitive dielectric layer 21", covering the outermost photosensitive dielectric layer 41" in the second photosensitive dielectric layer 41". The second conductive vias 321 ′′ are respectively stacked on the first conductive vias 221 ′′, and the third conductive vias 421 ′′ are respectively stacked on the second conductive vias 321 ′′.

The outermost third photosensitive dielectric layer 41" is the test end of the micro pitch test carrier of the embodiment, and a plurality of test end connection pads 422" are formed. The plurality of wafer test probes 1A (FIG. 1) are electrically connected, and the distance D between the center of each test terminal connection pad 422" and the center of each adjacent test terminal connection pad 422 is less than or equal to 140. Micron, in practice, depending on the wafer to be tested, by means of the wafer test probe spacing D, a small pitch test capability can be achieved.

The second circuit layer 102" is the ball-grating end of the micro-pitch test carrier of the embodiment, and is covered with a solder resist layer 80". The second circuit layer 102" is provided with a plurality of solder balls 81" for power supply. Connected to the printed circuit board 2A of the test equipment (Figure 1), and the way of electrical connection to the test equipment is not limited by the welding method.

[Fifth Embodiment]

Please refer to FIG. 8 and FIG. 8A , which are schematic diagrams showing the manufacturing method of a part of the layered structure of the micro pitch test carrier of the embodiment. The difference from the above embodiment is that the build-up structure 100a includes an inner photosensitive dielectric layer 31a and an outer photosensitive dielectric layer 41a, which are formed by the exposure and development method on the photosensitive dielectric layer 41a outside the build-up structure 100a. There is a recess 43a which exposes an inner layer circuit layer 3221a formed by an inner layer connection pad 322a of a portion of the inner conductive via 321a for embedding electronic components such as resistors, capacitors or inductors, and the recess The groove 43a forms an inner layer circuit layer 3221a located close to the object to be tested (DUT), which contributes to an improvement in electrical quality by shortening the path, and can achieve radio frequency (RF) tuning according to the characteristics of embedding various electronic components. Design requirements for various functions such as filtering and power integration.

In summary, the advantages of the present invention are at least:

(1) Cost reduction and working hours: The invention adopts the exposure and development process, and can simultaneously save the blackening, pressing and laser drilling time in the multilayer organic carrier (MLO) process, and can be combined with the line addition method. The production also helps to reduce the overall line width / line spacing, can increase the density of the wiring, can also save the cost and working hours of the multilayer ceramic carrier (MLC) silver paste printed circuit, and effectively reduce the number of layers.

(2) Reducing the aperture and eliminating the need for desmear: The invention adopts a photosensitive material as a dielectric layer, does not need to be mechanically processed, and is processed by an exposure and development process, and does not need to go through a desmear process to solve the aperture expansion. The problem, in addition, the processing time of blind holes can also be shortened.

(3) Increase the number of tests of the Device Under Test: reduce the aperture to make the spacing smaller, which helps to arrange the wiring at a small pitch, which can improve each The density of the layer design and contributes to the layout of multiple DUT designs.

(4) Power supply optimization: The present invention utilizes the characteristics of the photosensitive dielectric material to form a groove through the exposure and development near the DUT end to embed the electronic component on the circuit layer, which is comparable to the general layout. Better to improve power integrity.

(5) Increase the application range of the product: the glass transition temperature (Tg) of the photosensitive dielectric material is about 200 ° C, so there will be no restrictions on the selected plate, ceramic materials or printed circuit board materials can be used, so multiple layers The method of the present invention can be applied to both a ceramic substrate (MLC) or a multilayer organic substrate (MLO) product.

(known technology)

1A‧‧‧ test carrier

11A‧‧‧ wafer test probe

1B‧‧‧Multilayer ceramic substrate

1C‧‧‧Multilayer organic substrate

2A‧‧‧Printed circuit board

3A‧‧‧Mobile stage

4A‧‧‧ wafer

(this invention)

10, 10", 10a, 10b, 10c, 10d‧‧‧ core substrate

101, 101”‧‧‧First circuit layer

102, 102"‧‧‧second circuit layer

103, 103"‧‧‧ conductive through holes

21, 21" ‧ ‧ first photosensitive dielectric layer

211, 211" ‧ ‧ first opening

212‧‧‧ Conductive layer

213‧‧‧Light resistance

22, 22" ‧ ‧ first metal layer

221, 221"‧‧‧ first conductive blind hole

222, 222" ‧ ‧ first connection pad

31, 31"‧‧‧Second photosensitive dielectric layer

311‧‧‧Second opening

32‧‧‧Second metal layer

321,321"‧‧‧Second conductive blind hole

322‧‧‧Second connection pad

100, 100”, 100a, 200‧‧‧ layered structure

41, 41"‧‧‧ Third photosensitive dielectric layer

421, 421"‧‧‧ Third conductive blind hole

51‧‧‧The fourth photosensitive dielectric layer

521‧‧‧4th conductive blind hole

61‧‧‧ Fifth photosensitive dielectric layer

621‧‧‧5th conductive blind hole

622‧‧‧Test terminal connection pad

71‧‧‧ Sixth photosensitive dielectric layer

721‧‧‧6th conductive blind hole

722, 422" ‧ ‧ ball end connection pads

80, 80" ‧ ‧ solder mask

81, 81"‧‧‧ solder balls

D‧‧‧ aperture

D‧‧‧ spacing

31a‧‧‧Inner photosensitive dielectric layer

321a‧‧‧Inner conductive blind hole

322a‧‧‧ Inner connection pad

3221a‧‧‧ Inner layer

41a‧‧‧Outer photosensitive dielectric layer

422a‧‧‧Test end connection pad

43a‧‧‧ Groove

1 is a side elevational view of a vertical wafer test structure of the prior art.

2 is a schematic cross-sectional view showing a test carrier of the prior art as a multilayer ceramic substrate.

3 is a schematic cross-sectional view showing a test carrier of the prior art as a multilayer organic substrate.

4A to 4G are schematic flow charts showing the first embodiment of the method for manufacturing the micro pitch test carrier structure of the present invention.

5A to 5G are schematic flow charts showing a second embodiment of a method for manufacturing a micro pitch test carrier structure according to the present invention.

6A to 6G are schematic flow charts showing the manufacturing method of the double-sided layering of the micro-pitch test carrier structure of the present invention.

7A to 7E are schematic flow charts showing a method of manufacturing a single-sided build-up layer of a fine pitch test carrier structure according to the present invention.

Figure 8 is a partial layered structure of the micro pitch test carrier of the present invention. Schematic diagram of the system of law.

Fig. 8A is a top plan view showing the method of manufacturing the partial buildup structure of the micro pitch test carrier of the present invention.

9A is a cross-sectional view showing the core substrate of the micro pitch test carrier of the present invention as another double-sided core substrate.

9B is a schematic cross-sectional view showing the core substrate of the micro pitch test carrier of the present invention in combination with a multi-laminated core substrate.

9C is a cross-sectional view showing the core substrate of the micro pitch test carrier of the present invention as another core substrate combined with a multi-laminate.

FIG. 9D is a cross-sectional view showing the core substrate of the micro pitch test carrier of the present invention as a core substrate combined with multiple times of lamination.

10‧‧‧ core substrate

101‧‧‧First circuit layer

102‧‧‧Second circuit layer

103‧‧‧ conductive through hole

21‧‧‧First photosensitive dielectric layer

22‧‧‧First metal layer

211‧‧‧ first opening

221‧‧‧First conductive blind hole

222‧‧‧First connection pad

31‧‧‧Second photosensitive dielectric layer

32‧‧‧Second metal layer

311‧‧‧Second opening

321‧‧‧Second conductive blind hole

322‧‧‧Second connection pad

Claims (12)

A method for fabricating a fine pitch test carrier structure includes the steps of: providing a core substrate having opposite surfaces forming a first circuit layer and a second circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer Forming a photosensitive dielectric layer covering the surface of the core substrate; forming a plurality of openings in the photosensitive dielectric layer by exposure and development to expose a portion of the first circuit layer; forming a conductive through sputtering a layer covering the surface of the photosensitive dielectric layer and the openings; covering the photoresist on the surface of the photosensitive dielectric layer, and performing exposure and development according to a predetermined line totem; according to the predetermined line totem, through Forming a metal layer to fill the openings and the surface of the photosensitive dielectric layer; removing the photoresist and the conductive layer exposed on the surface of the photosensitive dielectric layer; and forming the photosensitive dielectric Forming a layered structure on the layer, the layered structure comprising a photosensitive dielectric layer forming at least one layer; wherein the plurality of conductive blind holes are formed in the photosensitive dielectric layers, and the conductive blinds hole Are disposed stacked on the first wiring layer. The method for manufacturing a micro pitch test carrier structure according to claim 1, wherein the core substrate is a double-sided core substrate or a multi-layer core plate. The method of fabricating a micro pitch test carrier structure as described in claim 1 wherein the line totem is formed by etching or addition. The method for manufacturing a micro pitch test carrier structure as described in claim 1, wherein the addition method is further a sputtering addition method. The method of fabricating a micro pitch test carrier structure according to claim 1, wherein the photoresist is overlaid or coated on the surface of the photosensitive dielectric layer. The method for manufacturing a fine pitch test carrier structure according to claim 1, wherein each of the openings has a pore diameter of 62.5 μm or less. The method for manufacturing a fine pitch test carrier structure according to claim 1, wherein a distance between a center of each of the conductive blind holes and a center of each of the adjacent conductive blind holes is less than or equal to 140 micrometers. The method for fabricating a micro pitch test carrier structure according to claim 1, further comprising forming an outermost photosensitive dielectric layer in the buildup layer and in the outermost photosensitive dielectric layer At least one recess is formed for embedding the electronic component. The method for manufacturing a micro pitch test carrier structure according to claim 1, wherein the embedded electronic component is a resistor, a capacitor, an inductor or a combination thereof. The method for fabricating the micro pitch test carrier structure according to claim 4, further comprising forming a plurality of test end connection pads on the outermost photosensitive dielectric layer, and the test end connection pads are arranged in a matrix Or wraparound, electrically connected to multiple wafer test probes. The method for fabricating the micro pitch test carrier structure according to claim 1, further comprising forming another build-up structure covering the surface of the core substrate and the second circuit layer. The method for manufacturing a micro pitch test carrier structure according to claim 1, wherein the core substrate further comprises a patterned power supply layer and a patterned ground layer, the patterned power supply layer and the patterned ground layer Sexually connected to the first and second circuit layers.