CN112002684A - Space conversion substrate based on rewiring circuit layer and preparation method thereof - Google Patents

Space conversion substrate based on rewiring circuit layer and preparation method thereof Download PDF

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Publication number
CN112002684A
CN112002684A CN202010825690.XA CN202010825690A CN112002684A CN 112002684 A CN112002684 A CN 112002684A CN 202010825690 A CN202010825690 A CN 202010825690A CN 112002684 A CN112002684 A CN 112002684A
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layer
connection
electronic
wafer
redistribution
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张银华
黄士芬
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Nanjing Xinjuqun Integrated Circuit Testing Co ltd
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Beijing Lanzhixin Technology Center LP
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2889—Interfaces, e.g. between probe and tester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Abstract

The invention provides a space conversion matrix structure based on a rewiring circuit layer and a preparation method thereof, wherein the matrix comprises: the redistribution electronic circuit layer comprises a first connecting surface, a second connecting surface and an electronic wiring layer structure between the first connecting surface and the second connecting surface, wherein the first connecting surface is provided with first electronic connection with a first interval, the second surface is provided with second electronic connection with a second interval, the first electronic connection is electrically connected with the second electronic connection through the wiring layer structure, the second interval is larger than the first interval, the first electronic connection is provided with a probe connecting layer, and the second electronic connection is provided with a metal bump; and inserting the circuit board, and bonding with the rewiring circuit layer through the metal bumps. The invention provides an advanced structure and a manufacturing process of a space conversion substrate compatible with a wafer manufacturing process, can synchronously and continuously reduce the micro-scale electronic connection of wafers and chips, and meets the requirements of the next generation of electronic tests of the wafers and the chips such as high-performance application chips, notebook computers, server chips and the like.

Description

Space conversion substrate based on rewiring circuit layer and preparation method thereof
Technical Field
The invention belongs to the field of semiconductor test equipment, and particularly relates to a structure of a space conversion substrate based on a rewiring circuit layer and a preparation method thereof, which are used for manufacturing an advanced probe card to realize electrical test of wafers and chips in a microelectronic manufacturing link
Background
In the semiconductor industry chain, wafer and chip testing provides testing on the electrical functions of wafers, and test data is fed back to the front-end manufacturing process of a wafer factory to improve the process or ensure the yield; meanwhile, the wafer test can filter the silicon wafer with poor electrical function before the silicon chip enters the final package, so as to avoid the increase of the manufacturing cost caused by the defective products. Probe cards are a core component of the wafer and chip testing process, providing electrical connections between the wafer/silicon chip and the test equipment. The space transformer substrate is a core component in the entire probe card.
At present, in the field of wafer and chip testing, a known space transformation substrate is formed by laminating and cutting a multilayer ceramic substrate and a multilayer organic polymer layer. Such as a multi-layer ceramic substrate, is made by co-firing a high-temperature or low-temperature co-fired ceramic through multi-layer lamination, and is generally called a multi-layer ceramic space conversion substrate (MLC). For a multi-layer organic poly (MLO), it is based on a conventional electronic packaging substrate that is laminated and cut in multiple steps.
Space-converting substrates, which are realized by laminating and dicing multilayer ceramic substrates and multilayer organic polymer layers, are generally formed by using low-end photolithography and laser etching techniques to form micro-via arrays, and are limited by material and process limitations, and the minimum line width L2/pitch L1 is generally 20 micrometers/20 micrometers, and can be as small as 15 micrometers/15 micrometers, respectively, as shown in fig. 1, thereby limiting the space-converting substrates to meet the requirements of next-generation high-performance application chip (AP) wafer and chip testing. The minimum pitch of electronic interconnects on high performance application chips (APs) has been reduced from 150 microns to 90-80 microns (um) and further to 50 microns and below, as the number of electronic interconnects has increased from hundreds to thousands, requiring better manufacturing processes to meet the demands of next generation high performance application chips, notebook computers and server chips for wafer and chip electronic testing.
Meanwhile, a space-converting substrate, which is realized by laminating and cutting a multilayer ceramic substrate and a multilayer organic polymer layer, requires a long manufacturing time for each layer, which seriously affects the manufacturing time and reduces the manufacturing efficiency.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a redistribution layer-based space transformer substrate and a method for manufacturing the same, which are used to solve the problems of the prior art, such as the limitation of scaling of the space transformer substrate, high manufacturing cost, and long manufacturing period, so as to meet the requirements of the next generation or generations of wafer and chip electrical tests.
To achieve the above and other related objects, the present invention provides a method for preparing a redistribution layer-based space transformer substrate for substrate assembly probe array to manufacture an advanced probe card for connecting a wafer with a wafer test system to complete electrical testing of silicon wafers and chips, the method comprising: 1) providing a wafer, and forming a redistribution layer on the wafer, wherein the redistribution layer comprises a signal layer and a power/ground layer, the redistribution layer comprises a first connection surface and a second connection surface which are opposite to each other, and a wiring layer structure between the first connection surface and the second connection surface, the first connection layer has first electronic connection with a first spacing, the second surface has second electronic connection with a second spacing, the first electronic connection is electrically connected with the second electronic connection through the wiring layer structure, and the second spacing is larger than the first spacing; 2) forming a metal bump on the second electronic connection of the second connection surface; 3) cutting the wafer to obtain an independent space conversion sheet; 4) the space conversion sheet is jointed to an insertion circuit board through the metal salient points; 5) stripping the wafer to expose the first connection surface; 6) and forming a probe connection layer on the first electronic connection of the first connection surface for assembling a probe array to complete the preparation of the probe card.
Optionally, before forming the redistribution layer on the wafer in step 1), a step of forming a temporary bonding layer on the wafer is further included; and 5) stripping the wafer by a chemical method or a laser stripping method based on the temporary bonding layer.
Optionally, the wiring layer structure includes a plurality of electronic circuit layers, each electronic circuit layer includes an electronic connection, an interlayer dielectric and a conductive via, and the pitch of the electronic connection of the plurality of electronic circuit layers increases layer by layer from the first connection face to the second connection face.
Optionally, the first pitch is between 2 microns and 150 microns and the second pitch is between 150 microns and 500 microns.
Optionally, the step 1) of forming a redistribution layer on the wafer includes: 1-1) forming a photosensitive organic body insulating layer on the wafer, and forming a through hole in the photosensitive organic body insulating layer through a photolithography process; 1-2) forming a seed layer on the photosensitive organic body insulating layer and the through hole; 1-3) forming a patterned photoresist barrier layer on the photosensitive organic body insulating layer; 1-4) forming a metal layer in the photosensitive organic body insulating layer and the through hole by an electroplating process; 1-5) removing the photoresist barrier layer and the seed layer below the photoresist barrier layer to form an electronic circuit layer; 1-6) repeating steps 1-1) to 1-5) to form a rewired circuit layer having a plurality of circuit layers.
Optionally, the photo-sensitive organism insulating layer comprises one of photo-sensitive polyimide and photo-sensitive benzocyclobutene, the seed layer comprises a titanium-copper alloy, and the metal layer comprises copper.
Optionally, in step 6), a probe connection layer is formed on the first electronic connection by using an electroplating process, where the probe connection layer includes a nickel plating layer and a gold plating layer, and then, the probe array is assembled to the gold plating layer to complete the preparation of the probe card.
Optionally, the space conversion slices prepared on the basis of the same wafer are all space conversion slices with the same structure.
Optionally, in step 4), one of the interposer circuit boards engages one of the space transformers, or one of the interposer circuit boards engages a plurality of space transformers of the same structure at the same time.
Optionally, the space conversion sheet prepared on the basis of the same wafer includes a plurality of different structures of space conversion sheets, wherein the plurality of different structures of space conversion sheets are prepared by mixing optical masks.
Optionally, in step 4), one of the interposer circuit boards simultaneously engages with a plurality of space transformer chips of different structures.
Optionally, the interposer circuit board contains multiple layers of electronic windings including signal and power/ground layers and corresponding plated metal drilled structures.
The invention also provides a space transformation substrate based on the rewiring circuit layer, which is used for connecting a wafer and a wafer test system and comprises: the rewiring circuit layer comprises a first connecting surface, a second connecting surface and a wiring layer structure between the first connecting surface and the second connecting surface, wherein the first connecting surface and the second connecting surface are opposite, the wiring layer structure is arranged between the first connecting surface and the second connecting surface, the first connecting layer is provided with first electronic connection with a first interval, the second surface is provided with second electronic connection with a second interval, the first electronic connection is electrically connected with the second electronic connection through the wiring layer structure, the second interval is larger than the first interval, a probe connecting layer is formed on the first electronic connection of the first connecting surface, and a metal bump is formed on the second electronic connection of the second connecting surface; and inserting a circuit board, and bonding the redistribution circuit layer through the metal bumps.
Optionally, the wiring layer structure includes a plurality of electronic circuit layers, each electronic circuit layer includes an electronic connection, an interlayer dielectric and a conductive via, and the pitch of the electronic connection of the plurality of electronic circuit layers increases layer by layer from the first connection face to the second connection face.
Optionally, the interlayer dielectric comprises one of a photosensitive polyimide and a photosensitive benzocyclobutene, and the electrical connection comprises copper.
Optionally, the first pitch is between 2 microns and 150 microns and the second pitch is between 150 microns and 500 microns.
Optionally, the interposer board includes a first surface, a second surface and a connection circuit therebetween, the first surface has a third electrical connection with a second pitch, the second surface has a fourth electrical connection with a third pitch, the third electrical connection and the fourth electrical connection are electrically connected through the connection circuit, and the third pitch is equal to or greater than the second pitch.
Optionally, the third pitch is between 300 microns and 1000 microns.
Optionally, the probe connection layer includes a nickel plating layer and a gold plating layer.
Alternatively, one of the interposer circuit boards engages one of the space transformers, or one of the interposer circuit boards simultaneously engages a plurality of the space transformers of the same configuration.
Optionally, one of the interposer circuit boards simultaneously engages a plurality of differently configured space transformer blades.
Optionally, the interposer circuit board contains multiple layers of electronic windings including signal and power/ground layers and corresponding plated metal drilled structures.
As described above, the redistribution layer-based space transformation substrate and the method for manufacturing the same according to the present invention have the following advantages:
the invention overcomes the manufacturing technical limitation which is difficult to overcome by the space conversion substrate of the traditional multilayer ceramic space conversion substrate (MLC) and multilayer organic polymer layer (MLO), provides the advanced structure and the manufacturing process of the multilayer space conversion substrate (MLS) based on the silicon wafer manufacturing process which are compatible with the wafer manufacturing process, can synchronously and continuously reduce the micro-scale electronic connection of the wafer and the chip, and meets the requirements of the next generation of electronic tests of the wafer and the chip such as high-performance application chips, notebook computers, server chips and the like. Meanwhile, the invention can utilize the mixed optical mask to manufacture the space conversion wafer for testing different silicon wafers and chips on the same wafer, thereby providing flexibility for manufacturing, generating the space conversion wafer with different testing requirements at one time by utilizing a single wafer, greatly reducing the manufacturing cost and shortening the manufacturing period. The invention fills the technical gap in the field of wafer test interfaces, can manufacture advanced probe cards and meets the requirement of electronic test in the advanced wafer manufacturing link.
Drawings
Fig. 1 is a schematic diagram showing minimum line width/pitch of a space-converting substrate obtained by laminating and cutting a multilayer ceramic substrate and a multilayer organic polymer layer.
Fig. 2a to fig. 11 are schematic structural diagrams of steps 1) of a method for manufacturing a redistribution layer-based space transformation substrate according to an embodiment of the invention.
Fig. 12 is a schematic structural diagram of step 2) of the method for preparing a redistribution layer-based space transformation substrate according to the embodiment of the invention.
FIGS. 13a to 14c are schematic structural diagrams of the redistribution layer-based space transformation matrix in step 3) according to an embodiment of the present invention.
Fig. 15a to 16 are schematic structural diagrams showing the steps 4) of the method for preparing a redistribution layer-based space transformation substrate according to the embodiment of the invention.
Fig. 17-18 are schematic structural diagrams of step 5) of the method for manufacturing a redistribution layer-based space transformation substrate according to an embodiment of the invention.
FIGS. 19 a-21 b are schematic structural diagrams of step 6) of a method for fabricating a redistribution layer-based space transformation matrix according to an embodiment of the invention.
Description of the element reference numerals
101 wafer
102 temporary tie layer
103 photosensitive organic body insulating layer
104 through hole
105 seed layer
106 photoresist barrier layer
107 metal layer
108 welding layer
109 metal bump
110 plug-in circuit board
111 probe connection layer
112 underfill layer
D1 first pitch
D2 second pitch
D3 third distance
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
The existing multilayer ceramic substrate and the multilayer organic polymer layer are independent of the back end of wafer manufacturing process, so that the advanced manufacturing process of the back end of wafer manufacturing and the advanced electronic packaging based on the wafer cannot be directly utilized. In order to overcome the above-mentioned disadvantages of the conventional space transformation substrate, including the limitations of scaling, high manufacturing cost and long manufacturing period, the present invention provides a structure and a manufacturing method of a space transformation substrate based on a redistribution circuit layer, which satisfy the requirements of the next generation of high performance application chips, notebook computers and server chips for wafer and chip electronic tests. The invention utilizes the advanced manufacturing process design of the advanced wafer back end manufacturing process or the wafer level packaging to manufacture and realize the space conversion substrate based on the rewiring circuit layer, realizes the line width and the space synchronous with the wafer manufacturing technology, for example, the line width/the space can be reduced to 2 micrometers/2 micrometers at the minimum, and the line width/the space can be further reduced along with the steps of the silicon wafer manufacturing technology, thereby synchronously and continuously scaling the wafer and the chip micro-scale electronic connection, meeting the test requirement of the wafer and the chip, and overcoming the manufacturing technology limitation which is difficult to overcome by the space conversion substrate of the traditional MLO and MLC. Meanwhile, the manufacturing period can be shortened from one layer for one week to one layer in 1-2 days depending on the manufacturing process and flow of the wafer manufacturing redistribution circuit layer, so that the manufacturing cost and time are reduced. Because the space transformer substrate is fabricated directly from wafer and chip fabrication processes, the present invention may be referred to as a multi-layer silicon (MLS) substrate based redistribution routing layer, but is not limited to silicon substrates and may include silicon and glass.
As shown in fig. 2a to 20, the present embodiment provides a method for preparing a redistribution layer-based space transformer substrate for substrate assembly probe array to manufacture an advanced probe card for connecting a wafer and a wafer test system to complete electrical testing of silicon wafers and chips, the method comprising:
as shown in fig. 2a to 11, step 1) is performed first, a wafer 101 is provided, and a redistribution layer is formed on the wafer 101, where the redistribution layer includes a first connection surface and a second connection surface opposite to each other and a wiring layer structure therebetween, the first connection layer has a first electrical connection with a first pitch D1, the second surface has a second electrical connection with a second pitch D2, the first electrical connection is electrically connected to the second electrical connection through the wiring layer structure, and the second pitch D2 is greater than the first pitch D1.
The wafer 101 may be a silicon wafer 101, but may also be a glass substrate, for example.
In this embodiment, before forming the redistribution layer on the wafer 101, a step of forming a temporary bonding layer 102 on the wafer 101 is further included, and the temporary bonding layer 102 may be removed by a chemical method or a laser heating method.
Specifically, the step 1) of forming the redistribution layer on the wafer 101 includes:
3 as 3 shown 3 in 3 fig. 3 2 3a 3 to 3 5 3, 3 wherein 3 fig. 3 2 3b 3 is 3a 3 schematic 3 cross 3- 3 sectional 3 view 3 taken 3 along 3a 3- 3a 3' 3 of 3 fig. 3 2 3a 3, 3 step 3 1 3- 3 1 3) 3 is 3 performed 3 to 3 form 3a 3 temporary 3 bonding 3 layer 3 102 3 on 3 the 3 wafer 3 101 3, 3 form 3a 3 photosensitive 3 organic 3 body 3 insulating 3 layer 3 103 3 on 3 the 3 temporary 3 bonding 3 layer 3 102 3, 3 and 3 form 3a 3 via 3 hole 3 104 3 in 3 the 3 photosensitive 3 organic 3 body 3 insulating 3 layer 3 103 3 through 3a 3 photolithography 3 process 3. 3
The photosensitive organic body insulating layer 103 can be one of photosensitive polyimide and photosensitive benzocyclobutene, and the through hole 104 is formed in the photosensitive organic body insulating layer 103 through a photoetching process, so that the manufacturing precision of the through hole 104 can be effectively improved, and the aperture and the interval of the through hole 104 can be reduced to be synchronous with the manufacturing process of the wafer 101.
As shown in fig. 6, step 1-2) is then performed to form a seed layer 105 on the photosensitive organic insulating layer 103 and the via hole 104.
For example, metal sputtering may be used to create an ultra-thin titanium copper alloy (Ti/Cu) based seed layer 105.
As shown in fig. 7, step 1-3) is followed by forming a patterned photoresist barrier layer 106 on the photosensitive organic insulating layer 103. Specifically, a photoresist may be spin-coated onto the upper surface of the photosensitive organic insulating layer 103, and then a photolithography process may be performed using a photolithography machine and a photomask alignment to form the patterned photoresist barrier layer 106.
As shown in fig. 8, steps 1-4) follow, forming a metal layer 107 in the photosensitive organic insulating layer 103 and the via hole 104 by an electroplating process. In this embodiment, the metal layer 107 may be copper. During electroplating, the photoresist barrier layer 106 can block the growth of copper, and finally a metal layer 107 pattern complementary to the photoresist barrier layer 106 is formed.
As shown in fig. 9 and 10, step 1-5) is then performed to remove the photoresist barrier layer 106 and the seed layer 105 thereunder to form an electronic circuit layer, where the metal layer 107 in the via 104 is the first electronic connection.
For example, because the seed layer 105 is thin, the seed layer 105 may be self-aligned and etched by using the metal layer 107 as a mask to remove the metal layer, so that a photolithography step may be omitted, and the process cost may be effectively saved.
As shown in fig. 11, step 1-6) is followed, and steps 1-1) to 1-5) are repeated to form a rewired wiring layer having a plurality of electronic wiring layers.
After the above steps, the wiring layer structure includes a plurality of electronic circuit layers, each of which includes an electronic connection, an interlayer dielectric (e.g., a photosensitive organic insulating layer 103), and a conductive via 104, and the pitch of the electronic connection of the plurality of electronic circuit layers increases from the first connection face to the second connection face. By way of example, the first distance D1 is between 2 microns and 150 microns and the second distance D2 is between 150 microns and 500 microns.
The present invention relies on wafer 101 fabrication equipment and processes or wafer 101 level package fabrication processes to fabricate multiple layers of microscale electrical connections on a silicon wafer 101 using a redistribution routing layer fabrication process, where each layer includes an insulating layer and a conductive layer, such that small-pitch electrical connections are relaxed, layer-by-layer, to large-pitch electrical connections, and repeating such redistribution routing layer fabrication process to relax 90 micron or less pitch electrical connections to 300 micron or more pitch electrical connections through three or more layer expansions.
As shown in fig. 12, step 2) is then performed to form a metal bump 109 on the second electrical connection of the second connection surface.
For example, a metal bump 109 may be fabricated on the second electrical connection of the second connection surface by using a wafer 101 micro-connection process, and the metal bump 109 may be a solder ball, for example.
In this embodiment, before forming the metal bump 109, a step of forming a solder layer 108 based on an ultra-thin titanium-copper alloy (Ti/Cu) on the second electrical connection by metal sputtering is further included, and the solder layer 108 can effectively block diffusion of the metal bump 109 on one hand, and can effectively improve the bonding strength between the metal bump 109 and the second electrical connection on the other hand.
As shown in fig. 13a to 14c, step 3) is performed next, and the wafer 101 is diced to obtain independent space conversion slices.
The space transformer fabricated in this embodiment is typically thin, typically between 600 microns and 700 microns thick, and typically between 80 microns and 120 microns thick, such as 100 microns, if wafer 101 is removed.
3 as 3 shown 3 in 3 fig. 3 13 3a 3 and 3 13 3b 3, 3 wherein 3 fig. 3 13 3b 3 is 3a 3 schematic 3 cross 3- 3 sectional 3 view 3 taken 3 along 3a 3- 3a 3' 3 of 3 fig. 3 13 3a 3, 3 in 3 an 3 implementation 3 process 3, 3 the 3 optical 3 mask 3 used 3 for 3 each 3 space 3 transformer 3 on 3 the 3 wafer 3 101 3 is 3 the 3 same 3, 3 so 3 that 3 the 3 space 3 transformers 3 prepared 3 on 3 the 3 same 3 wafer 3 101 3 are 3 all 3 space 3 transformers 3 with 3 the 3 same 3 structure 3. 3
3 as 3 shown 3 in 3 fig. 3 14 3a 3 to 3 14 3 c 3, 3 fig. 3 14 3b 3 is 3a 3 schematic 3 cross 3- 3 sectional 3 structure 3 at 3a 3- 3a 3 ' 3 in 3 fig. 3 14 3a 3, 3 and 3 fig. 3 14 3 c 3 is 3a 3 schematic 3 cross 3- 3 sectional 3 structure 3 at 3b 3- 3b 3' 3 in 3 fig. 3 14 3a 3, 3 in 3 another 3 embodiment 3, 3 for 3 each 3 space 3 conversion 3 sheet 3 on 3 the 3 wafer 3 101 3, 3 which 3 is 3 prepared 3 by 3a 3 hybrid 3 optical 3 mask 3, 3 the 3 space 3 conversion 3 sheet 3 prepared 3 based 3 on 3 the 3 same 3 wafer 3 101 3 includes 3a 3 plurality 3 of 3 space 3 conversion 3 sheets 3 with 3 different 3 structures 3. 3 The invention utilizes the mixed optical mask to manufacture the space conversion sheets for testing different silicon wafers and chips on the same wafer 101, provides flexibility for manufacturing, can generate the space conversion sheets with different testing requirements by utilizing a single wafer 101 at one time, greatly reduces the manufacturing cost and shortens the manufacturing period.
As shown in fig. 15a to 16, step 4) is performed next, and the space transformer is bonded to an interposer substrate 110 via the metal bumps 109.
The interposer circuit board 110 includes a first side having a third electrical connection at a second pitch D2, a second side having a fourth electrical connection at a third pitch D3, the third and fourth electrical connections being electrically connected through the connection circuitry, and connection circuitry therebetween, the third pitch D3 being equal to or greater than the second pitch D2. The third distance D3 is between 300 microns and 1000 microns. For example, the interposer circuit board 110 may contain multiple layers of electrical windings including signal layers and power/ground layers, and corresponding plated via structures.
Specifically, the diced space transformer pieces (which create multiple layers of electronic circuit layers, with small-pitch electrical connections relaxed layer-by-layer to large-pitch electrical connections) are soldered to a printed circuit board or other manufacturing process based Interposer board 110(Interposer) using a reflow or thermocompression bonding process.
In one embodiment, as shown in fig. 15a, one interposer circuit board 110 may engage one space transformer, or one interposer circuit board 110 may simultaneously engage a plurality of space transformers of the same structure.
In another embodiment, as shown in fig. 16, one interposer board 110 may simultaneously engage a plurality of space transformers of different structures to perform multiple functions.
As shown in fig. 15b, in this embodiment, a step of forming an underfill layer 112 between the metal bump 109 and the interposer 110 may be further included to strengthen the structural strength and protect the metal bump 109.
As shown in fig. 17 and 18, wherein fig. 17 corresponds to fig. 15 and fig. 18 corresponds to fig. 16, step 5) is performed to peel off the wafer 101 to expose the first connection surface.
For example, in the present embodiment, the wafer 101 may be peeled by a chemical method or a laser peeling method based on the temporary bonding layer 102. Of course, the wafer 101 may also be peeled by grinding and polishing the wafer 101, and is not limited to the examples listed herein.
As shown in fig. 19a to 21b, wherein fig. 19 corresponds to fig. 17, fig. 20 corresponds to fig. 18, and step 6) is finally performed to form a probe connecting layer 111 on the first electrical connections of the first connecting surface, wherein the probe connecting layer 111 is used for assembling the probe 113 array to complete the preparation of the probe card.
Specifically, a probe connection layer 111 is formed on the first electronic connection by using an electroplating process, the probe connection layer 111 includes one of a nickel plating layer and a gold plating layer, and the probe connection layer 111 may be soft gold or hard gold in preparation for assembling a probe on the space transformation substrate.
The fabricated redistribution layer-based space transformer substrate (MLS) is electrically and optically inspected and qualified for probe 113 assembly, as shown in fig. 21a and 21b, to form a final probe card for electrical testing of wafers and dies during the wafer 101 fabrication process, so that the fabricated redistribution layer-based space transformer substrate can be used for further probe assembly and probe card fabrication.
Through the above process steps, the structure of the space transformation substrate based on the redistribution layer is manufactured. Subsequent rewiring circuit layer based space transformer substrates may be assembled by a reflow process or array of compressible probes onto printed circuit boards that are ultimately loaded onto a tester. Wherein, the adoption of the reflow soldering process can effectively reduce the cost. And the assembly mode of the array type compressible measuring probe is adopted, so that the assembly and disassembly can be carried out for many times, the maintenance is simple, and the maintenance cost is lower.
As shown in fig. 19a to 20, the present embodiment further provides a redistribution layer-based space transformer substrate for connecting a wafer and a wafer test system, the space transformer substrate comprising: a redistribution layer including first and second opposing connection faces and a wiring layer structure therebetween, the wiring layer structure including a signal layer and a power/ground layer, the first connection layer having first electrical connections at a first spacing D1, the second face having second electrical connections at a second spacing D2, the first electrical connections being electrically connected to the second electrical connections through the wiring layer structure, and the second spacing D2 being greater than the first spacing D1, probe connection layers 111 being formed on the first electrical connections of the first connection faces, and metal bumps 109 being formed on the second electrical connections of the second connection faces; and a circuit board 110 is inserted and bonded to the redistribution layer through the metal bumps 109.
The wiring layer structure comprises a plurality of layers of electronic circuit layers, each layer of electronic circuit layer comprises an electronic connection, an interlayer medium and a conductive through hole 104, and the distance between the electronic connections of the plurality of layers of electronic circuit layers increases from the first connection surface to the second connection surface layer by layer. Wherein the interlayer dielectric comprises one of photosensitive polyimide and photosensitive benzocyclobutene, and the electronic connection comprises copper.
The interposer circuit board 110 includes a first side having a third electrical connection at a second pitch D2, a second side having a fourth electrical connection at a third pitch D3, the third and fourth electrical connections being electrically connected through the connection circuitry, and connection circuitry therebetween, the third pitch D3 being equal to or greater than the second pitch D2.
By way of example, the first distance D1 is between 2 microns and 150 microns and the second distance D2 is between 150 microns and 500 microns. The third distance D3 is between 300 microns and 1000 microns.
The probe connection layer 111 includes a nickel plating layer and a gold plating layer.
The interposer circuit board 110 may contain multiple layers of electronic windings including signal layers and power/ground layers, and corresponding plated metal drilling structures.
As shown in fig. 19a, one of the interposer circuit boards 110 may be coupled with one of the space transformers, or one of the interposer circuit boards 110 may be coupled with a plurality of the space transformers of the same structure at the same time. As shown in fig. 19b, an underfill layer 112 may be further formed between the metal bump 109 and the interposer board 110, and the underfill layer 112 may reinforce structural strength and protect the metal bump 109.
As shown in fig. 20, one of the interposer circuit boards 110 may also be simultaneously bonded with a plurality of space transformers of different structures to achieve various functions.
As shown in fig. 21a and 21b, the probe connecting layer 111 has an array of probes 113 formed thereon to form a complete probe card, which can be used to connect a wafer and a wafer test system to complete electrical testing of silicon wafers and chips.
As described above, the redistribution layer-based space transformation substrate and the method for manufacturing the same according to the present invention have the following advantages:
the invention overcomes the manufacturing technical limitation which is difficult to overcome by the space conversion substrate of the traditional multilayer ceramic space conversion substrate (MLC) and multilayer organic polymer layer (MLO), provides the advanced structure and the manufacturing process of the space conversion substrate (MLS) which are compatible with the wafer manufacturing process, can synchronously and continuously reduce the micro-scale electronic connection of the wafer and the chip, and meets the requirements of the next generation of electronic test of the wafer and the chip such as a high-performance application chip, a notebook computer, a server chip and the like. Meanwhile, the invention can utilize the mixed optical mask to manufacture the space conversion wafer for testing different silicon wafers and chips on the same wafer, thereby providing flexibility for manufacturing, generating the space conversion wafer with different testing requirements at one time by utilizing a single wafer, greatly reducing the manufacturing cost and shortening the manufacturing period. The invention fills the technical gap in the field of wafer test interfaces, can manufacture advanced probe cards and meets the requirement of electronic test in the advanced wafer manufacturing link.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (22)

1. A method for preparing a space transformer substrate based on a redistribution layer, wherein the space transformer substrate is used for assembling a probe array on a substrate to manufacture an advanced probe card, and the probe card is used for connecting a wafer and a wafer test system to complete electrical testing of silicon wafers and chips, the method comprising:
1) providing a wafer, and forming a redistribution layer on the wafer, wherein the redistribution layer comprises a signal layer and a power/ground layer, the redistribution layer comprises a first connection surface and a second connection surface which are opposite to each other, and a wiring layer structure between the first connection surface and the second connection surface, the first connection layer has first electronic connection with a first spacing, the second surface has second electronic connection with a second spacing, the first electronic connection is electrically connected with the second electronic connection through the wiring layer structure, and the second spacing is larger than the first spacing;
2) forming a metal bump on the second electronic connection of the second connection surface;
3) cutting the wafer to obtain an independent space conversion sheet;
4) the space conversion sheet is jointed to an insertion circuit board through the metal salient points;
5) stripping the wafer to expose the first connection surface;
6) and forming a probe connection layer on the first electronic connection of the first connection surface for assembling a probe array to complete the preparation of the probe card.
2. The method for preparing a spatial conversion matrix based on a redistribution layer as claimed in claim 1, wherein: step 1) before forming a redistribution layer on a wafer, forming a temporary bonding layer on the wafer; and 5) stripping the wafer by a chemical method or a laser stripping method based on the temporary bonding layer.
3. The method for preparing a spatial conversion matrix based on a redistribution layer as claimed in claim 1, wherein: the wiring layer structure comprises a plurality of layers of electronic circuit layers, each layer of electronic circuit layer comprises an electronic connection, an interlayer medium and a conductive through hole, and the distance between the electronic connections of the electronic circuit layers is increased from the first connection surface to the second connection surface layer by layer.
4. The method for preparing a spatial conversion matrix based on a redistribution layer as claimed in claim 1, wherein: the first distance is between 2 micrometers and 150 micrometers, and the second distance is between 150 micrometers and 500 micrometers.
5. The method for preparing a spatial conversion matrix based on a redistribution layer as claimed in claim 1, wherein: the step 1) of forming the redistribution layer on the wafer comprises the following steps:
1-1) forming a photosensitive organic body insulating layer on the wafer, and forming a through hole in the photosensitive organic body insulating layer through a photolithography process;
1-2) forming a seed layer on the photosensitive organic body insulating layer and the through hole;
1-3) forming a patterned photoresist barrier layer on the photosensitive organic body insulating layer;
1-4) forming a metal layer in the photosensitive organic body insulating layer and the through hole by an electroplating process;
1-5) removing the photoresist barrier layer and the seed layer below the photoresist barrier layer to form an electronic circuit layer;
1-6) repeating steps 1-1) to 1-5) to form a rewired circuit layer having a plurality of circuit layers.
6. The method for preparing a spatial transformation matrix based on a redistribution layer as claimed in claim 5, wherein: the photo-sensitive organism insulating layer includes one of photo-sensitive polyimide and photo-sensitive benzocyclobutene, the seed layer includes a titanium-copper alloy, and the metal layer includes copper.
7. The method for preparing a spatial conversion matrix based on a redistribution layer as claimed in claim 1, wherein: and 6), forming a probe connecting layer on the first electronic connection by adopting an electroplating process, wherein the probe connecting layer comprises a nickel plating layer and a gold plating layer, and then assembling the probe array to the gold plating layer to finish the preparation of the probe card.
8. The method for preparing a spatial conversion matrix based on a redistribution layer as claimed in claim 1, wherein: the space conversion pieces prepared on the basis of the same wafer are all space conversion pieces with the same structure.
9. The method for preparing a spatial conversion matrix based on a redistribution layer as claimed in claim 8, wherein: in step 4), one of the interposer circuit boards is bonded to one of the space transformers, or one of the interposer circuit boards is bonded to a plurality of space transformers of the same structure at the same time.
10. The method for preparing a spatial conversion matrix based on a redistribution layer as claimed in claim 1, wherein: the space conversion sheet prepared on the basis of the same wafer comprises a plurality of space conversion sheets with different structures, wherein the space conversion sheets with the different structures are prepared through a hybrid optical mask.
11. The method for preparing a spatial conversion matrix based on a redistribution layer as claimed in claim 10, wherein: in step 4), one inserting circuit board is simultaneously jointed with a plurality of space conversion sheets with different structures.
12. The method for preparing a spatial conversion matrix based on a redistribution layer as claimed in claim 1, wherein: the interposer circuit board contains a multilayer electronic winding including a signal layer and a power/ground layer, and corresponding plated metal drilling structures.
13. A redistribution routing layer-based space transformer substrate for interfacing a wafer with a wafer test system, the space transformer substrate comprising:
the rewiring circuit layer comprises a first connecting surface, a second connecting surface and a wiring layer structure between the first connecting surface and the second connecting surface, wherein the first connecting surface and the second connecting surface are opposite, the wiring layer structure is arranged between the first connecting surface and the second connecting surface, the first connecting layer is provided with first electronic connection with a first interval, the second surface is provided with second electronic connection with a second interval, the first electronic connection is electrically connected with the second electronic connection through the wiring layer structure, the second interval is larger than the first interval, a probe connecting layer is formed on the first electronic connection of the first connecting surface, and a metal bump is formed on the second electronic connection of the second connecting surface;
and inserting a circuit board, and bonding the redistribution circuit layer through the metal bumps.
14. The redistribution routing layer-based space transformation fabric of claim 13, wherein: the wiring layer structure comprises a plurality of layers of electronic circuit layers, each layer of electronic circuit layer comprises an electronic connection, an interlayer medium and a conductive through hole, and the distance between the electronic connections of the electronic circuit layers is increased from the first connection surface to the second connection surface layer by layer.
15. The redistribution routing layer-based space transformer fabric of claim 14, wherein: the interlayer dielectric comprises one of photosensitive polyimide and photosensitive benzocyclobutene, and the electronic connection comprises copper.
16. The redistribution routing layer-based space transformation fabric of claim 13, wherein: the first distance is between 2 micrometers and 150 micrometers, and the second distance is between 150 micrometers and 500 micrometers.
17. The redistribution routing layer-based space transformation fabric of claim 13, wherein: the insertion circuit board comprises a first surface, a second surface and a connecting circuit between the first surface and the second surface, the first surface is provided with a third electronic connection with a second distance, the second surface is provided with a fourth electronic connection with a third distance, the third electronic connection and the fourth electronic connection are electrically connected through the connecting circuit, and the third distance is equal to or larger than the second distance.
18. The redistribution routing layer-based space transformation fabric of claim 13, wherein: the third distance is between 300 and 1000 microns.
19. The redistribution routing layer-based space transformation fabric of claim 13, wherein: the probe connection layer comprises a nickel plating layer and a gold plating layer.
20. The redistribution routing layer-based space transformation fabric of claim 13, wherein: one of the interposer circuit boards engages one of the space transformers, or one of the interposer circuit boards simultaneously engages a plurality of the space transformers of the same configuration.
21. The redistribution routing layer-based space transformation fabric of claim 13, wherein: one of the interposer circuit boards simultaneously engages a plurality of space transformer chips of different configurations.
22. The redistribution routing layer-based space transformation fabric of claim 13, wherein: the interposer circuit board contains a multilayer electronic winding including a signal layer and a power/ground layer, and corresponding plated metal drilling structures.
CN202010825690.XA 2020-08-17 2020-08-17 Space conversion substrate based on rewiring circuit layer and preparation method thereof Pending CN112002684A (en)

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US6662442B1 (en) * 1999-07-19 2003-12-16 Nitto Denko Corporation Process for manufacturing printed wiring board using metal plating techniques
JP2007171140A (en) * 2005-12-26 2007-07-05 Apex Inc Probe card, interposer, and interposer manufacturing method
CN101261296A (en) * 2006-11-22 2008-09-10 台湾积体电路制造股份有限公司 Semiconductor element test structure
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Application publication date: 20201127

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