CN111366839B - Probe adapter plate for wafer test and manufacturing method thereof - Google Patents
Probe adapter plate for wafer test and manufacturing method thereof Download PDFInfo
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- CN111366839B CN111366839B CN202010232735.2A CN202010232735A CN111366839B CN 111366839 B CN111366839 B CN 111366839B CN 202010232735 A CN202010232735 A CN 202010232735A CN 111366839 B CN111366839 B CN 111366839B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
- G01R31/2808—Holding, conveying or contacting devices, e.g. test adapters, edge connectors, extender boards
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
Abstract
The invention relates to a probe adapter plate for wafer test, which comprises a substrate layer and a rewiring layer; the substrate layer is provided with a pad array and a transit pad array, and transit pads of the transit pad array are connected with bottom pads of the bottom pad array through via holes in a one-to-one correspondence manner; the top surface of the rewiring layer is provided with a test pad array, and the test pad array is arranged corresponding to the pin array of the chip of the wafer to be tested; each test pad of the test pad array is correspondingly connected with the transfer pad one by one through the lines and the blind holes arranged in the rewiring layer; the pitch of the underlying pad array > the pitch of the test pad array; the body material of the substrate layer is a ceramic material, and the base material of the rewiring layer is a PI resin material; the ceramic substrate has the characteristic of high strength; the PI resin layer has thinner lines and smaller interlayer conducting aperture, can be made into a wafer-level pad array in fewer layers, and reduces the number of layers of the probe adapter plate, thereby reducing the production cost and improving the success rate.
Description
Technical Field
The invention relates to the technical field of semiconductor testing, in particular to a probe adapter plate for wafer testing and a manufacturing method thereof.
Background
In order to improve the yield of chips, the wafer is tested before dicing the die (die) and the defective die is removed. The packaging method aims to avoid packaging unqualified products, improve the qualification rate of packaged finished products and save the packaging cost. To inspect the die on the wafer, a probe card is required. Conventional dimensions for wafers are 12 inches, 8 inches and 4 inches, with wafer dimensions typically dominated by 12 inches using MEMS probe cards. Hundreds of semi-finished dies are densely distributed on the wafer, and an I/O port of each tiny die is connected with a probe card during testing.
It is common practice to use a probe adapter plate as a connecting medium between the probe card and the wafer. The probe adapter plate requires a large number of wafer level pads to be fabricated in the 12 inch range, so the pads are very closely arranged. A common probe adapter plate is provided with a wiring layer manufactured by a multilayer ceramic process; the line processing capability of the printed circuit on the multilayer ceramic is 75 μm level, and the aperture is 50 μm minimum, so the number of layers is large, the process yield is low, and the price and the cost are very expensive.
Disclosure of Invention
The invention aims to solve the technical problem of designing a probe adapter plate for wafer testing and a manufacturing method thereof, which can reduce the number of layers and is easy to manufacture.
A probe adapter plate for wafer test comprises a substrate layer positioned at the bottom and a rewiring layer arranged on the upper part of the substrate layer;
the bottom of the substrate layer is provided with a bottom layer pad array, the upper part of the substrate layer is provided with a transfer pad array, and the transfer pads of the transfer pad array are connected with the bottom layer pads of the bottom layer pad array through via holes arranged on the substrate layer body in a one-to-one correspondence manner;
the top surface of the rewiring layer is provided with a test pad array, and the test pad array is arranged corresponding to the pin array of the chip of the wafer to be tested;
each test pad of the test pad array is correspondingly connected with the transfer pad one by one through the lines and the blind holes arranged in the rewiring layer;
the pitch of the underlying pad array > the pitch of the test pad array;
the substrate layer is made of ceramic material, and the redistribution layer is made of PI (Polyimide) resin material.
Preferably, the test pad is implanted with a probe, or the test pad is provided with a micro convex column.
Preferably, a rigid interposer is planted on the bottom bonding pad; or the like, or, alternatively,
the bottom layer bonding pad is provided with a connecting blind hole or a clamping blind hole.
Preferably, the rewiring layer comprises n rewiring unit layers, wherein n is more than or equal to 1;
each rewiring unit layer comprises a unit PI adhesive layer and a unit wiring layer, the unit wiring layer is positioned on the top surface of the unit PI adhesive layer, and a unit layer bonding pad array is arranged on the unit wiring layer;
when n is equal to 1, the unit layer pad arrays are arranged as test pad arrays, and each test pad is connected with the adapter pad in a one-to-one correspondence mode through a through hole arranged in the unit PI adhesive layer;
and when n is greater than 1, arranging the unit layer pad array of the rewiring unit layer positioned on the top layer as a test pad array, connecting the unit layer pad of the rewiring unit layer on the non-top layer corresponding to one of the adapter pads through a blind hole, and directly connecting each test pad with the corresponding adapter pad through the blind hole or connecting each test pad with the corresponding adapter pad through the unit layer pad and the blind hole of the rewiring unit layer on the non-top layer.
Preferably, n is 1, the test pad array includes more than 2 sub-test pad arrays, and each transfer pad corresponds to more than 2 test pads; and the test pad of each sub-test pad array is respectively connected with the corresponding adapter pad through a blind hole.
Preferably, the thickness of the unit PI glue layer is 10-20 μm, and the thickness of the unit wiring layer copper-clad layer is 1.5-2.5 μm.
Preferably, the aperture of the laser blind hole of the unit PI glue layer is 9-11 μm, and the line width of the unit wiring layer is 2-5 μm.
Preferably, the pitch of the bottom layer pad array is more than or equal to 0.5mm, and the pitch of the test pad array is less than or equal to 120 mu m.
A method for manufacturing a probe adapter plate for wafer testing comprises the following steps:
step S1, manufacturing a ceramic substrate with double-sided pads: respectively manufacturing a bottom layer bonding pad and a through bonding pad on the upper surface and the lower surface of the ceramic plate, punching a hole on the ceramic plate to obtain a through hole, electroplating and filling the through hole, and communicating the through hole with the bottom layer bonding pad and the through bonding pad;
step S2, printing a layer of PI glue on the upper surface of the ceramic substrate;
step S3, laser blind holes are punched on the adapter pad from the top surface of the PI glue;
step S4, sputtering a metal layer on the top surface of the PI glue;
step S5, etching the metal layer into a circuit, correspondingly arranging a test pad according to the chip array position of the wafer to be tested, carrying out metallization processing on the blind hole, and conducting the test pad and the adapter pad;
and step S6, welding a rigid interposer on the bottom layer bonding pad, testing the bonding pad welding probe or manufacturing a micro convex column.
A method for manufacturing a probe adapter plate for wafer testing comprises the following steps:
step A1, respectively manufacturing a bottom layer bonding pad and a transit bonding pad on the upper surface and the lower surface of a ceramic plate, punching a hole on the ceramic plate to obtain a via hole, and then electroplating and filling the via hole, wherein the via hole is communicated with the bottom layer bonding pad and the transit bonding pad;
step A2, manufacturing PI glue of a first rewiring unit layer on the upper surface of the ceramic substrate;
step A3, laser blind holes are punched on the top surface of the PI glue of the first rewiring unit to the transfer bonding pads;
step A4, sputtering a first rewiring unit layer metal layer on the top surface of the PI glue of the first rewiring unit layer;
step A5, etching the first rewiring unit layer metal layer into a circuit of the first rewiring unit wiring layer, processing a first unit layer pad, carrying out metallization treatment on the blind hole, and conducting the first unit layer pad and the transfer pad;
step A6, manufacturing a second rewiring unit layer PI adhesive on the upper surface of the first rewiring unit wiring layer;
step A7, laser blind holes are punched from the top surface of the PI glue of the second rewiring unit to the bonding pads of the first rewiring unit layer;
step A8, sputtering a second rewiring unit layer metal layer on the top surface of the PI glue of the second rewiring unit layer;
step A9, etching the second rewiring unit layer metal layer into a circuit of the second rewiring unit wiring layer, processing a second unit layer pad, carrying out metallization treatment on the blind hole, and conducting the second unit layer pad and the first unit layer pad;
step A10, repeating the steps A6-A9, and manufacturing a rewiring unit layer;
the unit layer pad array positioned at the top layer is a test pad array, and test pads of the test pad array are correspondingly arranged according to the pin positions of the chip array of the wafer to be tested;
and step A11, welding a rigid interposer on a bottom bonding pad, welding a probe on a top testing bonding pad or manufacturing a micro convex column.
The probe adapter plate for the wafer test has the beneficial effects that the probe adapter plate comprises a substrate layer positioned at the bottom and a rewiring layer arranged at the upper part of the substrate layer; the bottom of the substrate layer is provided with a bottom layer pad array, the upper part of the substrate layer is provided with a transfer pad array, and the transfer pads of the transfer pad array are connected with the bottom layer pads of the bottom layer pad array through via holes arranged on the substrate layer body in a one-to-one correspondence manner; the top surface of the rewiring layer is provided with a test pad array, and the test pad array is arranged corresponding to the pin array of the chip of the wafer to be tested; each test pad of the test pad array is correspondingly connected with the transfer pad one by one through the lines and the blind holes arranged in the rewiring layer; the pitch of the underlying pad array > the pitch of the test pad array; the substrate layer is made of ceramic material, and the redistribution layer is made of PI (Polyimide) resin material. The ceramic substrate has the characteristic of high strength, and the PI resin material is a rewiring layer base material; the lines are processed more finely, the interlayer conduction aperture is smaller, a wafer-level bonding pad array can be manufactured in fewer layers, the number of layers of the probe welding plate is reduced, and therefore production cost is reduced, and the yield of the adapter plate is increased.
Drawings
The probe adapter plate for wafer test and the manufacturing method thereof according to the present invention will be further described with reference to fig. 1 to 7.
Fig. 1 is a schematic structural diagram of a probe interposer for wafer testing according to a first embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a second embodiment of a probe interposer for wafer testing according to the present invention.
Fig. 3 is a schematic structural diagram of a third embodiment of a probe interposer for wafer testing according to the present invention.
Fig. 4 is a schematic structural diagram of a probe interposer for wafer testing according to a fourth embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a probe interposer for wafer testing according to a fifth embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a sixth embodiment of a probe interposer for wafer testing according to the present invention.
FIG. 7 is a schematic diagram of a step of fabricating a single-layer rewiring unit of a probe interposer for wafer testing according to the present invention.
In the figure:
1-a substrate layer, 11-a bottom layer pad array, 12-a transfer pad array, 13-a rigid interposer, 2-a rewiring layer, 21-a test pad array, 22-a probe, 23-a unit PI glue layer, 24-a unit wiring layer and 25-a unit layer pad array; 26-blind hole, 27-micro convex column.
The term of terminology:
1. pitch: in the integrated circuit, pitch is the distance between the centers of two "units" on the board, and in the present invention, is specifically the center line span of two pads.
Detailed Description
The following further describes a probe adapter plate for wafer testing and a technical scheme of a manufacturing method thereof by using specific embodiments with reference to fig. 1 to 3.
Probe keysets is used in wafer test
Example one
A probe adapter plate for wafer test comprises a substrate layer 1 positioned at the bottom and a rewiring layer 2 arranged on the upper part of the substrate layer 1;
the bottom of the substrate layer 1 is provided with a bottom layer pad array 11, the upper part of the substrate layer 1 is provided with a transit pad array 12, and the transit pads and the bottom layer pads are connected in a one-to-one correspondence mode through via holes arranged in a body of the substrate layer 1;
the top surface of the rewiring layer 2 is provided with a test pad array 21, and the test pad array 21 is arranged corresponding to the pin array of the chip of the wafer to be tested;
each test pad is connected with the switching pad 12 in a fan-out one-to-one correspondence mode through a line arranged in the rewiring layer 2;
the pitch of the lower pad array 11 is equal to or greater than the pitch of the test pad array 21.
In this embodiment, the substrate layer 1 is made of a ceramic material.
In this embodiment, the probe 22 is implanted on the test pad of the test pad array 21.
In this embodiment, a rigid interposer 13 is implanted on the bottom pad 11 for connection to a probe card.
In the present embodiment, the rewiring layer 2 is a single-layer rewiring unit.
The unit layer pad array 25 is the testing pad array 21, each testing pad of the testing pad array 21 is connected with the transfer pad 12 in a one-to-one correspondence manner through a via hole (blind hole 26) arranged on the unit PI adhesive layer 23, which is a via hole from the viewpoint of the PI adhesive layer 23, and is actually a blind hole 26 from the viewpoint of the overall structure.
In the embodiment, the thickness of the unit PI glue layer 23 is 10-20 μm, the thickness of the unit wiring layer 24 covering copper is 1.5-2.5 μm, the thickness of the glue layer and the thickness of the covering copper can give consideration to the conductivity and the insulating property between circuits required by chip testing, and the overall thickness and the cost of the adapter plate are reduced to the greatest extent.
In this embodiment, the aperture of the laser blind hole of the unit PI glue layer 23 is 9-11 μm, the line width of the unit wiring layer 24 is 2-5 μm, and the size of the blind hole affects the conduction performance of the buried electroplating hole.
In this embodiment, the pitch of the bottom pad array 11 is greater than or equal to 0.5mm, and the pitch of the test pad array 21 is less than or equal to 120 μm.
Example two
In this embodiment, the probe 22 is replaced by the conductive micro-post 27, and the other parts are the same as those in the first embodiment.
EXAMPLE III
In the present embodiment, the rewiring layer 2 is a single-layer rewiring unit.
In this embodiment, the probe 22 is implanted on the test pad of the test pad array 21.
In this embodiment, the thickness of the unit PI glue layer 23 is 15 μm, the thickness of the unit wiring layer 24 covering copper is 2 μm, and the thickness of the glue layer and the thickness of the covering copper can give consideration to the conductivity and the insulation between circuits required by the chip test, and reduce the overall thickness and the cost of the interposer to the greatest extent.
The unit layer pad array 25 is the testing pad array 21, and each testing pad of the testing pad array 21 is correspondingly connected with the transfer pad 12 through a via hole (laser blind hole 26) arranged on the unit PI adhesive layer 23.
Each landing pad 12 corresponds to more than 2 test pads. The test pad array 21 includes more than 2 sub-test pad arrays, and the test pads of each sub-test pad array are respectively connected with the corresponding through pads 12 through the laser blind vias 26. The arrangement of each sub-test pad array corresponds to the pin distribution of one wafer; therefore, the probe adapter plate for the wafer test can be suitable for more than two kinds of wafers, and more than 2 kinds of wafer arrays with different models can be respectively tested on the same test production line.
In this embodiment, the aperture of the laser blind via of the unit PI glue layer 23 is 10 μm, the line width of the unit wiring layer 24 is 3.5 μm, and the size of the blind via may affect the conduction performance of the plated buried via.
In this embodiment, the pitch of the lower pad array 11 is 0.6mm, and the pitch of the test pad array 21 is 90 μm.
Example four
In this embodiment, the probe 22 is replaced by the conductive micro-post 27, and the other parts are the same as those in the third embodiment.
EXAMPLE five
A probe adapter plate for wafer test comprises a substrate layer 1 positioned at the bottom and a rewiring layer 2 arranged on the upper part of the substrate layer 1;
the bottom of the substrate layer 1 is provided with a bottom layer pad array 11, the upper part of the substrate layer 1 is provided with a transit pad array 12, and the transit pads and the bottom layer pads are connected in a one-to-one correspondence mode through via holes arranged in a body of the substrate layer 1;
the top surface of the rewiring layer 2 is provided with a test pad array 21, and the test pad array 21 is arranged corresponding to the pin array of the chip of the wafer to be tested;
each test pad is connected with the switching pad 12 in a fan-out one-to-one correspondence mode through a line arranged in the rewiring layer 2;
the pitch of the lower pad array 11 is equal to or greater than the pitch of the test pad array 21.
In this embodiment, the substrate layer 1 is made of a ceramic material.
In this embodiment, the probe 22 is implanted on the test pad of the test pad array 21.
In this embodiment, each rewiring unit layer includes a unit PI adhesive layer 23 and a unit wiring layer 24, each unit wiring layer 24 is located on the top surface of the unit PI adhesive layer 23 of the corresponding layer, and a unit layer pad array 25 is arranged on the unit wiring layer 24;
when the chip array on the wafer to be tested is dense, the pin pitch of the wafer is too small, and a single-layer rewiring unit structure cannot arrange all circuits on one wiring layer, a multi-layer rewiring unit structure is required, namely n is more than 1; n is 2, 3, 4, 5, … … or other natural number.
At this time, the unit layer pad array 25 of the rewiring unit layer located at the top layer is directly used as the test pad array 21, and one end of the test pad of this layer is connected to the pin of each chip on the wafer to be tested through the probe 22 or the micro post 27.
Meanwhile, part of the test pads are directly connected to the landing pads 12 through blind vias, or connected to the landing pads 12 through stepped blind vias; the other part of the test pad is connected to a second layer rewiring unit layer, a third layer rewiring unit layer or more rewiring unit layers through the rewiring unit and the conduction blind holes and is finally connected with the transit pad 12;
the manufacturing processes of all rewiring unit layers including the top layer are basically the same, the specific circuit layout can be optimally designed according to the layout of chip particles on the wafer, and after all, the wafer chip particle layouts of different chip products are different;
each unit layer pad of the rewiring unit layer on the non-top layer is correspondingly connected with one transfer pad 12 through a conductive blind hole, and each test pad is directly connected with the corresponding transfer pad 12 through the blind hole or is connected with the corresponding transfer pad 12 through the unit PI glue layer 24 of the rewiring unit layer on the non-top layer.
The test pad on the top layer and the corresponding transfer pad 12 are directly connected by the blind hole, and the connection mode is divided into two modes: one is that the blind holes are arranged in a stepped manner, namely, each layer of PI glue layer 24 is provided with one blind hole, and the blind holes are arranged on the blind holes, so that the filling problem of fine deep holes can be avoided, the processing difficulty is low, and the process is complicated; alternatively, a blind via is formed through the PI layers 24 to connect the landing pad 12 to the test pad of the top array 21.
In this embodiment, the substrate layer 1 made of a ceramic material is provided with blind holes which are tightly filled, so that the large current passing through and the heat conductivity of the pads of the adapter pad 12 and the pad array 11 are facilitated, and meanwhile, the PI glue layer is prevented from penetrating through the substrate layer 1.
In this embodiment, the peripheral sides of the adapter pad 12 are provided with chamfers, so that the smooth transition of the top surfaces of the substrate layer 1 and the adapter pad 12 is realized, and the uniform flow of the PI adhesive and the convenient leveling are facilitated.
In this embodiment, the aperture of the laser blind via of the unit PI glue layer 23 is 9 μm, the line width of the unit wiring layer 24 is 4 μm, and the size of the blind via may affect the conduction performance of the buried via for electroplating.
In this embodiment, the pitch of the lower pad array 11 is 0.6mm, and the pitch of the test pad array 21 is 90 μm.
EXAMPLE six
In this embodiment, the probe 22 is replaced by the conductive micro-post 27, and the rest is the same as that of the fifth embodiment.
The invention also provides a manufacturing method of the probe adapter plate for the wafer test.
Example one
A method for manufacturing a probe adapter plate for wafer testing, wherein a rewiring unit layer is a single layer, comprises the following steps:
step S1, manufacturing a ceramic substrate with double-sided pads: manufacturing a ceramic plate by a sintering process, punching a hole on the ceramic plate, electroplating and filling the via hole, and processing bonding pads on the upper surface and the lower surface of the ceramic plate;
step S2, printing or spin-coating a layer of PI glue on the upper surface of the ceramic substrate;
step S3, laser blind holes are punched on the adapter pad from the top surface of the PI glue;
step S4, sputtering a metal layer on the top surface of the PI glue;
step S5, etching the metal layer into a circuit, correspondingly arranging a test pad according to the chip array position of the wafer to be tested, and communicating the test pad with the adapter pad through a blind hole filling process;
step S6, welding rigid interposer on bottom pad, welding probe on test pad or setting micro convex column.
Example two
A method for manufacturing a probe adapter plate for wafer test, wherein the rewiring unit layers are of multiple layers, comprises the following steps:
step A1, manufacturing a ceramic substrate with double-sided pads: manufacturing a ceramic plate by a sintering process, punching a hole on the ceramic plate, electroplating and filling the via hole, and processing bonding pads on the upper surface and the lower surface of the ceramic plate;
step A2, printing a first rewiring unit layer PI adhesive on the upper surface of the ceramic substrate;
step A3, laser blind holes are punched on the top surface of the PI glue of the first rewiring unit to the transfer bonding pads;
step A4, sputtering a first rewiring unit layer metal layer on the top surface of the PI glue of the first rewiring unit layer;
step A5, etching the first rewiring unit layer metal layer into a circuit of the first rewiring unit wiring layer, processing a first unit layer pad, filling a blind hole, and conducting the pad and the transfer pad of the first rewiring unit layer;
step A6, printing a second rewiring unit layer PI adhesive on the upper surface of the first rewiring unit wiring layer line;
step A7, laser blind holes are punched from the top surface of the PI glue of the second rewiring unit to the bonding pads of the first rewiring unit layer;
step A8, sputtering a second rewiring unit layer metal layer on the top surface of the PI glue of the second rewiring unit layer;
step A9, etching the second rewiring unit layer metal layer into the circuit of the second rewiring unit wiring layer, processing the second unit layer pad, filling the blind hole, and conducting the pad of the first rewiring unit layer and the pad of the second rewiring unit layer;
and step A10, repeating the steps A6-A9, and manufacturing an nth rewiring unit layer, wherein unit layer bonding pads of the nth rewiring unit layer are correspondingly arranged into test bonding pads according to the chip array position of the wafer to be tested, and the nth rewiring unit layer is a top rewiring layer.
And step A11, welding a rigid interposer on the bottom layer bonding pad, and arranging a micro convex column or a welding probe on the top layer rewiring layer including a test bonding pad.
The present invention is not limited to the above embodiments, and the technical solutions of the above embodiments of the present invention may be combined with each other in a crossing manner to form a new technical solution, and all technical solutions formed by using equivalent substitutions fall within the scope of the present invention.
Claims (9)
1. A probe adapter plate for wafer testing is characterized by comprising a substrate layer positioned at the bottom and a rewiring layer arranged on the upper part of the substrate layer;
the bottom of the substrate layer is provided with a bottom layer pad array, the upper part of the substrate layer is provided with a transfer pad array, and the transfer pads of the transfer pad array are connected with the bottom layer pads of the bottom layer pad array through via holes arranged on the substrate layer body in a one-to-one correspondence manner;
the top surface of the rewiring layer is provided with a test pad array, and the test pad array is arranged corresponding to the pin array of the chip of the wafer to be tested;
each test pad of the test pad array is correspondingly connected with the transfer pad one by one through the circuit and the blind hole arranged in the rewiring layer;
the pitch of the underlying pad array > the pitch of the test pad array;
the body material of the substrate layer is a ceramic material, and the base material of the rewiring layer is a PI resin material;
each transfer bonding pad corresponds to more than 2 test bonding pads; the test pad array comprises more than 2 sub-test pad arrays, and the test pad of each sub-test pad array is respectively connected with the corresponding adapter pad through a laser blind hole; the arrangement of each sub-test pad array corresponds to the pin distribution of one wafer.
2. The probe adapter plate for wafer test as claimed in claim 1, wherein the test pad has a probe implanted thereon, or the test pad has a micro-bump disposed thereon.
3. The probe adapter plate for wafer test as claimed in claim 1, wherein a rigid interposer is implanted on the bottom pad; or the like, or, alternatively,
the bottom layer bonding pad is provided with a connecting blind hole or a clamping blind hole.
4. The probe adapter plate for wafer test as claimed in claim 1, wherein the redistribution layer comprises n redistribution unit layers, wherein n ≧ 1;
each rewiring unit layer comprises a unit PI adhesive layer and a unit wiring layer, the unit wiring layer is positioned on the top surface of the unit PI adhesive layer, and a unit layer bonding pad array is arranged on the unit wiring layer;
when n is equal to 1, the unit layer pad arrays are arranged as test pad arrays, and each test pad is connected with the adapter pad in a one-to-one correspondence mode through a through hole arranged in the unit PI adhesive layer;
and when n is greater than 1, arranging the unit layer pad array of the rewiring unit layer positioned on the top layer as a test pad array, connecting the unit layer pad of the rewiring unit layer on the non-top layer corresponding to one of the adapter pads through a blind hole, and directly connecting each test pad with the corresponding adapter pad through the blind hole or connecting each test pad with the corresponding adapter pad through the unit layer pad and the blind hole of the rewiring unit layer on the non-top layer.
5. The method for manufacturing the probe adapter plate for wafer test according to claim 1, wherein the thickness of the unit PI adhesive layer is 10-20 μm, and the thickness of the unit wiring layer copper clad is 1.5-2.5 μm.
6. The method of claim 1, wherein the laser blind via hole of the PI layer has a diameter of 9-11 μm, and the wiring width of the PI layer is 2-5 μm.
7. The method of claim 1, wherein the bottom pad array pitch is not less than 0.5mm, and the test pad array pitch is not more than 120 μm.
8. A method for manufacturing a probe adapter plate for wafer testing is characterized by comprising the following steps:
step S1, manufacturing a ceramic substrate with double-sided pads: respectively manufacturing a bottom layer bonding pad and a through bonding pad on the upper surface and the lower surface of a ceramic plate, punching a hole on the ceramic plate to obtain a through hole, electroplating and filling the through hole, and communicating the through hole with the bottom layer bonding pad and the through bonding pad;
step S2, printing a layer of PI glue on the upper surface of the ceramic substrate;
step S3, laser blind holes are punched on the adapter pad from the top surface of the PI glue;
step S4, sputtering a metal layer on the top surface of the PI glue;
step S5, etching the metal layer into a circuit, correspondingly arranging a test pad according to the chip array position of the wafer to be tested, carrying out metallization processing on the blind hole, and conducting the test pad and the adapter pad;
step S6, welding a rigid interposer on a bottom bonding pad, testing the bonding pad and welding a probe or manufacturing a micro convex column;
each transfer bonding pad corresponds to more than 2 test bonding pads; the test pad array comprises more than 2 sub-test pad arrays, and the test pad of each sub-test pad array is respectively connected with the corresponding adapter pad through a laser blind hole; the arrangement of each sub-test pad array corresponds to the pin distribution of one wafer.
9. A method for manufacturing a probe adapter plate for wafer testing is characterized by comprising the following steps:
step A1, respectively manufacturing a bottom layer bonding pad and a transit bonding pad on the upper surface and the lower surface of a ceramic plate, punching a hole on the ceramic plate to obtain a via hole, and then electroplating and filling the via hole, wherein the via hole is communicated with the bottom layer bonding pad and the transit bonding pad;
step A2, manufacturing PI glue of a first rewiring unit layer on the upper surface of the ceramic substrate;
step A3, laser blind holes are punched on the top surface of the PI glue of the first rewiring unit to the transfer bonding pads;
step A4, sputtering a first rewiring unit layer metal layer on the top surface of the PI glue of the first rewiring unit layer;
step A5, etching the first rewiring unit layer metal layer into a circuit of the first rewiring unit wiring layer, processing a first unit layer pad, carrying out metallization treatment on the blind hole, and conducting the first unit layer pad and the transfer pad;
step A6, manufacturing a second rewiring unit layer PI adhesive on the upper surface of the first rewiring unit wiring layer;
step A7, laser blind holes are punched from the top surface of the PI glue of the second rewiring unit to the bonding pads of the first rewiring unit layer;
step A8, sputtering a second rewiring unit layer metal layer on the top surface of the PI glue of the second rewiring unit layer;
step A9, etching the second rewiring unit layer metal layer into a circuit of the second rewiring unit wiring layer, processing a second unit layer pad, carrying out metallization treatment on the blind hole, and conducting the second unit layer pad and the first unit layer pad;
step A10, repeating the steps A6-A9, and manufacturing a rewiring unit layer;
the unit layer pad array positioned at the top layer is a test pad array, and test pads of the test pad array are correspondingly arranged according to the pin positions of the chip array of the wafer to be tested;
step A11, welding a rigid interposer on a bottom bonding pad, welding a probe on a top testing bonding pad or manufacturing a micro convex column;
each transfer bonding pad corresponds to more than 2 test bonding pads; the test pad array comprises more than 2 sub-test pad arrays, and the test pad of each sub-test pad array is respectively connected with the corresponding adapter pad through a laser blind hole; the arrangement of each sub-test pad array corresponds to the pin distribution of one wafer.
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