CN101472403B - Printed circuit board and method for producing the same - Google Patents
Printed circuit board and method for producing the same Download PDFInfo
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- CN101472403B CN101472403B CN 200710160668 CN200710160668A CN101472403B CN 101472403 B CN101472403 B CN 101472403B CN 200710160668 CN200710160668 CN 200710160668 CN 200710160668 A CN200710160668 A CN 200710160668A CN 101472403 B CN101472403 B CN 101472403B
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Abstract
A printed circuit board comprises wiring layers with the number from one to N, and further comprises at least a first kind of connection bonding pad which is positioned on the first wiring layer and used for being electrically connected with a semiconductor packaging part, at least a second kind of connection bonding pad which is positioned on the N-1 wiring layer and electrically connected with a signal pin of the semiconductor packaging part, at least a third kind of connection bonding pad which is positioned on the N wiring layer and used for being electrically connected a grounding pin and a power supply pin of the semiconductor packaging part, at least a blind hole penetrating from the first wiring layer to the N-1 wiring layer and corresponding to the position of the second kind of connection bonding pad, and at least a through hole penetrating from the first wiring layer to the N wiring layer and corresponding to the position of the third kind of connection bonding pad. The printed circuit board enables a coupling capacitor to be arranged in the center of the third kind of connection bonding pad, thereby reducing the distance between the grounding pin and the power supply pin of the semiconductor packaging part, and the coupling capacitor, and improving the decoupling effect of a decoupling capacitor. The invention further provides a manufacturing method of the printed circuit board.
Description
Technical field
The present invention relates to EMC Design and high speed signal integrity analysis technical field, particularly a kind of printed substrate and preparation method thereof.
Background technology
Along with development of electronic technology, the processing speed of semiconductor chip is more and more faster, and rising and fall time are shorter and shorter, and supply voltage falls and ground plays problem so be easy to generate when chip logic switches, switch the time, this problem is just even more serious simultaneously for particularly a large amount of gate circuits.For fear of or alleviate described problem, normally the electricity of semiconductor chip, decoupling capacitor is set between the pin, in order to obtain best decoupling effect, require semiconductor chip electricity, the line distance between pin and decoupling capacitor short more good more.
For the trickle degree of present height, the semiconductor packages of high pin number, ball grid array (ball grid array, BGA) be a kind of advanced person's packaged type, described packaged type is produced spherical salient point in order to replace pin at the back side of printed substrate by array way, the structure of two kinds of circuit boards that typically contain bga structure as shown in Figures 1 and 2, in the accompanying drawing 1, include a plurality of electric contacts 10 on the package surface 11 of printed substrate, described electric contact 10 circularizes arrangement at the periphery of package surface 11, described electric contact 10 comprises all pins of semiconductor chip, comprises grounding pin, power pins and other signal pins.In the accompanying drawing 2, include a plurality of electric contacts 20 on the package surface 22 of printed substrate, described electric contact 20 all circularizes arrangement at the periphery and the center of package surface 22, described electric contact 20 comprises all pins of semiconductor chip, comprises grounding pin, power pins and other signal pins.For the printed substrate design that contains described bga structure, because electric contact 20 is closely arranged, gap ratio is less, so decoupling capacitor can only be arranged on described bga structure around, make conduct electricity in the bga structure, the electric contact of pin and the line between decoupling capacitor apart from increasing, make the decoupling effect of decoupling capacitor greatly reduce.
The internal structure of described printed substrate is with reference to the accompanying drawings shown in 3, in the accompanying drawing 111,112,113......11 (N-1), 11N represents first wiring layer of described printed substrate, second wiring layer ... N wiring layer, N is a positive integer, through hole 303 runs through the 1st to the N wiring layer, be coated with on the hole wall of through hole 303 layer of metal for example copper be used as connecting the pad (not shown) of each layer, be used for the printed wire flaggy with the layer between signal be connected, 202 expression connection pads, be positioned at first wiring layer and the N wiring layer of printed substrate, be used for packaged semiconductor and other device, each conductive layer of described printed substrate all also has via pad, is used for the holding wire connection of printed substrate with one deck inside.The manufacture method of described printed substrate is that elder generation forms through hole 101 layer by layer at the 1st wiring layer to the N distribution of printed substrate, described through hole is corresponding one by one with the connection pads of first wiring layer and N wiring layer, and described connection pads is as grounding pin, power pins and other the signal pins of printed substrate semiconductor-on-insulator device.The structure of the BGA packaging part of the printed substrate that described manufacture method forms is shown in accompanying drawing 1 and accompanying drawing 2, cause decoupling capacitor can only be arranged on described semiconductor die package surface around, the line between the power pins of semiconductor chip, grounding pin and decoupling capacitor is apart from increasing.
Application number is that 00819211.1 Chinese patent application file has provided a kind of printed circuit-board assembly 100, with reference to the accompanying drawings shown in 4, comprise: printed circuit board (PCB) 101, wherein this printed substrate 101 comprises at least one contact pad, this at least one contact pad forms ball grid array (BGA) footprint 102, and BGA packaging part 110, described BGA packaging part has at least one contact, be electrically connected to described contact pad, and capacitor package 103 is inserted between this printed substrate 101 and this BGA packaging part 110, and 107 is the semiconductor chip that connects on the printed circuit board (PCB) 101.In the described patent, because described capacitor package 103 is plugged between printed substrate 101 and this BGA packaging part 110, therefore, thickness for capacitor package has bigger restriction, only be suitable for thin capacitor package, and, packaging technology is also had higher requirement.
Summary of the invention
In view of this, the technical problem that the present invention solves provides a kind of printed substrate and preparation method thereof, can improve the decoupling effect of decoupling capacitor.
A kind of printed substrate has N layer wiring layer, is respectively first wiring layer, second wiring layer, and the rest may be inferred, and N-1 wiring layer, and N wiring layer also comprise:
Be positioned at least one first kind connection pads on first wiring layer of described printed substrate, be used to be electrically connected semiconductor package part;
Be arranged at least one the second class connection pads on any one wiring layer of second wiring layer to the N-1 wiring layer of described printed substrate, be used for being electrically connected with the signal pins of semiconductor package part;
Be positioned at least one the 3rd class connection pads on the N wiring layer of described printed substrate, be used for being electrically connected with the ground connection or the power pins of semiconductor package part;
At least one blind hole that runs through first wiring layer to the second wiring layer, first wiring layer to the, three wiring layers or first wiring layer to the N-1 wiring layer of described printed substrate, described blind hole position is corresponding one by one with the position of the second class connection pads, has electric conducting material in the blind hole;
Run through at least one through hole of first wiring layer to the N wiring layer of described printed substrate, the position of described through hole is corresponding one by one with the position of the 3rd class connection pads, has electric conducting material in the through hole, and wherein N is a positive integer.
Preferably, the described second class connection pads is positioned on the N-1 wiring layer of printed substrate, and described blind hole runs through first wiring layer to the N-1 wiring layer.
Described the 3rd class connection pads is electrically connected by the electric conducting material in the through hole with described first kind connection pads, and the described second class connection pads is electrically connected by the electric conducting material in the blind hole with described first kind connection pads.
Wherein, the first kind connection pads on the described printed wire base board forms the ball grid array footprint.
Wherein, described semiconductor package part is the ball grid array packaging part.
First wiring layer to the N wiring layer material of described printed substrate is a metallic copper.
Described electric conducting material is a copper, is formed on described blind hole or through-hole wall by electroplating technology.
A kind of manufacture method of printed substrate, comprise: formation has first wiring layer, the printed substrate of second wiring layer, N-1 wiring layer, wherein, has first kind connection pads on described first wiring layer, be used to connect semiconductor package part, have the second class connection pads on the described N-1 wiring layer, be used for being electrically connected with the signal pins of semiconductor package part;
Form at least one blind hole run through first wiring layer, second wiring layer to the N-1 wiring layer on described printed substrate, the position of the position of described blind hole and the second class connection pads the is corresponding one by one;
In blind hole, form electric conducting material;
Formation has the printed substrate of N wiring layer, has the 3rd class connection pads on the described N wiring layer, is used for being electrically connected with the ground connection or the power pins of semiconductor package part;
Form at least one through hole that runs through first wiring layer to the N wiring layer on described printed substrate, the position of described through hole is corresponding one by one with the position of the 3rd class connection pads, and wherein N is a positive integer;
In through hole, form electric conducting material.
Described the 3rd class connection pads is electrically connected by the electric conducting material in the through hole with described connection pads, and the described second class connection pads is electrically connected by the electric conducting material in the blind hole with described connection pads.
Wherein, the connection pads on the described printed wire base board forms the ball grid array footprint.
Wherein, described semiconductor package part is the ball grid array packaging part.
First wiring layer to the N wiring layer material of described printed substrate is a metallic copper.
Described electric conducting material is a copper, is formed on described blind hole or through-hole wall by electroplating technology.
Compared with prior art, such scheme has the following advantages:
The described printed substrate of present embodiment, on first wiring layer, has first kind connection pads, described first kind connection pads forms spherical grid array footprint, be used for linking to each other with the pin of spherical grid array packaging member, also has second wiring layer that is positioned at described printed substrate, the 3rd wiring layer ... the perhaps second class connection pads of at least one on the N-1 wiring layer, be used for being electrically connected with the signal pins of semiconductor package part, also has at least one the 3rd class connection pads on the N wiring layer that is positioned at described printed substrate, be used for being electrically connected with the ground connection or the power pins of semiconductor package part, the printed substrate of described structure, the second class connection pads that will be electrically connected with the signal pins of semiconductor package part is arranged on second wiring layer of printed substrate, the 3rd wiring layer ... perhaps on the N-1 wiring layer, on the N wiring layer of printed substrate, only be useful on the 3rd class connection pads that is electrically connected with the ground connection and the power pins of semiconductor package part, this just can make coupling capacitance be arranged on ground connection with semiconductor package part, in the middle of the 3rd class connection pads that power pins is electrically connected, farthest reduce the ground connection of semiconductor package part, distance between power pins and the coupling capacitance, the decoupling effect of raising decoupling capacitor.
Preferably, the described second class connection pads is positioned at the N-1 wiring layer of described printed substrate, adopt described structure, can on the N wiring layer that guarantees printed substrate, only be useful on the 3rd class connection pads that is electrically connected with the ground connection and the power pins of semiconductor package part, under the situation of the coupling effect of raising coupling capacitance, simplify the manufacture craft of described printed substrate, improve the accuracy of technology.
Description of drawings
Fig. 1 is the structural representation of a kind of BGA packaging part of prior art;
Fig. 2 is the structural representation of the another kind of BGA packaging part of prior art;
Fig. 3 is the cross section structure schematic diagram of prior art printed substrate;
Fig. 4 is a kind of printed substrate structure schematic diagram that reduces the decoupling path of prior art;
Fig. 5 is the cross section structure schematic diagram of printed substrate of the present invention;
Fig. 6 is the surface texture schematic diagram of the N wiring layer of printed substrate of the present invention;
Fig. 7 is the process chart of the embodiment of the invention 2 printed wire board manufacturing methods.
Embodiment
The object of the present invention is to provide a kind of printed substrate and preparation method thereof, with reduce bga structure on the prior art printed substrate cause decoupling capacitor can only be arranged on described bga structure around, make conduct electricity in the bga structure, the electric contact of pin and the line between decoupling capacitor apart from increasing, make the defective that the decoupling effect of decoupling capacitor greatly reduces.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Present embodiment provides a kind of printed substrate, has N layer wiring layer, is respectively first wiring layer, second wiring layer, and the like, N-1 wiring layer, and N wiring layer also comprise:
Be positioned at least one first kind connection pads on first wiring layer of described printed substrate, be used to be electrically connected semiconductor package part;
Be arranged at least one the second class connection pads on any one wiring layer of second wiring layer to the N-1 wiring layer of described printed substrate, be used for being electrically connected with the signal pins of semiconductor package part;
Be positioned at least one the 3rd class connection pads on the N wiring layer of described printed substrate, be used for being electrically connected with the ground connection or the power pins of semiconductor package part;
At least one blind hole that runs through first wiring layer to the second wiring layer, first wiring layer to the, three wiring layers or first wiring layer to the N-1 wiring layer of described printed substrate, described blind hole position is corresponding one by one with the position of the second class connection pads, has electric conducting material in the blind hole;
Run through at least one through hole of first wiring layer to the N wiring layer of described printed substrate, the position of described through hole is corresponding one by one with the position of the 3rd class connection pads, has electric conducting material in the through hole, and wherein N is a positive integer.
Preferably, the described second class connection pads is positioned on the N-1 wiring layer of printed substrate, and described blind hole runs through first wiring layer to the N-1 wiring layer.
Described printed substrate also has first insulating medium layer, second insulating medium layer, ... and the N-1 insulating medium layer, wherein, first insulating medium layer is between first wiring layer and second wiring layer, second insulating medium layer between second wiring layer and the 3rd wiring layer ... the N-1 insulating medium layer is between N-1 wiring layer and N wiring layer.
Described the 3rd class connection pads is electrically connected by the electric conducting material in the through hole with described first kind connection pads, and the described second class connection pads is electrically connected by the electric conducting material in the blind hole with described first kind connection pads.Wherein, the first kind connection pads on the described printed wire base board forms the ball grid array footprint, and described semiconductor package part is the ball grid array packaging part.
With reference to the accompanying drawings shown in 5, the cross section structure schematic diagram of the printed substrate that provides for present embodiment, in the accompanying drawing 5, sequence number 1 correspondence be described printed substrate first wiring layer of present embodiment, sequence number 2 is described printed substrate second wiring layer of present embodiment, sequence number 3 is described printed substrate the 3rd wiring layer of present embodiment, and the like, sequence number N-1 correspondence be the described printed substrate of present embodiment N-1 wiring layer, sequence number N is the described printed substrate of a present embodiment N wiring layer, wherein, N is a positive integer, and preferably, N is the positive integer greater than 1, for example, N is 5 or 10.
In like manner, in the accompanying drawing 5, what sequence number 1 ' was corresponding is described printed substrate first insulating medium layer of present embodiment, between first wiring layer and second wiring layer, sequence number 2 ' is the described printed substrate of a present embodiment insulating medium layer, between second wiring layer and the 3rd wiring layer, sequence number 3 ' is described printed substrate the 3rd insulating medium layer of present embodiment, between the 3rd wiring layer and the 4th wiring layer, and the like, sequence number (N-2) ' corresponding be the described printed substrate of present embodiment (N-2) insulating medium layer, between N-2 wiring layer and N-1 wiring layer, sequence number (N-1) ' be the described printed substrate of present embodiment (N-1) insulating medium layer, between N-1 wiring layer and N wiring layer, wherein, N is a positive integer, and preferably, N is the positive integer greater than 1, for example, N is 5 or 10.
Described first wiring layer, second wiring layer, ... and the N wiring layer is used to realize the electrical connection of printed wire flaggy internal layer circuit, usually adopt for example copper of metal material, described first wiring layer, second wiring layer ... and all be formed with at least one connection pads on the N wiring layer, decide according to the design needs of described printed circuit board (PCB) the quantity of described connection pads and position.Described connection pads comprises the described first kind connection pads of present embodiment, the second class connection pads, and the connection pads of the 3rd class connection pads and other purposes normally is being used to form the technology formation of passing through chemical etching on the Copper Foil of wiring layer.
Described first insulating medium layer, second insulating medium layer, ... and the N-1 insulating medium layer is used for the electrical isolation between printed wire flaggy and the layer, described dielectric material is a photosensitive resin, for example positive acrylates, epoxy resin, polyimides etc., can also be thermosetting resin, for example polyimides or epoxy resin etc.
The described printed substrate of present embodiment contains through hole 210, described through hole 210 runs through the 1st to the N wiring layer, the position of described through hole 210 is corresponding with first the position of part connection pads to the N wiring layer, in the present embodiment, the above the position of the 3rd class connection pads 240 of the position of described through hole 210 and N wiring layer is corresponding one by one, described the 3rd class connection pads 240 is positioned on the N wiring layer, is used for being electrically connected with the ground connection or the power pins of semiconductor package part.
On first wiring layer with described through hole 210 positions one to one connection pads be first kind connection pads 230, described first kind connection pads 230 is used to connect semiconductor package part.
The described through hole 210 and second wiring layer, the 3rd wiring layer ... the position of the part connection pads to the N-2 wiring layer also is one to one, concrete according to second wiring layer, the 3rd wiring layer ... as to need and decide to the line design of N-2 wiring layer.
The formation technology of described through hole 210 can be any technology well known to those skilled in the art, for example adopts the mode of laser or machine drilling to form.Have electric conducting material in the described through hole 210, with realize the printed wire flaggy with layer between be electrically connected, described electric conducting material is a various material well known to those skilled in the art, is metallic copper preferably, can adopt electroplating technology to be formed on through hole 210 inwalls.
The described printed substrate of present embodiment also contains blind hole 220, the position of described blind hole 220 is corresponding with first the position of part connection pads to the N-1 wiring layer, in the present embodiment, the position of described blind hole 220 is corresponding one by one with the position of the described second class connection pads 250, the described second class connection pads 250 is used to connect other all pins except ground connection, power pins of semiconductor package part, in the present embodiment, semiconductor package part other all pins except ground connection, power pins are referred to as signal pins.The position of the described second class connection pads 250 can be at second wiring layer, the 3rd wiring layer ... perhaps on the N-1 wiring layer, can make the 3rd class connection pads that is connected with the signal pins of semiconductor package part not appear at N wiring layer surface, but, if second connection pads 250 is arranged on second wiring layer, the 3rd wiring layer ... the perhaps any one deck or the several layers of N-1 wiring layer, the technology relative complex that then can cause described printed substrate, cost increases, therefore, preferably, the described second class connection pads 250 is arranged on the N-1 wiring layer, can simplify the manufacture craft of described printed substrate, reduces cost of manufacture, and, the accuracy and the controllability of raising technology.
On first wiring layer with described blind hole 220 positions one to one connection pads be first kind connection pads 230, described first kind connection pads 230 is used to connect semiconductor package part.In the present embodiment, on first wiring layer with through hole 210 positions one to one on first kind connection pads 230 and first wiring layer with blind hole 220 positions first kind connection pads 230 common all first kind connection pads that are used to be connected semiconductor package part on first wiring layers of forming one to one.
In the present embodiment, all first kind connection pads 230 form spherical grid array footprint, preferably, are the spherical grid array footprint of full array, spherical grid array footprint figure as shown in Figure 1.The described semiconductor package part of present embodiment is spherical grid array packaging member, preferably, is the spherical grid array packaging member of full array.
When the position of the second class connection pads 250 is positioned on the N-1 wiring layer, the described blind hole 220 and second wiring layer, the 3rd wiring layer ... the position of the part connection pads to the N-2 wiring layer also is one to one, concrete according to second wiring layer, the 3rd wiring layer ... as to need and decide to the line design of N-2 wiring layer.
The formation technology of described blind hole 220 can be any technology well known to those skilled in the art, for example adopts the mode of laser or machine drilling to form.Have electric conducting material in the described blind hole 220, with realize the printed wire flaggy with layer between be electrically connected, described electric conducting material is a various material well known to those skilled in the art, is metallic copper preferably, can adopt electroplating technology to be formed on blind hole 220 inwalls.
In the present embodiment, the surface texture schematic diagram of first wiring layer of described printed substrate is with reference to the accompanying drawings shown in 6, because the second class connection pads all is arranged on the N-1 wiring layer of printed substrate, therefore, only be useful on the ground connection of connection semiconductor package part and the 3rd class connection pads 240 of power pins on the N wiring layer, the connection pads of the spherical grid array footprint that on the N wiring layer, forms compared to existing technology, the 3rd class connection pads 240 on the present embodiment N wiring layer surface 300 disperses to arrange, and the spacing between the 3rd class connection pads 240 can make decoupling capacitor be arranged between two the 3rd class connection pads easily.
For example shown in the accompanying drawing 6, suppose that the 3rd class connection pads 240a is used for linking to each other with the grounding pin of semiconductor package part, the 3rd class connection pads 240b is used for linking to each other with the power pins of semiconductor package part, when then between the 3rd class connection pads 240a and the 3rd class connection pads 240b, decoupling capacitor 260 being set, can on the N layer printed substrate of printed substrate, pin 270a and pin 270b be set, the 3rd class connection pads 240a and the 3rd class connection pads 240b are electrically connected with pin 270a and pin 270b respectively, two pins of decoupling capacitor 260 only need to be electrically connected with pin 270a and pin 270b, can be easily with semiconductor packages between ground connection and power pins be electrically connected.
The printed substrate structure of prior art, will with the ground connection of semiconductor package part, the pad that power pins and quotation marks pin are electrically connected all concentrates on the N wiring layer, because ground connection described and semiconductor package part, the connection pads that power pins and signal pins are electrically connected forms spherical grid array footprint, therefore, on described printed substrate after the encapsulated semiconductor packaging part, be used for ground connection with semiconductor package part, the coupling capacitance that power pins is electrically connected can only be arranged on semiconductor package part around, strengthened the ground connection of semiconductor package part, distance between power pins and the coupling capacitance has reduced coupling effect.
The described printed substrate of present embodiment forms first kind connection pads on first wiring layer, described first kind connection pads forms spherical grid array footprint, is used for linking to each other with the pin of spherical grid array packaging member.At second wiring layer ... perhaps form the second class connection pads on the N-1 wiring layer, preferably on the N-1 wiring layer, form the second class connection pads, the described second class connection pads is used for being electrically connected with the signal pins that is connected semiconductor package part, on the N wiring layer, form the 3rd class connection pads, described the 3rd class connection pads is used for being electrically connected with the ground connection and the power pins of semiconductor package part, adopt the printed substrate of the described structure of present embodiment, on the N wiring layer of printed substrate, only be useful on the 3rd class connection pads that is electrically connected with the ground connection and the power pins of semiconductor package part, this just can make coupling capacitance be arranged on ground connection with semiconductor package part, in the middle of the 3rd class connection pads that power pins is electrically connected, farthest reduce the ground connection of semiconductor package part, distance between power pins and the coupling capacitance, the decoupling effect of raising decoupling capacitor.
Present embodiment provides a kind of manufacture method of printed substrate, shown in 7, comprising with reference to the accompanying drawings:
Step S100, formation has first wiring layer, the printed substrate of second wiring layer, N-1 wiring layer, wherein, has first kind connection pads on described first wiring layer, be used to connect semiconductor package part, have the second class connection pads on the described N-1 wiring layer, be used for being electrically connected with the signal pins of semiconductor package part;
Step S110 forms at least one blind hole run through first wiring layer, second wiring layer to the N-1 wiring layer on described printed substrate, the position of the position of described blind hole and the second class connection pads the is corresponding one by one;
Step S120 forms electric conducting material in blind hole;
Step S130 forms the printed substrate with N wiring layer, has the 3rd class connection pads on the described N wiring layer, is used for being electrically connected with the ground connection or the power pins of semiconductor package part;
Step S140 forms at least one through hole that runs through first wiring layer to the N wiring layer on described printed substrate, the position of described through hole is corresponding one by one with the position of the 3rd class connection pads, and wherein N is a positive integer;
Step S150 forms electric conducting material in through hole.
Described printed substrate also has first insulating medium layer, second insulating medium layer, ... and the N-1 insulating medium layer, wherein, first insulating medium layer is between first wiring layer and second wiring layer, second insulating medium layer between second wiring layer and the 3rd wiring layer ... the N-1 insulating medium layer is between N-1 wiring layer and N wiring layer.
Described have first wiring layer, first insulating medium layer, second wiring layer, second insulating medium layer ..., the N-2 insulating medium layer, the manufacture method of the printed substrate of N-1 wiring layer can be any prior art well known to those skilled in the art, present embodiment provides a kind of possible execution mode: adopt laminated type, first insulating medium layer is arranged between first wiring layer and second wiring layer, increase by second insulating medium layer then successively, the 3rd wiring layer ... N-1 wiring layer is pressed into described printed circuit board (PCB) with described N laminar substrate heating then.The ground floor wiring layer of described printed substrate, second layer wiring layer ... N layer wiring layer material is a metallic copper.
Described first wiring layer, second wiring layer ... and the N-1 wiring layer on all be formed with at least one connection pads, decide according to the design needs of described printed circuit board (PCB) the quantity of described connection pads and position.Wherein, the connection pads on first wiring layer is a first kind connection pads, is used to connect semiconductor package part, and described first kind connection pads forms the ball grid array footprint, and described semiconductor package part also is the ball grid array packaging part.Connection pads on the described N-1 wiring layer is the second class connection pads, is used for being electrically connected with the signal pins of semiconductor package part.Described connection pads normally is being used to form the technology formation of passing through chemical etching on the Copper Foil of wiring layer.
Described second wiring layer ... be used to realize the electrical connection of printed wire flaggy internal layer circuit to the N-1 wiring layer, adopt for example copper of metal material usually.
The technology that forms at least one blind hole that runs through first wiring layer to the N-2 insulating medium layer, N-1 wiring layer on described printed substrate is any technology well known to those skilled in the art, for example the laser drill technology.
The technology that forms electric conducting material in blind hole is any technology well known to those skilled in the art, preferably, adopts electroplating technology, at blind hole inwall electrodeposit metals copper.
On the N-1 wiring layer, add N-1 insulating medium layer, N wiring layer successively, formation has first wiring layer, first insulating medium layer, second wiring layer, second insulating medium layer ..., the N-1 insulating medium layer, the technology of the printed substrate of N wiring layer also can be any prior art well known to those skilled in the art, is preferably the employing laminated type.
The technology that forms at least one through hole that runs through first wiring layer to the N-1 insulating medium layer, N wiring layer on described printed substrate is identical with the technology that forms blind hole.In the technology of through-hole wall deposits conductive material also with identical in the technology of blind hole inwall deposits conductive material.
In the present embodiment, described the 3rd class connection pads is electrically connected by the electric conducting material in the blind hole with described connection pads, and the described second class connection pads is electrically connected by the electric conducting material in the through hole with described connection pads.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (15)
1. a printed substrate has N layer wiring layer, is respectively first wiring layer, second wiring layer, and the like, the N-1 wiring layer, the N wiring layer is characterized in that, also comprises:
Be positioned at least one first kind connection pads on first wiring layer of described printed substrate, be used to be electrically connected semiconductor package part;
Be arranged at least one the second class connection pads on any one wiring layer of second wiring layer to the N-1 wiring layer of described printed substrate, be used for being electrically connected with the signal pins of semiconductor package part;
Be positioned at least one the 3rd class connection pads on the N wiring layer of described printed substrate, be used for being electrically connected with the ground connection or the power pins of semiconductor package part;
At least one blind hole that runs through any one wiring layer in first wiring layer to the second wiring layer, first wiring layer to the, three wiring layers or first wiring layer to the N-1 wiring layer of described printed substrate, described blind hole position is corresponding one by one with the position of the second class connection pads, has electric conducting material in the blind hole;
Run through at least one through hole of first wiring layer to the N wiring layer of described printed substrate, the position of described through hole is corresponding one by one with the position of the 3rd class connection pads, has electric conducting material in the through hole, and wherein N is a positive integer.
2. printed substrate according to claim 1 is characterized in that, the described second class connection pads is positioned on the N-1 wiring layer of printed substrate, and described blind hole runs through first wiring layer to the N-1 wiring layer.
3. according to claim 1 or 2 described printed substrates, it is characterized in that described the 3rd class connection pads is electrically connected by the electric conducting material in the through hole with described first kind connection pads.
4. according to claim 1 or 2 described printed substrates, it is characterized in that the described second class connection pads is electrically connected by the electric conducting material in the blind hole with described first kind connection pads.
5. according to claim 1 or 2 described printed substrates, it is characterized in that the first kind connection pads on the described printed wire base board forms the ball grid array footprint.
6. according to claim 1 or 2 described printed substrates, it is characterized in that described semiconductor package part is the ball grid array packaging part.
7. according to claim 1 or 2 described printed substrates, it is characterized in that first wiring layer to the N wiring layer material of described printed substrate is a metallic copper.
8. according to claim 1 or 2 described printed substrates, it is characterized in that described electric conducting material is a copper, be positioned at the inwall of blind hole or through hole.
9. the manufacture method of printed substrate according to claim 2 is characterized in that, comprising:
Formation has first wiring layer, the printed substrate of second wiring layer, N-1 wiring layer, wherein, has first kind connection pads on described first wiring layer, be used to connect semiconductor package part, have the second class connection pads on the described N-1 wiring layer, be used for being electrically connected with the signal pins of semiconductor package part;
Form at least one blind hole run through first wiring layer, second wiring layer to the N-1 wiring layer on described printed substrate, the position of the position of described blind hole and the second class connection pads the is corresponding one by one;
In blind hole, form electric conducting material;
Formation has the printed substrate of N wiring layer, has the 3rd class connection pads on the described N wiring layer, is used for being electrically connected with the ground connection or the power pins of semiconductor package part;
Form at least one through hole that runs through first wiring layer to the N wiring layer on described printed substrate, the position of described through hole is corresponding one by one with the position of the 3rd class connection pads, and wherein N is a positive integer;
In through hole, form electric conducting material.
10. the manufacture method of printed substrate according to claim 9 is characterized in that, described the 3rd class connection pads is electrically connected by the electric conducting material in the through hole with described first kind connection pads.
11. the manufacture method of printed substrate according to claim 9 is characterized in that, the electric conducting material in the described second class connection pads and the described first kind connection pads through hole is electrically connected.
12. the manufacture method of printed substrate according to claim 9 is characterized in that, the first kind connection pads on the described printed wire base board forms the ball grid array footprint.
13. the manufacture method of printed substrate according to claim 9 is characterized in that, described semiconductor package part is the ball grid array packaging part.
14. the manufacture method of printed substrate according to claim 9 is characterized in that, first wiring layer to the N wiring layer material of described printed substrate is a metallic copper.
15. the manufacture method of printed substrate according to claim 9 is characterized in that, described electric conducting material is a copper, is positioned at the inwall of blind hole or through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710160668 CN101472403B (en) | 2007-12-26 | 2007-12-26 | Printed circuit board and method for producing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710160668 CN101472403B (en) | 2007-12-26 | 2007-12-26 | Printed circuit board and method for producing the same |
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| CN102458035B (en) * | 2010-10-20 | 2014-11-19 | 上海嘉捷通电路科技有限公司 | Structure of slotting printed board |
| CN102105018B (en) * | 2010-12-31 | 2013-10-23 | 深圳市金宏威技术股份有限公司 | Multilayer circuit board |
| CN102736651A (en) * | 2012-06-29 | 2012-10-17 | 浪潮电子信息产业股份有限公司 | Design method for eliminating Ground noise |
| CN104470203A (en) * | 2013-09-25 | 2015-03-25 | 深南电路有限公司 | HDI circuit board and interlayer interconnection structure and machining method thereof |
| CN105574237B (en) * | 2015-12-10 | 2018-12-21 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | System in package BGA power ground pin distribution optimization method based on population |
| CN109688694B (en) * | 2018-12-29 | 2024-03-22 | 北京行易道科技有限公司 | Circuit structure and device |
| CN115497901B (en) * | 2022-11-22 | 2023-03-10 | 井芯微电子技术(天津)有限公司 | High-density packaging device and method for improving bump cracking failure |
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| CN1447639A (en) * | 2003-04-15 | 2003-10-08 | 威盛电子股份有限公司 | Method for fabricating multiplayer circuit boards |
| CN1568135A (en) * | 2003-06-13 | 2005-01-19 | 华通电脑股份有限公司 | Manufacturing method for multilayer printed circuit board and inter-layer ducting structure formed thereby |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1447639A (en) * | 2003-04-15 | 2003-10-08 | 威盛电子股份有限公司 | Method for fabricating multiplayer circuit boards |
| CN1568135A (en) * | 2003-06-13 | 2005-01-19 | 华通电脑股份有限公司 | Manufacturing method for multilayer printed circuit board and inter-layer ducting structure formed thereby |
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