KR20240040494A - Ceramic Interface Board for Semiconductor Test and Manufacturing Method thereof - Google Patents

Abstract

The present invention relates to a ceramic interface board for semiconductor testing and a method of manufacturing the same. The high-strength, low-thermal expansion rewiring ceramic board for semiconductor testing is mounted on a probe card, a device that connects a semiconductor chip and test equipment to inspect the operation of the semiconductor. The probe needle sends electricity as it touches the pad of the wafer, and is used to select defective semiconductor chips according to the feedback signal. The high-strength, low-thermal expansion SLC substrate and the redistribution layer (RDL) layer where the probe needle is formed are independently connected. The purpose is to increase the final process yield of the ceramic interface board, reduce process costs, and shorten the manufacturing period by manufacturing the final SLC substrate and RDL intruder through bonding.

Description

Ceramic interface board for semiconductor test and manufacturing method thereof {Ceramic Interface Board for Semiconductor Test and Manufacturing Method}

The present invention relates to a ceramic interface board for memory/non-memory semiconductor testing and a method of manufacturing the same. More specifically, the present invention relates to a ceramic interface board for memory/non-memory semiconductor testing and a method of manufacturing the same. More specifically, the present invention relates to a probe needle mounted on a probe card, which is a device that connects a semiconductor chip and test equipment to inspect the operation of a semiconductor. This relates to a ceramic interface board for semiconductor inspection that transmits electricity while contacting the pad of a wafer and selects defective semiconductor chips according to the feedback signal, and a method of manufacturing the same.

Generally, in the semiconductor manufacturing process, a probe station that determines whether a device is defective is equipped with a probe card to transmit electrical signals to the pad of the device. The probe card is equipped with a probe card board and one or more needles. This needle is brought into contact with a pad connected to the device on the semiconductor wafer, and the semiconductor device inspection equipment determines whether the device is defective by exchanging electrical signals with the pad of the device through the needle of the probe card connected to the substrate of the probe card.

The probe card consists of a PCB assembly, a space transformer forming the main body, and a plurality of probes arranged below. The space transformer is configured to be connected to the analysis system through an interface such as a cable or connector, and the lower probe uses a tip mounted at the end to contact the semiconductor chip pad on the wafer to electrically connect the analysis system and the semiconductor chip. It is composed.

Multilayer ceramic substrates are mainly used in space transformers, which serve as a substrate on which multiple probes are fixed.

Multilayer ceramic substrates are not only durable, but also have a low vertical expansion rate and good high-frequency efficiency, so they are attracting attention as substrates for highly integrated circuit configurations, including probe cards that require the formation of complex signal patterns and use a lot of high-frequency signals.

In addition, semiconductor devices are manufactured through a fabrication process that forms circuit patterns and contact pads for inspection on a wafer, and an assembly process that assembles wafers with circuit patterns and contact pads formed into individual chips. It is manufactured.

Between the fabrication process and the assembly process, an inspection process (EDS; Electrical Die Sorting) is performed to inspect the electrical characteristics of the wafer by applying an electrical signal to the contact pad formed on the wafer. Semiconductor devices are made of good quality through this inspection process. and are classified as defective products.

Testing the electrical characteristics of these semiconductor devices includes a tester responsible for generating test signals and judging test results, a performance board, and a probe station responsible for loading and unloading semiconductor wafers. Inspection devices including a probe station, a chuck, a prober, and a probe card are mainly used.

Among these, the probe card is responsible for the electrical connection between the semiconductor wafer and the tester. It receives signals generated from the tester through the performance board and transfers them to the pads of the chips within the wafer, and transmits the signals output from the pads of these chips to the performance board. It is responsible for transmitting information to the tester through the board.

This probe card is made by stacking a plurality of ceramic green sheets containing circuit patterns, electrode pads, and via electrodes to produce a laminate, then firing the laminate to manufacture a substrate, and attaching probe pins to the substrate. It can be configured in the form

As the size of semiconductor devices continues to be miniaturized due to the development of semiconductor circuit integration technology, inspection equipment for these semiconductor devices also requires high precision, and the circuit pattern formed on the wafer through the fabrication process and the contact pad connected to the circuit pattern are required. is being formed persistently.

In substrates for highly integrated probe cards for inspection of highly integrated wafers, there is a serious problem of power noise due to an increase in the current required for operation evaluation, and the decoupling capacitor is installed on the outside of the substrate surface away from the test pin area. It is difficult to further improve power noise with the current ceramic substrate structure mounted on the area.

To solve this problem, improvement in the structure of the probe card substrate and improvement in noise are required.

Republic of Korea Patent Publication No. 10-2015-0012994 (publication date April 4, 2015)

The high-strength, low-thermal expansion rewired ceramic board for semiconductor testing of the present invention is mounted on a probe card, which is a device that connects a semiconductor chip and test equipment to test the operation of a semiconductor, and the probe needle sends electricity and provides feedback ( The purpose is to provide a ceramic interface board for semiconductor inspection and a manufacturing method for selecting defective semiconductor chips according to the feedback signal.

Another object of the present invention is to manufacture the existing complex MLC (Multi Layer Ceramic) process into a simple SLC (Single Layer Ceramic), and to independently manufacture the redistribution layer (RDL) layers on which the probe needle is formed, thereby producing the final SLC/RDL. The purpose is to increase the final process yield of the ceramic interface board, reduce process costs, and shorten the production period by manufacturing through bonding.

A ceramic interface board for semiconductor inspection to achieve the purpose of the present invention is mounted on a probe card, a device that connects a semiconductor chip and test equipment, and selects defective semiconductor chips according to the electrical signal received when the probe needle contacts the pad of the wafer. In the ceramic board for semiconductor inspection, the ceramic board includes a high-strength, low-coefficient thermal expansion (SLC) single layer ceramic (SLC) substrate and an RDL (Redistribution Layer) interposer with a redistribution layer bonded to the surface thereof, The SLC substrate is formed with a plurality of through holes, each through hole is filled with a conductive metal, an electrode is formed on the surface of each through hole, and the upper surface is patterned so that the metal material connected to the through hole is exposed. A bonding layer is formed, a dynamic peeling layer is formed on the surface of the RDL interposer substrate, and a plurality of redistribution layers are formed to form vertical and horizontal wiring and connect them to each other.

Here, the RDL interposer is bonded to a bonding layer formed on the SLC, and the dynamic exfoliation layer is activated by a laser irradiated on the upper surface of the RDL interposer to remove the interposer.

The manufacturing process of a ceramic board for semiconductor inspection to achieve the purpose of the present invention is to install a probe card, which is a device that connects a semiconductor chip and a test equipment, and detect defective semiconductor chips according to the electrical signal received when the probe needle contacts the pad of the wafer. In the method of manufacturing a ceramic board for screening semiconductors, a conductive metal is filled into a plurality of through holes in a ceramic substrate, an electrode is formed on the surface, and a bonding layer is formed on the upper surface of the SLC (Single Layer Ceramic) substrate. procedure; RDL (Redistribution Layer) interposer manufacturing process of forming vertical and horizontal wiring on the surface of the dynamic peeling layer formed on the regenerative substrate and forming a multi-layer redistribution layer to be connected to each other; A bonding process of bonding the bonding layer of the SLC substrate and the RDL interposer; and a peeling process of removing the sacrificial substrate of the RDL interposer.

Here, the SLC substrate manufacturing process includes forming a plurality of through-via hole patterns on the ceramic substrate; Filling each via hole with a conductive material; Flattening the upper and lower surfaces of the ceramic substrate; forming electrodes of a conductive material on the upper and lower surfaces of each via hole; And forming a cementum on the upper surface.

In addition, the RDL interposer manufacturing process includes forming a dynamic peeling layer on the upper surface of the regenerative substrate; Depositing a conductive seed metal layer on the surface of the dynamic exfoliation layer; Forming an electrode for bonding a probe needle for semiconductor inspection on the seed metal layer; forming the insulating layer and the via hole, and forming at least one unit redistribution layer that forms a redistribution circuit vertically and horizontally using plating and a conductor in the via hole; and forming a bonding pad on the surface of the redistribution layer.

As described above, the ceramic interface board for semiconductor inspection of the present invention uses a high-strength/low-thermal expansion single-layer ceramic board, so the thermal expansion coefficient is 0.2 ~ 1 ppm/℃ less than 1 ppm/℃) Burn-in test when testing memory semiconductor devices There is no need for holding time (approximately 30 to 60 minutes/lot), which has the effect of shortening test time.

In addition, because the high-strength, low-thermal expansion rewiring ceramic interface board of the present invention uses a high-strength substrate, it has the effect of enabling multi-layer RDL formation than before.

In addition, since the high-strength, low-thermal expansion rewiring ceramic interface board of the present invention manufactures the SLC (Single Layer Ceramic) and RDL substrates independently, the process of forming the redistribution layer in the existing ceramic interface board manufacturing method is different. It has the effect of preventing risks such as rework process as a result of failure.

In addition, the high-strength, low-thermal expansion rewired ceramic board of the present invention has the advantage of high freedom of raw material utilization and shortened delivery time from the perspective of mass production of ceramic interface boards.

In addition, the high-strength, low-thermal expansion rewiring ceramic board of the present invention is mounted on a probe card, which is a device that connects a semiconductor chip and test equipment to inspect the operation of the semiconductor, so that the probe needle contacts the pad of the wafer to send electricity and feedback (feedback). It is effective in producing a ceramic board with high strength and low coefficient thermal expansion to select defective semiconductor chips according to the back signal.

In addition, the high-strength, low-thermal expansion redistribution ceramic interface board of the present invention replaces the existing complex MLC (Multi Layer Ceramic) process with a simple SLC (Single Layer Ceramic), and the redistribution (RDL) layer where the probe needle is formed is independently By manufacturing each SLC/RDL through bonding, there is an effect of increasing the final process yield of the ceramic interface board, reducing process costs, and shortening the manufacturing period.

In addition, the high-strength, low-thermal expansion rewired ceramic board of the present invention has the effect of increasing the final process yield of the ceramic interface board, reducing the process cost, and shortening the production period, enabling short delivery time to customers, and providing multi-parameter support. When manufactured for use, its applicability has various effects.

1 is a cross-sectional configuration diagram of a ceramic interface board for semiconductor inspection according to an embodiment of the present invention;
Figure 2 is a flowchart of the entire manufacturing process of a ceramic interface board for semiconductor inspection according to the present invention;
Figure 3 is a cross-sectional view of the SLC substrate at each stage of the SLC manufacturing process in Figure 2;
Figure 4 is a cross-sectional view of the RDL interposer at each stage according to the RDL interposer manufacturing process in Figure 2;
FIG. 5 is a cross-sectional view for explaining the SLC and RDL substrate bonding and sacrificial substrate peeling processes in FIG. 2.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Throughout the specification, similar parts are given the same reference numerals.

The configuration and manufacturing process of a ceramic interface board for semiconductor inspection according to an embodiment of the present invention will be described in detail with reference to the attached drawings as follows.

First, the ceramic interface board for semiconductor inspection according to the present invention is mounted on a probe card, which is a device that connects a semiconductor chip and test equipment, and selects defective semiconductor chips according to the electrical signal received when the probe needle contacts the pad of the wafer. This is a ceramic board for inspection. A high-strength, low-coefficient thermal expansion SLC (Single Layer Ceramic) board and an RDL (Redistribution Layer) interposer with a redistribution layer bonded to the surface are manufactured according to the manufacturing process and bonded together. do.

Referring to FIG. 1, the SLC substrate 10 is made by filling a plurality of through holes in a ceramic substrate 10a with conductive metal 12, and forming an electrode 13 on the surface of each conductive metal 12. A bonding layer 14 is formed by exposing the metal material patterned on the upper surface and connected to each electrode 12, and the RDL interposer 20 is perpendicular to the first to sixth insulating layers 21 to 26. A plurality of redistribution layers are formed to be connected to each other through wiring and horizontal wiring 28a and 28b, and an electrode 29 for probe needle bonding is formed on the outer surface of the sixth insulating layer 26, and the first insulating layer (21) A bonding pad 27 is formed on the outer surface.

Here, when the thermal expansion coefficient of the ceramic substrate 10 is set to 1ppm/℃ or less, preferably 0.2 to 1ppm/℃, the burn-in test holding time is 30 to 60 minutes when testing a memory semiconductor device. Since a lot is not required, test time can be shortened, and multi-layer RDL can be formed because a high-strength substrate is used.

The RDL interposer 20 is not limited to the first to sixth insulating layers 21 to 26, and can be configured with at least one redistribution insulating layer.

The manufacturing process of the ceramic interface board for semiconductor inspection according to the present invention configured as described above will be described in more detail with reference to the attached FIGS. 2 to 5 as follows.

Figure 2 is a flowchart of the manufacturing process of a ceramic interface board for semiconductor inspection according to an embodiment of the present invention. An SLC substrate 10 and an RDL interposer 20 are manufactured respectively, and a sacrificial substrate is formed through bonding and laser irradiation. A ceramic board is produced through a peeling process.

First, the manufacturing process of the SLC substrate 10 will be described in detail with reference to FIG. 3 as follows.

The SLC substrate 10 uses a high-strength, low-thermal expansion ceramic board, and a via hole pattern is formed by processing through via holes 11 in the ceramic substrate 10a, and a conductive material 12 is placed in each of the patterned via holes 11. After filling, the upper and lower surfaces are processed so that they are flat.

After forming the electrode 13 on the conductive material 12 on the upper and lower surfaces of each of the patterned via holes 11 of the flattened ceramic substrate 10a, an electrode 13 is formed on the upper surface for bonding to the RDL interposer 20. Forms a bonding layer.

Here, the bonding layer 14 is formed of a photosensitive material, an anisotropic conductive film (ACF), or a bump.

4 is a cross-sectional view of each manufacturing process of the RDL interposer 20. Referring to this, a laser-reactive dynamic lamination or coating layer 20b is formed on the upper surface of the sacrificial substrate 20a. The dynamic peeling layer 20b can be made of PI, polymer, etc.

After depositing a conductive seed metal layer on the surface of the dynamic exfoliation layer 20b, an electrode 29 for probe needle bonding for semiconductor inspection is formed on the seed metal layer.

An insulating layer and a via hole are formed on the surface of the operating release layer 20b, and a sixth insulating layer 26 is formed with a redistribution circuit using vertical wiring 28a and horizontal wiring 28b using plating and conductors in the via hole. form

A fifth insulating layer 25 is formed on the sixth insulating layer 26, in which a redistribution circuit is formed with vertical wiring 28a and horizontal wiring 28b, and in the same manner, the fourth to first insulating layers ( 24~21).

A bonding pad 27 is formed on the upper surface of the first insulating layer 21 for bonding to the SLC substrate 10.

The process of joining the SLC substrate 10 and the RDL interposer 20 manufactured through each of the above processes will be described in detail with reference to FIG. 5 as follows.

The upper surface of the first insulating layer 21 on which the bonding pad 27 of the RDL interposer 20 is formed is bonded to the bonding layer 14 of the SLC substrate 10.

When the SLC substrate 10 and the RDL interposer 20 are bonded, a laser is irradiated from the upper surface of the sacrificial substrate 20a to activate the dynamic peeling layer 20b, thereby performing a peeling process in which the sacrificial substrate is removed. It will be performed.

Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above embodiments and may be modified in various ways by those skilled in the art without departing from the spirit of the invention. Transformation and change are possible. Such modifications and variations should be considered to fall within the scope of the present invention and the appended claims.

10: SLC substrate 10a: Ceramic substrate
11: via hole 12: conductive material
13: electrode 14: bonding layer
20: RDL interposer 20a: Sacrificial substrate
20b: Dynamic peeling layer 21-26: 1st to 6th insulating layer
27: Bonding pad 28a, 28b: Vertical, horizontal wiring
29: Electrode for probe bonding

Claims (10)

In a ceramic interface board for semiconductor inspection that is mounted on a probe card, which is a device that connects a semiconductor chip and test equipment, and selects defective semiconductor chips according to the electrical signal received when the probe needle contacts the pad of the wafer,
The ceramic board includes a high-strength, low-coefficient thermal expansion (SLC) single layer ceramic (SLC) substrate and an RDL (Redistribution Layer) interposer with a redistribution layer bonded to the surface thereof,
The SLC substrate is formed with a plurality of through holes, each through hole is filled with a conductive metal, an electrode is formed on the conductive metal surface of each through hole, and the upper surface is patterned to expose a metal material connected to the through hole. A bonding layer is formed in the state,
The RDL interposer is a ceramic interface board for semiconductor inspection, characterized in that a dynamic peeling layer is formed on the surface of the substrate and a plurality of redistribution layers are formed to be connected to each other through vertical and horizontal wiring. According to paragraph 1,
A ceramic interface board for semiconductor inspection, wherein the RDL interposer is bonded to a bonding layer formed on the SLC substrate, and the dynamic exfoliation layer is activated by a laser irradiated on the upper surface of the RDL interposer to remove the interposer. . According to paragraph 1,
A ceramic interface board for semiconductor inspection, characterized in that the thermal expansion coefficient of the SLC substrate is 0.2 ~ 1ppm/℃. A method of manufacturing a ceramic interface board for semiconductor inspection that is mounted on a probe card, which is a device that connects a semiconductor chip and test equipment, and selects defective semiconductor chips according to the electrical signal received when the probe needle contacts the pad of the wafer, comprising:
A SLC (Single Layer Ceramic) substrate manufacturing process in which a plurality of through holes in a ceramic substrate are filled with a conductive metal, electrodes are formed on the surface, and a bonding layer is formed on the upper surface;
RDL (Redistribution Layer) interposer manufacturing process of forming vertical and horizontal wiring on the surface of the dynamic peeling layer formed on the regenerative substrate and forming a multi-layer redistribution layer to be connected to each other;
A bonding process of bonding the bonding layer of the SLC substrate and the RDL interposer; and
A method of manufacturing a ceramic interface board for semiconductor inspection, comprising: a peeling process of removing the sacrificial substrate of the RDL interposer. According to paragraph 4,
A method of manufacturing a ceramic interface board for semiconductor inspection, characterized in that the SLC substrate and the RDL interposer are manufactured in independent processes and then bonded. According to paragraph 4,
The SLC substrate manufacturing process includes forming a plurality of through-via hole patterns on the ceramic substrate;
Filling each via hole with a conductive material;
Flattening the upper and lower surfaces of the ceramic substrate;
forming electrodes of a conductive material on the upper and lower surfaces of each via hole; and
A method of manufacturing a ceramic interface board for semiconductor inspection, comprising: forming a bond on the upper surface. According to clause 6,
A method of manufacturing a ceramic interface board for semiconductor inspection, wherein the bonding layer is formed of one of a photosensitive material, an anisotropic conductive film (ACF), or a bump. According to paragraph 4,
The RDL interposer manufacturing process includes forming a dynamic peeling layer on the upper surface of the regenerative substrate;
Depositing a conductive seed metal layer on the surface of the dynamic exfoliation layer;
Forming an electrode for bonding a probe needle for semiconductor inspection on the seed metal layer;
forming the insulating layer and the via hole, and forming at least one unit redistribution layer that forms a redistribution circuit vertically and horizontally using plating and a conductor in the via hole; and
A method of manufacturing a ceramic interface board for semiconductor inspection, comprising: forming a bonding pad on the surface of the redistribution layer. According to clause 8,
The bonding process is a method of manufacturing a ceramic interface board for semiconductor inspection, characterized in that the bonding pad of the RDL interposer and the bonding layer of the SLC substrate are bonded. According to paragraph 4,
The peeling process is a method of manufacturing a ceramic interface board for semiconductor inspection, characterized in that the sacrificial substrate is removed by irradiating a laser to the upper surface of the RDL interposer to activate the dynamic peeling layer.