WO2023070328A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2023070328A1
WO2023070328A1 PCT/CN2021/126477 CN2021126477W WO2023070328A1 WO 2023070328 A1 WO2023070328 A1 WO 2023070328A1 CN 2021126477 W CN2021126477 W CN 2021126477W WO 2023070328 A1 WO2023070328 A1 WO 2023070328A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
pixel
display substrate
substrate according
substrate
Prior art date
Application number
PCT/CN2021/126477
Other languages
English (en)
French (fr)
Inventor
黄海涛
徐传祥
于勇
吴慧利
崔钊
刘文渠
舒适
井丽娜
孟德天
倪子博
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/126477 priority Critical patent/WO2023070328A1/zh
Priority to EP21961704.0A priority patent/EP4333063A4/en
Priority to CN202180003096.5A priority patent/CN116569672A/zh
Priority to CN202310881416.8A priority patent/CN116669473A/zh
Publication of WO2023070328A1 publication Critical patent/WO2023070328A1/zh
Priority to US18/360,851 priority patent/US20240023381A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H10K59/877—Arrangements for extracting light from the devices comprising scattering means

Definitions

  • Embodiments of the present disclosure relate to but are not limited to the field of display technology, especially a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • PM Passive Matrix
  • AM Active Matrix
  • TFT Thin Film Transistor
  • An embodiment of the present disclosure provides a display substrate, including: a substrate, at least one insulating film layer disposed on the substrate, and a first electrode disposed on a side of the insulating film layer away from the substrate; wherein: at least one A concave-convex structure is provided on a side of the insulating film layer away from the substrate, and an orthographic projection of the concave-convex structure on the substrate and an orthographic projection of the first electrode on the substrate include an overlapping area.
  • the display substrate includes: a planar layer, a light-emitting structure layer, an encapsulation layer, and a color filter layer sequentially formed on the base,
  • the light-emitting structure layer includes a pixel definition layer, an anode, a cathode, and a An organic light-emitting layer between the anode and the cathode
  • the pixel definition layer includes a plurality of pixel openings, the pixel openings expose at least part of the anode; the cathode covers the pixel definition layer;
  • the color filter layer includes a black matrix and color filters arranged at intervals, the black matrix has a plurality of opening areas arranged in a matrix, the color filter is at least partially filled in the opening areas, and the color filter is at least partially filled in the opening areas.
  • the optical filter and the black matrix at least include a partial overlapping area, and in the overlapping area, the color filter covers the black matrix.
  • At least one of the insulating film layers includes: the pixel definition layer, and the first electrode includes: the cathode.
  • the pixel definition layer includes a plurality of first protrusions, and first depressions are formed between adjacent first protrusions.
  • the first depression is a groove surrounding the pixel opening, and the distance between adjacent grooves is formed by the edge of the opening area of the black matrix and the pixel definition layer. Between 1/8 and 7/8 of the distance between the edges of the pixel openings.
  • the distance between adjacent grooves is between 1 micron and 2 microns.
  • the width of the groove is between 0.8 microns and 1.5 microns.
  • the first recess is an opening surrounding the pixel opening, and the width of the opening is between 0.5 ⁇ m and 1.8 ⁇ m.
  • the plurality of openings form a plurality of annular structural units, at least one annular structural unit includes N annular structures arranged around the pixel opening and parallel to each other, and the innermost annular structure includes a plurality of An opening, the first opening is adjacent to the pixel opening, and N is a natural number greater than 1.
  • serrated protrusions are formed between the plurality of first openings, and the width of the serrated protrusions is between 0.8 ⁇ m and 1.5 ⁇ m.
  • N is a natural number between 1 and 50.
  • At least one of the insulating film layers includes: the planar layer, and the first electrode includes: the anode.
  • the flat layer includes a plurality of second protrusions, and second depressions are formed between adjacent second protrusions.
  • the second protrusion is sawtooth-shaped.
  • a step difference between the second protrusion and the second depression is between 1/8 and 7/8 of the thickness of the flat layer.
  • the step difference between the second protrusion and the second depression is between 0.2 microns and 0.8 microns.
  • At least one of the insulating film layers includes the pixel definition layer and the flat layer, and the first electrode includes the cathode and the anode; the pixel definition layer is far away from the substrate
  • One side is provided with a first concave-convex structure, and the orthographic projection of the first concave-convex structure on the substrate and the positive projection of the cathode on the substrate include an overlapping area; the side of the flat layer away from the substrate
  • a second concave-convex structure is provided, and the orthographic projection of the second concave-convex structure on the substrate and the orthographic projection of the anode on the substrate include overlapping regions.
  • the display substrate further includes a touch structure layer disposed between the encapsulation layer and the color filter layer, the touch structure layer includes a plurality of touch electrodes, and the black matrix
  • the orthographic projection on the substrate includes the orthographic projection of the touch electrode on the substrate.
  • An embodiment of the present disclosure also provides a display device, including the display substrate as described in any one of the preceding items.
  • An embodiment of the present disclosure provides a method for preparing a display substrate, comprising: forming at least one insulating film layer on a base, at least one side of the insulating film layer away from the base is provided with a concave-convex structure; The side of the layer away from the substrate forms a first electrode, and the orthographic projection of the concave-convex structure on the substrate and the orthographic projection of the first electrode on the substrate include an overlapping area.
  • 1 is a schematic structural view of a display device
  • FIG. 2 is a schematic plan view of a display substrate
  • Figure 3a and Figure 3b are schematic diagrams of two kinds of color separation phenomena
  • FIG. 4 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 5a and Figure 5b are schematic diagrams of the improved color separation results of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a display substrate after preparing a flexible substrate pattern according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a display substrate after preparing a driving structure layer pattern according to an embodiment of the present disclosure
  • FIG. 8 is a schematic structural view of a display substrate after forming a flat layer pattern according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural view of a display substrate after forming an anode pattern according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a display substrate after forming a pixel definition layer pattern according to an embodiment of the present disclosure
  • FIG. 11 and FIG. 12 are schematic structural diagrams of two pixel definition layers according to embodiments of the present disclosure.
  • FIG. 13 is a schematic structural view of a display substrate after forming a spacer layer pattern according to an embodiment of the present disclosure
  • FIG. 14 is a schematic structural view of a display substrate after forming a cathode pattern according to an embodiment of the present disclosure
  • FIG. 15 is a schematic structural diagram of a display substrate after forming an encapsulation layer pattern according to an embodiment of the present disclosure
  • FIG. 16 is a schematic structural diagram of a display substrate after forming a touch structure layer pattern according to an embodiment of the present disclosure
  • FIG. 17 is a schematic structural diagram of a display substrate after forming a color filter layer pattern according to an embodiment of the present disclosure
  • FIG. 18 is a schematic structural diagram of a display substrate after bonding a cover according to an embodiment of the present disclosure.
  • 19 is a schematic structural diagram of an optically improved color separation test model according to an embodiment of the present disclosure.
  • Figure 20a and Figure 20b are schematic diagrams of the simulation results when the incident light in Figure 19 is along the long axis direction of the color filter;
  • FIG. 21a and FIG. 21b are schematic diagrams of simulation results when the incident light in FIG. 19 is along the short axis direction of the color filter.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figure.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the accompanying drawings. The shape or value shown in the figure, etc.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged, and “source terminal” and “drain terminal” can be interchanged.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • triangle, rectangle, trapezoid, pentagon, or hexagon in this specification are not strictly defined, and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, etc., and there may be some small deformations caused by tolerances. There can be chamfers, arc edges, deformations, etc.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data signal driver, a scanning signal driver and a pixel array, the timing controller is respectively connected to the data signal driver and the scanning signal driver, and the data signal driver is respectively connected to a plurality of data signal lines ( D1 to Dn) are connected, and the scan signal drivers are respectively connected to a plurality of scan signal lines (S1 to Sm).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scanning signal line, at least one data signal line and pixel drive circuit.
  • the timing controller may provide grayscale values and control signals suitable for the specifications of the data signal driver to the data signal driver, and may provide a clock signal, a scan start signal suitable for the specifications of the scan signal driver, etc. and so on are supplied to the scan signal driver.
  • the data signal driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, . . .
  • the data signal driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan signal driver may sequentially supply scan signals having turn-on level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver can be constructed in the form of a shift register, and can generate scans in such a way that a scan start signal supplied in the form of a conduction level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal signal, m can be a natural number.
  • FIG. 2 is a schematic plan view of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color, and a second sub-pixel P1 that emits light of a second color.
  • each of the four sub-pixels may include a circuit unit and a light emitting device, and the circuit unit may include scanning signal lines, data The signal line and the pixel driving circuit, the pixel driving circuit is respectively connected to the scanning signal line and the data signal line, the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line, and output the corresponding voltage to the light emitting device current.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel to emit light with a corresponding brightness.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a green sub-pixel (G) emitting green light
  • the third sub-pixel P3 may be is a white sub-pixel (W) that emits white light
  • the fourth sub-pixel P4 may be a blue sub-pixel (B) that emits blue light.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • four sub-pixels may be arranged horizontally in parallel to form an RWBG pixel arrangement.
  • the four sub-pixels may be arranged in a square, a diamond, or vertical arrangement, which is not limited in the present disclosure.
  • At least one of the plurality of pixel units P may include a red (R) sub-pixel emitting red light, a green (G) sub-pixel emitting green light, and a blue sub-pixel emitting blue light.
  • color (B) sub-pixel or may include a red sub-pixel emitting red light, two green sub-pixels emitting green light, and a blue sub-pixel emitting blue light, which is not limited in this disclosure.
  • the pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically or squarely.
  • the pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically or squarely. Arrangement, the disclosure is not limited here.
  • a plurality of sub-pixels arranged in sequence in the horizontal direction is called a pixel row
  • a plurality of sub-pixels arranged in sequence in the vertical direction are called a pixel column
  • a plurality of pixel rows and a plurality of pixel columns constitute pixels arranged in an array array.
  • COE technology will have the phenomenon of color separation in the dark state, that is, when the screen is off, the phenomenon of color separation of reflected light will be seen under the light source, which will affect the user's experience of absolute black screen, as shown in Figure 3a and Figure 3b.
  • the main reason for the phenomenon of dark state color separation is that after the circular polarizer is removed, the intensity distribution of the ambient light is changed to varying degrees after being reflected by the red, green and blue pixels and the directional reflection of the light by the cathode and anode.
  • Some technologies scatter light by doping scattering particles in the coating protective layer (OC) to improve the color separation phenomenon, but the introduction of scattering particles will reduce the light transmittance, thus losing the advantage of high transmittance of COE.
  • An embodiment of the present disclosure provides a display substrate, including: a base, at least one insulating film layer disposed on the base, and a first electrode disposed on a side of the insulating film layer away from the base; wherein: at least one insulating film layer is far away from the base; A concave-convex structure is provided on one side, and the orthographic projection of the concave-convex structure on the substrate and the orthographic projection of the first electrode on the substrate include overlapping regions.
  • At least one insulating film layer opposite to the first electrode is processed to form a concave-convex structure, which interferes with the reflection path of ambient light, destroys the emission of ambient light, and improves the color separation phenomenon, and
  • the display substrate of the present disclosure has the advantages of simple preparation process, high production efficiency, low production cost and high yield rate, etc., and has good application prospects.
  • FIG. 4 is a schematic cross-sectional structure diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate according to an embodiment of the present disclosure includes: a base, a flat layer 95 and a light emitting structure layer sequentially formed on the base, and the light emitting structure layer Including anode 51; at least one insulating film layer includes: planar layer 95, the first electrode includes: anode 51;
  • the side of the flat layer 95 away from the substrate is provided with a second concave-convex structure, and the orthographic projection of the second concave-convex structure on the substrate and the orthographic projection of the anode 51 on the substrate include overlapping regions.
  • the flat layer 95 facing the anode 51 is gently undulated, so that the anode 51 forms a certain undulating shape, that is, a diffuse reflection anode is formed, which interferes with the reflection of ambient light. path, which destroys the exit of ambient light and improves color separation.
  • the display substrate of the embodiment of the present disclosure can greatly reduce the color separation phenomenon, and can maintain a good black color under strong light irradiation in a dark state, and has obvious effects through user experience tests.
  • the second concave-convex structure includes a plurality of second protrusions, and second depressions are formed between adjacent second protrusions.
  • the second protrusion may be sawtooth-shaped.
  • the step difference between the second protrusion and the second depression may be between 0.2 microns and 0.8 microns.
  • the light emitting structure layer further includes a pixel definition layer 96, the pixel definition layer 96 includes a plurality of pixel openings, and the pixel openings expose the anode 51; the side of the pixel definition layer 96 away from the substrate is provided with a first concave-convex structure .
  • At least one insulating film layer includes: a pixel definition layer 96
  • the first electrode includes: a cathode
  • the pixel definition layer 96 is also subjected to gentle undulation treatment, so that the pixel definition layer 96 forms a concave-convex topography, so that Depositing the cathode can also make the cathode form an uneven morphology, that is, a scattering cathode surface is formed, which interferes with the reflection path of ambient light, destroys the emission of ambient light, and further improves the color separation phenomenon.
  • the first concave-convex structure includes a plurality of first protrusions, and first depressions are formed between adjacent first protrusions.
  • the first depression is a groove surrounding the pixel opening
  • the width of the groove is between 0.8 micron and 1.5 micron
  • the distance between adjacent grooves is between 1 micron and 2 micron.
  • the distance between adjacent grooves is between 1/8 and 7/8 of the distance between the edge of the opening area of the black matrix and the edge of the pixel opening formed by the pixel definition layer.
  • the first recess is an opening surrounding the pixel opening, and the width of the opening is between 0.5 microns and 1.8 microns.
  • a plurality of openings form a plurality of annular structural units, each annular structural unit includes N annular structures arranged around the pixel opening and parallel to each other, and the innermost annular structure includes a plurality of first openings , the first opening is adjacent to the pixel opening, saw-toothed protrusions are formed between the first openings, the width of each saw-toothed protrusion is between 0.8 ⁇ m and 1.5 um, and N is a natural number greater than 1.
  • N is a natural number between 1 and 50.
  • N is 3.
  • the light-emitting structure layer further includes an organic light-emitting layer 52 and a cathode 53, wherein the organic light-emitting layer 52 is disposed on the anode 51; the cathode 53 is disposed on the organic light-emitting layer 52, and the organic light-emitting layer 52 and the anode 51
  • the cathode 53 is connected to the organic light-emitting layer 52 , and the organic light-emitting layer 52 emits light of a corresponding color under the drive of the anode 51 and the cathode 53 .
  • the positions of the organic light emitting layer 52 and the cathode 53 corresponding to the first concave-convex structure and/or the second concave-convex structure are non-planar surfaces.
  • the organic light emitting layer 52 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a light emitting layer (EML), a hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and all sub-pixels
  • the light-emitting layers of the sub-pixels can be a common layer connected together, or can be isolated from each other, and the light-emitting layers of adjacent sub-pixels can have a small amount of overlap.
  • the display substrate may include other film layers, which is not limited in this disclosure.
  • the display substrate further includes an encapsulation layer 98 disposed on a side of the light emitting structure layer away from the substrate.
  • the encapsulation layer 98 may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may use inorganic materials, the second encapsulation layer may use organic materials, and the second encapsulation layer Being arranged between the first encapsulation layer and the third encapsulation layer can ensure that external water vapor cannot enter the light-emitting structure layer.
  • the substrate includes a substrate 10 and a driving structure layer 102 disposed on the substrate 10 .
  • Substrate 10 may be a flexible substrate, or may be a rigid substrate.
  • the driving structure layer 102 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and storage capacitors.
  • the anode 51 is connected to the first thin film transistor in the driving structure layer through the via hole opened in the planar layer 95 .
  • the display substrate further includes a color filter layer disposed on the side of the encapsulation layer 98 away from the base, the color filter layer includes black matrixes 71 and color filters 72 arranged at intervals, and the black
  • the matrix 71 has a plurality of opening areas arranged in a matrix, and the color filters 72 are filled in the opening areas.
  • the color filter 72 and the black matrix 71 include at least a partial overlapping area. In the overlapping area between the black matrix 71 and the color filter 72 , the color filter 72 covers the black matrix 71 .
  • the display substrate further includes a touch structure layer 103 disposed between the encapsulation layer 98 and the color filter layer, the touch structure layer 103 may include a plurality of touch electrodes, and the black matrix 71 on the substrate
  • the orthographic projection includes the orthographic projection of the touch electrodes on the substrate.
  • the "patterning process” mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, developing, etching and stripping photoresist.
  • the "photolithography process” mentioned in this embodiment includes coating film layer, mask exposure, development and other treatments, which is a mature preparation process in the related art.
  • Deposition can adopt any one or more selected from sputtering, evaporation and chemical vapor deposition, coating can adopt any one or more selected from spray coating and spin coating, and etching can adopt any one or more selected from dry etching. Any one or more of wet engraving.
  • “Film” refers to a layer of film produced by depositing or coating a certain material on a substrate. If the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. When the “thin film” still needs patterning process in the whole production process, it is called “film” before the patterning process, and it is called “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. "A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of A includes the orthographic projection of B” means that the orthographic projection of B falls within the range of the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.
  • the manufacturing process of the display substrate shown in FIG. 4 may include the following steps:
  • the flexible substrate 10 may adopt a two-layer flexible layer structure, and the flexible substrate 10 includes a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second a flexible material layer and a second inorganic material layer.
  • Materials such as the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft films, and the first inorganic material
  • the material of the layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., which are used to improve the water and oxygen resistance of the substrate.
  • the first inorganic material layer and the second inorganic material layer are also called Materials for the barrier (Barrier) layer and the semiconductor layer may be amorphous silicon (a-si).
  • the preparation process of the flexible substrate 10 may include: first coating a layer of polyimide on the glass carrier 1 , form the first flexible (PI1) layer after curing into a film; then deposit a layer of barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then deposit on the first barrier layer A layer of amorphous silicon film forms an amorphous silicon (a-si) layer covering the first barrier layer; then coats a layer of polyimide on the amorphous silicon layer, and forms a second flexible (a-si) layer after curing into a film.
  • PI2 layer then a barrier film is deposited on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, and the preparation of the flexible substrate 10 is completed, as shown in FIG. 6 .
  • the flexible substrate 10 may adopt a flexible layer structure, for example, the flexible substrate 10 includes a stacked flexible (PI) layer and a barrier (Barrier) layer.
  • PI stacked flexible
  • Barrier barrier
  • the drive structure layer includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines vertically intersect to define a plurality of pixel units arranged in a matrix, each pixel unit includes at least 3 sub-pixels, at least one sub-pixel Including at least one first thin film transistor (Thin Film Transistor, TFT) (in a possible embodiment, in the under-screen camera area, at least one sub-pixel is not provided with a TFT, and only an anode is provided).
  • TFT Thin Film Transistor
  • the first thin film transistor may have a bottom gate structure or a top gate structure, may be an amorphous silicon (a-Si) thin film transistor, or may be a low temperature polysilicon (LTPS) thin film transistor or an oxide (Oxide) thin film transistor, where No limit.
  • a-Si amorphous silicon
  • LTPS low temperature polysilicon
  • Oxide oxide
  • one pixel unit includes three sub-pixels, which are red sub-pixel R, green sub-pixel G and blue sub-pixel B respectively.
  • the solution of this embodiment is also applicable to the case where one pixel unit includes 4 sub-pixels (red sub-pixel R, green sub-pixel G, blue sub-pixel B and white sub-pixel W).
  • the preparation process of the driving structure layer may include:
  • the active layer pattern includes at least the first active layer 11 .
  • the first insulating layer 91 is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate.
  • a second insulating film and a first metal film are deposited in sequence, and the first metal film is patterned by a patterning process to form a second insulating layer 92 covering the active layer, and a first gate disposed on the second insulating layer 92.
  • the electrode layer pattern, the first gate electrode layer at least includes a first gate electrode 21 and a first capacitor electrode 22 , a plurality of gate lines (not shown) and a plurality of gate leads (not shown).
  • the second insulating layer 92 is referred to as a first gate insulating (GI1) layer.
  • a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned by a patterning process to form a third insulating layer 93 covering the first gate electrode layer, and a third insulating layer 93 disposed on the third insulating layer 93
  • the second gate electrode layer at least includes a second capacitor electrode 31 and a second gate lead (not shown), the position of the second capacitor electrode 31 corresponds to the position of the first capacitor electrode 22 .
  • the third insulating layer 93 is also referred to as a second gate insulating (GI2) layer.
  • a fourth insulating film is deposited, and the fourth insulating film is patterned by a patterning process to form a pattern of a fourth insulating layer 94 covering the second gate electrode layer.
  • a plurality of first via holes are opened on the fourth insulating layer 94.
  • the positions of the first via holes correspond to the positions of both ends of the first active layer respectively, and the fourth insulating layer 94, the third insulating layer 93 and the second insulating layer 92 in the plurality of first via holes are etched away, Surfaces of the first active layer are respectively exposed.
  • the fourth insulating layer 94 is also referred to as an interlayer insulating (ILD) layer.
  • the source-drain metal layer includes at least the first source electrode 41, the first Drain electrode 42, low voltage (VSS) line (not shown), a plurality of data lines (not shown) and a plurality of data lead wires (not shown) patterns, the first source electrode 41 and the first drain electrode 42 pass through the first source electrode 41 and the first drain electrode 42 respectively.
  • a via hole is connected to both ends of the first active layer 11 .
  • the source-drain metal layer may further include any one or more of a power line (VDD), a compensation line and an auxiliary cathode.
  • the pattern of the driving structure layer has been prepared on the flexible substrate 10 , as shown in FIG. 7 .
  • the first active layer 11, the first gate electrode 21, the first source electrode 41 and the first drain electrode 42 form a first thin film transistor, the first capacitor electrode 22 and the second capacitor electrode 31 form a storage capacitor, and a plurality of gate leads and The data wires form the driving wires of the gate driver on array (GOA) of the array substrate.
  • GAA gate driver on array
  • the second concave-convex structure 951 includes a plurality of second protrusions, and second depressions are formed between adjacent second protrusions.
  • the pattern of openings on the mask can correspond to the second concave portion of the second concave-convex structure 951, thus, the second concave-convex structure 951 can be formed according to the desired Designing the position, shape and arrangement of the opening pattern of the mask plate is beneficial to simplify the manufacturing process of the display substrate.
  • the second protrusion may be sawtooth-shaped.
  • the step h1 between the second protrusion and the second depression may be between 1/8 and 7/8 of the thickness h2 of the flat layer 95 .
  • the step h1 between the second protrusion and the second depression may be 0.2 microns to 0.8 microns.
  • the step difference between the second protrusion and the second depression refers to the height difference between the highest point of the second protrusion and the lowest point of the second depression.
  • the anode 51 is connected to the first drain electrode D through the second via hole V2. Since the side of the flat layer 95 at the corresponding position of the anode 51 away from the flexible substrate has an undulating morphology, the anode 51 can also form an undulating morphology, which can also form a diffuse reflective anode surface.
  • forming the pattern of the anode 51 includes: depositing a fourth metal film on the substrate forming the aforementioned pattern, coating a layer of photoresist on the fourth metal film, and using a monotone mask to perform photolithography.
  • the photoresist in the fully exposed area is developed to remove the photoresist in the fully exposed area, and then the fourth metal thin film in the fully exposed area is etched away, and the photoresist is stripped to form
  • the pattern of the anode 51 is shown in FIG. 9 .
  • the anode 51 is a reflective electrode, and metals with high reflectivity can be used, such as silver Ag, gold Au, palladium Pd, platinum Pt, etc., or alloys of these metals, or these metals composite layer.
  • metals with high reflectivity such as silver Ag, gold Au, palladium Pd, platinum Pt, etc., or alloys of these metals, or these metals composite layer.
  • a composite layer structure of an indium tin oxide ITO layer and a metal reflective layer can also be used, which has good electrical conductivity, high reflectivity, and good shape stability.
  • the orthographic projection of the first concave-convex structure 961 on the flexible substrate 10 does not overlap with the orthographic projection of the pixel opening K on the flexible substrate 10 .
  • the first concave-convex structure 961 is located on the side of the pixel definition layer 96 close to the subsequently formed organic light-emitting layer 52, so that a fluctuating topography can be formed at the edge of the pixel definition layer 96 close to the light-emitting region .
  • the first concave-convex structure 961 includes a plurality of first protrusions 96a, and first recesses 96b are formed between adjacent first protrusions 96a.
  • the pixel definition layer in the pixel opening K is completely developed, and the pixel definition layer in the first recessed portion 96b is partially developed, so as to prevent the subsequently formed cathode and anode from short circuit through the first recessed portion 96b.
  • the first concave portion 96b is a groove surrounding the pixel opening K, and the width d1 of the groove can be determined according to the resolution limit of the current exposure equipment.
  • the distance d2 between the grooves is 1/8-7/8 of the distance d3 between the edge of the opening area of the black matrix 71 formed subsequently and the edge of the pixel opening K formed by the pixel definition layer 96 .
  • the first recess 96b is a groove surrounding the pixel opening K
  • the width d1 of the groove is between 0.8 microns and 1.5 microns
  • the distance between adjacent grooves d2 is between 1 micron and 2 microns.
  • the first concave portion 96b includes an opening surrounding the pixel opening K, and the width d4 of the opening can be determined according to the resolution limit of the current exposure equipment.
  • the distance d5 between adjacent openings is between 1/8-7/8 of the distance d3 between the edge of the opening area of the subsequently formed black matrix 71 and the edge of the pixel opening K formed by the pixel definition layer 96 .
  • the width d4 of the opening may be between 0.5 microns and 1.8 microns.
  • a plurality of openings form a plurality of ring structure units 96c, each ring structure unit 96c includes N ring structures arranged around the pixel opening K and parallel to each other, the innermost layer
  • the annular structure includes a plurality of first openings 96b1, the first openings 96b1 are adjacent to the pixel opening K, and saw-tooth-shaped protrusions 96a1 are formed between the plurality of first openings 96b1, and N is a natural number greater than 1.
  • the width d6 of the serrated protrusion 96a1 can be determined according to the resolution limit of the current exposure equipment.
  • the distance d7 between adjacent serrated protrusions 96a1 is between 1/8-7/8 of the distance between the edge of the opening area of the black matrix 71 formed subsequently and the edge of the pixel opening K formed by the pixel definition layer 96 .
  • the width d6 of the serrated protrusion 96a1 is between 0.8 ⁇ m and 1.5 ⁇ m.
  • N is between 1 and 50.
  • N may be 3.
  • the width of the opening is set between 0.5 micron and 1.8 micron, which can ensure that the designed opening is not exposed when the pixel opening is exposed, so that the pixel definition layer 96 can form a concave-convex shape. Therefore, when depositing the cathode 53 later, the cathode 53 can also be made to form an uneven morphology, and thus a scattering cathode surface can also be formed.
  • the organic light-emitting layer 52 and a cathode 53 are sequentially formed on the aforementioned patterned substrate, as shown in FIG. 14 .
  • the organic light-emitting layer 52 includes a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer, and is formed in the pixel opening to realize the connection between the organic light-emitting layer 52 and the anode 51 . Since the anode 51 is connected to the first drain electrode 42 of the first transistor, light emission control of the organic light emitting layer 52 is realized.
  • the cathode 53 is connected to the organic light emitting layer 52 .
  • the organic light-emitting layer 52 and the cathode 53 can also respectively form undulating topography, thus forming a scattering cathode surface.
  • the cathode 53 may be a unitary structure communicated together.
  • the light-emitting structure layer pattern is prepared on the driving circuit layer.
  • the light-emitting structure layer includes an anode, a pixel definition layer, a spacer layer, an organic light-emitting layer and a cathode.
  • the organic light-emitting layer is connected to the anode and the cathode respectively.
  • encapsulation layer 98 pattern on the base that forms aforementioned pattern, as shown in Figure 15, encapsulation layer 98 can adopt the lamination structure of inorganic material/organic material/inorganic material, and organic material layer is arranged on two inorganic material layers between.
  • forming the pattern of the encapsulation layer 98 may include: first depositing a first inorganic thin film by means of plasma enhanced chemical vapor deposition (PECVD) using an open mask to form the first encapsulation layer. Subsequently, the inkjet printing process is used to inkjet print the organic material on the first encapsulation layer, and after curing to form a film, the second encapsulation layer is formed. Subsequently, a second inorganic thin film is deposited by using an open mask to form a third encapsulation layer, and the first encapsulation layer, the second encapsulation layer and the third encapsulation layer form the encapsulation layer.
  • PECVD plasma enhanced chemical vapor deposition
  • the first encapsulation layer and the third encapsulation layer may use any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), which may be Single layer, multi-layer or composite layer
  • the second encapsulation layer can use resin material to form a laminated structure of inorganic material/organic material/inorganic material
  • the organic material layer is set between the two inorganic material layers, which can ensure that the external water vapor cannot Enter the light-emitting structure layer.
  • the touch structure layer 103 may include a buffer layer stacked on the encapsulation layer 98, a first touch electrode layer (ie, a bridge layer), a touch insulating layer (TLD), a second touch
  • a first touch electrode layer ie, a bridge layer
  • a touch insulating layer TLD
  • the control electrode layer and the protective layer multiple first touch electrodes, multiple second touch electrodes and multiple first connection parts can be arranged on the second touch electrode layer in the same layer, and can be formed by the same patterning process
  • the first touch electrodes and the first connection part may be an integral structure connected to each other.
  • the second connection part can be arranged on the first touch electrode layer, and the adjacent second touch electrodes are connected to each other through via holes, and a touch insulating layer is arranged between the second touch electrode layer and the first touch electrode layer .
  • a plurality of first touch electrodes, a plurality of second touch electrodes and a plurality of second connecting parts can be arranged on the second touch electrode layer in the same layer, and the second touch electrodes and the second
  • the connection part may be an integral structure connected to each other, and the first connection part may be disposed on the first touch electrode layer, and connect adjacent first touch electrodes to each other through via holes.
  • the color filter layer includes a black matrix 71 and a color filter 72 arranged on the same layer, the black matrix 71 has a plurality of opening areas arranged in a matrix, and the color filter The sheet 72 is filled in the opening area, and the color filter 72 and the black matrix 71 at least partially include an overlapping area. In the overlapping area, the color filter 72 covers the black matrix 71, as shown in FIG. 17 .
  • forming the pattern of the color filter layer includes: first coating a polymer photoresist layer mixed with a black matrix material on the substrate forming the aforementioned pattern, and forming a black matrix 71 pattern after exposure and development; Then, coat the polymer photoresist layer mixed with the red pigment on the substrate forming the aforementioned pattern, and form the pattern of the red area after exposure and development; use the same method and steps to form the pattern of the green area and the blue area in turn graphics. Finally, color filters 72 of the three primary colors of red, green and blue arranged according to certain rules are formed.
  • the display substrate is peeled off from the glass carrier 1 through a peeling process, and then attached to the back of the display substrate (the surface of the flexible substrate 10 away from the film layer) by roller bonding
  • One layer of base film as shown in Figure 4.
  • the preparation of the display substrate shown in FIG. 4 of this embodiment is completed.
  • the display panel of this embodiment is described with a top emission structure, the solution of this embodiment is also applicable to a bottom emission structure or a double-sided emission structure, and is also applicable to a large-size or small-size display panel.
  • each display unit may include 3 or 4 sub-pixels.
  • the pixel driving circuit may be 5T1C or 7T1C.
  • other electrodes or leads may also be arranged in the film layer structure, which is not specifically limited in this disclosure.
  • the source-drain metal layer may also have a double-layer structure, that is, on a plane perpendicular to the display substrate, the display substrate includes a first insulating layer, an active layer, and a second insulating layer sequentially formed on the base.
  • the source-drain electrode layer at least includes an anode connection electrode, and the anode connection electrode is connected to the drain electrode of the first thin film transistor through the via hole on the first planar layer, and connected to the anode through the via hole on the second planar layer.
  • FIG 19. An optically improved color separation test model is shown in Figure 19.
  • the simulation results are shown in Figure 20a, Figure 20b and Table 1.
  • the simulation results are shown in Figure 21a, Figure 21b and Table 2.
  • the preparation process of the display substrate in the embodiment of the present disclosure can be realized by using the existing mature preparation equipment, the improvement of the existing process is small, and the dark state color separation can be improved without adding procedures and steps, and it can be well integrated with the existing
  • the preparation process is compatible, the process is simple to implement, easy to implement, high in production efficiency, low in production cost and high in yield.
  • the display substrate of the present disclosure can be applied in a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display ( QDLED), etc., the disclosure is not limited here.
  • a pixel driving circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display ( QDLED), etc.
  • Exemplary embodiments of the present disclosure also provide a method for manufacturing a display substrate, which may include a plurality of sub-pixels; the method may include:
  • a first electrode is formed on a side of the insulating film layer away from the substrate, and an orthographic projection of the concave-convex structure on the substrate and an orthographic projection of the first electrode on the substrate include an overlapping area.
  • Embodiments of the present disclosure also provide a display device, including the display panel of the foregoing embodiments.
  • the display device can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板及其制备方法、显示装置，所述显示基板包括基底(10)、设置在所述基底(10)上的至少一个绝缘膜层以及设置在所述绝缘膜层远离所述基底(10)一侧的第一电极；其中：至少一个所述绝缘膜层远离所述基底(10)的一侧设置有凹凸结构，所述凹凸结构在所述基底(10)上的正投影与所述第一电极在所述基底(10)上的正投影包含重叠区域。

Description

显示基板及其制备方法、显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有发光、超薄、广视角、高亮度、高对比度、较低耗电、极高反应速度等优点。依据驱动方式的不同，OLED可分为无源矩阵驱动(Passive Matrix，简称PM)型和有源矩阵驱动(Active Matrix，简称AM)型两种，其中AMOLED是电流驱动器件，采用独立的薄膜晶体管(Thin Film Transistor，简称TFT)控制每个子像素，每个子像素皆可以连续且独立的驱动发光。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板，包括：基底、设置在所述基底上的至少一个绝缘膜层以及设置在所述绝缘膜层远离所述基底一侧的第一电极；其中：至少一个所述绝缘膜层远离所述基底的一侧设置有凹凸结构，所述凹凸结构在所述基底上的正投影与所述第一电极在所述基底上的正投影包含重叠区域。
在示例性实施例中，所述显示基板包括：依次形成在所述基底上的平坦层、发光结构层、封装层和彩膜层，所述发光结构层包括像素定义层、阳极、阴极以及位于所述阳极和所述阴极之间的有机发光层，所述像素定义层包括多个像素开口，所述像素开口暴露出至少部分所述阳极；所述阴极覆盖所述像素定义层；
所述彩膜层包括间隔设置的黑矩阵和彩色滤光片，所述黑矩阵具有呈矩阵排列的多个开口区域，所述彩色滤光片至少部分填充于所述开口区域内，所述彩色滤光片与所述黑矩阵至少包括部分交叠区域，在所述交叠区域，所述彩色滤光片覆盖所述黑矩阵。
在示例性实施例中，至少一个所述绝缘膜层包括：所述像素定义层，所述第一电极包括：所述阴极。
在示例性实施例中，所述像素定义层包括多个第一凸起部，相邻的所述第一凸起部之间形成有第一凹陷部。
在示例性实施例中，所述第一凹陷部为环绕所述像素开口的凹槽，相邻所述凹槽之间的距离为所述黑矩阵的开口区域的边缘与所述像素定义层形成的像素开口的边缘之间的距离的1/8到7/8之间。
在示例性实施例中，相邻所述凹槽之间的距离在1微米至2微米之间。
在示例性实施例中，所述凹槽的宽度在0.8微米至1.5微米之间。
在示例性实施例中，所述第一凹陷部为环绕所述像素开口的开孔，所述开孔的宽度在0.5微米至1.8微米之间。
在示例性实施例中，多个所述开孔组成多个环形结构单元，至少一个环形结构单元包括N个围绕所述像素开口设置且相互平行的环形结构，最内层环形结构包括多个第一开孔，所述第一开孔与所述像素开口邻接，N为大于1的自然数。
在示例性实施例中，多个所述第一开孔之间形成锯齿状凸起，所述锯齿状凸起的宽度在0.8微米至1.5um之间。
在示例性实施例中，N为1至50之间的自然数。
在示例性实施例中，至少一个所述绝缘膜层包括：所述平坦层，所述第一电极包括：所述阳极。
在示例性实施例中，所述平坦层包括多个第二凸起部，相邻的所述第二凸起部之间形成有第二凹陷部。
在示例性实施例中，所述第二凸起部为锯齿形。
在示例性实施例中，所述第二凸起部与所述第二凹陷部之间的段差为所述平坦层的厚度的1/8到7/8之间。
在示例性实施例中，所述第二凸起部与所述第二凹陷部之间的段差在0.2微米至0.8微米之间。
在示例性实施例中，至少一个所述绝缘膜层包括所述像素定义层和所述平坦层，所述第一电极包括所述阴极和所述阳极；所述像素定义层远离所述基底的一侧设置有第一凹凸结构，所述第一凹凸结构在所述基底上的正投影与所述阴极在所述基底上的正投影包含重叠区域；所述平坦层远离所述基底的一侧设置有第二凹凸结构，所述第二凹凸结构在所述基底上的正投影与所述阳极在所述基底上的正投影包含重叠区域。
在示例性实施例中，所述显示基板还包括设置在所述封装层和所述彩膜层之间的触控结构层，所述触控结构层包括多个触控电极，所述黑矩阵在所述基底上的正投影包含所述触控电极在所述基底上的正投影。
本公开实施例还提供了一种显示装置，包括如前任一所述的显示基板。
本公开实施例提供了一种显示基板的制备方法，包括：在基底上形成至少一个绝缘膜层，至少一个所述绝缘膜层远离所述基底的一侧设置有凹凸结构；在所述绝缘膜层远离所述基底的一侧形成第一电极，所述凹凸结构在所述基底上的正投影与所述第一电极在所述基底上的正投影包含重叠区域。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3a和图3b为两种色分离现象示意图；
图4为本公开实施例的一种显示基板的结构示意图；
图5a和图5b为本公开色分离改善后的结果示意图；
图6为本公开实施例一种制备柔性基底图案后的显示基板结构示意图；
图7为本公开实施例一种制备驱动结构层图案后的显示基板结构示意图；
图8为本公开实施例一种形成平坦层图案后的显示基板结构示意图；
图9为本公开实施例一种形成阳极图案后的显示基板结构示意图；
图10为本公开实施例一种形成像素定义层图案后的显示基板结构示意图；
图11和图12为本公开实施例两种像素定义层的结构示意图；
图13为本公开实施例一种形成隔垫物层图案后的显示基板结构示意图；
图14为本公开实施例一种形成阴极图案后的显示基板结构示意图；
图15为本公开实施例一种形成封装层图案后的显示基板结构示意图；
图16为本公开实施例一种形成触控结构层图案后的显示基板结构示意图；
图17为本公开实施例一种形成彩膜层图案后的显示基板结构示意图；
图18为本公开实施例一种贴合盖板后的显示基板结构示意图；
图19为本公开实施例一种光学改善色分离测试模型结构示意图；
图20a和图20b为图19中的入射光沿着彩色滤光片长轴方向时的仿真结果示意图；
图21a和图21b为图19中的入射光沿着彩色滤光片短轴方向时的仿真结果示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电 极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据信号驱动器、扫描信号驱动器和像素阵列，时序控制器分别与数据信号驱动器和扫描信号驱动器连接，数据信号驱动器分别与多个数据信号线(D1到Dn)连接，扫描信号驱动器分别与多个扫描信号线(S1到Sm)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一 个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个扫描信号线、至少一个数据信号线和像素驱动电路。在一些示例性实施例中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2、出射第三颜色光线的第三子像素P3和出射第四颜色光线的第四子像素P4，四个子像素可以均包括电路单元和发光器件，电路单元可以包括扫描信号线、数据信号线和像素驱动电路，像素驱动电路分别与扫描信号线和数据信号线连接，像素驱动电路被配置为在扫描信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在一些示例性实施例中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射绿色光线的绿色子像素(G)，第三子像素P3可以是出射白色光线的白色子像素(W)，第四子像素P4可以是出射蓝色光线的蓝色子像素(B)。
在一些示例性实施例中，子像素的形状可以是矩形状、菱形、五边形或六边形。在一种示例性实施方式中，四个子像素可以采用水平并列方式排列，形成RWBG像素排布。在另一种示例性实施方式中，四个子像素可以采用正方形(Square)、钻石形(Diamond)或竖直并列等方式排列，本公开在此不做限定。
在另一些示例性实施方式中，多个像素单元P的至少一个可以包括一个出射红色光线的红色(R)子像素、一个出射绿色光线的绿色(G)子像素和一个出射蓝色光线的蓝色(B)子像素，或者可以包括一个出射红色光线的红色子像素、两个出射绿色光线的绿色子像素和一个出射蓝色光线的蓝色子像素，本公开在此不做限定。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
在一些示例性实施例中，水平方向依次设置的多个子像素称为像素行，竖直方向依次设置的多个子像素称为像素列，多个像素行和多个像素列构成阵列排布的像素阵列。
目前，OLED面板相对于液晶显示屏(Liquid Crystal Display，LCD)最显著的特点是全固态显示(不含液晶)，在弯曲甚至折叠能力上有明显优势。为了提高OLED产品弯折性能，需要持续减薄模组厚度，而防反射的圆偏光片和贴合的触控模组在整体厚度中占有较大比例。为了解决该问题，人们采用了将触控结构和彩色滤光片结构整合在OLED封装层上的方法，即薄膜封装层上的触控结构(Touch on TFE，TOT)技术和色阻结构(CF on Encapsulation，COE)技术，大幅降低了模组厚度。但COE技术会存在暗态色分离现象，即熄屏状态时，在光源照射下会看到明显反射光颜色分离的现象，影响用户对绝对黑画面的体验，如图3a和图3b所示。
经过分析验证发现，出现暗态色分离现象的主要原因是去掉了圆偏光片后，环境光经红绿蓝像素反射以及阴极和阳极对光的定向反射后被不同程度的改变了强度分布。一些技术通过在涂覆保护层(OC)中参杂散射粒子来对 光进行散射，以改善色分离现象，但是散射粒子的引入会降低光透过率，进而失去COE高透过率的优势。
本公开实施例提供了一种显示基板，包括：基底、设置在基底上的至少一个绝缘膜层以及设置在绝缘膜层远离基底一侧的第一电极；其中：至少一个绝缘膜层远离基底的一侧设置有凹凸结构，该凹凸结构在基底上的正投影与第一电极在基底上的正投影包含重叠区域。
本公开实施例提供的显示基板，通过将与第一电极相对位置的至少一个绝缘膜层进行处理，形成凹凸结构，干扰环境光反射的路径，破坏环境光的出射，改善了色分离现象，且本公开的显示基板制备过程简单，生产效率高，具有生产成本低和良品率高等优势，具有良好的应用前景。
图4为本公开实施例一种显示基板的剖面结构示意图，如图4所示，本公开实施例的显示基板包括：基底以及依次形成在基底上的平坦层95和发光结构层，发光结构层包括阳极51；至少一个绝缘膜层包括：平坦层95，第一电极包括：阳极51；
平坦层95远离基底的一侧设置有第二凹凸结构，第二凹凸结构在基底上的正投影与阳极51在基底上的正投影包含重叠区域。
本实施例所提供的显示基板，通过将与阳极51正对位置的平坦层95进行平缓起伏处理，使得阳极51形成一定的起伏波动的形貌，即形成了漫反射阳极，干扰环境光反射的路径，破坏环境光的出射，改善了色分离现象。如图5a和图5b所示，本公开实施例的显示基板，色分离现象大幅减轻，在暗态强光照射下可以保持较好的黑色，经用户体验测试有明显的效果。
在一些示例性实施例中，第二凹凸结构包括多个第二凸起部，相邻的第二凸起部之间形成有第二凹陷部。
在一些示例性实施例中，第二凸起部可以为锯齿形。
在一些示例性实施例中，第二凸起部与第二凹陷部之间的段差可以在0.2微米至0.8微米之间。
在一些示例性实施例中，发光结构层还包括像素定义层96，像素定义层 96包括多个像素开口，像素开口暴露出阳极51；像素定义层96远离基底的一侧设置有第一凹凸结构。
本实施例中，至少一个绝缘膜层包括：像素定义层96，第一电极包括：阴极，通过对像素定义层96也进行平缓起伏处理，使得像素定义层96形成凹凸起伏的形貌，从而在沉积阴极时也可以使得阴极形成凹凸不平的形貌，即形成了散射阴极面，干扰环境光反射的路径，破坏环境光的出射，进一步改善了色分离现象。
在一些示例性实施例中，第一凹凸结构包括多个第一凸起部，相邻的第一凸起部之间形成有第一凹陷部。
在一些示例性实施例中，第一凹陷部为环绕像素开口的凹槽，凹槽的宽度在0.8微米至1.5微米之间，相邻凹槽之间的距离在1微米至2微米之间。
在一些示例性实施例中，相邻凹槽之间的距离为黑矩阵的开口区域的边缘与像素定义层形成的像素开口的边缘之间的距离的1/8到7/8之间。
在另一些示例性实施例中，第一凹陷部为环绕像素开口的开孔，开孔的宽度在0.5微米至1.8微米之间。
在一些示例性实施例中，多个开孔组成多个环形结构单元，每个环形结构单元包括N个围绕像素开口设置且相互平行的环形结构，最内层环形结构包括多个第一开孔，第一开孔与像素开口邻接，多个第一开孔之间形成锯齿状凸起，每个锯齿状凸起的宽度在0.8微米至1.5um之间，N为大于1的自然数。
在一些示例性实施例中，N为1至50之间的自然数。
在一些示例性实施例中，N为3。
在一些示例性实施例中，发光结构层还包括有机发光层52和阴极53，其中，有机发光层52设置在阳极51上；阴极53设置在有机发光层52上，有机发光层52与阳极51连接，阴极53与有机发光层52连接，有机发光层52在阳极51和阴极53驱动下出射相应颜色的光线。有机发光层52和阴极53与第一凹凸结构和/或第二凹凸结构相对应的位置为非平坦表面。
在一些示例性实施例中，有机发光层52可以包括叠设的空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、发光层(EML)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在一些示例性实施例中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层可以是连接在一起的共通层，所有子像素的发光层可以是连接在一起的共通层，或者可以是相互隔离的，相邻子像素的发光层可以有少量的交叠。在一些可能的实现方式中，显示基板可以包括其它膜层，本公开在此不做限定。
在一些示例性实施例中，显示基板还包括设置在发光结构层远离基底一侧的封装层98。封装层98可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在一些示例性实施例中，基底包括基底10、设置在基底10上的驱动结构层102。基底10可以是柔性基底，或者可以是刚性基底。每个子像素的驱动结构层102可以包括由多个晶体管和存储电容构成的像素驱动电路。阳极51通过平坦层95上开设的过孔与驱动结构层中的第一薄膜晶体管连接。
在一些示例性实施例中，如图4所示，显示基板还包括设置在封装层98远离基底一侧的彩膜层，彩膜层包括间隔设置的黑矩阵71和彩色滤光片72，黑矩阵71具有呈矩阵排列的多个开口区域，彩色滤光片72填充于开口区域内。在示例性实施例中，彩色滤光片72与黑矩阵71至少包括部分交叠区域。在黑矩阵71和彩色滤光片72的交叠区域，彩色滤光片72覆盖黑矩阵71。
在一些示例性实施例中，显示基板还包括设置在封装层98和彩膜层之间的触控结构层103，触控结构层103可以包括多个触控电极，黑矩阵71在基底上的正投影包含触控电极在基底上的正投影。
下面通过本实施例显示面板的制备过程进一步说明本实施例的技术方案。其中，本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模 曝光、显影、刻蚀和剥离光刻胶等处理。本实施例中所说的“光刻工艺”包括涂覆膜层、掩模曝光、显影等处理，是相关技术中成熟的制备工艺。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。当在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
在一些示例性实施例中，图4的显示基板的制备过程可以包括如下步骤：
(1)在玻璃载板1上制备柔性基底10。
本公开实施例的一个示例中，柔性基底10可以采用两层柔性层结构，柔性基底10包括在玻璃载板1上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一柔性材料层、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一无机材料层、第二无机材料层也称之为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。
在一些示例性实施例中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，柔性基底10的制备过程可以包括：先在玻璃载板1上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2) 层，完成柔性基底10的制备，如图6所示。
在其他示例中，柔性基底10可以采用一层柔性层结构，比如，柔性基底10包括叠设的柔性(PI)层和阻挡(Barrier)层。
(2)在柔性基底10上制备驱动结构层102图案。驱动结构层包括多条栅线和多条数据线，多条栅线和多条数据线垂直交叉限定出多个矩阵排布的像素单元，每个像素单元包括至少3个子像素，至少一个子像素包括至少一个第一薄膜晶体管(Thin Film Transistor，TFT)(在一种可能的实施例中，在屏下摄像头区域，至少一个子像素不设置TFT，只设置阳极)。第一薄膜晶体管可以是底栅结构，也可以是顶栅结构，可以是非晶硅(a-Si)薄膜晶体管，也可以是低温多晶硅(LTPS)薄膜晶体管或氧化物(Oxide)薄膜晶体管，在此不做限定。本实施例中，一个像素单元包括3个子像素，分别为红色子像素R、绿色子像素G和蓝色子像素B。当然，本实施例方案也适用于一个像素单元包括4个子像素(红色子像素R、绿色子像素G、蓝色子像素B和白色子像素W)情形。在一些示例性实施例中，驱动结构层的制备过程可以包括：
在柔性基底10上依次沉积第一绝缘薄膜和有源层薄膜，通过构图工艺对有源层薄膜进行构图，形成覆盖整个柔性基底10的第一绝缘层91，以及设置在第一绝缘层91上的有源层图案，有源层至少包括第一有源层11。在一示例性实施例中，第一绝缘层91称之为缓冲(Buffer)层，用于提高基底的抗水氧能力。
随后，依次沉积第二绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖有源层的第二绝缘层92，以及设置在第二绝缘层92上的第一栅电极层图案，第一栅电极层至少包括第一栅电极21和第一电容电极22、多条栅线(未示出)和多条栅引线(未示出)。在一示例性实施例中，第二绝缘层92称之为第一栅绝缘(GI1)层。
随后，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一栅电极层的第三绝缘层93，以及设置在第三绝缘层93上的第二栅电极层图案，第二栅电极层至少包括第二电容电极 31和第二栅引线(未示出)，第二电容电极31的位置与第一电容电极22的位置相对应。在一示例性实施例中，第三绝缘层93又称之为第二栅绝缘(GI2)层。
随后，沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成覆盖第二栅电极层的第四绝缘层94图案，第四绝缘层94上开设有多个第一过孔，多个第一过孔位置分别与第一有源层的两端位置相对应，多个第一过孔内的第四绝缘层94、第三绝缘层93和第二绝缘层92被刻蚀掉，分别暴露出第一有源层的表面。在一示例性实施例中，第四绝缘层94又称之为层间绝缘(ILD)层。
随后，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在第四绝缘层94上形成源漏金属层(SD)图案，源漏金属层至少包括第一源电极41、第一漏电极42、低压(VSS)线(未示出)、多条数据线(未示出)和多条数据引线(未示出)图案，第一源电极41和第一漏电极42分别通过第一过孔与第一有源层11的两端连接。在一示例性实施方式中，根据实际需要，源漏金属层还可以包括电源线(VDD)、补偿线和辅助阴极中的任意一种或多种。
至此，在柔性基底10上制备完成驱动结构层图案，如图7所示。第一有源层11、第一栅电极21、第一源电极41和第一漏电极42组成第一薄膜晶体管，第一电容电极22和第二电容电极31组成存储电容，多条栅引线和数据引线组成阵列基板栅极驱动(Gate Driver on Array，GOA)的驱动引线。
(3)在形成前述图案的柔性基底上涂覆第一平坦薄膜，通过构图工艺对第一平坦薄膜进行构图，形成覆盖整个柔性基底10的平坦(PLN)层95，如图8所示，平坦层95上设置有第二过孔V2，第二过孔V2内的平坦层95被刻蚀掉，暴露出第一薄膜晶体管的第一漏电极42的表面，平坦层95远离柔性基底10的一侧设置有第二凹凸结构951，第二凹凸结构951在柔性基底10上的正投影与后续形成的阳极51在柔性基底10上的正投影具有重叠区域，即在阳极51对应位置的平坦层95上形成起伏波动的形貌。
在一些示例性实施例中，第二凹凸结构951包括多个第二凸起部，相邻 的第二凸起部之间形成有第二凹陷部。
本实施例中，在对第一平坦薄膜进行构图时，掩膜版上的开口图形可以对应于第二凹凸结构951的第二凹陷部，由此，可以根据所需的第二凹凸结构951来设计掩膜版的开口图形的位置、形状以及布置方式，这样有利于简化显示基板的制造工序。
在一些示例性实施例中，第二凸起部可以为锯齿形。
在一些示例性实施例中，如图4所示，第二凸起部与第二凹陷部之间的段差h1可以为平坦层95的厚度h2的1/8到7/8之间。
在一些示例性实施例中，第二凸起部与第二凹陷部之间的段差h1可以为0.2微米至0.8微米。本实施例中，第二凸起部与第二凹陷部之间的段差指的是第二凸起部的最高点和第二凹陷部的最低点之间的高度差。
(4)在形成前述图案的基底上沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，形成阳极51图案，阳极51通过第二过孔V2与第一漏电极D连接。由于阳极51对应位置的平坦层95远离柔性基底的一侧具有起伏波动的形貌，因此，阳极51也可以形成起伏波动的形貌，也就可以形成漫反射阳极面。
在一些示例性实施例中，形成阳极51图案包括：在形成前述图案的基底上沉积第四金属薄膜，在第四金属薄膜上涂覆一层光刻胶，使用单色调掩膜版对光刻胶进行曝光，在阳极51所在位置形成未曝光区域，在其它位置形成完全曝光区域，显影去除完全曝光区域的光刻胶，随后刻蚀掉完全曝光区域第四金属薄膜，剥离光刻胶后形成阳极51图案，如图9所示。
由于本实施例显示面板为顶发射结构，因此阳极51为反射电极，可以采用具有高反射率的金属，如银Ag、金Au、钯Pd、铂Pt等，或这些金属的合金，或这些金属的复合层。实际实施时，还可以采用氧化铟锡ITO层和金属反射层的复合层结构，具有良好的导电性、高的反射率、良好的形态稳定性。
(5)在形成前述图案的基底上涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，形成像素定义(PDL)层96图案，如图10所示，像素定义层96 上开设有像素开口K，像素开口K内的像素定义薄膜被显影掉，暴露出至少部分阳极51的表面，像素定义层96远离柔性基底10的一侧设置有第一凹凸结构961。像素开口K和第一凹凸结构961可以通过灰阶掩模设计实现。
在一些示例性实施例中，第一凹凸结构961在柔性基底10上的正投影与像素开口K在柔性基底10上的正投影不重叠。
在一些示例性实施例中，第一凹凸结构961位于像素定义层96靠近后续形成的有机发光层52的一侧位置，这样可以在像素定义层96接近发光区域的边缘位置形成起伏波动的形貌。
在一些示例性实施例中，如图10所示，第一凹凸结构961包括多个第一凸起部96a，相邻的第一凸起部96a之间形成有第一凹陷部96b。本公开实施例中，像素开口K内的像素定义层被全部显影掉，第一凹陷部96b内的像素定义层被部分显影掉，防止后续形成的阴极与阳极通过第一凹陷部96b发生短路。
在一些示例性实施例中，结合图4和图11所示，第一凹陷部96b为环绕像素开口K的凹槽，凹槽的宽度d1可以根据目前曝光设备的分辨率极限决定，相邻的凹槽之间的距离d2为后续形成的黑矩阵71的开口区域的边缘与像素定义层96形成的像素开口K的边缘之间的距离d3的1/8～7/8之间。
在一些示例性实施例中，如图11所示，第一凹陷部96b为环绕像素开口K的凹槽，凹槽的宽度d1在0.8微米至1.5微米之间，相邻凹槽之间的距离d2为1微米至2微米之间。
在另一些示例性实施例中，结合图4和图12所示，第一凹陷部96b包括环绕像素开口K的开孔，开孔的宽度d4可以根据目前曝光设备的分辨率极限决定。相邻开孔之间的距离d5为后续形成的黑矩阵71的开口区域的边缘与像素定义层96形成的像素开口K的边缘之间的距离d3的1/8～7/8之间。
示例性的，开孔的宽度d4可以在0.5微米至1.8微米之间。
在一些示例性实施例中，如图12所示，多个开孔组成多个环形结构单元96c，每个环形结构单元96c包括N个围绕像素开口K设置且相互平行的环形结构，最内层环形结构包括多个第一开孔96b1，第一开孔96b1与像素 开口K邻接，多个第一开孔96b1之间形成锯齿状凸起96a1，N为大于1的自然数。
在些示例性实施例中，如图12所示，锯齿状凸起96a1的宽度d6可以根据目前曝光设备的分辨率极限决定。相邻锯齿状凸起96a1之间的距离d7为后续形成的黑矩阵71的开口区域的边缘与像素定义层96形成的像素开口K的边缘之间的距离的1/8～7/8之间。
示例性的，锯齿状凸起96a1的宽度d6在0.8微米至1.5um之间。
在一些示例性实施例中，N在1至50之间。示例性的，N可以为3。
本实施例中，开孔的宽度设置在0.5微米至1.8微米之间，可以保证在像素开口曝开的同时而所设计的开孔曝不透，这样可以使得像素定义层96形成凹凸起伏的形貌，从而后续在沉积阴极53时也可以使得阴极53形成凹凸不平的形貌，也就可以形成散射阴极面。
(6)在形成前述图案的基底上涂覆有机材料薄膜，通过掩膜、曝光、显影工艺，形成隔垫物(PS)层97图案，如图13所示。
(7)在形成前述图案的基底上依次形成有机发光层52和阴极53，如图14所示。有机发光层52包括叠设的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，形成在像素开口内，实现有机发光层52与阳极51连接。由于阳极51与第一晶体管的第一漏电极42连接，因而实现了有机发光层52的发光控制。阴极53与有机发光层52连接。由于阳极51和像素定义层96均具有起伏波动的形貌，因此，有机发光层52和阴极53也可以分别形成起伏波动的形貌，也就可以形成散射阴极面。在示例性实施方式中，阴极53可以是连通在一起的整体结构。
至此，在驱动电路层上制备完成发光结构层图案，发光结构层包括阳极、像素定义层、隔垫物层、有机发光层和阴极，有机发光层分别与阳极和阴极连接。
(8)在形成前述图案的基底上形成封装层98图案，如图15所示，封装层98可以采用无机材料/有机材料/无机材料的叠层结构，有机材料层设置在两个无机材料层之间。
在一些示例性实施例中，形成封装层98图案可以包括：先利用开放式掩膜板采用等离子体增强化学气相沉积(PECVD)方式沉积第一无机薄膜，形成第一封装层。随后，利用喷墨打印工艺在第一封装层上喷墨打印有机材料，固化成膜后，形成第二封装层。随后，利用开放式掩膜板沉积第二无机薄膜，形成第三封装层，第一封装层、第二封装层和第三封装层组成封装层。在一些示例性实施例中，第一封装层和第三封装层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层，第二封装层可以采用树脂材料，形成无机材料/有机材料/无机材料的叠层结构，有机材料层设置在两个无机材料层之间，可以保证外界水汽无法进入发光结构层。
(9)在形成前述图案的基底上形成触控结构层103图案，如图16所示。
在一些示例性实施例中，触控结构层103可以包括叠层设置在封装层98上的缓冲层、第一触控电极层(即桥接层)、触控绝缘层(TLD)、第二触控电极层和保护层，多个第一触控电极、多个第二触控电极和多个第一连接部可以同层设置在第二触控电极层，并且可以通过同一次构图工艺形成，第一触控电极和第一连接部可以为相互连接的一体结构。第二连接部可以设置在第一触控电极层，通过过孔使相邻的第二触控电极相互连接，第二触控电极层与第一触控电极层之间设置有触控绝缘层。
在一些可能的实现方式中，多个第一触控电极、多个第二触控电极和多个第二连接部可以同层设置在第二触控电极层，第二触控电极和第二连接部可以为相互连接的一体结构，第一连接部可以设置在第一触控电极层，通过过孔使相邻的第一触控电极相互连接。
(10)在形成前述图案的基底上形成彩膜层图案，彩膜层包括同层设置的黑矩阵71和彩色滤光片72，黑矩阵71具有呈矩阵排列的多个开口区域，彩色滤光片72填充于开口区域内，彩色滤光片72与黑矩阵71至少包括部分交叠区域，在交叠区域，彩色滤光片72覆盖黑矩阵71，如图17所示。
在一些示例性实施例中，形成彩色滤光层图案包括：首先在形成前述图案的基底上涂覆混合了黑矩阵材料的高分子光刻胶层，经过曝光、显影，形 成黑矩阵71图形；然后，在形成前述图案的基底上涂覆混合了红色颜料的高分子光刻胶层，经过曝光、显影，形成红色区域的图形；采用相同的方法和步骤依次形成绿色区域的图形以及蓝色区域的图形。最终形成按照一定规则排列的红、绿、蓝三原色的彩色滤光片72。
(11)在形成前述图案的基底上进行薄膜封装工艺，形成涂覆保护层99图案；在形成涂覆保护层99图案的基底上涂覆光学胶100，在光学胶100上贴合盖板101，如图18所示。
(12)在制备完成上述膜层结构后，通过剥离工艺将显示基板从玻璃载板1上剥离，然后采用滚轮贴合方式在显示基板背面(柔性基底10远离膜层的一侧表面)贴附一层底膜，如图4所示。
通过上述过程，即完成本实施例图4所示的显示基板的制备。虽然本实施例的显示面板以顶发射结构进行了说明，但本实施例方案同样适用于底发射结构或双面发射结构，且同样适用于大尺寸或小尺寸显示面板。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，每个显示单元可以包括3个或4个子像素。又如，像素驱动电路可以是5T1C或7T1C。再如，膜层结构中还可以设置其它电极或引线，本公开在此不做具体的限定。在示例性实施例中，源漏金属层也可以为双层结构，即，在垂直于显示基板的平面上，显示基板包括依次形成在基底上的第一绝缘层、有源层、第二绝缘层、第一栅电极层、第三绝缘层、第二栅电极层、第四绝缘层、第一源漏电极层、第一平坦层、第二源漏电极层和第二平坦层，第二源漏电极层至少包括阳极连接电极，阳极连接电极通过第一平坦层上的过孔与第一薄膜晶体管的漏电极连接，并通过第二平坦层上的过孔与阳极连接。
通过以上描述的显示基板的结构和制备流程可以看出，本公开所提供的显示基板，通过将与阳极正对的平坦层进行平缓起伏处理，使得阳极形成具有一定的起伏波动的形貌，即形成了漫反射阳极；同时，通过对像素定义层也进行平缓起伏处理，使得像素定义层形成凹凸起伏的形貌，从而在沉积阴极时也可以使得阴极形成凹凸不平的形貌，即形成了散射阴极面，这样在熄 屏状态下可以对外界环境光进入屏幕内时，散射阴阳极对光形成散射，破坏环境光出射方向，改善色分离现象，实现较好的熄屏效果，避免了在涂覆保护层中掺杂散射粒子会降低透过率的问题，无成本增加，且可以保持COE高透过率的优势，可应对未来5G及低功耗柔性产品需求。
一种光学改善色分离测试模型如图19所示，当入射光沿着彩色滤光片(CF)长轴方向时，仿真结果如图20a、图20b和表1所示，当入射光沿着彩色滤光片(CF)短轴方向时，仿真结果如图21a、图21b和表2所示。
Figure PCTCN2021126477-appb-000001
表1
Figure PCTCN2021126477-appb-000002
表2
本公开实施例的显示基板的制备工艺利用现有成熟的制备设备即可实现，对现有工艺改进较小，不需要增加工序和步骤既可以改善暗态色分离，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开示例性实施例还提供了一种显示基板的制备方法，显示基板可以包括多个子像素；所述制备方法可以包括：
在基底上形成至少一个绝缘膜层，至少一个所述绝缘膜层远离所述基底的一侧设置有凹凸结构；
在所述绝缘膜层远离所述基底的一侧形成第一电极，所述凹凸结构在所述基底上的正投影与所述第一电极在所述基底上的正投影包含重叠区域。
本公开实施例还提供了一种显示装置，包括前述实施例的显示面板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示基板，包括：基底、设置在所述基底上的至少一个绝缘膜层以及设置在所述绝缘膜层远离所述基底一侧的第一电极；其中：
    至少一个所述绝缘膜层远离所述基底的一侧设置有凹凸结构，所述凹凸结构在所述基底上的正投影与所述第一电极在所述基底上的正投影包含重叠区域。
  2. 根据权利要求1所述的显示基板，包括：依次形成在所述基底上的平坦层、发光结构层、封装层和彩膜层，所述发光结构层包括像素定义层、阳极、阴极以及位于所述阳极和所述阴极之间的有机发光层，所述像素定义层包括多个像素开口，所述像素开口暴露出至少部分所述阳极；所述阴极覆盖所述像素定义层；
    所述彩膜层包括间隔设置的黑矩阵和彩色滤光片，所述黑矩阵具有呈矩阵排列的多个开口区域，所述彩色滤光片至少部分填充于所述开口区域内，所述彩色滤光片与所述黑矩阵至少包括部分交叠区域，在所述交叠区域，所述彩色滤光片覆盖所述黑矩阵。
  3. 根据权利要求2所述的显示基板，其中，至少一个所述绝缘膜层包括：所述像素定义层，所述第一电极包括：所述阴极。
  4. 根据权利要求3所述的显示基板，其中，所述像素定义层包括多个第一凸起部，相邻的所述第一凸起部之间形成有第一凹陷部。
  5. 根据权利要求4所述的显示基板，其中，所述第一凹陷部为环绕所述像素开口的凹槽，相邻所述凹槽之间的距离为所述黑矩阵的开口区域的边缘与所述像素定义层形成的像素开口的边缘之间的距离的1/8到7/8之间。
  6. 根据权利要求5所述的显示基板，其中，相邻所述凹槽之间的距离在1微米至2微米之间。
  7. 根据权利要求5所述的显示基板，其中，所述凹槽的宽度在0.8微米 至1.5微米之间。
  8. 根据权利要求4所述的显示基板，其中，所述第一凹陷部为环绕所述像素开口的开孔，所述开孔的宽度在0.5微米至1.8微米之间。
  9. 根据权利要求8所述的显示基板，其中，多个所述开孔组成多个环形结构单元，至少一个环形结构单元包括N个围绕所述像素开口设置且相互平行的环形结构，最内层环形结构包括多个第一开孔，所述第一开孔与所述像素开口邻接，N为大于1的自然数。
  10. 根据权利要求9所述的显示基板，其中，多个所述第一开孔之间形成锯齿状凸起，所述锯齿状凸起的宽度在0.8微米至1.5um之间。
  11. 根据权利要求10所述的显示基板，其中，N为1至50之间的自然数。
  12. 根据权利要求2所述的显示基板，其中，至少一个所述绝缘膜层包括：所述平坦层，所述第一电极包括：所述阳极。
  13. 根据权利要求12所述的显示基板，其中，所述平坦层包括多个第二凸起部，相邻的所述第二凸起部之间形成有第二凹陷部。
  14. 根据权利要求13所述的显示基板，其中，所述第二凸起部为锯齿形。
  15. 根据权利要求13所述的显示基板，其中，所述第二凸起部与所述第二凹陷部之间的段差为所述平坦层的厚度的1/8到7/8之间。
  16. 根据权利要求13所述的显示基板，其中，所述第二凸起部与所述第二凹陷部之间的段差在0.2微米至0.8微米之间。
  17. 根据权利要求2所述的显示基板，其中，
    至少一个所述绝缘膜层包括所述像素定义层和所述平坦层，所述第一电极包括所述阴极和所述阳极；
    所述像素定义层远离所述基底的一侧设置有第一凹凸结构，所述第一凹凸结构在所述基底上的正投影与所述阴极在所述基底上的正投影包含重叠区域；
    所述平坦层远离所述基底的一侧设置有第二凹凸结构，所述第二凹凸结构在所述基底上的正投影与所述阳极在所述基底上的正投影包含重叠区域。
  18. 根据权利要求6所述的显示基板，还包括设置在所述封装层和所述彩膜层之间的触控结构层，所述触控结构层包括多个触控电极，所述黑矩阵在所述基底上的正投影包含所述触控电极在所述基底上的正投影。
  19. 一种显示装置，包括权利要求1至18任一所述的显示基板。
  20. 一种显示基板的制备方法，包括：
    在基底上形成至少一个绝缘膜层，至少一个所述绝缘膜层远离所述基底的一侧设置有凹凸结构；
    在所述绝缘膜层远离所述基底的一侧形成第一电极，所述凹凸结构在所述基底上的正投影与所述第一电极在所述基底上的正投影包含重叠区域。
PCT/CN2021/126477 2021-10-26 2021-10-26 显示基板及其制备方法、显示装置 WO2023070328A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/CN2021/126477 WO2023070328A1 (zh) 2021-10-26 2021-10-26 显示基板及其制备方法、显示装置
EP21961704.0A EP4333063A4 (en) 2021-10-26 2021-10-26 DISPLAY SUBSTRATE AND PREPARATION METHOD THEREFOR, AND DISPLAY APPARATUS
CN202180003096.5A CN116569672A (zh) 2021-10-26 2021-10-26 显示基板及其制备方法、显示装置
CN202310881416.8A CN116669473A (zh) 2021-10-26 2021-10-26 显示基板及其制备方法、显示装置
US18/360,851 US20240023381A1 (en) 2021-10-26 2023-07-28 Display Substrate and Preparation Method Therefor, and Display Apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/126477 WO2023070328A1 (zh) 2021-10-26 2021-10-26 显示基板及其制备方法、显示装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/916,047 A-371-Of-International US20240215335A1 (en) 2021-10-26 Display Substrate and Preparation Method Therefor, and Display Apparatus
US18/360,851 Continuation US20240023381A1 (en) 2021-10-26 2023-07-28 Display Substrate and Preparation Method Therefor, and Display Apparatus

Publications (1)

Publication Number Publication Date
WO2023070328A1 true WO2023070328A1 (zh) 2023-05-04

Family

ID=86158996

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/126477 WO2023070328A1 (zh) 2021-10-26 2021-10-26 显示基板及其制备方法、显示装置

Country Status (4)

Country Link
US (1) US20240023381A1 (zh)
EP (1) EP4333063A4 (zh)
CN (2) CN116569672A (zh)
WO (1) WO2023070328A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160380037A1 (en) * 2015-06-25 2016-12-29 Japan Display Inc. Display device
US20180006273A1 (en) * 2016-06-30 2018-01-04 Lg Display Co., Ltd. Organic light-emitting display device
CN109524422A (zh) * 2019-01-07 2019-03-26 京东方科技集团股份有限公司 阵列基板及其制作方法、反射式显示面板和显示装置
CN109728197A (zh) * 2019-01-02 2019-05-07 京东方科技集团股份有限公司 显示基板及其制备方法和显示装置
CN111326636A (zh) * 2020-02-27 2020-06-23 京东方科技集团股份有限公司 一种阵列基板、其制作方法、显示面板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160380037A1 (en) * 2015-06-25 2016-12-29 Japan Display Inc. Display device
US20180006273A1 (en) * 2016-06-30 2018-01-04 Lg Display Co., Ltd. Organic light-emitting display device
CN109728197A (zh) * 2019-01-02 2019-05-07 京东方科技集团股份有限公司 显示基板及其制备方法和显示装置
CN109524422A (zh) * 2019-01-07 2019-03-26 京东方科技集团股份有限公司 阵列基板及其制作方法、反射式显示面板和显示装置
CN111326636A (zh) * 2020-02-27 2020-06-23 京东方科技集团股份有限公司 一种阵列基板、其制作方法、显示面板及显示装置

Also Published As

Publication number Publication date
CN116669473A (zh) 2023-08-29
EP4333063A1 (en) 2024-03-06
EP4333063A4 (en) 2024-06-26
CN116569672A (zh) 2023-08-08
US20240023381A1 (en) 2024-01-18

Similar Documents

Publication Publication Date Title
US11721122B2 (en) Display panel, manufacturing method thereof, and display apparatus
US11362148B2 (en) Quantum dot display panel and manufacturing method thereof
US11744130B2 (en) Display substrate and preparation method thereof, and display apparatus
KR20180071538A (ko) 표시 장치용 기판과 그를 포함하는 표시 장치
WO2022028183A1 (zh) 显示基板及其制备方法、显示装置
WO2021244643A1 (zh) 显示面板及其制备方法、显示装置
WO2021238465A1 (zh) 显示基板及其制备方法、显示装置
WO2021189482A1 (zh) 显示基板及其制备方法、显示装置
JP4271000B2 (ja) 異なるセルギャップを有する、半透過型液晶ディスプレイ装置
US7688419B2 (en) Thin film transistor array substrate structures and fabrication method thereof
KR102052432B1 (ko) 유기전계발광소자 및 그 제조방법
CN114420871A (zh) 显示面板及其制备方法、显示装置
WO2021254150A1 (zh) 显示基板及其制备方法、显示装置
WO2021238343A1 (zh) 显示面板及显示装置
CN112578585B (zh) 显示面板及其制备方法、显示装置
WO2021189484A9 (zh) 显示基板及其制作方法、显示装置
CN114846615A (zh) 显示面板及显示装置
WO2023070328A1 (zh) 显示基板及其制备方法、显示装置
US11974455B2 (en) Display device and method of manufacturing the same
US20220013603A1 (en) Display device and method of providing the same
WO2022133829A1 (zh) 显示基板及其制备方法、显示装置
US20240215335A1 (en) Display Substrate and Preparation Method Therefor, and Display Apparatus
WO2022227114A1 (zh) 显示装置以及显示装置的制造方法
WO2024045021A1 (zh) 显示面板及其制备方法、显示装置
WO2023178597A1 (zh) 显示基板及其驱动方法、制备方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202180003096.5

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 17916047

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21961704

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2021961704

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2021961704

Country of ref document: EP

Effective date: 20231128