WO2023065195A1 - 铁电器件、存储装置及电子设备 - Google Patents

铁电器件、存储装置及电子设备 Download PDF

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WO2023065195A1
WO2023065195A1 PCT/CN2021/125156 CN2021125156W WO2023065195A1 WO 2023065195 A1 WO2023065195 A1 WO 2023065195A1 CN 2021125156 W CN2021125156 W CN 2021125156W WO 2023065195 A1 WO2023065195 A1 WO 2023065195A1
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ferroelectric
metal oxide
variable
doped region
layer
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PCT/CN2021/125156
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English (en)
French (fr)
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谭万良
李宇星
李维谷
蔡佳林
吕杭炳
许俊豪
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华为技术有限公司
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Priority to PCT/CN2021/125156 priority Critical patent/WO2023065195A1/zh
Priority to CN202180099649.1A priority patent/CN117561804A/zh
Publication of WO2023065195A1 publication Critical patent/WO2023065195A1/zh

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  • the present application relates to the storage field, in particular to a ferroelectric device, a storage device and electronic equipment.
  • Ferroelectric random access memory has the advantages of low write power consumption and high read speed. It is one of the new memories that will replace dynamic random access memory (DRAM) in the future.
  • DRAM dynamic random access memory
  • FeRAM uses ferroelectric materials to replace the original dielectric in DRAM, and its polarization direction switches between two stable states ("0" and "1") to realize data writing and reading, even after the electric field is withdrawn. can still remain unchanged.
  • the FeRAM in the related art uses metal electrodes. During the process of making FeRAM (including the deposition of the metal electrodes and the process of subsequent annealing), the metal electrodes will take away the oxygen (oxygen scavenging) of the ferroelectric film, resulting in the durability of the FeRAM. Endurance declines.
  • Embodiments of the present application provide a ferroelectric device, a storage device, and electronic equipment, which can improve the durability of the ferroelectric device.
  • the present application provides a ferroelectric device, which includes a top electrode, a bottom electrode, and a ferroelectric layer between the top electrode and the bottom electrode.
  • the ferroelectric layer includes variable valence metal oxides and ferroelectric materials.
  • the variable valence metal oxide includes at least one of a variable valence transition metal oxide and a variable valence rare earth metal oxide.
  • the ferroelectric layer doped with variable valence metal oxide (MO X ) by using the ferroelectric layer doped with variable valence metal oxide (MO X ), based on The valence state change of metal elements in the ferroelectric material (M 2x+ /M 2(x- ⁇ )+ ), can generate oxygen atoms (O) and neutralize the oxygen vacancies (V O ) in the ferroelectric material, thereby regulating the concentration of oxygen in the ferroelectric layer.
  • the concentration of vacancies reduces the awakening and fatigue of the ferroelectric film, delays the breakdown of the device, and thus improves the durability of the ferroelectric device.
  • the rare earth metal element in the variable valence state rare earth metal oxide is at least one of Ce, Eu, and Nd.
  • the rare earth metal oxide with a variable valence state may be one or more of CeO 2 , Eu 2 O 3 , and Nd 2 O 3 .
  • the transition metal element in the transition metal oxide with a variable valence state is at least one of Mn, Fe, and Co.
  • the variable valence transition metal oxide may be one or more of MnO 2 , Fe 2 O 3 , and Co 2 O 3 .
  • the ferroelectric material includes a hafnium oxide-based ferroelectric material, so as to ensure the compatibility and size scalability of the ferroelectric device and CMOS (complementary metal oxide semiconductor, complementary metal oxide semiconductor) process.
  • CMOS complementary metal oxide semiconductor, complementary metal oxide semiconductor
  • the doping concentration of the variable valence state metal oxide in the ferroelectric material is periodically distributed.
  • atomic layer deposition can be used to alternately form multiple ferroelectric thin film layers and multiple metal oxide thin film layers with variable valence states; wherein, the thickness of the multiple ferroelectric thin film layers It can be basically the same, and the thicknesses of the multiple variable valence state metal oxide film layers can be basically the same, so that the variable valence state metal oxides are periodically and uniformly distributed in the thickness direction of the ferroelectric layer.
  • the ferroelectric layer includes a first doped region, an intrinsic region, and a second doped region arranged in sequence in the thickness direction.
  • the first doped region is located on the side of the intrinsic region close to the bottom electrode; the second doped region is located on the side of the intrinsic region near the top electrode; the intrinsic region includes ferroelectric material; the first doped region includes a variable valence metal Oxide and ferroelectric material; the second doped region includes variable valence metal oxide and ferroelectric material.
  • the doping concentration of the metal oxide in the variable valence state in the ferroelectric material is periodically distributed along the thickness direction of the ferroelectric layer.
  • atomic layer deposition may be used to alternately form a plurality of ferroelectric thin film layers with substantially uniform thicknesses and a plurality of variable-valence metal oxide thin film layers with substantially uniform thicknesses.
  • the doping concentration of the variable-valence metal oxide in the ferroelectric material gradually increases along a direction close to the bottom electrode.
  • atomic layer deposition may be used to alternately form a plurality of ferroelectric thin film layers and a plurality of variable valence metal oxide thin film layers on the surface of the bottom electrode.
  • the thickness of a plurality of ferroelectric thin film layers can be basically the same, along the direction close to the bottom electrode, the thickness of the ferroelectric thin film layer between two adjacent variable valence metal oxide thin film layers decreases gradually, so that The content of the ferroelectric material in the first doped region decreases gradually in the direction close to the bottom electrode, that is, the doping concentration of the variable-valence metal oxide gradually increases in the direction close to the bottom electrode.
  • the doping concentration of the metal oxide in the variable valence state in the ferroelectric material is periodically distributed along the thickness direction of the ferroelectric layer.
  • atomic layer deposition may be used to alternately form a plurality of ferroelectric thin film layers with substantially uniform thicknesses and a plurality of variable-valence metal oxide thin film layers with substantially uniform thicknesses.
  • the doping concentration of the metal oxide in the variable valence state in the ferroelectric material gradually increases along a direction close to the top electrode.
  • atomic layer deposition can be used to alternately form multiple ferroelectric thin film layers and multiple metal oxide thin film layers with variable valence states.
  • the thickness of a plurality of ferroelectric thin film layers can be basically the same, along the direction close to the top electrode, the thickness of the ferroelectric thin film layer between two adjacent variable valence state metal oxide thin film layers decreases gradually, so that The content of the ferroelectric material in the second doped region decreases gradually in the direction close to the top electrode, that is, the doping concentration of the variable-valence metal oxide gradually increases in the direction close to the top electrode.
  • An embodiment of the present application further provides a storage device, including a controller and a ferroelectric device as provided in any one of the foregoing possible implementation manners; the controller is connected to the ferroelectric device.
  • An embodiment of the present application further provides an electronic device, including a printed circuit board and a storage device provided in any one of the foregoing possible implementation manners; the storage device is connected to the printed circuit board.
  • FIG. 1 is a schematic structural diagram of a ferroelectric device provided in an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a storage device provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a storage unit provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a ferroelectric field effect transistor provided in an embodiment of the present application.
  • Fig. 5 is a ferroelectric dipole (upper) and ferroelectric phase (lower) transition schematic diagram of a ferroelectric device provided in the related art of the present application during original, awakening, fatigue, and breakdown;
  • FIG. 6 is a schematic structural diagram of a ferroelectric device provided in an embodiment of the present application.
  • Fig. 7 is the durability characterization curve of the HZO thin film and the HZCO thin film not doped with CeO2 ;
  • FIG. 8 is a schematic structural diagram of a ferroelectric device provided in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a ferroelectric device provided by an embodiment of the present application.
  • At least one (item) means one or more, and “multiple” means two or more.
  • “And/or” is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, “A and/or B” can mean: only A exists, only B exists, and A and B exist at the same time , where A and B can be singular or plural.
  • the character “/” generally indicates that the contextual objects are an “or” relationship.
  • At least one of the following” or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • At least one item (piece) of a, b or c can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c ", where a, b, c can be single or multiple.
  • An embodiment of the present application provides an electronic device, which includes a printed circuit board (printed circuit board, PCB) and a ferroelectric device connected to the printed circuit board.
  • the electronic device may be electronic products such as a mobile phone, a tablet computer, a notebook, a vehicle computer, a smart watch, and a smart bracelet.
  • the ferroelectric device includes: a stacked structure 01 formed by a bottom electrode 1 , a ferroelectric layer 3 , and a top electrode 2 .
  • the stack structure 01 may be a metal electrode-ferroelectric film-metal electrode (metal ferroelectrics metal, MFM) structure, but it is not limited thereto.
  • MFM metal ferroelectrics metal
  • the bottom electrode 1 and the top electrode 2 are also Materials other than metals, such as semiconductors, can be used.
  • the bottom electrode 1 and the top electrode 2 are two opposite electrodes, wherein the bottom electrode 1 is closer to the substrate in the ferroelectric device than the top electrode 2 , That is to say, in actual fabrication, the bottom electrode 1 is fabricated first, and then the top electrode 2 is fabricated.
  • the present application does not limit the specific arrangement form of the above-mentioned ferroelectric device 01 .
  • a ferroelectric device can be used as a ferroelectric memory in a storage device.
  • the storage device can be a ferroelectric random access memory, and other devices connected to the ferroelectric memory can also be arranged in the storage device, such as a controller, a buffer, a central processing unit (central processing unit, CPU), etc.
  • the storage unit inside the ferroelectric memory can include a transistor T (including source S, drain D, gate G, etc.) and the ferroelectric capacitor C connected to the transistor T; wherein, the ferroelectric capacitor C adopts the stacked structure 01 formed by the aforementioned bottom electrode, ferroelectric layer, and top electrode, and adjusts the bottom electrode 1 and the top electrode by controlling the transistor T.
  • the electric field between the top electrodes 2 makes the polarization direction of the ferroelectric layer 3 switch between two stable states, thereby realizing the storage of data ("0" and "1").
  • the ferroelectric device can be an electronic device provided with a ferroelectric field effect transistor (FeFET), and in the FeFET, the gate G (2), the gate insulating layer (3) ,
  • the active layer (1) forms an MFS (metal-ferroelectric-semiconductor, metal-ferroelectric film-semiconductor) structure, or forms an MFIS (metal-ferroelectric-insulator-semiconductor, metal-ferroelectric film-insulator film-semiconductor) structure, that is, the aforementioned stack structure 01; by using the ferroelectric layer 3 as the gate insulating layer, it has a relatively high dielectric constant, thereby enhancing the driving capability of the transistor and increasing the switching speed.
  • MFS metal-ferroelectric-semiconductor, metal-ferroelectric film-semiconductor
  • MFIS metal-ferroelectric-insulator-semiconductor, metal-ferroelectric film-insulator film
  • the performance of the ferroelectric layer 3 largely determines the performance of the ferroelectric device.
  • the ferroelectric layer 3 uses perovskite ferroelectric materials, such as Pb(Zr,Ti)O 3 , BaTiO 3 , SrBi 2 TaO 9 , etc., although perovskite Type ferroelectric materials themselves have excellent ferroelectric properties, but they are not compatible with the existing CMOS (complementary metal oxide semiconductor, complementary metal oxide semiconductor) process, and cannot continue to shrink in size.
  • perovskite ferroelectric materials such as Pb(Zr,Ti)O 3 , BaTiO 3 , SrBi 2 TaO 9 , etc.
  • the ferroelectric layer 3 is made of hafnium oxide (HfO 2 )-based ferroelectric material.
  • the remnant polarization (P r ) of ferroelectric materials will show three characteristics with the cycle of the applied electric field: (1) wake-up, P r increases with the increase of the initial electric field cycle number (2) fatigue (fatigue), after P r is stable for a certain number of cycles, it begins to decrease with the increase of the number of cycles; (3) breakdown (breakdown), the leakage current of the device increases rapidly, resulting in the breakdown of the device Wear and lose ferroelectricity.
  • the ferroelectric film continues to lose oxygen, the electrode interface is continuously oxidized, more defects and oxygen vacancies begin to be generated, and the interface begins to divide the applied electric field, resulting in a decrease in the electric field on the ferroelectric layer; at the same time, the defect capture
  • the charges and vacancies also start to pin some ferroelectric dipoles to prevent them from flipping, resulting in a decrease in P r , which is "fatigue" (refer to C in Figure 5).
  • conductive filaments of oxygen vacancies are gradually formed, which causes the breakdown of the ferroelectric material (refer to D in FIG. 5 ), resulting in decreased device durability.
  • the embodiment of the present application provides a ferroelectric device, in which the ferroelectric layer 3 is doped with a variable valence metal oxide, that is, the ferroelectric layer 3 includes a ferroelectric material, and the ferroelectric material is doped with The variable valence metal oxide in the metal oxide; through the change of the valence state of the variable valence metal oxide, oxygen atoms are generated to neutralize the oxygen vacancies in the ferroelectric material in the electric iron film, thereby controlling the concentration of oxygen vacancies and reducing the oxygen vacancy of the electric iron film. Awakening, fatigue, delay device breakdown, and then improve the durability of ferroelectric devices.
  • the metal oxide of variable valence state doped in the ferroelectric layer 3 may include at least one of a transition metal oxide of variable valence state and a rare earth metal oxide of variable valence state.
  • the ferroelectric layer 3 may only be doped with transition metal oxides with variable valence states; the transition metal oxides with variable valence states may be one type or multiple types.
  • the ferroelectric layer 3 may only be doped with variable valence state rare earth metal oxides, and the doped variable valence state rare earth metal oxides may be one type or multiple types.
  • the ferroelectric layer 3 may be doped with a transition metal oxide with a variable valence state and a rare earth metal oxide with a variable valence state at the same time.
  • the rare earth metal element in the aforementioned variable valence state rare earth metal oxide may be at least one of Ce (cerium), Eu (europium), and Nd (neodymium).
  • the rare earth metal oxide with a variable valence state can be one or more of CeO 2 , Eu 2 O 3 , and Nd 2 O 3 ; but it is not limited thereto.
  • the transition metal element in the transition metal oxide with a variable valence state may be at least one of Mn (manganese), Fe (iron), and Co (cobalt).
  • the variable valence transition metal oxide may be one or more of MnO 2 , Fe 2 O 3 , and Co 2 O 3 ; but it is not limited thereto.
  • variable valence state metal oxide means that the valence state of the metal element (M) in the metal oxide (MO X ) can be changed, that is, the metal element (M) has Two or more valence states.
  • transition metal elements For transition metal oxides with variable valence states, transition metal elements have two or more valence states.
  • rare earth metal oxides with variable valence states the rare earth metal elements have two or more valence states.
  • variable valence state metal oxide can be dynamically converted; as That is, the two valence metal elements (M 2x+ /M 2(x- ⁇ )+ ) can be converted to each other.
  • the ferroelectric device provided by the embodiment of the present application, by using the ferroelectric layer 3 doped with variable valence metal oxide (MO X ), based on The valence state change of metal elements in the ferroelectric material (M 2x+ /M 2(x- ⁇ )+ ), can generate oxygen atoms (O) to neutralize the oxygen vacancies ( VO ) in the ferroelectric material, thereby regulating the oxygen vacancies in the ferroelectric layer Concentration, reduce the awakening and fatigue of the ferroelectric thin film, delay the breakdown of the device, and then improve the durability of the ferroelectric device.
  • MO X variable valence metal oxide
  • the present application does not limit the ferroelectric material used in the ferroelectric layer 3 .
  • the ferroelectric material in the ferroelectric layer 3 can use hafnium oxide (HfO 2 )-based ferroelectric material, so as to ensure the compatibility and size scalability of the ferroelectric device and CMOS process .
  • the hafnium oxide-based ferroelectric material can be zirconium (Zr) doped hafnium oxide-based ferroelectric system ferroelectric materials, HZO), or other hafnium oxide-based ferroelectric materials, such as Si (silicon), Y (yttrium), Cd (cadmium), Sr (strontium), La (lanthanum) and other elements doped hafnium oxide based ferroelectric materials.
  • Zr zirconium
  • HZO hafnium oxide-based ferroelectric materials
  • the ferroelectric material in the ferroelectric layer 3 is hafnium zirconium oxide ferroelectric material (HZO), and the variable valence metal oxide adopts CeO2 as an example; that is, the ferroelectric layer 3 adopts hafnium zirconium oxide Ferroelectric materials (cerium doped hafnium zirconium oxide ferroelectric materials, HZCO).
  • HZO hafnium zirconium oxide ferroelectric material
  • HZCO hafnium zirconium oxide ferroelectric materials
  • Ce 4+ and Ce 3+ are two reversible redox states
  • the oxygen vacancies ( VO ) in HZO can be generated or annihilated very quickly in ceria, endowing ceria with a high oxygen storage and release capacity.
  • the HZO will continuously lose oxygen and the gap between the top electrode 2 and the ferroelectric layer 3 Oxygen vacancies are generated at the interface, and the oxygen vacancies in the ferroelectric phase can be regulated by doping CeO2 in HZO, avoiding the continuous accumulation of oxygen vacancies at the interface between the electrodes (1, 2) and the ferroelectric layer 3 to form oxygen vacancy storage Therefore, excessive oxygen vacancies are prevented from accumulating in the ferroelectric layer 3 to form conductive filaments to cause breakdown of the device, and the durability of the ferroelectric device is improved.
  • the present application does not limit the specific arrangement of the bottom electrode 1 and the top electrode 2 in the ferroelectric device.
  • the ferroelectric device provided by the embodiment of the present application is made by doping the ferroelectric layer 3 with a metal oxide of a variable valence state, and the oxygen vacancies in the ferroelectric material are controlled by the metal oxide of a variable valence state. And, thereby reducing the requirement for the bottom electrode 1 and the top electrode 2 of the ferroelectric device.
  • the bottom electrode 1 can be a metal (such as Ru, Pt, Ir, Mo, W, etc.) electrode, or a nitride (TaN, TiN, etc.) electrode, or a metal oxide (such as RuO 2 , SrRuO 3 ) . , IrO 2 , ITO (indium tin oxide), etc.) electrodes; similarly, such as the setting of the top electrode 2 .
  • a metal such as Ru, Pt, Ir, Mo, W, etc.
  • a nitride (TaN, TiN, etc.) electrode or a metal oxide (such as RuO 2 , SrRuO 3 ) .
  • IrO 2 , ITO (indium tin oxide), etc.) electrodes similarly, such as the setting of the top electrode 2 .
  • the bottom electrode 1 and the top electrode 2 can be symmetrical electrodes (that is, the bottom electrode 1 and the top electrode 2 are made of the same material), or asymmetrical electrodes (that is, the bottom electrode 1 and the top electrode 2 are made of different materials).
  • the bottom electrode 1 and the top electrode 2 may be TiN symmetrical electrodes.
  • the bottom electrode 1 and the top electrode 2 may be W-TiN asymmetric electrodes.
  • the bottom electrode 1 may adopt a single-layer structure or a composite-layer structure; similarly, the arrangement of the top electrode 2 may be used.
  • the present application does not limit the doping method, doping concentration, etc. of the variable-valence metal oxide in the ferroelectric layer 3 .
  • the metal oxide with a variable valence state can be inserted into the ferroelectric material in the form of a film layer structure.
  • the film layer of the variable-valence metal oxide may or may not be in contact with the electrodes (1, 2), which is not limited in the present application.
  • metal oxides with variable valence states can be dispersed and mixed in the ferroelectric material.
  • the doping method and doping concentration of the variable-valence metal oxide in the ferroelectric layer 3 may be determined according to the actual manufacturing process.
  • variable valence state metal oxide can be doped by means of atomic layer deposition (atomic layer deposition, ALD), epitaxial growth (epitaxial growth), magnetron sputtering (sputtering), solution method and the like.
  • ALD atomic layer deposition
  • epitaxial growth epitaxial growth
  • magnetron sputtering sputtering
  • the distribution of the doping concentration of the variable-valence metal oxide in the ferroelectric layer 3 will be schematically described in the following by taking the method of atomic layer deposition as an example, combined with the specific arrangement method of the ferroelectric layer 3 .
  • the doping concentration of the variable-valence metal oxide in the ferroelectric material is periodically distributed.
  • FIG. 1 Schematically, taking ferroelectric layer 3 using cerium-doped hafnium-zirconium oxide ferroelectric material (ie HZCO) as an example, as shown in FIG.
  • HZCO cerium-doped hafnium-zirconium oxide ferroelectric material
  • FIG. 1 A plurality of HZO thin film layers a and a plurality of CeO2 thin film layers b; wherein, the thickness of a plurality of HZO thin film layers a can be substantially the same, and the thickness of a plurality of CeO2 thin film layers b can be substantially consistent, so that the variable valence metal oxide Periodically and uniformly distributed in the thickness direction DD' of the ferroelectric layer 3 .
  • the order of forming the HZO thin film layer a and the CeO 2 thin film layer b is not limited.
  • the thickness of the HZO thin film layer a and the CeO 2 thin film layer b formed by atomic layer deposition is very thin, generally only a few atomic layers thick.
  • the thickness of the HZO thin film layer a can be 1-30 atomic layers
  • the thickness of the CeO2 thin film layer b can be 1-10 atomic layers thick.
  • they can be annealed by an annealing process to form the ferroelectric layer 3 .
  • FIG. 6 is only for the purpose of clearly illustrating the manufacturing process of HZO thin film layer a and CeO2 thin film layer b. Since HZO thin film layer a and CeO2 thin film layer b are relatively thin, and 2 The atoms in the thin film layer b may move during the subsequent annealing process; therefore, in the actual ferroelectric layer 3, there will not be an obvious interlayer between the HZO thin film layer a and the CeO 2 thin film layer b structure, but in the thickness direction DD' of the ferroelectric layer 3, the doping concentration of CeO 2 is still distributed periodically.
  • S1 is the remnant polarization-electric field (4MV/cm) cycle number curve of the HZO thin film without doping CeO2
  • S2 is the remanent polarization-electric field (4MV/cm) of the HZCO thin film after CeO uniformly doped cm) cycle number curve
  • S1 and S2 it can be seen that the HZO film without doped CeO 2 has been broken down before the number of electrical field cycles (electrical field cycles) reaches 10 4 times, while the HZCO film can persist until After 10 5 times, good ferroelectricity is still maintained; that is to say, the durability of the ferroelectric device can be improved by doping the ferroelectric layer 3 provided by the embodiment of the present application by doping a metal oxide with a variable valence state.
  • the ferroelectric layer 3 includes a first doped region C1, an intrinsic region C0, and a second doped region C2 arranged in sequence in the thickness direction DD'.
  • the first doped region C1 is located on the side of the intrinsic region C0 close to the bottom electrode 1 ; the second doped region C2 is located on the side of the intrinsic region C0 close to the top electrode 2 .
  • the ferroelectric material in the intrinsic region C0 is not doped with variable valence metal oxides, and the ferroelectric materials in the first doped region C1 and the second doped region C2 are both doped with variable valence metal oxides.
  • the doping concentration of the variable valence metal oxide in the ferroelectric material is distributed periodically.
  • atomic layer deposition can be used to alternately form multiple A HZO thin film layer a with a substantially uniform thickness and a plurality of CeO 2 thin film layers b with a substantially uniform thickness form the first doped region C1 of the ferroelectric layer 3 . Then a thicker HZO film layer a is formed, that is, the intrinsic region C0 of the ferroelectric layer 3 is formed.
  • HZCO cerium-doped hafnium-zirconium oxide ferroelectric material
  • a plurality of HZO thin film layers a with substantially uniform thickness and a plurality of CeO 2 thin film layers b with substantially uniform thickness are alternately formed in sequence, that is, the second doped region C2 of the ferroelectric layer 3 is formed.
  • the thickness of the HZO thin film layer a in the intrinsic region C0 may be more than three times the thickness of the HZO thin film layer a in the first doped region C1 and the second doped region C2.
  • the interlayer structure in FIG. 8 is only for clearly illustrating the manufacturing process of the HZO thin film layer a and the CeO2 thin film layer b.
  • the ferroelectric layer 3 formed by actual manufacturing it will not absolutely show obvious
  • the interlayer structure of the HZO film layer a and the CeO2 film layer b, but in the thickness direction DD' of the ferroelectric layer 3, the doping concentration of CeO2 in the first doped region C1 and the second doped region C2 is still It is distributed periodically; for details, please refer to the relevant instructions in the aforementioned setting method 1.
  • the ferroelectric layer 3 includes a first doped region C1, an intrinsic region C0, and a second doped region C2 arranged in sequence in the thickness direction DD'.
  • the first doped region C1 is located on the side of the intrinsic region C0 close to the bottom electrode 1 ; the second doped region C2 is located on the side of the intrinsic region C0 close to the top electrode 2 .
  • the ferroelectric material in the intrinsic region C0 is not doped with variable valence metal oxides, and the ferroelectric materials in the first doped region C1 and the second doped region C2 are both doped with variable valence metal oxides.
  • the doping concentration of the variable valence state metal oxide in the ferroelectric material gradually increases along the direction close to the bottom electrode 1; in the second doped region C2, the variable valence state The doping concentration of the metal oxide in the ferroelectric material gradually increases along the direction close to the top electrode 2 .
  • the thickness of a plurality of HZO thin film layers a can be basically the same, and along the direction close to the bottom electrode 1, the thickness of the HZO thin film layer a between adjacent two CeO2 thin film layers b decreases gradually, so that at the The content of HZO in a doped region C1 decreases gradually in the direction close to the bottom electrode 1 , that is, the doping concentration of CeO 2 gradually increases in the direction close to the bottom electrode 1 .
  • multiple HZO thin film layers a and multiple CeO 2 thin film layers b may be alternately formed in sequence by means of atomic layer deposition.
  • the thickness of a plurality of HZO thin film layers a can be substantially the same, and along the direction close to the top electrode, the thickness of the HZO thin film layer a between adjacent two CeO2 thin film layers b decreases gradually, so that in the second The content of HZO in the doped region C2 decreases gradually in the direction close to the top electrode 2 , that is, the doping concentration of CeO 2 gradually increases in the direction close to the top electrode 2 .
  • first doping region C1 and second doping region C2 with graded doping concentration; this application is not limited thereto.
  • the intrinsic region C0 in the ferroelectric layer 3 adopts a thicker HZO film layer a.
  • the thickness of the HZO thin film layer in the intrinsic region C0 may be more than three times the average thickness of the plurality of HZO thin film layers a in the first doped region C1 and the second doped region C2.
  • the interlayer structure in FIG. 9 is only for clearly illustrating the manufacturing process of the HZO thin film layer a and the CeO2 thin film layer b.
  • the ferroelectric layer 3 formed by actual manufacturing it will not absolutely show obvious
  • the doping concentration of CeO 2 is still gradually increasing along the direction close to the top electrode 2 .
  • the variable valence state metal oxide in the entire ferroelectric layer 3 adopts a relatively uniform doping method
  • the ferroelectric layer 3 A certain thickness of the undoped region (that is, the setting of the intrinsic region C0) is reserved in the middle, and only the region (C1, C2) close to the electrode is doped with a variable valence metal oxide, so as to ensure that the system has a sufficient content of iron The electric phase can effectively control the oxygen vacancies at the interface.
  • variable-valence metal oxide can trap abundant oxygen vacancies at the interface to reduce its concentration, resulting in more free ferroelectric dipoles that can be flipped in the initial state , thereby increasing the initial Pr and correspondingly reducing the “wake-up” phenomenon.
  • the first doped region C1 and the second doped region C2 adopt a relatively uniform doping concentration
  • the first doped region C1 and the second doped region C2 adopt a relatively uniform doping concentration.
  • a gradually changing doping concentration is adopted in the region C2.
  • the variable valence metal oxide has a larger doping concentration near the electrodes (1, 2) of the ferroelectric layer 3, so that the ferroelectric thin film can be precisely regulated Oxygen vacancies in the interior and at the interface can maximize the ferroelectric phase content in the system with ferroelectric properties, and achieve the dual beneficial effects of reducing "wake-up" and improving durability.
  • the doping concentration distribution of the variable valence state metal oxide in the first doped region C1 and the second doped region C2 is symmetric as an example for illustration. but the present application is not limited thereto.
  • the concentration distribution of oxygen vacancies in the ferroelectric device can be obtained through characterization, so that the doping concentration distribution of the variable valence state metal oxide in the ferroelectric layer 3 can be designed accordingly, that is, Precise doping according to the change of oxygen vacancy concentration.
  • variable valence metal oxide in the first doped region C1 can be set to adopt a uniform doping concentration, that is, the doping concentration is periodically distributed in the thickness direction; the second doped region The doping concentration of the variable-valence metal oxide in C2 increases gradually along the direction close to the top electrode.
  • the doping concentration of the variable valence metal oxide in the first doped region C1 gradually increases along the direction close to the bottom electrode; the variable valence metal oxide in the second doped region C2
  • the doping concentration of the material is periodically distributed in the thickness direction.
  • the doping concentration of the variable-valence metal oxide in the first doped region C1 can be set to gradually decrease along the direction close to the bottom electrode, and the variable-valence metal oxide in the second doped region C2 The doping concentration of the state metal oxide decreases gradually along the direction close to the top electrode.
  • ferroelectric device in the embodiment of the present application adopts ferroelectric materials doped with variable valence metal oxides to form the ferroelectric layer 3, which can be achieved by adjusting the growth process of the ferroelectric layer 3.
  • Realizing the control of the doping concentration of the variable valence state metal oxide has the advantages of simple manufacturing method and simple device structure.
  • the ferroelectric layer 3 can be fabricated by atomic layer deposition without introducing additional manufacturing equipment; at the same time, it can also be compatible with upstream and downstream processes (such as compatible with CMOS processes) , that is process friendly.

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Abstract

本申请提供了一种铁电器件、存储装置及电子设备，涉及存储领域，能够提高铁电器件的耐久性。该铁电器件包括顶电极、底电极以及位于顶电极和底电极之间的铁电层。铁电层包括可变价态金属氧化物和铁电材料。可变价态金属氧化物包括可变价态过渡金属氧化物和可变价态稀土金属氧化物中的至少一种。

Description

铁电器件、存储装置及电子设备 技术领域
本申请涉及存储领域，尤其涉及一种铁电器件、存储装置及电子设备。
背景技术
铁电随机存储器(ferroelectric random access memory，FeRAM)具有低写入功耗，高读取速度的优势，它是未来取代动态随机存储器(dynamic random access memory，DRAM)的新型存储器之一。
FeRAM采用铁电材料取代DRAM中原有的介电质，其极化方向在两个稳定状态(“0”和“1”)之间转换，实现数据的写入和读取，即使电场撤出后仍可保持不变。相关技术中的FeRAM采用金属电极，在制作FeRAM的过程中(包括金属电极的沉积以及后道退火处理的过程中)，金属电极会夺走铁电薄膜的氧(oxygen scavenging)，导致FeRAM的耐久性(endurance)下降。
发明内容
本申请实施例提供一种铁电器件、存储装置及电子设备，能够提高铁电器件的耐久性。
本申请提供一种铁电器件，包括顶电极、底电极以及位于顶电极和底电极之间的铁电层。铁电层包括可变价态金属氧化物和铁电材料。可变价态金属氧化物包括可变价态过渡金属氧化物和可变价态稀土金属氧化物中的至少一种。
在本申请实施例提供的铁电器件中，通过采用掺杂有可变价态金属氧化物(MO X)的铁电层，基于
Figure PCTCN2021125156-appb-000001
中金属元素的价态变化(M 2x+/M 2(x-δ)+)，能够产生氧原子(O)进而对铁电材料内氧空位(V O)中和，从而调控铁电层中氧空位浓度，降低电铁薄膜的觉醒、疲劳，延迟器件被击穿，进而提升了铁电器件的耐久性。
在一些可能实现的方式中，可变价态稀土金属氧化物中的稀土金属元素为Ce、Eu、Nd中的至少一种。例如，可变价态稀土金属氧化物可以为CeO 2、Eu 2O 3、Nd 2O 3中的一种或多种。
在一些可能实现的方式中，可变价态过渡金属氧化物中的过渡金属元素为Mn，Fe，Co中的至少一种。例如，可变价态过渡金属氧化物可以为MnO 2、Fe 2O 3、Co 2O 3中的一种或多种。
在一些可能实现的方式中，铁电材料包括氧化铪基铁电材料，从而能够保证铁电器件与CMOS(complementary metal oxide semiconductor，互补金属氧化物半导体)工艺可兼容性、尺寸可缩性。
在一些可能实现的方式中，沿铁电层的厚度方向上，可变价态金属氧化物在铁电材料中掺杂浓度呈周期性分布。在此情况下，在制作铁电层时，可以采用原子层沉积的方式依次交替形成多个铁电薄膜层和多个可变价态金属氧化物薄膜层；其中，多个铁电薄膜层的厚度可以基本一致，多个可变价态金属氧化物薄膜层的厚度可以基本一致，从而使得可变 价态金属氧化物在铁电层的厚度方向上呈周期性均匀分布。
在一些可能实现的方式中，铁电层在厚度方向上包括依次设置的第一掺杂区、本征区、第二掺杂区。第一掺杂区位于本征区靠近底电极的一侧；第二掺杂区位于本征区靠近顶电极的一侧；本征区包括铁电材料；第一掺杂区包括可变价态金属氧化物和铁电材料；第二掺杂区包括可变价态金属氧化物和铁电材料。在此情况下，通过在铁电层的中间保留一定厚度的未掺杂区(即本征区的设置)，仅在靠近电极的区域掺杂可变价态金属氧化物，从而能够保证体系有足够含量的铁电相，进而能够有效的调控界面的氧空位。
在一些可能实现的方式中，在第一掺杂区中，可变价态金属氧化物在铁电材料中的掺杂浓度，沿铁电层的厚度方向上呈周期性分布。在此情况下，可以采用原子层沉积的方式，依次交替形成多个厚度基本一致的铁电薄膜层和多个厚度基本一致的变价态金属氧化物薄膜层。
在一些可能实现的方式中，在第一掺杂区中，可变价态金属氧化物在铁电材料中的掺杂浓度，沿靠近底电极的方向上逐渐增加。在此情况下，可以采用原子层沉积的方式，在底电极的表面依次交替形成多个铁电薄膜层和多个可变价态金属氧化物薄膜层。其中，多个铁电薄膜层的厚度可以基本一致，沿靠近底电极的方向上，位于相邻两个可变价态金属氧化物薄膜层之间的铁电薄膜层的厚度逐渐减小，从而使得在第一掺杂区中铁电材料的含量在靠近底电极的方向上逐渐减小，也即在靠近底电极的方向上可变价态金属氧化物的掺杂浓度逐渐增加。
在一些可能实现的方式中，在第二掺杂区中，可变价态金属氧化物在铁电材料中的掺杂浓度，沿铁电层的厚度方向上呈周期性分布。在此情况下，可以采用原子层沉积的方式，依次交替形成多个厚度基本一致的铁电薄膜层和多个厚度基本一致的变价态金属氧化物薄膜层。
在一些可能实现的方式中，在第二掺杂区中，可变价态金属氧化物在铁电材料中的掺杂浓度，沿靠近顶电极的方向上逐渐增加。在此情况下，可以采用原子层沉积的方式，依次交替形成多个铁电薄膜层和多个可变价态金属氧化物薄膜层。其中，多个铁电薄膜层的厚度可以基本一致，沿靠近顶电极的方向上，位于相邻两个可变价态金属氧化物薄膜层之间的铁电薄膜层的厚度逐渐减小，从而使得在第二掺杂区中铁电材料的含量在靠近顶电极的方向上逐渐减小，也即在靠近顶电极的方向上可变价态金属氧化物的掺杂浓度逐渐增加。
本申请实施例还提供一种存储装置，包括控制器以及如前述任一种可能实现的方式中提供的铁电器件；控制器与铁电器件连接。
本申请实施例还提供一种电子设备，包括印刷线路板以及如前述任一种可能实现的方式中提供的存储装置；存储装置与印刷线路板连接。
附图说明
图1为本申请实施例提供的一种铁电器件的结构示意图；
图2为本申请实施例提供的一种存储装置的结构示意图；
图3为本申请实施例提供的一种存储单元的结构示意图；
图4为本申请实施例提供的一种铁电场效应晶体管的结构示意图；
图5为本申请相关技术中提供的一种铁电器件的铁电偶极子(上)和铁电相(下)在原始、觉醒、疲劳、击穿时的转变示意图；
图6为本申请实施例提供的一种铁电器件的结构示意图；
图7为未掺CeO 2的HZO薄膜与HZCO薄膜的耐久性表征曲线；
图8为本申请实施例提供的一种铁电器件的结构示意图；
图9为本申请实施例提供的一种铁电器件的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。“连接”、“相连”等类似的词语，用于表达不同组件之间的互通或互相作用，可以包括直接相连或通过其他组件间接相连。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“上”、“下”、“左”、“右”等仅用于相对于附图中的部件的方位而言的，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
应当理解，在本申请中，“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”，其中a，b，c可以是单个，也可以是多个。
本申请实施例提供一种电子设备，该电子设备中包括印刷线路板(printed circuit board，PCB)以及与该印刷线路板连接的铁电器件。本申请对于该电子设备的设置形式不做限制。例如，该电子设备可以为手机、平板电脑、笔记本、车载电脑、智能手表、智能手环等电子产品。
如图1所示，本申请实施例提供的铁电器件中包括：底电极1、铁电层3、顶电极2形成的堆叠结构01。示意的，该堆叠结构01可以为金属电极-铁电薄膜-金属电极(metal ferroelectrics metal，MFM)结构，但并不限制于此，例如，在一些实施例中，底电极1、顶电极2也可以采用金属以外的其他材质，如半导体等。
本领域的技术人员可以理解的是，在铁电器件中，底电极1和顶电极2为相对设置的两个电极，其中，底电极1相对于顶电极2更靠近于铁电器件中的基板，也就是说，在实际中制作时，先进行底电极1的制作，然后再进行顶电极2的制作。
本申请对于上述铁电器件01的具体设置形式不做限制。
例如，在一些可能实现的方式中，铁电器件可以作为存储装置中的铁电存储器。示意的，如图2所示，存储装置可以为铁电随机存储器，该存储装置中还可以设置有与铁电存储器连接的其他器件，如控制器、缓存器、中央处理器(central processing unit，CPU)等。
以存储装置为铁电随机存储器为例，上述铁电器件作为铁电存储器，如图3所示，铁电存储器内部的存储单元中可以包括晶体管T(包括源极S、漏极D、栅极G等)以及与晶体管T连接的铁电电容C；其中，铁电电容C采用前述的底电极、铁电层、顶电极形成的堆叠结构01，通过对晶体管T的控制来调整底电极1和顶电极2之间的电场，以使得铁电层3的极化方向在两个稳定状态之间转换，进而实现数据(“0”和“1”)的存储。
又例如，参考图4所示，铁电器件可以是设置有铁电场效应晶体管(ferroelectric field effect transistor，FeFET)的电子器件，在FeFET中，栅极G(2)、栅极绝缘层(3)、有源层(1)形成MFS(metal-ferroelectric-semiconductor，金属-铁电薄膜-半导体)结构，或者，形成MFIS(metal-ferroelectric-insulator-semiconductor，金属-铁电薄膜-绝缘薄膜-半导体)结构，也即前述的堆叠结构01；通过采用铁电层3作为栅极绝缘层，具有较高介电常数，从而能够增强晶体管的驱动能力，提高开关速度。
以下实施例均是以铁电器件为铁电随机存储器中的存储器件为例，对本申请进行说明
对于上述铁电器件而言，铁电层3的性能很大程度上决定了铁电器件的性能。
例如，在一些相关的铁电随机存储器中，铁电层3采用钙钛矿型铁电材料，如可以是Pb(Zr,Ti)O 3、BaTiO 3、SrBi 2TaO 9等，尽管钙钛矿型铁电材料自身具有优异的铁电性能，但是它们并不兼容现有CMOS(complementary metal oxide semiconductor，互补金属氧化物半导体)工艺，也无法继续缩小尺寸。
又例如，在另一些相关的铁电随机存储器中，铁电层3采用氧化铪(HfO 2)基的铁电材料，尽管可以满足CMOS工艺可兼容性、尺寸可缩性，但是大多氧化铪基铁电材料的剩余极化性能(remnant polarization；即P r)随着所加电场的循环会表现出三特征：(1)觉醒(wake-up)，P r随着初始电场循环次数的增加而提高直到稳定；(2)疲劳(fatigue)，P r稳定一定循环数量后，开始随着循环次数的增加而降低；(3)击穿(breakdown)，器件漏电流急速增大，导致器件被击穿而丧失铁电性。这些现象主要是由于在沉积顶、底电极以及后道退火处理时，金属电极夺走铁电薄膜的氧(oxygen scavenging)，从而在金属-铁电层界面产生一定数量氧空位，引起内建电场，在初始时钉扎部分铁电偶极子(ferroelectric dipole)，甚至造成相反的极化方向(参考图5中A)。随着循环施加电场，在界面的氧空位开始移动，释放被钉扎的铁电偶极子，P r开始提高。由于氧空位同时也起着稳定铁电相的作用，当氧空位开始扩散、转移至铁电薄膜体相，可以让部分非铁电相(M-phase)转变为铁电相(O-phase)，使P r进一步增大(参考图5中B)。随着电场的不断循环，铁电薄膜内持续失去氧，电极界面不断被氧化，更多缺陷和氧空位开始生成，界面开始分压所加电场，造成铁电层所受电场降低；同时缺陷捕获的电荷、空位也开始钉扎部分铁电偶极子阻止其翻转，致使P r降低，此为“疲劳”(参考图5中C)。甚者，由于铁电层内的氧空位不断累积，逐渐形成氧空位导电细丝(filament)，使铁电材料被击穿(参考图5中D)，导致器件耐久性(endurance)下降。
相比之下，本申请实施例提供一种铁电器件，在铁电层3中掺杂可变价态金属氧化物， 也即，铁电层3包括铁电材料，以及掺杂在铁电材料中的可变价态金属氧化物；通过可变价态金属氧化物的价态变化产生氧原子来实现对电铁薄膜中铁电材料内氧空位的中和，从而控制氧空位浓度，降低电铁薄膜的觉醒、疲劳，延迟器件被击穿，进而提升铁电器件的耐久性。本申请实施例提供的铁电器件中，铁电层3中掺杂的可变价态金属氧化物可以包括可变价态过渡金属氧化物和可变价态稀土金属氧化物中的至少一种。
例如，在一些可能实现的方式中，铁电层3可以仅掺杂可变价态过渡金属氧化物；该可变价态过渡金属氧化物可以是一种，也可以是多种。
又例如，在一些可能实现的方式中，铁电层3可以仅掺杂可变价态稀土金属氧化物，该掺杂可变价态稀土金属氧化物可以是一种，也可以是多种。
再例如，在一些可能实现的方式中，铁电层3可以同时掺杂可变价态过渡金属氧化物和可变价态稀土金属氧化物。
示意的，上述可变价态稀土金属氧化物中的稀土金属元素可以为Ce(铈)、Eu(铕)、Nd(钕)中的至少一种。例如，可变价态稀土金属氧化物可以为CeO 2、Eu 2O 3、Nd 2O 3中的一种或多种；但并不限制于此。
示意的，上述可变价态过渡金属氧化物中的过渡金属元素可以为Mn(锰)、Fe(铁)、Co(钴)中的至少一种。例如，可变价态过渡金属氧化物可以为MnO 2、Fe 2O 3、Co 2O 3中的一种或多种；但并不限制于此。
应当理解的是，对于上述“可变价态金属氧化物”而言，是指该金属氧化物(MO X)中的金属元素(M)的价态可以变化，也即该金属元素(M)具有两个或两个以上的价态。对于可变价态过渡金属氧化物而言，过渡金属元素具有两个或两个以上的价态。对于可变价态稀土金属氧化物而言，稀土金属元素具有两个或两个以上的价态。
还应当理解的是，随着体系中氧空位(V O)和氧原子(O)的浓度变化，可变价态金属氧化物的不同价态的金属元素之间能够进行动态转换；如
Figure PCTCN2021125156-appb-000002
即两种价态金属元素(M 2x+/M 2(x-δ)+)之间可以互相转换。
综上所述，在本申请实施例提供的铁电器件中，通过采用掺杂有可变价态金属氧化物(MO X)的铁电层3，基于
Figure PCTCN2021125156-appb-000003
中金属元素的价态变化(M 2x+/M 2(x-δ)+)，能够产生氧原子(O)对铁电材料内氧空位(V O)中和，从而调控铁电层中氧空位浓度，降低电铁薄膜的觉醒、疲劳，延迟器件被击穿，进而提升了铁电器件的耐久性。
另外，本申请对铁电层3采用的铁电材料不作限制。示意的，在一些可能实现的方式中，铁电层3中的铁电材料可以采用氧化铪(HfO 2)基铁电材料，从而能够保证铁电器件与CMOS工艺可兼容性、尺寸可缩性。
本申请对于上述氧化铪基铁电材料的本征(或第一)掺杂元素不作限制；例如，氧化铪基铁电材料可以是锆(Zr)掺杂氧化铪基铁电体系(hafnium zirconium oxide ferroelectric materials，HZO)，也可以是其他氧化铪基铁电材料，如Si(硅)、Y(钇)、Cd(镉)、Sr(锶)、La(镧)等元素的掺杂的氧化铪基铁电材料。
示意的，以铁电层3中的铁电材料为铪锆氧铁电材料(HZO)，可变价态金属氧化物采用CeO 2为例；也即铁电层3采用铈掺杂的铪锆氧铁电材料(cerium doped hafnium zirconium oxide ferroelectric materials，HZCO)。在氧化铈中，Ce 4+和Ce 3+是可逆的两种氧化还原态
Figure PCTCN2021125156-appb-000004
致使HZO中的氧空位(V O)在氧化铈中可以很快 速的产生或湮灭，赋予了氧化铈一个很高的氧存储和释放能力。
在此情况下，尽管在制作铁电器件的过程中，因沉积顶电极、退火工艺以及铁电器件在电场循环时，会造成HZO不断失氧而在顶电极2与铁电层3之间的界面产生氧空位，通过在HZO中掺杂CeO 2能够进行铁电体相中的氧空位进行调控，避免了氧空位不断在电极(1、2)与铁电层3的界面累积形成氧空位贮藏所，进而避免了过多的氧空位在铁电层3里累积形成导电细丝导致器件击穿，提升了铁电器件的耐久性。
此外，本申请对于铁电器件中底电极1和顶电极2的具体设置不作限制。本领域的技术人员可以理解的是，本申请实施例提供的铁电器件通过在铁电层3中掺杂可变价态金属氧化物，通过可变价态金属氧化物对铁电材料内氧空位中和，从而降低了铁电器件对底电极1和顶电极2的设置要求。
示意的，底电极1可以采用金属(如Ru、Pt、Ir、Mo、W等)电极，也可以采用氮化物(TaN、TiN等)电极，还可以采用金属氧化物(如RuO 2、SrRuO 3、IrO 2、ITO(indium tin oxide)等)电极；类似的，如顶电极2的设置。
示意的，底电极1和顶电极2可以采用对称电极(即底电极1和顶电极2采用相同的材料)，也可以采用不对称电极(即底电极1和顶电极2采用不同的材料)。例如，在一些可能实现的方式中，底电极1和顶电极2可以采用TiN的对称电极。又例如，在一些可能实现的方式中，底电极1和顶电极2可以采用W-TiN的不对称电极。
示意的，底电极1可以采用单膜层结构，也可以采用复合膜层结构；类似的，如顶电极2的设置。
另外，本申请对铁电层3中可变价态金属氧化物的掺杂方式、掺杂浓度等均不作限制。
例如，在一些可能实现的方式中，在铁电层3中，可变价态金属氧化物可以通过膜层结构的方式，插入在铁电材料中。当然，可变价态金属氧化物的膜层可以与电极(1、2)接触，也可以不接触，本申请对此不作限制。
又例如，在一些可能实现的方式中，可变价态金属氧化物可以分散混合在铁电材料中。
实际中，铁电层3中可变价态金属氧化物的掺杂方式、掺杂浓度等，可以根据实际的制作工艺而定。
示意的，可变价态金属氧化物可以采用原子层沉积(atomic layer deposition，ALD)、外延生长(epitaxial growth)、磁控溅射(sputtering)、溶液法等方式进行掺杂。
以下以采用原子层沉积的方式为例，结合铁电层3的具体设置方式，对铁电层3中可变价态金属氧化物的掺杂浓度的分布进行示意的说明。
设置方式一
在该设置方式一中，参考图6所示，沿铁电层3的厚度方向DD’上，可变价态金属氧化物在铁电材料中掺杂浓度呈周期性分布。
示意的，以铁电层3采用铈掺杂的铪锆氧铁电材料(即HZCO)为例，参考图6所示，在制作铁电层3时，可以采用原子层沉积的方式依次交替形成多个HZO薄膜层a和多个CeO 2薄膜层b；其中，多个HZO薄膜层a的厚度可以基本一致，多个CeO 2薄膜层b的厚度可以基本一致，从而使得可变价态金属氧化物在铁电层3的厚度方向DD’上呈周期性均匀分布。当然，形成HZO薄膜层a和CeO 2薄膜层b的先后顺序不作限制。
本领域的技术人员可以理解的是，采用原子层沉积的形成的HZO薄膜层a和CeO 2 薄膜层b的厚度很薄，一般仅为几个原子层的厚度。例如，HZO薄膜层a的厚度可以为1-30个原子层的厚度，CeO 2薄膜层b的厚度为1-10个原子层的厚度。并且在多个HZO薄膜层a和多个CeO 2薄膜层b沉积完成后，可以通过退火工艺进行退火，以形成铁电层3。
需要说明的是，图6仅是为了清楚的对HZO薄膜层a和CeO 2薄膜层b制作过程进行示意，由于HZO薄膜层a和CeO 2薄膜层b自身较薄，并且HZO薄膜层a和CeO 2薄膜层b中的原子在后续退火过程中可能产生移动；因此，在实际制作形成的铁电层3中，并不绝对会呈现出明显的HZO薄膜层a和CeO 2薄膜层b的层间结构，但是在铁电层3的厚度方向DD’上，CeO 2的掺杂浓度依然呈周期性分布。
图7中S1为未掺杂CeO 2的HZO薄膜的剩余极化强度-电场(4MV/cm)循环次数曲线，S2为CeO 2均匀掺杂后的HZCO薄膜的剩余极化强度-电场(4MV/cm)循环次数曲线；对比S1和S2可以看出，未掺杂CeO 2的HZO薄膜在电场循环次数(electrical field cycles)未到10 4次就已经被击穿，而通过HZCO薄膜却可以坚持到10 5次后依然保有很好的铁电性；也就是说，采用本申请实施例提供的铁电层3通过掺杂可变价态金属氧化物，能够提升铁电器件的耐久性。
设置方式二
在该设置方式二中，参考图8所示，铁电层3在厚度方向DD’上包括依次设置的第一掺杂区C1、本征区C0、第二掺杂区C2。第一掺杂区C1位于本征区C0靠近底电极1的一侧；第二掺杂区C2位于本征区C0靠近顶电极2的一侧。本征区C0的铁电材料中未掺杂可变价态金属氧化物，第一掺杂区C1和第二掺杂区C2的铁电材料中均掺杂有可变价态金属氧化物。其中，沿铁电层3的厚度方向DD’上，第一掺杂区C1和第二掺杂区C2中，可变价态金属氧化物在铁电材料中的掺杂浓度均呈周期性分布。
示意的，以铁电层3采用铈掺杂的铪锆氧铁电材料(即HZCO)为例，参考图8所示，可以采用原子层沉积的方式，在底电极1的表面依次交替形成多个厚度基本一致的HZO薄膜层a和多个厚度基本一致的CeO 2薄膜层b，也即形成铁电层3的第一掺杂区C1。然后形成较厚的HZO薄膜层a，即形成铁电层3的本征区C0。接下来，依次交替形成多个厚度基本一致的HZO薄膜层a和多个厚度基本一致的CeO 2薄膜层b，也即形成铁电层3的第二掺杂区C2。
示意的，本征区C0的HZO薄膜层a的厚度可以是第一掺杂区C1和第二掺杂区C2中HZO薄膜层a的厚度的3倍以上。
需要说明的是，图8中的层间结构仅是为了清楚的对HZO薄膜层a和CeO 2薄膜层b制作过程进行示意，实际制作形成的铁电层3中，并不绝对会呈现出明显的HZO薄膜层a和CeO 2薄膜层b的层间结构，但是在铁电层3的厚度方向DD’上，第一掺杂区C1和第二掺杂区C2中CeO 2的掺杂浓度依然呈周期性分布；具体可以参考前述设置方式一中的相关说明。
设置方式三
在该设置方式三中，参考图9所示，铁电层3在厚度方向DD’上包括依次设置的第一掺杂区C1、本征区C0、第二掺杂区C2。第一掺杂区C1位于本征区C0靠近底电极1的一侧；第二掺杂区C2位于本征区C0靠近顶电极2的一侧。本征区C0的铁电材料中未掺 杂可变价态金属氧化物，第一掺杂区C1和第二掺杂区C2的铁电材料中均掺杂有可变价态金属氧化物。其中，在第一掺杂区C1中，可变价态金属氧化物在铁电材料中的掺杂浓度，沿靠近底电极1的方向上逐渐增加；在第二掺杂区C2中，可变价态金属氧化物在铁电材料中的掺杂浓度，沿靠近顶电极2的方向上逐渐增加。
示意的，以铁电层3采用铈掺杂的铪锆氧铁电材料(即HZCO)为例，参考图9所示，对于铁电层3的第一掺杂区C1而言，可以采用原子层沉积的方式形成依次交替形成多个HZO薄膜层a和多个CeO 2薄膜层b。其中，多个HZO薄膜层a的厚度可以基本一致，沿靠近底电极1的方向上，位于相邻两个CeO 2薄膜层b之间的HZO薄膜层a的厚度逐渐减小，从而使得在第一掺杂区C1中HZO的含量在靠近底电极1的方向上逐渐减小，也即在靠近底电极1的方向上CeO 2的掺杂浓度逐渐增加。
类似的，对于铁电层3的第二掺杂区C2而言，可以采用原子层沉积的方式，依次交替形成多个HZO薄膜层a和多个CeO 2薄膜层b。其中，多个HZO薄膜层a的厚度可以基本一致，沿靠近顶电极的方向上，位于相邻两个CeO 2薄膜层b之间的HZO薄膜层a的厚度逐渐减小，从而使得在第二掺杂区C2中HZO的含量在靠近顶电极2的方向上逐渐减小，也即在靠近顶电极2的方向上CeO 2的掺杂浓度逐渐增加。
当然，还可以采用其他的掺杂方式形成上述具有渐变掺杂浓度的第一掺杂区C1、第二掺杂区C2；本申请对此不作限制。
铁电层3中的本征区C0采用厚度较厚的HZO薄膜层a。示意的，本征区C0的HZO薄膜层的厚度可以是第一掺杂区C1、第二掺杂区C2中多个HZO薄膜层a的平均厚度的3倍以上。
需要说明的是，图9中的层间结构仅是为了清楚的对HZO薄膜层a和CeO 2薄膜层b制作过程进行示意，实际制作形成的铁电层3中，并不绝对会呈现出明显的HZO薄膜层a和CeO 2薄膜层b的层间结构，但是第一掺杂区C1中CeO 2的掺杂浓度依然是沿靠近底电极1的方向上逐渐增加，第二掺杂区C2中CeO 2的掺杂浓度依然是沿靠近顶电极2的方向上逐渐增加。
应当理解的是，相比于设置方式一中，整个铁电层3中可变价态金属氧化物采用较为均匀的掺杂方式而言，设置方式二和设置方式三中，通过在铁电层3的中间保留一定厚度的未掺杂区(即本征区C0的设置)，仅在靠近电极的区域(C1、C2)处掺杂可变价态金属氧化物，从而能够保证体系有足够含量的铁电相，进而能够有效的调控界面的氧空位。在此情况下，在进行高温退火处理时，可变价态金属氧化物可以对界面丰富的氧空位进行俘获来降低其浓度，致使有更多的自由铁电偶极子在初始状态时可以被翻转，从而提升初始Pr，相应地降低“觉醒”(wake-up)现象。
另外，相比于设置方式二中，第一掺杂区C1和第二掺杂区C2采用相对均匀的掺杂浓度而言，设置方式三中，在第一掺杂区C1和第二掺杂区C2中采用渐变的掺杂浓度，在此情况下，可变价态金属氧化物在铁电层3靠近电极(1、2)处具有较大的掺杂浓度，从而能够精准的调控铁电薄膜内及界面处的氧空位，并能使体系中含有铁电性能的铁电相含量最大化，实现降低“觉醒”(wake-up)，提升耐久性的双重有益效果。
此外还需要说明的是，前述设置方式二和设置方式三中，仅是以第一掺杂区C1和第二掺杂区C2中可变价态金属氧化物的掺杂浓度分布对称为例进行说明的；但本申请并不 限制于此，实际中可以通过表征获取铁电器件中氧空位的浓度分布，从而相应的设计铁电层3中可变价态金属氧化物的掺杂浓度分布，也即根据氧空位浓度的变化进行精准掺杂。
例如，在一些可能实现的方式中，可以设置第一掺杂区C1中可变价态金属氧化物采用均匀的掺杂浓度，即掺杂浓度在厚度方向上呈周期性分布；第二掺杂区C2中可变价态金属氧化物的掺杂浓度沿靠近顶电极的方向上逐渐增加。
又例如，在一些可能实现的方式中，第一掺杂区C1中可变价态金属氧化物的掺杂浓度沿靠近底电极的方向上逐渐增加；第二掺杂区C2中可变价态金属氧化物的掺杂浓度在厚度方向上呈周期性分布。
再例如，在一些可能实现的方式中，可以设置第一掺杂区C1中可变价态金属氧化物的掺杂浓度沿靠近底电极的方向上逐渐减小，第二掺杂区C2中可变价态金属氧化物的掺杂浓度沿靠近顶电极的方向上逐渐减小。
另外，本领域的技术人员可以理解的是，本申请实施例中铁电器件采用在铁电材料中掺杂可变价态金属氧化物形成铁电层3，可以通过调节铁电层3的生长工艺来实现对可变价态金属氧化物的掺杂浓度的调控，具有制作方法简单，器件结构简单的优势。
以铁电器件在铁电随机存储器中的应用为例，可以采用原子层沉积的方式制作铁电层3，无需引入额外的制作设备；同时还可以与上下游工艺兼容(如与CMOS工艺兼容)，即工艺友好。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种铁电器件，其特征在于，包括顶电极、底电极以及位于所述顶电极和所述底电极之间的铁电层；
    所述铁电层包括可变价态金属氧化物和铁电材料；
    所述可变价态金属氧化物包括可变价态过渡金属氧化物和可变价态稀土金属氧化物中的至少一种。
  2. 根据权利要求1所述的铁电器件，其特征在于，
    所述可变价态稀土金属氧化物中的稀土金属元素为Ce、Eu、Nd中的至少一种。
  3. 根据权利要求1或2所述的铁电器件，其特征在于，
    所述可变价态过渡金属氧化物中的过渡金属元素为Mn，Fe，Co中的至少一种。
  4. 根据权利要求1-3任一项所述的铁电器件，其特征在于，
    所述铁电材料包括氧化铪基铁电材料。
  5. 根据权利要求1-4任一项所述的铁电器件，其特征在于，
    沿所述铁电层的厚度方向上，所述可变价态金属氧化物在所述铁电材料中掺杂浓度呈周期性分布。
  6. 根据权利要求1-4任一项所述的铁电器件，其特征在于，
    所述铁电层在厚度方向上包括依次设置的第一掺杂区、本征区、第二掺杂区；
    所述第一掺杂区位于所述本征区靠近所述底电极的一侧；
    所述第二掺杂区位于所述本征区靠近所述顶电极的一侧；
    所述本征区包括所述铁电材料；
    所述第一掺杂区包括所述可变价态金属氧化物和所述铁电材料；
    所述第二掺杂区包括所述可变价态金属氧化物和所述铁电材料。
  7. 根据权利要求6所述的铁电器件，其特征在于，
    在所述第一掺杂区中，所述可变价态金属氧化物在所述铁电材料中的掺杂浓度，沿所述铁电层的厚度方向上呈周期性分布；
    或者，在所述第一掺杂区中，所述可变价态金属氧化物在所述铁电材料中的掺杂浓度，沿靠近所述底电极的方向上逐渐增加。
  8. 根据权利要求6或7所述的铁电器件，其特征在于，
    在所述第二掺杂区中，所述可变价态金属氧化物在所述铁电材料中的掺杂浓度，沿所述铁电层的厚度方向上呈周期性分布；
    或者，在所述第二掺杂区中，所述可变价态金属氧化物在所述铁电材料中的掺杂浓度，沿靠近所述顶电极的方向上逐渐增加。
  9. 一种存储装置，其特征在于，包括控制器以及如权利要求1-8任一项所述的铁电器件；所述控制器与所述铁电器件连接。
  10. 一种电子设备，其特征在于，包括印刷线路板以及如权利要求9所述的存储装置；所述存储装置与所述印刷线路板连接。
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CN111033738A (zh) * 2017-08-30 2020-04-17 美光科技公司 铁电电容器、铁电场效应晶体管以及用于形成包括导电材料和铁电材料的电子装置的方法
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