WO2023060863A1 - 一种数字测试向量自动学习方法及系统 - Google Patents

一种数字测试向量自动学习方法及系统 Download PDF

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WO2023060863A1
WO2023060863A1 PCT/CN2022/087321 CN2022087321W WO2023060863A1 WO 2023060863 A1 WO2023060863 A1 WO 2023060863A1 CN 2022087321 W CN2022087321 W CN 2022087321W WO 2023060863 A1 WO2023060863 A1 WO 2023060863A1
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timing
output pin
output
state
pin
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PCT/CN2022/087321
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French (fr)
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刘万超
毛国梁
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南京宏泰半导体科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods

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  • the invention relates to a method and system for writing and debugging digital vectors, belonging to the technical field of electronics.
  • IC testing In IC testing, if it is distinguished by function, it can be divided into digital integrated circuits, analog integrated circuits and digital/analog hybrid integrated circuits. Among them, in digital integrated circuit testing, the complexity and task load of test program writing are relatively large, but the writing and debugging of digital vectors account for the most important part.
  • the present invention provides a method and system for automatically learning digital test vectors.
  • the present invention improves the writing and debugging efficiency of pattern vectors, and solves the difficulty of writing complex logic chips.
  • the problem of low efficiency It greatly improves the writing efficiency of digital vectors and reduces the difficulty of debugging.
  • a digital test vector automatic learning method comprising the following steps:
  • Step 1 Write a graphic file, which includes input pin timing and output pin timing, wherein the input pin timing is given by the device under test, and the output pin timing is set to a learning state.
  • Step 2 run the graphics file, and record the running status.
  • Step 3 read the recorded running state data, and obtain the state of the output pins recorded within a certain period of time in the running state data.
  • step 4 the state of the output pin obtained in step 3 is corrected for the timing sequence of the output pin in the graphics file run in step 2, to obtain the corrected output timing sequence, and then to obtain the corrected graphics file.
  • Step 5 execute steps 2-4 with the corrected graphic file obtained in step 4, until the corrected graphic file is within the set threshold range, complete the correction of the graphic file, and obtain the final graphic file.
  • the method of setting the timing of the output pin to the learning state, and the data bit of the timing of the output pin is described by "E".
  • step 4 the method for correcting the output pin timing in the graphic file run in step 2 is to perform the output pin state obtained in step 3 on the "E" on the data bit corresponding to the output pin timing in the graphic file Replace, get the corrected output pin timing.
  • the input pin timing in step 1 includes clock timing, driving data timing, and enable signal timing.
  • a digital test vector automatic learning system including a host computer, a graphic generator PG, a driver DRIVER, a comparator COMPARE, and a history memory HRAM, wherein:
  • the upper computer is used for writing graphic files, and sends the compiled graphic file information to the graphic generator PG.
  • Graphics files include input pin timing and output pin timing. It is used to generate the information reading control signal, read the output pin timing based on the output pin state recorded in the history memory HRAM through the information reading control signal, and output the output pin in the graphic file according to the output pin timing based on the output pin state The timing is corrected to obtain the corrected output pin timing, and then the corrected graphic file is obtained.
  • the graphic generator PG is used to analyze the graphic file sent by the host computer to obtain the timing of the input pin and the timing of the output pin, and send the timing of the input pin and the output pin to the driver DRIVER and the comparator COMPARE.
  • the driver DRIVER generates a driving signal to drive the device under test according to the timing of the input pin and the timing of the output pin.
  • the comparator COMPARE collects the state of the output pin generated by the device under test at this time, compares the state of the output pin with the timing of the output pin, fills the state of the output pin in the corresponding position in the timing of the output pin, and obtains the state based on the state of the output pin.
  • the timing of the output pins, and the timing of the input pins and the timing of the output pins based on the state of the output pins are given to the history memory HRAM.
  • the history memory HRAM is used to store the timing of input pins and the timing of output pins based on the state of output pins.
  • the host computer is a PC host computer.
  • the present invention has the following beneficial effects:
  • the present invention adopts the self-verification of the pattern graphic file, which greatly reduces the difficulty and efficiency of development.
  • the user only needs to write the input timing of the chip, write the specific comparison signal for the output pin, and then run the pattern graphic file to obtain the output characteristics of the device under test, and then check its function against the instruction manual of the device under test. Yes, thus greatly improving the development efficiency, reducing the writing of the characteristics of the chip output pins, and reducing the difficulty of writing.
  • Figure 1 shows the existing pattern graphic file debugging process.
  • Figure 2 shows the improved debugging process of the pattern graphics file.
  • Figure 3 is a schematic diagram of the pattern graphic file self-learning structure.
  • Figure 4 is a description of the pattern graphic file structure.
  • Fig. 5 is a schematic diagram of the improvement of the pattern graphic file.
  • Fig. 6 is a schematic diagram of the structure of pattern graphic file writing.
  • Fig. 7 is a flow chart of pattern graphic file writing.
  • a digital test vector automatic learning method as shown in Figure 2-7, comprises the following steps:
  • Step 1 Write a graphic file.
  • the graphic file includes input pin timing and output pin timing.
  • the input pin timing is given by the device under test, and the input pin timing includes clock timing, driving data timing, and enable signal timing.
  • the timing of the output pin is set to the learning state.
  • the user only needs to care about the input timing of the device under test, that is, only write the pin data such as Driver and Clk, and the output pin data does not need to be concerned.
  • Just write the learning state of the pin by running the pattern graphic file, and then modify the pattern source file through the pin state recorded in History Ram, so as to achieve a pattern file that conforms to the actual operation logic for users to use, which greatly reduces the development difficulty and debugging time.
  • Step 2 run the graphics file, and record the running status.
  • Step 3 read the recorded running state data, and obtain the state of the output pins recorded within a certain period of time in the running state data.
  • step 4 the state of the output pin obtained in step 3 is corrected for the timing sequence of the output pin in the graphics file run in step 2, to obtain the corrected output timing sequence, and then to obtain the corrected graphics file. Replace the "E" on the corresponding data bit of the output pin timing obtained in step 3 with the output pin timing in the graphics file to obtain the corrected output pin timing.
  • Step 5 Perform steps 2-4 on the corrected graphic file obtained in step 4, until the corrected graphic file is within the set threshold range, complete the correction of the graphic file, and obtain the final graphic file.
  • Pattern Head command which is used to define the external file information referenced by the Pattern file (such as: Tset Map, Pin
  • each timing code defines a set of information, including: period, time edge, waveform, etc.
  • each column represents a channel
  • each symbol represents the channel level
  • 1 is drive high level
  • 0 is drive low level, used for DUT input of the device under test
  • H compare high level Level
  • L compare low level, used to compare with DUT output
  • X means don't care.
  • FIG. 5 The schematic diagram on the left side of Figure 5 is the description of the traditional pattern file.
  • Each column is clock, data, and enable pins, and each line represents the level value at the current moment. It can be found that due to the difference in data, in a repeated serial sequence It is necessary to repeatedly fill in the bits of different data.
  • Figure 5 is a schematic diagram of the right measurement.
  • the improved method of this invention follows the method described in the traditional pattern file and improves it at the same time.
  • the data bits are described with a unified "E", which makes a complete serial timing of the description of the pattern graphics file reusable.
  • the pattern file adds load, move in, and move out instructions. After the test equipment parses the pattern file, it loads, moves in, and moves out the data controlled graphically by the upper computer at the corresponding time. At the same time, loop instructions can be used, and serial timing loops can be used only through graphical control of different data input and comparison.
  • the pattern graphics file is written.
  • the user only needs to write specific clock timing, drive data, and enable signals, and does not need to care about the characteristics of the chip output.
  • the self-learning function After running the pattern graphics file, you can get the output characteristics of the chip under the input of the target, which greatly reduces the difficulty of vector writing and debugging.
  • a kind of digital test vector automatic learning system as shown in Figure 3, comprises upper computer, graphic generator PG, driver DRIVER, comparator COMPARE, historical memory HRAM, and described upper computer is PC upper computer, wherein:
  • the upper computer is used for writing graphic files, and sends the compiled graphic file information to the graphic generator PG.
  • Graphics files include input pin timing and output pin timing. It is used to generate the information reading control signal, read the output pin timing based on the output pin state recorded in the history memory HRAM through the information reading control signal, and output the output pin in the graphic file according to the output pin timing based on the output pin state The timing is corrected to obtain the corrected output pin timing, and then the corrected graphic file is obtained.
  • the graphic generator PG is used to analyze the graphic file sent by the host computer to obtain the timing of the input pin and the timing of the output pin, and send the timing of the input pin and the output pin to the driver DRIVER and the comparator COMPARE.
  • the full name of the graphic generator PG is pattern generator, and its main duty is to generate pattern graphic file signals.
  • the driver DRIVER generates a driving signal to drive the device under test according to the timing of the input pin and the timing of the output pin.
  • the comparator COMPARE collects the state of the output pin generated by the device under test at this time, compares the state of the output pin with the timing of the output pin, fills the state of the output pin in the corresponding position in the timing of the output pin, and obtains the state based on the state of the output pin.
  • the timing of the output pins, and the timing of the input pins and the timing of the output pins based on the state of the output pins are given to the history memory HRAM.
  • the history memory HRAM is used to store the timing of input pins and the timing of output pins based on the status of output pins.
  • the full name of HRAM is History Random Access Memory. PC reads.
  • the output state does not need to be written according to the specific logic, just write the output pin data as "E", and then check the self-learning function when running the pattern graphic file to produce A pattern graphic file for the specific logic of the DUT.
  • the generated pattern graphics file can be used as the test standard of the device under test
  • Pattern graphic file self-learning uses the results captured in HRAM to correct failing vectors.
  • the failure vector can be updated with the learned vector, by changing the expect data to match the value retrieved from HRAM so that the expect data matches the comparator data, or by changing the expect data to X so that failures are ignored.
  • the storage space of the hardware board is limited.
  • the software adopts segmentation processing inside the software. For the user, what they see is to learn the entire pattern graphic file at one time. It greatly simplifies the user's operation process.
  • the self-learning function realized in this way greatly reduces the complexity of pattern graphic file writing and related debugging complexity. And it is also very convenient to use, the user only needs to choose whether to start changing the function, and then the corresponding function can be completed.

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Abstract

本发明公开了一种数字测试向量自动学习方法及系统，包括上位机、图形发生器PG、驱动器DRIVER、比较器COMPARE、历史存储器HRAM，编写图形文件，图形文件包括输入脚时序和输出脚时序，其中，输入脚时序由被测器件给出，输出脚时序设置为学习状态；运行图形文件，对运行状态进行记录；读取记录的运行状态数据，获取运行状态数据中某个时间内记录的输出管脚状态；将获取的输出管脚状态对运行的图形文件中的输出脚时序进行修正，得到修正后的输出时序，进而得到修正后的图形文件。本发明极大的提升了开发效率，也减少了对芯片输出脚特性的编写，降低了编写难度。

Description

一种数字测试向量自动学习方法及系统 技术领域
本发明涉及一种数字向量的编写和调试方法及系统，属于电子学技术领域。
背景技术
IC测试中按功能区分的话，分为数字集成电路、模拟集成电路和数/模混合集成电路。其中数字集成电路测试中，测试程序编写的复杂度和任务量是比较大的，然而其中数字向量的编写和调试又占了其最重要的一部分。
由于当前的芯片逻辑功能越来越复杂，所以要编写的测试case越来越多，不仅需要将被测器件的驱动脚逻辑编写出来，还需要将对应的输出逻辑编写出来。当面临新产品特性待验证的情况下，对芯片输出脚的功能验证就更复杂了，只能通过被测器件的理论状态编写对应的CLK、Driver和理论输出状态信号等的pattern，但是当输出时时序上存在一些波动时，在变化的附近时是非常难调试的,需要多次进行修改和调试，重复工作任务量非常大，其操作方法如图1所示，撰写pattern图形文件，运行，如果没用通过，在人工进行修改调试，直至运行通过。
由于现在技术中依赖测试人员手动的去反复的修改和验证，在这个过程中存在大量的重复工作，并且由于pattern时序比较复杂，及其容易出现错误，大大降低了开发效率。
发明内容
发明目的：为了克服现有技术中存在的不足，本发明提供一种数字测试向量自动学习方法及系统，本发明改进pattern向量的编写和调试效率，解决了复杂逻辑芯片的向量编写难度大，调试效率低的问题。极大提升了数字向量的编写效率、降低调试难度。
技术方案：为实现上述目的，本发明采用的技术方案为：
一种数字测试向量自动学习方法，包括以下步骤：
步骤1，编写图形文件，图形文件包括输入脚时序和输出脚时序，其中，输入脚时序由被测器件给出，输出脚时序设置为学习状态。
步骤2，运行图形文件，对运行状态进行记录。
步骤3，读取记录的运行状态数据，获取运行状态数据中某个时间内记录的输出管脚状态。
步骤4，将步骤3获取的输出管脚状态对步骤2运行的图形文件中的输出脚时序进行修正，得到修正后的输出时序，进而得到修正后的图形文件。
步骤5，将步骤4得到的修正后的图形文件执行步骤2-4，直至修正后的图形文件在设定 的阈值范围内，完成图形文件的修正，得到最终的图形文件。
优选的：将输出脚时序设置为学习状态的方法，将输出脚时序的数据位用“E”描述。
优选的：步骤4中对步骤2运行的图形文件中的输出脚时序进行修正的方法，将步骤3获取的输出管脚状态对图形文件中的输出脚时序相应的数据位上的“E”进行替换，得到修正后的输出脚时序。
优选的：步骤1中输入脚时序包括时钟时序、驱动数据时序、使能信号时序。
一种数字测试向量自动学习系统，包括上位机、图形发生器PG、驱动器DRIVER、比较器COMPARE、历史存储器HRAM，其中：
所述上位机用于图形文件的编写，并将编写后的图形文件信息发送给图形发生器PG。图形文件包括输入脚时序和输出脚时序。用于产生信息读取控制信号，通过信息读取控制信号读取历史存储器HRAM中记录的基于输出管脚状态的输出脚时序，根据基于输出管脚状态的输出脚时序对图形文件中的输出脚时序进行修正，得到修正后的输出脚时序，进而得到修正后的图形文件。
所述图形发生器PG用于根据上位机发送的图形文件进行解析，得到输入脚时序和输出脚时序，并将输入脚时序和输出脚时序发送给驱动器DRIVER和比较器COMPARE。
所述驱动器DRIVER根据输入脚时序和输出脚时序产生驱动信号对被测器件进行驱动。
所述比较器COMPARE采集被测器件此时产生的输出管脚状态，将输出管脚状态与输出脚时序进行比较，将输出管脚状态填充在输出脚时序中相应位置，得到基于输出管脚状态的输出脚时序，将输入脚时序和基于输出管脚状态的输出脚时序给历史存储器HRAM。
历史存储器HRAM用于存储输入脚时序和基于输出管脚状态的输出脚时序。
优选的：所述上位机为PC上位机。
本发明相比现有技术，具有以下有益效果：
1.本发明采用pattern图形文件的自验证，极大了降低了开发难度和效率。用户只需要编写芯片的输入时序，输出管脚编写特定的比较信号，然后通过运行该pattern图形文件，即可得出被测器件的输出特性，然后对照被测器件的说明手册检查其功能检查即可，从而极大的提升了开发效率，也减少了对芯片输出脚特性的编写，降低了编写难度。
2.芯片输出管脚特性在编写pattern图形文件时，可以不用关心，大大节省了pattern图形文件的编写时间和效率。
3.新产品特性观察，通过学习输出管脚特性，来了解新产品的特性。
4.减少了用户对pattern图形文件的调试任务，可通过输出pattern图形文件进行少量修改以到达预期效果。
附图说明
图1为现有的pattern图形文件调试流程。
图2为改进后的pattern图形文件调试流程。
图3为pattern图形文件自学习结构原理图。
图4为pattern图形文件结构说明。
图5为pattern图形文件改进示意图。
图6为pattern图形文件编写结构示意图。
图7为pattern图形文件编写流程图。
具体实施方式
下面结合附图和具体实施例，进一步阐明本发明，应理解这些实例仅用于说明本发明而不用于限制本发明的范围，在阅读了本发明之后，本领域技术人员对本发明的各种等价形式的修改均落于本申请所附权利要求所限定的范围。
一种数字测试向量自动学习方法，如图2-7所示，包括以下步骤：
步骤1，编写图形文件，图形文件包括输入脚时序和输出脚时序，其中，输入脚时序由被测器件给出，输入脚时序包括时钟时序、驱动数据时序、使能信号时序。输出脚时序设置为学习状态。Pattern图形文件编写时用户只用关心被测器件的输入时序即可，即只编写Driver、Clk等管脚数据，输出管脚数据可以不用关心，只需在需要关心的某个时间内，对输出管脚编写学习状态即可；通过运行pattern图形文件，然后通过History Ram记录的管脚状态，对pattern源文件进行修正，以达到符合实际运行逻辑的pattern文件供用户使用，大大降低了开发难度和调试时间。此外，大部分情况下，硬件支持的History Ram的深度是有限的，为了突破硬件的限制，在软件中进行软算法处理，使得用户不需要手动的去频繁设置参数以达到对cycle个数较大的pattern的学习。将输出脚时序设置为学习状态的方法，将输出脚时序的数据位用“E”描述。
步骤2，运行图形文件，对运行状态进行记录。
步骤3，读取记录的运行状态数据，获取运行状态数据中某个时间内记录的输出管脚状态。
步骤4，将步骤3获取的输出管脚状态对步骤2运行的图形文件中的输出脚时序进行修正，得到修正后的输出时序，进而得到修正后的图形文件。将步骤3获取的输出管脚状态对图形文件中的输出脚时序相应的数据位上的“E”进行替换，得到修正后的输出脚时序。
步骤5，将步骤4得到的修正后的图形文件执行步骤2-4，直至修正后的图形文件在设定的阈值范围内，完成图形文件的修正，得到最终的图形文件。
如图4所示，Pattern图形文件结构说明如下：
①为Pattern Head命令，用于定义Pattern文件所引用的外部文件信息(如：Tset Map,Pin
Map等)。
②是每行Pattern的指令名称。该指令控制PG执行的执行顺序。
③是每行Pattern的时序代号，每个时序代号定义了一组信息，包括：周期、时沿、波形等。
④是每行Pattern的通道数据，每列代表一个通道，每个符号代表通道电平，1为drive高电平，0为drive低电平，用于被测器件DUT输入；H为compare高电平，L为compare低电平，用于和DUT输出进行比较；X为不关心。
如图5所示，pattern文件改进示意图说明如下：
图5左测示意图是传统pattern文件描述，每列分别为时钟、数据、使能管脚，逐行表示各自当前时刻的电平值，可以发现，由于数据的不同，在一个重复的串行时序内需要反复的填写不同数据的bit位。
图5右测示意图本次发明改进后的方法，沿用传统pattern文件描述的方式同时加以改进。数据位用统一的“E”描述，使得pattern图形文件的描述的一个完整的串行时序具有复用性。Pattern文件新增装载、移入和移出指令，测试设备解析pattern文件后，在对应时刻装载、移入和移出上位机图形化控制的数据。同时可以使用循环指令，串行时序循环使用，仅需通过图形化控制不同数据输入和比较。
如图6所示，Pattern图形文件编写，用户在编写pattern图形文件的时候，只需要编写特定的时钟时序、驱动数据、使能信号，不需要关心芯片输出的特性。通过自学习功能，运行完pattern图形文件后，可以到的在目标的输入情况下，芯片的输出特性，大大降低了向量的编写和调试难度。
一种数字测试向量自动学习系统，如图3所示，包括上位机、图形发生器PG、驱动器DRIVER、比较器COMPARE、历史存储器HRAM，所述上位机为PC上位机，其中：
所述上位机用于图形文件的编写，并将编写后的图形文件信息发送给图形发生器PG。图形文件包括输入脚时序和输出脚时序。用于产生信息读取控制信号，通过信息读取控制信号读取历史存储器HRAM中记录的基于输出管脚状态的输出脚时序，根据基于输出管脚状态的输出脚时序对图形文件中的输出脚时序进行修正，得到修正后的输出脚时序，进而得到修正后的图形文件。
所述图形发生器PG用于根据上位机发送的图形文件进行解析，得到输入脚时序和输出脚时序，并将输入脚时序和输出脚时序发送给驱动器DRIVER和比较器COMPARE。图形发生 器PG全称为pattern generator，主要职责为产生pattern图形文件信号。
所述驱动器DRIVER根据输入脚时序和输出脚时序产生驱动信号对被测器件进行驱动。
所述比较器COMPARE采集被测器件此时产生的输出管脚状态，将输出管脚状态与输出脚时序进行比较，将输出管脚状态填充在输出脚时序中相应位置，得到基于输出管脚状态的输出脚时序，将输入脚时序和基于输出管脚状态的输出脚时序给历史存储器HRAM。
历史存储器HRAM用于存储输入脚时序和基于输出管脚状态的输出脚时序HRAM全称为History Random Access Memory,主要作用是对pattern实际运行的结果记录，将每个周期cycle的实际数据存储下来，供上位机读取。
用户编写被测器件的输入逻辑信号后，输出状态不需要按照特定逻辑编写，只需将输出管脚数据编写为“E”即可，然后运行pattern图形文件时勾选自学习功能，就可以生产该被测器件特定逻辑的pattern图形文件。可以将生成pattern图形文件作为被测器件的测试标准
Pattern图形文件自学习使用HRAM中捕获的结果来纠正失败向量。可以使用学习向量更新失败向量，通过更改expect数据以匹配从HRAM检索到的值，以便expect数据与比较器数据匹配，或者将expect数据更改为X，以便忽略失败。
一般情况下硬件板卡存储空间有限，为了支持时序个数特别多，存储空间限制的问题，软件内部采用了分段处理。对于用户来讲，看到的是一次性将整个pattern图形文件学习完成。大大简化了用户的操作流程。
通过该方式实现的自学习功能，大大降低了pattern图形文件编写的复杂度已经相关的调试复杂度。并且在使用上也非常的便利，用户只需选择是否开始改功能，即可完成相应的功能。
以上所述仅是本发明的优选实施方式，应当指出：对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (6)

  1. 一种数字测试向量自动学习方法，其特征在于，包括以下步骤：
    步骤1，编写图形文件，图形文件包括输入脚时序和输出脚时序，其中，输入脚时序由被测器件给出，输出脚时序设置为学习状态；
    步骤2，运行图形文件，对运行状态进行记录；
    步骤3，读取记录的运行状态数据，获取运行状态数据中某个时间内记录的输出管脚状态；
    步骤4，将步骤3获取的输出管脚状态对步骤2运行的图形文件中的输出脚时序进行修正，得到修正后的输出时序，进而得到修正后的图形文件；
    步骤5，将步骤4得到的修正后的图形文件执行步骤2-4，直至修正后的图形文件在设定的阈值范围内，完成图形文件的修正，得到最终的图形文件。
  2. 根据权利要求1所述数字测试向量自动学习方法，其特征在于：将输出脚时序设置为学习状态的方法，将输出脚时序的数据位用“E”描述。
  3. 根据权利要求2所述数字测试向量自动学习方法，其特征在于：步骤4中对步骤2运行的图形文件中的输出脚时序进行修正的方法，将步骤3获取的输出管脚状态对图形文件中的输出脚时序相应的数据位上的“E”进行替换，得到修正后的输出脚时序。
  4. 根据权利要求3所述数字测试向量自动学习方法，其特征在于：步骤1中输入脚时序包括时钟时序、驱动数据时序、使能信号时序。
  5. 一种基于权利要求1所述数字测试向量自动学习方法的自动学习系统，其特征在于：包括上位机、图形发生器PG、驱动器DRIVER、比较器COMPARE、历史存储器HRAM，其中：
    所述上位机用于图形文件的编写，并将编写后的图形文件信息发送给图形发生器PG；图形文件包括输入脚时序和输出脚时序；用于产生信息读取控制信号，通过信息读取控制信号读取历史存储器HRAM中记录的基于输出管脚状态的输出脚时序，根据基于输出管脚状态的输出脚时序对图形文件中的输出脚时序进行修正，得到修正后的输出脚时序，进而得到修正后的图形文件；
    所述图形发生器PG用于根据上位机发送的图形文件进行解析，得到输入脚时序和输出脚时序，并将输入脚时序和输出脚时序发送给驱动器DRIVER和比较器COMPARE；
    所述驱动器DRIVER根据输入脚时序和输出脚时序产生驱动信号对被测器件进行驱动；
    所述比较器COMPARE采集被测器件此时产生的输出管脚状态，将输出管脚状态与输出脚时序进行比较，将输出管脚状态填充在输出脚时序中相应位置，得到基于输出管脚状态的输出脚时序，将输入脚时序和基于输出管脚状态的输出脚时序给历史存储器HRAM；
    历史存储器HRAM用于存储输入脚时序和基于输出管脚状态的输出脚时序。
  6. 根据权利要求5所述自动学习系统，其特征在于：所述上位机为PC上位机。
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