WO2023060753A1 - Led芯片及其制备方法 - Google Patents

Led芯片及其制备方法 Download PDF

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Publication number
WO2023060753A1
WO2023060753A1 PCT/CN2021/138501 CN2021138501W WO2023060753A1 WO 2023060753 A1 WO2023060753 A1 WO 2023060753A1 CN 2021138501 W CN2021138501 W CN 2021138501W WO 2023060753 A1 WO2023060753 A1 WO 2023060753A1
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Prior art keywords
type electrode
type
insulating layer
electrode
led chip
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PCT/CN2021/138501
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English (en)
French (fr)
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王思博
李冬梅
廖汉忠
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淮安澳洋顺昌光电技术有限公司
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Priority claimed from CN202111198536.5A external-priority patent/CN113793889A/zh
Priority claimed from CN202122479725.1U external-priority patent/CN215988811U/zh
Application filed by 淮安澳洋顺昌光电技术有限公司 filed Critical 淮安澳洋顺昌光电技术有限公司
Priority to US18/256,173 priority Critical patent/US20240038936A1/en
Publication of WO2023060753A1 publication Critical patent/WO2023060753A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
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    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
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    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
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    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • the present disclosure relates to the technical field of semiconductor manufacturing, in particular, to an LED chip and a preparation method thereof.
  • LED As a new generation of light source, LED is widely used in technical fields such as lighting, display, backlight and even optical communication.
  • flip chip As a product with higher light efficiency, flip chip has been more and more favored by users. There are many structures in the flip chip process, and the process is complicated. Therefore, there are higher requirements and challenges for reliability.
  • the metal layer of the P-type metal electrode extends to the bottom of the N-type pad, and the two are separated from each other by the SiO 2 insulating layer to form the area shown by the dotted box.
  • the insulating layer breaks or cracks due to some reasons, it may lead to the connection between the P-type electrode and the N-type pad, resulting in leakage and reducing the reliability of the existing LED.
  • the first object of the present disclosure is to provide an LED chip.
  • the electrode design of the flip chip by improving the electrode design of the flip chip and adopting double-layer homogeneous electrodes, it can avoid electromigration of solder paste or breakage of the insulating layer. The problem of chip failure, thereby improving the reliability of the chip.
  • the second purpose of the present disclosure is to provide the above-mentioned LED chip preparation method, the method by adding the third N-type electrode and the third P-type electrode, and the third N-type electrode and the P-type pad have no space In the same way, there is no overlap between the third P-type electrode and the N-type pad in space. There is no possibility of contact between the two, and there is no possibility of breaking the insulating layer for any reason. Even the problem of leakage failure occurs.
  • the present disclosure provides an LED chip, comprising:
  • An epitaxial wafer with PN steps includes an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer;
  • At least one first P-type electrode located on the PN step and electrically connected to the P-type semiconductor layer;
  • At least one first N-type electrode located on the N-type semiconductor layer and electrically connected to the N-type semiconductor layer;
  • the first insulating layer covers the first N-type electrode, the PN step, the first P-type electrode and the N-type semiconductor layer, and is provided with a plurality of first through holes and a plurality of second through holes ;
  • a second P-type electrode disposed on the first insulating layer, and electrically connected to the first P-type electrode through the first through hole;
  • a second N-type electrode disposed on the first insulating layer, and electrically connected to the first N-type electrode through the second through hole;
  • a second insulating layer covering the second P-type electrode, the second N-type electrode and the first insulating layer, and having a plurality of third through holes and a plurality of fourth through holes;
  • a third P-type electrode disposed on the second insulating layer, and electrically connected to the second P-type electrode through the third through hole;
  • a third N-type electrode disposed on the second insulating layer, and electrically connected to the second N-type electrode through the fourth through hole;
  • a P-type pad disposed on the third P-type electrode, and electrically connected to the third P-type electrode;
  • the N-type welding pad is arranged on the third N-type electrode and electrically connected to the third N-type electrode.
  • At least a third N-type electrode is disposed between the N-type pad and the second P-type electrode in the direction of the vertical cross-sectional view;
  • At least the third P-type electrode is disposed between the P-type pad and the second N-type electrode.
  • the second layer directly below the N-type pad is a second insulating layer and/or a second N-type electrode
  • the projection on the horizontal plane of the N-type pad is located within the projection on the horizontal plane of the third N-type electrode.
  • the LED chip further includes a third insulating layer, and the third insulating layer covers the third P-type electrode and the third N-type electrode;
  • a plurality of fifth through holes and sixth through holes are provided on the third insulating layer
  • the P-type pad is electrically connected to the third P-type electrode through the fifth through hole
  • the N-type pad is electrically connected to the third N-type electrode through the sixth through hole.
  • the distance between the third P-type electrode and the third N-type electrode is greater than 15 ⁇ m;
  • the sum of the areas of the third P-type electrode and the third N-type electrode accounts for 50%-75% of the area of the entire LED chip
  • the sum of the areas of the P-type pad and the N-type pad accounts for 30%-55% of the area of the entire LED chip.
  • the shortest distance between the second P-type electrode region and the side of the PN step is D 1
  • the shortest distance between the third N-type electrode and the side of the PN step is D 2
  • the The shortest distance between the N-type pad and the side of the PN step is D 3 , and D 1 ⁇ D 2 ⁇ D 3 ;
  • D 1 >5 ⁇ m
  • D 2 >8 ⁇ m
  • D 3 >15 ⁇ m
  • a plurality of the first P-type electrodes are disposed on the PN step at intervals; and a plurality of the first N-type electrodes are disposed on the N-type semiconductor layer at intervals.
  • the first insulating layer is silicon oxide and a DBR reflective layer
  • the thickness of the first insulating layer is 2 ⁇ m to 7 ⁇ m, and further the thickness is 3.5 ⁇ m to 5.5 ⁇ m.
  • the second insulating layer and/or the third insulating layer include at least one of silicon oxide, silicon nitride, and silicon oxynitride;
  • the thickness of the second insulating layer and/or the third insulating layer is
  • the preparation method of the LED chip provided by the present disclosure includes the following steps:
  • the disclosure relates to an LED chip. Compared with the conventional ODR structure, by improving the electrode design of the flip chip, by adding a third N-type electrode and a third P-type electrode, and the third N-type electrode and the P-type pad There is no overlap in space. Similarly, there is no overlap in space between the third P-type electrode and the N-type pad. There is no possibility of contact between the two. , The problem of leakage failure due to the interconnection of N-type electrodes, thereby improving the reliability of the chip.
  • Figure 1 is a cross-sectional view of an existing ODR structure flip-chip LED chip
  • FIG. 2 is a schematic plan view of the LED chip provided by an embodiment of the present disclosure
  • Fig. 3 is a cross-sectional view of the LED chip provided by the embodiment of the present disclosure cut along the mode A of Fig. 1;
  • Fig. 4 is a cross-sectional view of the LED chip provided by the embodiment of the present disclosure cut along the way B in Fig. 1;
  • FIG. 5 is a schematic diagram of the distances between the third P-type electrode, the third N-type electrode, the fourth P-type electrode, and the fourth N-type electrode of the LED chip provided by the embodiment of the present disclosure;
  • FIG. 6 is a schematic plan view of the LED chip provided by another embodiment of the present disclosure.
  • 300-current blocking layer 400-current spreading layer; 510-first P-type electrode;
  • 1100-P type pad 1200-N type pad; 1300-third insulation layer.
  • Figure 2 is a schematic plan view of the LED chip provided by the embodiment of the present disclosure
  • Figure 3 is a cross-sectional view of the LED chip provided by the embodiment of the present disclosure along the way A of Figure 1;
  • the LED chip provided by the embodiment of the present disclosure includes:
  • An epitaxial wafer with PN steps 211 the epitaxial wafer includes an N-type semiconductor layer 210, a light emitting layer 220 and a P-type semiconductor layer 230;
  • At least one first P-type electrode 510 located on the PN step 211, and electrically connected to the P-type semiconductor layer 230;
  • At least one first N-type electrode 520 located on the N-type semiconductor layer 210 and electrically connected to the N-type semiconductor layer 210;
  • the first insulating layer 600 covers the first N-type electrode 520, the PN step 211, the first P-type electrode 510 and the N-type semiconductor layer 210, and is provided with a plurality of first through holes 511 and A plurality of second through holes 521;
  • the second P-type electrode 710 is disposed on the first insulating layer 600 and is electrically connected to the first P-type electrode 510 through the first through hole 511;
  • the second N-type electrode 720 is disposed on the first insulating layer 600 and is electrically connected to the first N-type electrode 520 through the second through hole 521;
  • the second insulating layer 800 covers the second P-type electrode 710, the second N-type electrode 720 and the first insulating layer 600, and is provided with a plurality of third through holes 711 and a plurality of fourth through holes 721;
  • the third P-type electrode 910 is disposed on the second insulating layer 800 and electrically connected to the second P-type electrode 710 through the third through hole 711;
  • the third N-type electrode 920 is disposed on the second insulating layer 800 and electrically connected to the second N-type electrode 720 through the fourth through hole 721;
  • the P-type pad 1100 is disposed on the third P-type electrode 910 and electrically connected to the third P-type electrode 910;
  • the N-type pad 1200 is disposed on the third N-type electrode 920 and is electrically connected to the third N-type electrode 920 .
  • the epitaxial layer 200 includes a PN step 211, the upper step surface of the PN step 211 is the P-type semiconductor layer 230, the lower step surface is the N-type semiconductor layer 210, and the upper step surface and the lower step surface are The side connections form the PN steps 211;
  • the substrate 100 may be a sapphire substrate 100, but it is not limited thereto.
  • a patterned substrate 100 can also be selected.
  • the material of the N-type semiconductor layer 210 can be N-type doped gallium nitride
  • the material of the P-type semiconductor layer 230 can be P-type doped gallium nitride, but not limited to these two semiconductors type.
  • the light-emitting layer 220 includes alternately stacked quantum wells and quantum barriers, but is not limited thereto.
  • the light emitting layer 220 includes but not limited to a red light emitting layer 220 , a yellow light emitting layer 220 , a green light emitting layer 220 or a blue light emitting layer 220 .
  • the quantum wells include but not limited to InGaN quantum wells or AlInGaN quantum wells.
  • the current blocking layer 300 includes but not limited to SiO 2 .
  • the current spreading layer 400 includes but not limited to one of ITO, ZITO, ZIO, GIO, ZTO, FTO, AZO and GZO.
  • the thickness of the current spreading layer 400 is for example can be 200 Furthermore, the current spreading layer 400 can be deposited by magnetron sputtering or evaporation.
  • the current spreading layer 400 accounts for 70%-90% of the area of the LED chip.
  • a plurality of the first P-type electrodes 510 and a plurality of first N-type electrodes 520 are deposited on the surface of the chip, and the first P-type electrodes and the first N-type electrodes 520 Finger-shaped electrodes (Finger electrodes) may be used.
  • the first P-type electrode 510 and the first N-type electrode 520 are isolated from each other, and have an isolation groove.
  • the electrode structure of the first P-type electrode 510 and the first N-type electrode 520 can adopt metal electrode structures such as Cr/Al/Ti/Ni/Pt/Au, and can be a single metal layer or a composite layer of several metals .
  • the second electrode with the same polarity as the pad layer must be sandwiched between the second electrode layer and the pad layer, so that the second electrode layer and the pad layer There is no contact possibility on the pad layer.
  • at least a third N-type electrode 920 is disposed between the N-type pad 1200 and the second P-type electrode 710; and/or, the P-type pad 1100 and the second N-type electrode
  • At least the third P-type electrode 910 is disposed between 720 .
  • the second layer directly under the N-type pad is the second insulating layer 800 and/or the second N-type electrode 720 .
  • the projection on the horizontal plane of the N-type pad is located within the projection on the horizontal plane of the third N-type electrode 920, so as to ensure that there is no space between the third N-type electrode 920 and the P-type pad 1100.
  • the third P-type electrode 910 and the N-type pad 1200 do not have any overlap in space. There is no possibility of contact between the two, and there is no P and N-type electrodes with different polarities caused by silicon oxide fracture for any reason. The problem of leakage failure occurs due to the interconnection of electrodes, thereby improving the reliability of the chip.
  • an insulating layer can be further coated outside the third electrode layer.
  • the LED chip further includes a third insulating layer 1300, and the third insulating layer 1300 covers the third P-type electrode 910 and the third electrode.
  • the third N-type electrode 920; the third insulating layer 1300 is provided with a plurality of fifth through holes and sixth through holes; the P-type pad 1100 is connected to the third P-type through the fifth through hole.
  • the electrode 910 is electrically connected, and the N-type pad 1200 is electrically connected to the third N-type electrode 920 through the sixth through hole.
  • the distance between the third P-type electrode 910 and the third N-type electrode 920 is greater than 15 ⁇ m;
  • the sum of the areas of the third P-type electrode 910 and the third N-type electrode 920 accounts for 50%-75% of the area of the entire LED chip, such as 50%, 60%, 70%, 75%.
  • the sum of the areas of the P-type pad 1100 and the N-type pad 1200 accounts for 30%-55% of the area of the entire LED chip, such as 30%, 40%, 45%, and 55%.
  • the shortest distance between the region of the second P-type electrode 710 and the side of the PN step 211 is D 1
  • the shortest distance between the third N-type electrode 920 and the side of the PN step 211 is D 2.
  • the shortest distance between the N-type pad 1200 and the side of the PN step 211 is D 3 , and D 1 ⁇ D 2 ⁇ D 3 ;
  • D 1 >5 ⁇ m
  • D 2 >8 ⁇ m
  • D 3 >15 ⁇ m
  • a plurality of the first P-type electrodes 510 are arranged at intervals on the PN step 211; a plurality of the first N-type electrodes 520 are arranged at intervals on the N-type semiconductor layer 210, further, the first There are one or more two N-electrode regions, and there are gaps between the second N-electrode region and the second P-electrode region respectively, wherein part of the second N-electrode region is located on the PN step 211 .
  • the first insulating layer 600 is silicon oxide and a DBR reflective layer.
  • the DBR reflective layer includes but is not limited to any one or more of SiO 2 , TiO 2 and Ti 3 O 5 , such as SiO 2 and/or TiO 2 , or SiO 2 and/or Ti 3 O 5 . Furthermore, the DBR reflective layer may be formed by alternately depositing SiO 2 and Ti 3 O 5 .
  • first through hole 511 through the first P-type electrode 510 and the second through hole 521 through the first N-type electrode 520 are obtained by etching on the DBR reflective layer.
  • the second P-type electrode 710 is formed by electron beam evaporation at the through hole 511
  • the second N-type electrode 720 is formed by electron beam evaporation at the second through hole 521 .
  • the second P-type electrode 710 and the second N-type electrode 720 form an ODR structure with the DBR reflective layer, so that the reflectivity of this layer of electrodes is between 60% and 95%, and the angle of this layer of metal electrodes is required to be 30° to 75°.
  • the thickness of the first insulating layer 600 is 2 ⁇ m ⁇ 7 ⁇ m, such as 2 ⁇ m, 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, and further the thickness is 3.5 ⁇ m ⁇ 5.5 ⁇ m.
  • the second insulating layer 800 and/or the third insulating layer 1300 include at least one of silicon oxide, silicon nitride, and silicon oxynitride; for example, silicon oxide and/or silicon nitride , or, silicon nitride and/or silicon oxynitride.
  • the thickness of the second insulating layer 800 and/or the third insulating layer 1300 is For example for
  • the P-type pad 1100 and the N-type pad 1200 may use one of Ti, Al, Pt, Ni, Au metal or a combination of several metal layers.
  • the thickness of Al is The thickness of Pt is The thickness of Ti is The thickness of Ni is The thickness of Au is the thickness of Al.
  • the P-type pad 1100 and the N-type pad 1200 may be bump electrodes, and the electrode composition is Sn.
  • the bump electrodes can be made by printing, electroplating or vapor deposition and other methods.
  • the height of the bump electrode is ⁇ 5 ⁇ m, and the height of the solder paste is ⁇ 20 ⁇ m;
  • the sum of the areas of the P-type pad 1100 and the N-type pad 1200 accounts for 30% to 55% of the area of the entire LED chip, such as 50%, 60%, and 70%. , 75%.
  • the sum of the areas of the third P-type electrode 910 and the third N-type electrode 920 is greater than the sum of the areas of the P-type pad 1100 and the N-type pad 1200 .
  • the embodiment of the present disclosure also provides a specific preparation method of the LED chip, including the following steps:
  • a substrate 100 is provided, and an N-type semiconductor layer 210, a light-emitting layer 220, and a P-type semiconductor layer 230 are sequentially fabricated on the substrate 100 to form an epitaxial layer 200;
  • a first through hole 511 and a second through hole 521 are respectively obtained by photolithography above the first P-type electrode 510 and the first N-type electrode 520 , and deposited at the first through hole 511
  • the second P-type electrode 710, the first through hole 511 and the second through hole 521 are separated from each other without any extension crossing;
  • the second N-type electrode 720 is deposited at the second through hole 521, and the second P-type electrode 710 and the second N-type electrode 720 are isolated from each other, the second P-type electrode 710 communicates with the first P-type electrode 510 through the first pass, and the second N-type electrode 720 communicates with the first P-type electrode 510 through the first pass.
  • the first N-type electrode 520 is connected so that the reflectivity of the electrode is 60%-95%, and the angle of the metal electrode of this layer is required to be 30°-75°;
  • the second insulating layer 800 deposit the second insulating layer 800, the thickness is And use yellow light and ICP dry etching above the second P-type electrode 710 and the second N-type electrode 720 to obtain a third through hole 711 and a fourth through hole 721 respectively, and on the third through hole
  • the third P-type electrode 910 is deposited at the hole 711
  • the third N-type electrode 920 is deposited at the fourth through hole 721, so that the reflectivity of the electrode is 60% to 95%.
  • the metal electrode angle of this layer The requirement is 30° ⁇ 75°;
  • the third P-type electrode 910 and the third N-type electrode 920 are isolated from each other, and the second P-type electrode 710 extends below the third N-type electrode 920, and except for the third through hole 711 and the fourth through hole 721, the remaining front chip of the second insulating layer 800 has no breaks, so as to ensure that the upper third N-type electrode 920 and the lower layer extend to the third N-type electrode 920.
  • the second P-type electrode 710 is separated to cut off the leakage path;
  • the P-type pad 1100 is interconnected with the third P-type electrode 910 through the fifth through hole of the third insulating layer 1300, and the N-type pad 1200 is interconnected through the fifth through hole of the third insulating layer 1300.
  • the sixth through hole realizes interconnection with the third N-type electrode 920, while the surface of the fourth P-type pad 1100 facing the substrate 100 is only connected to the third P-type electrode 910, and the surface of the N-type pad 1200 facing the substrate 100 It is only connected to the third N-type electrode 920 .
  • no surface of the P-type pad 1100 is in direct or indirect contact with the third N-type electrode 920 , and no extension intersects. The same applies to the N-type pad 1200 and the third P-type electrode 910 . Therefore, there is no leakage failure problem due to any PN-type electrode interconnection with different polarities due to silicon oxide breakage.
  • Another embodiment of the present disclosure also provides a specific method for preparing the LED chip.
  • the structure schematic diagram of the prepared LED chip is shown in FIG.
  • the pads are in the form of NP pad group 1000 as shown in the figure, and the size of each pad is 688 ⁇ m*244 ⁇ m.
  • the present disclosure provides an LED chip.
  • the disclosure improves the chip reliability by improving the electrode design of the flip chip and adopting double-layer homogeneous electrodes to avoid the problem of chip failure caused by electromigration of solder paste or breakage of the insulating layer.

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Abstract

本公开涉及半导体制造技术领域，具体而言，涉及一种LED芯片及其制备方法。包括：衬底、外延层、电流阻挡层、电流扩展层、第一P型电极、第一N型电极、第一绝缘层、第二P型电极、第二N型电极、第二绝缘层、第三P型电极、第三N型电极、P型焊盘和N型焊盘。该LED芯片通过改进倒装芯片的电极设计，通过增加第三N型电极和第三P型电极，且第三N型电极与P型焊盘在空间上无任何重叠，同理第三P型电极与N型焊盘在空间上也无任何重叠，二者无接触可能，不存在因为任何原因导致氧化硅断裂，而导致极性不同的P、N型电极互连而发生漏电失效的问题，从而提高了芯片的可靠性。

Description

LED芯片及其制备方法
相关申请的交叉引用
本申请要求于2021年10月14日提交中国专利局的申请号为2021111985365、名称为“LED芯片及其制备方法”的中国专利申请的优先权，以及申请号为2021224797251、名称为“LED芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体制造技术领域，具体而言，涉及LED芯片及其制备方法。
背景技术
LED作为新一代光源，被广泛应用在照明、显示、背光乃至光通信等技术领域。倒装芯片作为更高光效的产品已经越来越受到用户的青睐。倒装芯片制程结构较多，工艺制程复杂。因此，对可靠性有了更高的要求和挑战。
常规的ODR结构，如图1所示，P型金属电极金属层延伸至N型焊盘下方，二者中间通过SiO 2绝缘层相互隔离，形成如虚线方框所示的区域。当绝缘层因为某些原因导致断裂或出现裂痕，均可能导致P型电极和N型焊盘连通，导致漏电的发生，使现有LED使用时的可靠性降低。
发明内容
有鉴于此，本公开的第一目的在于提供一种LED芯片，相比常规的ODR结构，通过改进倒装芯片的电极设计，采用双层同质电极，避免锡膏电迁移或绝缘层断裂导致的芯片失效问题，从而提高了芯片的可靠性。
本公开的第二目的在于提供如上所述的LED芯片的制备方法，该方法通过增加第三N型电极和第三P型电极，且第三N型电极与P型焊盘在空间上无任何重叠，同理第三P型电极与N型焊盘在空间上也无任何重叠，二者无接触可能，不存在因为任何原因导致绝缘层断裂，而导致极性不同的P、N型电极互连而发生漏电失效的问题。
为了实现本公开的上述目的，特采用以下技术方案：
本公开提供了一种LED芯片，包括：
衬底；
具有PN台阶的外延片，所述外延片包括N型半导体层、发光层和P型半导体层；
至少一个第一P型电极，位于所述PN台阶上，并与所述P型半导体层电性连接；
至少一个第一N型电极，位于所述N型半导体层上与所述N型半导体层电性连接；
第一绝缘层，覆盖所述第一N型电极、所述PN台阶、所述第一P型电极以及所述N型半导体层，并设置有多个第一通孔和多个第二通孔；
第二P型电极，设置于所述第一绝缘层上，通过所述第一通孔与所述第一P型电极电性连接；
第二N型电极，设置于所述第一绝缘层上，通过所述第二通孔与所述第一N型电极电性连接；
第二绝缘层，覆盖所述第二P型电极、所述第二N型电极和所述第一绝缘层，并设置有多个第三通孔和多个第四通孔；
第三P型电极，设置于第二绝缘层上，通过所述第三通孔与所述第二P型电极电性连接；
第三N型电极，设置于第二绝缘层上，通过所述第四通孔与所述第二N型电极电性连接；
P型焊盘，设置于所述第三P型电极上，并与第三P型电极电性连接；
N型焊盘，设置于所述第三N型电极上，并于第三N型电极电性连接。
本公开一实施方式中，在垂直剖视图方向，所述N型焊盘与所述第二P型电极之间至少设置有第三N型电极；
和/或，所述P型焊盘与所述第二N型电极之间至少设置有所述第三P型电极。
本公开一实施方式中，所述N型焊盘正下方的第二层为第二绝缘层和/或第二N型电极；
进一步地，所述N型焊盘的水平面上的投影位于所述第三N型电极在水平方面上的投影内。
本公开一实施方式中，所述LED芯片还包括第三绝缘层，所述第三绝缘层覆盖所述第三P型电极和所述第三N型电极；
所述第三绝缘层上设置有多个第五通孔和第六通孔；
所述P型焊盘通过所述第五通孔与所述第三P型电极电性连接，所述N型焊盘通过所述第六通孔与所述第三N型电极电性连接。
本公开一实施方式中，所述第三P型电极和所述第三N型电极的距离大于15μm；
和/或；所述第三P型电极和所述第三N型电极的面积和占整个所述LED芯片的面积的50％～75％；
和/或；所述P型焊盘和所述N型焊盘的面积和占整个所述LED芯片的面积的30％～55％。
本公开一实施方式中，所述第二P型电极区域与所述PN台阶侧面的最短距离为D 1，所述第三N型电极与所述PN台阶侧面的最短距离为D 2，所述N型焊盘与所述PN台阶侧面的最短距离为D 3，且D 1＜D 2＜D 3；
进一步地，所述D 1＞5μm，D 2＞8μm，D 3＞15μm。
本公开一实施方式中，多个所述第一P型电极间隔设置于所述PN台阶上；多个所述第一N型电极间隔设置于所述N型半导体层上。
本公开一实施方式中，一个或多个所述第二N型电极分别与所述第二P型电极之间具有间隙，其中部分所述第二N型电极位于PN台阶之上。
本公开一实施方式中，所述第一绝缘层为氧化硅和DBR反射层；
进一步地，所述第一绝缘层的厚度为2μm～7μm，更进一步的厚度为3.5μm～5.5μm。
本公开一实施方式中，所述第二绝缘层和/或所述第三绝缘层包括氧化硅、氮化硅和氮氧化硅中的至少一种；
进一步地，所述第二绝缘层和/或所述第三绝缘层的厚度为
Figure PCTCN2021138501-appb-000001
本公开所提供的所述的LED芯片的制备方法，包括以下步骤：
(a)、提供一衬底，并在所述衬底上依次沉积N型半导体层、发光层和P型半导体层以形成外延层；
(b)、在所述外延层上沉积SiO 2，并通过光刻得到电流阻挡层，再沉积得到电流扩展层，通过刻蚀得到PN台阶；
(c)、将多个第一P型电极和多个第一N型电极相间分布沉积于芯片表面，然后沉积第一绝缘层；
(d)、在所述第一P型电极和所述第一N型电极上方光刻分别得到第一通孔和第二通孔，并在所述第一通孔处沉积第二P型电极，在所述第二通孔处沉积第二N型电极，所述第二P型电极和所述第二N型电极彼此隔离；
(e)、沉积第二绝缘层，并在所述第二P型电极和所述第二N型电极上方光刻分别得到第三通孔和第四通孔，并在所述第三通孔处沉积第三P型电极，在所述第四通孔处沉积第三N型电极，所述第三P型电极和所述第三N型电极彼此隔离，且所述第二P型电极延伸至所述第三N型电极的下方；
(f)、沉积第三绝缘层，并在所述第三P型电极和所述第三N型电极上方光刻分别得到第五通孔和第六通孔，在所述第五通孔处沉积P型焊盘，在所述第六通孔处沉积N型焊盘。
与现有技术相比，本公开的有益效果为：
本公开涉及了一种LED芯片，相比常规的ODR结构，通过改进倒装芯片的电极设计， 通过增加第三N型电极和第三P型电极，且第三N型电极与P型焊盘在空间上无任何重叠，同理第三P型电极与N型焊盘在空间上也无任何重叠，二者无接触可能，不存在因为任何原因导致氧化硅断裂，而导致极性不同的P、N型电极互连而发生漏电失效的问题，从而提高了芯片的可靠性。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为现有ODR结构倒装LED芯片剖面图；
图2为本公开实施例所提供的LED芯片的平面结构示意图；
图3为本公开实施例所提供的LED芯片沿图1的方式A切割的剖面图；
图4为本公开实施例所提供的LED芯片沿图1的方式B切割的剖面图；
图5为本公开实施例所提供的LED芯片第三P型电极、第三N型电极、第四P型电极、第四N型电极的距离示意图；
图6为本公开又一实施例所提供的LED芯片的平面结构示意图。
附图标记：
100-衬底；                 200-外延层；             210-N型半导体层；
211-PN台阶；               220-发光层；             230-P型半导体层；
300-电流阻挡层；           400-电流扩展层；         510-第一P型电极；
511-第一通孔；             520-第一N型电极；        521-第二通孔；
600-第一绝缘层；           710-第二P型电极；        711-第三通孔；
720-第二N型电极；          721-第四通孔；           800-第二绝缘层；
910-第三P型电极；          920-第三N型电极；        1000-NP焊盘组；
1100-P型焊盘；             1200-N型焊盘；           1300-第三绝缘层。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本公开的实 施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
图2为本公开实施例所提供的LED芯片的平面结构示意图；图3为本公开实施例所提供的LED芯片沿图1的方式A切割的剖面图，图4为本公开实施例所提供的LED芯片沿图1的方式B切割的剖面图。如图2和图3所示本公开实施例提供的LED芯片，包括：
衬底100；
具有PN台阶211的外延片，所述外延片包括N型半导体层210、发光层220和P型半导体层230；
至少一个第一P型电极510，位于所述PN台阶211上，并与所述P型半导体层230电性连接；
至少一个第一N型电极520，位于所述N型半导体层210上与所述N型半导体层210电性连接；
第一绝缘层600，覆盖所述第一N型电极520、所述PN台阶211、所述第一P型电极510以及所述N型半导体层210，并设置有多个第一通孔511和多个第二通孔521；
第二P型电极710，设置于所述第一绝缘层600上，通过所述第一通孔511与所述第一P型电极510电性连接；
第二N型电极720，设置于所述第一绝缘层600上，通过所述第二通孔521与所述第一N型电极520电性连接；
第二绝缘层800，覆盖所述第二P型电极710、所述第二N型电极720和所述第一绝缘层600，并设置有多个第三通孔711和多个第四通孔721；
第三P型电极910，设置于第二绝缘层800上，通过所述第三通孔711与所述第二P型电极710电性连接；
第三N型电极920，设置于第二绝缘层800上，通过所述第四通孔721与所述第二N型电极720电性连接；
P型焊盘1100，设置于所述第三P型电极910上，并与第三P型电极910电性连接；
N型焊盘1200，设置于所述第三N型电极920上，并于第三N型电极920电性连接。
其中，所述外延层200包括PN台阶211，所述PN台阶211的上台阶面为P型半导体层230，下台阶面为N型半导体层210，所述上台阶面和所述下台阶面之间连接形成PN台阶211的侧面；
在设计该LED芯片的过程中，通过增加第三N型电极920和第三P型电极910，且第三N型电极920与P型焊盘1100在垂直空间或其他任何方向上无任何重叠，同理第三P 型电极910与N型焊盘1200在垂直空间或其他任何方向上也无任何重叠，二者无接触可能，不存在因为任何因绝缘层断裂，而导致极性不同的P、N型电极互连而发生漏电失效的问题，从而提高了芯片的可靠性。
进一步地，所述衬底100可以选择蓝宝石衬底100，但是也不限于此。此外，也可以选择图形化的衬底100。
进一步地，所述N型半导体层210的材质可以为N型掺杂的氮化镓，所述P型半导体层230的材质可以为P型掺杂的氮化镓，但不仅限于这两种半导体类型。
进一步地，所述发光层220包括交替层叠设置的量子阱和量子垒，但是不限于此。所述发光层220包括但不限于红光发光层220、黄光发光层220、绿光发光层220或蓝光发光层220。所述量子阱包括但不限于InGaN量子阱或AlInGaN量子阱。
进一步地，所述电流阻挡层300包括但不限于SiO 2。
进一步地，所述电流扩展层400包括但不限于ITO、ZITO、ZIO、GIO、ZTO、FTO、AZO和GZO中的一种。
进一步地，所述电流扩展层400包括的厚度为
Figure PCTCN2021138501-appb-000002
例如可以为
Figure PCTCN2021138501-appb-000003
200
Figure PCTCN2021138501-appb-000004
更进一步地，所述电流扩展层400可以通过磁控溅射或蒸镀的方式进行沉积得到。
在本公开一实施方式中，所述电流扩展层400占所述LED芯片的面积的70％～90％。
进一步地，根据图案形成的光刻胶形貌，在芯片表面沉积多个所述第一P型电极510和多个第一N型电极520，第一型P型电极和第一N型电极520可以为手指形状电极(Finger电极)。且第一P型电极510和第一N型电极520之间相互隔离，具有一隔离槽。进一步地，第一P型电极510和第一N型电极520的电极结构可采用Cr/Al/Ti/Ni/Pt/Au等金属的电极结构，可以为单一金属层或几种金属的复合层。
在本公开一实施方式中，为了提高LED芯片的使用稳定性，保证第二电极层与焊盘层之间，必定夹着与焊盘层相同极性的第二电极，使第二电极层和焊盘层无接触可能。具体地，所述N型焊盘1200与所述第二P型电极710之间至少设置有第三N型电极920；和/或，所述P型焊盘1100与所述第二N型电极720之间至少设置有所述第三P型电极910。更进一步地，所述N型焊盘正下方的第二层为第二绝缘层800和/或第二N型电极720。
进一步地，所述N型焊盘的水平面上的投影位于所述第三N型电极920在水平方面上的投影内，以确保第三N型电极920与P型焊盘1100在空间上无任何重叠，同理第三P型电极910与N型焊盘1200在空间上也无任何重叠，二者无接触可能，不存在因为任何原因导致氧化硅断裂，而导致极性不同的P、N型电极互连而发生漏电失效的问题，从而提高了芯片的可靠性。
本公开一实施方式中，可以再第三电极层外进一步包覆绝缘层所述LED芯片还包括第三绝缘层1300，所述第三绝缘层1300覆盖所述第三P型电极910和所述第三N型电极920；所述第三绝缘层1300上设置有多个第五通孔和第六通孔；所述P型焊盘1100通过所述第五通孔与所述第三P型电极910电性连接，所述N型焊盘1200通过所述第六通孔与所述第三N型电极920电性连接。
本公开一实施方式中，一个或多个所述第二N型电极720分别与所述第二P型电极710之间具有间隙，其中部分所述第二N型电极720位于PN台阶211之上。
本公开一实施方式中，如图5所示的P3，所述第三P型电极910和所述第三N型电极920的距离大于15μm；
所述第三P型电极910和所述第三N型电极920的面积和占整个所述LED芯片的面积的50％～75％，例如50％、60％、70％、75％。
所述P型焊盘1100和所述N型焊盘1200的面积和占整个所述LED芯片的面积的30％～55％，例如30％、40％、45％、55％。
本公开一实施方式中，所述第二P型电极710区域与所述PN台阶211侧面的最短距离为D 1，所述第三N型电极920与所述PN台阶211侧面的最短距离为D 2，所述N型焊盘1200与所述PN台阶211侧面的最短距离为D 3，且D 1＜D 2＜D 3；
进一步地，所述D 1＞5μm，D 2＞8μm，D 3＞15μm。
进一步地，多个所述第一P型电极510间隔设置于所述PN台阶211上；多个所述第一N型电极520间隔设置于所述N型半导体层210上，更进一步地，第二N电极的区域有一个或多个，所述第二N电极区的域分别与第二P电极区域之间具有间隙，其中部分第二N电极区域位于PN台阶211之上。
本公开一实施方式中，所述第一绝缘层600为氧化硅和DBR反射层。
进一步地，所述DBR反射层包括但不限于SiO 2、TiO 2和Ti 3O 5中的任一种或多种，例如为SiO 2和/或TiO 2，或者是，SiO 2和/或Ti 3O 5。更进一步地，所述DBR反射层可以为交替沉积SiO 2和Ti 3O 5形成。
进一步地，在所述DBR反射层上刻蚀得到直通所述第一P型电极510的第一通孔511和直通所述第一N型电极520的第二通孔521，在所述第一通孔511处电子束蒸发形成第二P型电极710，在所述第二通孔521处电子束蒸发形成第二N型电极720。第二P型电极710和第二N型电极720与DBR反射层形成ODR结构，使得该层电极的反射率在60％～95％之间，该层金属电极角度要求为30°～75°。
进一步地，所述第一绝缘层600的厚度为2μm～7μm、例如2μm、3μm、4μm、5μm、6μm、7μm，更进一步的厚度为3.5μm～5.5μm。
本公开一实施方式中，所述第二绝缘层800和/或所述第三绝缘层1300包括氧化硅、氮化硅和氮氧化硅中的至少一种；例如氧化硅和/或氮化硅，或者是，氮化硅和/或氮氧化硅。
进一步地，所述第二绝缘层800和/或所述第三绝缘层1300的厚度为
Figure PCTCN2021138501-appb-000005
例如为
Figure PCTCN2021138501-appb-000006
进一步地，所述P型焊盘1100和N型焊盘1200可以使用Ti、Al、Pt、Ni、Au金属中的一种或者几种金属层的组合。更进一步地，Al的厚度为
Figure PCTCN2021138501-appb-000007
Pt的厚度为
Figure PCTCN2021138501-appb-000008
Ti的厚度为
Figure PCTCN2021138501-appb-000009
Ni的厚度为
Figure PCTCN2021138501-appb-000010
Au的厚度为
Figure PCTCN2021138501-appb-000011
进一步地，所述P型焊盘1100和N型焊盘1200可以为凸点的Bump电极，电极成分为Sn。更进一步地，凸点电极可以采用印刷、电镀或蒸镀等方法制得。所述Bump电极的高度≥5μm，锡膏高度≥20μm；
在本公开一实施方式中，所述P型焊盘1100和所述N型焊盘1200的面积和占整个所述LED芯片的面积的30％～55％，例如50％、60％、70％、75％。
在本公开一实施方式中，所述第三P型电极910和所述第三N型电极920的面积和大于所述P型焊盘1100和所述N型焊盘1200的面积和。
本公开实施例还提供了所述的LED芯片具体的制备方法，包括以下步骤：
(1)、提供一衬底100，并在所述衬底100上依次制作N型半导体层210、发光层220和P型半导体层230以形成外延层200；
(2)、在所述外延层200上沉积SiO 2，并通过黄光和刻蚀得到电流阻挡层300，再通过磁控溅射方式或蒸镀沉积厚度在
Figure PCTCN2021138501-appb-000012
的ITO薄膜，得到电流扩展层400，通过刻蚀得到PN台阶211，通过深刻蚀形成隔离槽；
(3)、根据图案进行黄光形成光刻胶形貌，将第一P型电极510和第一N型电极520相间分布沉积于芯片表面，然后沉积第一绝缘层600；
(4)、在所述第一P型电极510和所述第一N型电极520上方光刻分别得到第一通孔511和第二通孔521，并在所述第一通孔511处沉积第二P型电极710，第一通孔511和第二通孔521互相分离，无任何延伸交叉；在所述第二通孔521处沉积第二N型电极720，所述第二P型电极710和所述第二N型电极720彼此隔离，所述第二P型电极710通过第一通过与所述第一P型电极510相连通，所述第二N型电极720通过第一通过与所述第一N型电极520相连通，使得电极反射率在60％～95％，该层金属电极角度要求为30°～75°；
(5)、沉积第二绝缘层800，厚度为
Figure PCTCN2021138501-appb-000013
并在所述第二P型电极710和所述第二N型电极720上方采用黄光和ICP干法刻蚀分别得到第三通孔711和第四通孔721，并在所述第三通孔711处沉积第三P型电极910，在所述第四通孔721处沉积第三N型电极920，使得电极反射率在60％～95％，为保证后续薄膜覆盖，该层金属电极角度要求为 30°～75°；
所述第三P型电极910和所述第三N型电极920彼此隔离，且所述第二P型电极710延伸至所述第三N型电极920的下方，并且除所述第三通孔711和所述第四通孔721处，所述第二绝缘层800其余正面芯片无断裂处，从而保证上层第三N型电极920和下层延伸至所述第三N型电极920下方的所述第二P型电极710电极分离，切断漏电路径；
(6)、沉积第三绝缘层1300，并在所述第三P型电极910和所述第三N型电极920上方光刻分别得到第五通孔和第六通孔，该刻蚀角度要求为20°～80°，在所述第五通孔处沉积P型焊盘1100，在所述第六通孔处沉积N型焊盘1200；
(7)、进行研磨、划裂等形成芯粒，其中研磨厚度范围为80μm～300μm。
由此可以得到倒装LED芯片，P型焊盘1100通过第三绝缘层1300的第五通孔通孔实现与第三P型电极910互连，N型焊盘1200通过第三绝缘层1300的第六通孔实现与第三N型电极920互连，同时第四P型焊盘1100的朝向衬底100面只与第三P型电极910相连，N型焊盘1200的朝向衬底100面只与第三N型电极920相连。P型焊盘1100从横向和纵向看，无任何面与第三N型电极920直接或间接接触，无任何延伸相交。同理，适用于N型焊盘1200和第三P型电极910。因此，不存在因为任何因氧化硅断裂而导致极性不同的PN型电极互连，发生漏电失效问题。
本公开又一实施例还提供的一种所述的LED芯片具体的制备方法，所制备得到的LED芯片结构示意图如图6所示，N型焊盘1200和P型焊盘1100分别为两个焊盘的形式，如图中所示的NP焊盘组1000，每个焊盘的大小为688μm*244μm。
工业实用性
综上所述，本公开提供了一种LED芯片。本公开通过改进倒装芯片的电极设计，采用双层同质电极，避免锡膏电迁移或绝缘层断裂导致的芯片失效问题，从而提高了芯片的可靠性。

Claims (15)

  1. LED芯片，其特征在于，包括：
    衬底；
    具有PN台阶的外延片，所述外延片包括N型半导体层、发光层和P型半导体层；
    至少一个第一P型电极，位于所述PN台阶上，并与所述P型半导体层电性连接；
    至少一个第一N型电极，位于所述N型半导体层上与所述N型半导体层电性连接；
    第一绝缘层，覆盖所述第一N型电极、所述PN台阶、所述第一P型电极以及所述N型半导体层，并设置有多个第一通孔和多个第二通孔；
    第二P型电极，设置于所述第一绝缘层上，通过所述第一通孔与所述第一P型电极电性连接；
    第二N型电极，设置于所述第一绝缘层上，通过所述第二通孔与所述第一N型电极电性连接；
    第二绝缘层，覆盖所述第二P型电极、所述第二N型电极和所述第一绝缘层，并设置有多个第三通孔和多个第四通孔；
    第三P型电极，设置于第二绝缘层上，通过所述第三通孔与所述第二P型电极电性连接；
    第三N型电极，设置于第二绝缘层上，通过所述第四通孔与所述第二N型电极电性连接；
    P型焊盘，设置于所述第三P型电极上，并与第三P型电极电性连接；
    N型焊盘，设置于所述第三N型电极上，并于第三N型电极电性连接。
  2. 根据权利要求1所述的LED芯片，其特征在于，在垂直剖视图方向，所述N型焊盘与所述第二P型电极之间至少设置有第三N型电极；
    和/或，所述P型焊盘与所述第二N型电极之间至少设置有所述第三P型电极。
  3. 根据权利要求1所述的LED芯片，其特征在于，所述N型焊盘正下方的第二层为第二绝缘层和/或第二N型电极。
  4. 根据权利要求3所述的LED芯片，其特征在于，所述N型焊盘的水平面上的投影位于所述第三N型电极在水平方面上的投影内。
  5. 根据权利要求1所述的LED芯片，其特征在于，所述LED芯片还包括第三绝缘层，所述第三绝缘层覆盖所述第三P型电极和所述第三N型电极；
    所述第三绝缘层上设置有多个第五通孔和第六通孔；
    所述P型焊盘通过所述第五通孔与所述第三P型电极电性连接，所述N型焊盘通 过所述第六通孔与所述第三N型电极电性连接。
  6. 根据权利要求1所述的LED芯片，其特征在于，所述第三P型电极和所述第三N型电极的距离大于15μm；
    和/或；所述第三P型电极和所述第三N型电极的面积和占整个所述LED芯片的面积的50％～75％；
    和/或；所述P型焊盘和所述N型焊盘的面积和占整个所述LED芯片的面积的30％～55％。
  7. 根据权利要求1所述的LED芯片，其特征在于，所述第二P型电极区域与所述PN台阶侧面的最短距离为D 1，所述第三N型电极与所述PN台阶侧面的最短距离为D 2，所述N型焊盘与所述PN台阶侧面的最短距离为D 3，且D 1＜D 2＜D 3。
  8. 根据权利要求7所述的LED芯片，其特征在于，所述D 1＞5μm，D 2＞8μm，D 3＞15μm。
  9. 根据权利要求1所述的LED芯片，其特征在于，多个所述第一P型电极间隔设置于所述PN台阶上；多个所述第一N型电极间隔设置于所述N型半导体层上；
    和/或；
    一个或多个所述第二N型电极分别与所述第二P型电极之间具有间隙，其中部分所述第二N型电极位于PN台阶之上。
  10. 根据权利要求1所述的LED芯片，其特征在于，所述第一绝缘层为氧化硅和DBR反射层。
  11. 根据权利要求1所述的LED芯片，其特征在于，所述第一绝缘层的厚度为2μm～7μm。
  12. 根据权利要求1所述的LED芯片，其特征在于，所述第一绝缘层的厚度为3.5μm～5.5μm。
  13. 根据权利要求5所述的LED芯片，其特征在于，所述第二绝缘层和/或所述第三绝缘层包括氧化硅、氮化硅和氮氧化硅中的至少一种。
  14. 根据权利要求5所述的LED芯片，其特征在于，所述第二绝缘层和/或所述第三绝缘层的厚度为
    Figure PCTCN2021138501-appb-100001
  15. 根据权利要求1-14任一项所述的LED芯片的制备方法，其特征在于，包括以下步骤：
    (a)、提供一衬底，并在所述衬底上依次沉积N型半导体层、发光层和P型半导体层以形成外延层；
    (b)、在所述外延层上沉积SiO 2，并通过光刻得到电流阻挡层，再沉积得到电流 扩展层，通过刻蚀得到PN台阶；
    (c)、将多个第一P型电极和多个第一N型电极相间分布沉积于芯片表面，然后沉积第一绝缘层；
    (d)、在所述第一P型电极和所述第一N型电极上方光刻分别得到第一通孔和第二通孔，并在所述第一通孔处沉积第二P型电极，在所述第二通孔处沉积第二N型电极，所述第二P型电极和所述第二N型电极彼此隔离；
    (e)、沉积第二绝缘层，并在所述第二P型电极和所述第二N型电极上方光刻分别得到第三通孔和第四通孔，并在所述第三通孔处沉积第三P型电极，在所述第四通孔处沉积第三N型电极，所述第三P型电极和所述第三N型电极彼此隔离，且所述第二P型电极延伸至所述第三N型电极的下方；
    (f)、沉积第三绝缘层，并在所述第三P型电极和所述第三N型电极上方光刻分别得到第五通孔和第六通孔，在所述第五通孔处沉积P型焊盘，在所述第六通孔处沉积N型焊盘。
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