WO2023060752A1 - Led芯片及其制备方法 - Google Patents

Led芯片及其制备方法 Download PDF

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Publication number
WO2023060752A1
WO2023060752A1 PCT/CN2021/138500 CN2021138500W WO2023060752A1 WO 2023060752 A1 WO2023060752 A1 WO 2023060752A1 CN 2021138500 W CN2021138500 W CN 2021138500W WO 2023060752 A1 WO2023060752 A1 WO 2023060752A1
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Prior art keywords
layer
electrode
type
led chip
hole
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PCT/CN2021/138500
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English (en)
French (fr)
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王思博
李冬梅
廖汉忠
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淮安澳洋顺昌光电技术有限公司
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Priority claimed from CN202122484455.3U external-priority patent/CN215869439U/zh
Priority claimed from CN202111200185.7A external-priority patent/CN113823721A/zh
Application filed by 淮安澳洋顺昌光电技术有限公司 filed Critical 淮安澳洋顺昌光电技术有限公司
Publication of WO2023060752A1 publication Critical patent/WO2023060752A1/zh
Priority to US18/213,319 priority Critical patent/US20230335682A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the technical field of semiconductor manufacturing, in particular, to an LED chip and a preparation method thereof.
  • LED As a new generation of light source, LED is widely used in lighting, display, backlight and even optical communication and other fields.
  • flip chip As a product with higher luminous efficiency, flip chip has been more and more favored by the market.
  • the flip chip process structure has many structures and the process is complicated, so there are higher requirements and challenges for reliability.
  • the metal layer of the P-type metal electrode extends to the bottom of the N-type pad, and the two are separated from each other by the SiO 2 insulating layer to form the area shown in the dotted box.
  • the insulating layer breaks or cracks due to some reasons, it may lead to the connection between the P-type electrode and the N-type pad, resulting in leakage and reducing the reliability of the existing LED.
  • the first object of the present disclosure is to provide an LED chip, by adding a support layer not connected to the second electrode layer and the third electrode layer, and an insulating layer isolated from the third electrode layer, so as to The insulating effect of isolating the second electrode and the third electrode is achieved, thereby avoiding the leakage phenomenon caused by the rupture of the insulating layer, and increasing the reliability of the LED chip.
  • the second object of the present disclosure is to provide a method for manufacturing the above-mentioned LED chip.
  • the present disclosure provides an LED chip, comprising: a substrate, an epitaxial layer, a current blocking layer, a current spreading layer, a first electrode layer, a first insulating layer, a second electrode layer, a second insulating layer, a supporting layer, a third Electrode layer, third insulating layer;
  • the supporting layer is disposed between the second insulating layer and the third electrode layer;
  • the first electrode layer includes at least one first P-type electrode and at least one first N-type electrode;
  • the second electrode layer includes at least one second P-type electrode and at least one second N-type electrode;
  • the third electrode layer includes at least one P-type pad and at least one N-type pad.
  • the supporting layer and the third insulating layer by adding the supporting layer and the third insulating layer, the pad of the third electrode layer and the supporting layer, and the supporting layer and the second electrode layer are not connected and insulated from each other, while the third insulating layer and the second electrode layer
  • the electrical connection is conducted through a via hole penetrating through the second insulating layer and the third insulating layer.
  • the third insulating layer and the second insulating layer are etched with the same lithography, so that the support layer is wrapped in the insulating SiO2 film from all sides, so that the support layer and the electrodes of each layer are not connected to each other. , It plays the role of insulation and isolation of the opposite sex electrodes, effectively avoiding the leakage of LED chips caused by the breakage of the insulation layer.
  • the support layer is not electrically connected to any electrode layer, including a P-region support layer and an N-region support layer;
  • the P-region supporting layer covers the area of the second P-type electrode; the N-region supporting layer covers the area of the second N-type electrode;
  • the support layer further includes a support layer in the pin area, the support layer in the pin area is arranged in the central area of the LED chip, and there is no electrode below the central area.
  • the thickness of the support layer is ⁇ 2 ⁇ m.
  • the support layer is a metal layer or a metal oxide layer or a DBR reflective layer
  • the metal layer includes a metal monolayer of Cr, Ni, Ti, Pt and Au or several A composite metal layer composed of a single metal layer.
  • the distance between the side surface of the support layer and the third through hole and/or the fourth through hole is ⁇ 5 ⁇ m.
  • the area of the support layer accounts for 50%-80% of the area of the LED chip.
  • the area of the third electrode layer accounts for 30%-55% of the area of the LED chip.
  • the area of the third electrode layer is smaller than the area of the supporting layer.
  • the distance between the P-type pad and the N-type pad is ⁇ 50 ⁇ m.
  • the third electrode layer includes a single metal layer of Cr, Ni, Ti, Pt and Au, or a composite layer of several metals and/or alloys.
  • the third electrode layer is a bump electrode including a Sn component.
  • the present disclosure also provides a method for preparing the LED chip, comprising the following steps:
  • the LED chip provided by the present disclosure, by adding a supporting layer that is not in contact with the second electrode layer and the third electrode layer, and an insulating layer that is isolated from the third electrode layer, it can isolate the second electrode and the third electrode layer.
  • the function of the third electrode avoids the leakage phenomenon caused by the breakage of the insulating layer and increases the reliability of the LED chip.
  • the support layer added at the center of the chip realizes the effect of preventing the thimble from bursting, further increasing the reliability of the LED chip.
  • FIG. 1 is a schematic cross-sectional view of an ODR structure of a flip-chip LED chip in the prior art
  • FIG. 2 is a schematic plan view of an LED chip provided by an embodiment of the present disclosure
  • FIG. 3 is a partially enlarged view of a schematic plan view of an LED chip of the present disclosure
  • FIG. 4 is a schematic diagram of a plane layout of a supporting layer of an LED chip provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of the plane layout of the support layer of the LED chip shown in FIG. 4, corresponding to the plane layout of the third through hole and the fourth through hole;
  • FIG. 6 is a schematic diagram of the NP distance between the second electrode layer and the third electrode layer of the LED chip provided by the embodiment of the present disclosure
  • Fig. 7 is a partially enlarged view of the plane thimble area of the LED chip provided by the embodiment of the present disclosure.
  • Fig. 9 is a partial cross-sectional schematic diagram obtained according to the cutting method B in Fig. 6;
  • Fig. 10 is a partial cross-sectional schematic diagram obtained according to cutting mode C in Fig. 7;
  • Fig. 11 is a partial cross-sectional schematic diagram obtained according to the cutting method D in Fig. 7;
  • FIG. 12 is a schematic plan view of the LED chip provided by another embodiment of the present application.
  • 300-current blocking layer 400-current spreading layer; 510-first P-type electrode;
  • FIG. 2 is a schematic plan view of an LED chip provided by an embodiment of the present disclosure
  • FIG. 3 is a partially enlarged view of a plan view of an LED chip of the present disclosure
  • Fig. 4 is a schematic diagram of the planar layout of the support layer 900 of the LED chip provided by the embodiment of the present disclosure
  • Fig. 5 is a schematic diagram of the planar layout of the support layer 900 of the LED chip shown in Fig. 4 .
  • FIG. 6 is a schematic diagram of the NP distance between the second electrode layer and the third electrode layer of the LED chip provided by the embodiment of the present disclosure
  • FIG. 7 is a partially enlarged view of the plane thimble area of the LED chip provided by the embodiment of the present disclosure
  • FIG. 6 is a partial cross-sectional schematic diagram obtained according to cutting method A;
  • Fig. 9 is a partial cross-sectional schematic diagram obtained according to cutting method B in Fig. 6;
  • Fig. 10 is a partial cross-sectional schematic diagram obtained according to cutting method C in Fig. 7;
  • An LED chip provided by an embodiment of the present disclosure includes: a substrate 100, an epitaxial layer 200, a current blocking layer 300, a current spreading layer 400, a first electrode layer, a first insulating layer 600, a second electrode layer, a second An insulating layer 800, a supporting layer 900, a third electrode layer, and a third insulating layer 1000;
  • the supporting layer 900 is disposed between the second insulating layer 800 and the third electrode layer, and is not electrically connected to any electrode layer;
  • the first electrode layer includes at least one first P-type electrode 510 and at least one first N-type electrode 520;
  • the second electrode layer includes at least one second P-type electrode 710 and at least one second N-type electrode 720;
  • the third electrode layer includes at least one P-type pad 1310 and at least one N-type pad 1320 .
  • the epitaxial layer 200 is set on the surface of the substrate 100, and the epitaxial layer 200 includes an N-type semiconductor layer 210, which is sequentially stacked on the surface of the substrate 100, Light emitting layer 220 and P-type semiconductor layer 230;
  • the epitaxial layer 200 includes a PN step 211, the upper step surface of the PN step 211 is a P-type semiconductor layer 230, and the lower step surface is an N-type semiconductor layer 210, and the connection between the upper step surface and the lower step surface is forming the sides of the PN step 211;
  • the current blocking layer 300 and the current spreading layer 400 are sequentially disposed on the surface of the P-type semiconductor layer 230;
  • the first electrode layer includes a first P-type electrode 510 and a first N-type electrode 520; the first P-type electrode 510 is connected to the current spreading layer 400; the first N-type electrode 520 is connected to the The lower step surfaces of the PN steps 211 are connected;
  • the first P-type electrode 510 and the first N-type electrode 520 are isolated from each other;
  • the first insulating layer 600 covers the first N-type electrode 520 , the current spreading layer 400 , the sides of the PN step 211 , the first P-type electrode 510 , and the first N-type electrode 520 The lower step surface between the side of the PN step 211;
  • the first insulating layer 600 is provided with a first through hole 511 directly connected to the first P-type electrode 510 and a second through hole 521 directly connected to the first N-type electrode 520;
  • the second electrode layer includes a second P-type electrode 710 and a second N-type electrode 720, the second P-type electrode 710 and the second N-type electrode 720 are isolated from each other; the second P-type electrode 710 passes through The first through hole 511 is connected to the first P-type electrode 510; the second N-type electrode 720 is connected to the first N-type electrode 520 through the second through hole 521;
  • the second insulating layer 800 is disposed on the surface of the second electrode layer
  • the supporting layer 900 is disposed between the second insulating layer 800 and the third electrode layer;
  • the third insulating layer completely covers the surface formed by the second insulating layer 800 and the supporting layer 900;
  • the third through hole 1100 and the fourth through hole 1200 penetrate through the second insulating layer 800 and the third insulating layer and directly lead to the second P-type electrode 710 and the second N-type electrode 720 respectively;
  • the third electrode layer includes at least one P-type pad 1310 and at least one N-type pad 1320, the P-type pad 1310 and the N-type pad 1320 are isolated from each other; the P-type pad 1310 and the The second P-type electrode 710 is connected through the third through hole 1100, and the N-type pad 1320 and the second N-type electrode 720 are connected through the fourth through hole 1200;
  • the supporting layer 900 is insulated and isolated from the second electrode layer through the second insulating layer 800 ; and the supporting layer 900 is insulated and isolated from the third electrode layer through the third insulating layer.
  • the pads of the third electrode layer and the supporting layer 900, and the supporting layer 900 and the second electrode layer are not connected and insulated from each other, while the third insulating layer and the second electrode layer are not connected.
  • the two electrode layers are electrically connected through the through holes penetrating the second insulating layer 800 and the third insulating layer.
  • the third insulating layer and the second insulating layer 800 are etched with the same photolithography, so that the support layer 900 is wrapped in the insulating SiO2 film from all sides, thereby realizing the mutual connection between the support layer 900 and the electrodes of each layer. Not connected, it plays the role of insulating and isolating the electrodes of the opposite sex, effectively avoiding the leakage of LED chips caused by the breakage of the insulating layer.
  • the support layer 900 includes a P-region support layer 910, an N-region support layer 920, and a thimble region support layer 930;
  • the P-region supporting layer 910 covers the area of the second P-type electrode 710 to block the second P-type electrode 710;
  • the N-region supporting layer 920 covers the area of the second N-type electrode 720 to function blocking the function of the second N-type electrode 720;
  • the support layer 930 in the thimble area is arranged in the central area of the LED chip, and the newly added support layer is made of metal, which has a stronger blocking force than the insulating layer and protects the first LED chip.
  • the second insulating layer is not affected by the thimble, realizing the effect of preventing the thimble from bursting.
  • the substrate 100 may include but not limited to a sapphire substrate 100 .
  • a patterned substrate 100 can also be selected.
  • the material of the N-type semiconductor layer 210 may be N-type doped GaN
  • the material of the P-type semiconductor layer 230 may be P-doped GaN, but not limited to these two semiconductor types.
  • the light-emitting layer 220 includes quantum wells and quantum barriers that are alternately stacked, but is not limited thereto.
  • the light emitting layer 220 includes but not limited to a red light emitting layer, a yellow light emitting layer, a green light emitting layer or a blue light emitting layer.
  • the quantum wells include but not limited to InGaN quantum wells or AlInGaN quantum wells.
  • the current blocking layer 300 includes but not limited to SiO 2 .
  • the current spreading layer 400 occupies 70%-90% of the area of the LED chip, including but not limited to one of ITO, ZITO, ZIO, GIO, ZTO, FTO, AZO and GZO. Further, the thickness of the current spreading layer 400 is for example can be Furthermore, the current spreading layer 400 can be deposited by magnetron sputtering or evaporation.
  • first through hole 511 and the second through hole 521 are separated from each other without any extension crossing; as shown in FIG. 5 , the third through hole 1100 and the fourth through hole 1200 are separated from each other without any extension crossing, In this way, the separation of the upper electrode and the lower heterogeneous electrode is ensured, and possible leakage paths are cut off.
  • the first insulating layer 600 is a DBR reflective layer, and the DBR reflective layer may be formed by alternately depositing SiO 2 and Ti 3 O 5 . Furthermore, the thickness of the first insulating layer 600 is 2 ⁇ m ⁇ 7 ⁇ m, among which 3.5 ⁇ m ⁇ 5.5 ⁇ m is optimal.
  • the second insulating layer 800 and/or the third insulating layer include at least one of silicon oxide, silicon nitride and silicon oxynitride.
  • the thickness of the second insulating layer 800 and/or the third insulating layer is For example for
  • the supporting layer 900 can be made of any material.
  • the material of the supporting layer 900 can be a metal layer.
  • the metal layer includes a metal monolayer of Cr, Ni, Ti, Pt and Au or a composite metal layer composed of several metal monolayers.
  • the support layer 900 in order to ensure that each surface of the support layer 900 is covered with an insulating layer and that no metal is exposed on any surface, refer to the schematic cross-sectional view shown in FIG. 8 , the support layer 900
  • the distance between the side surface of the side surface and the third through hole 1100 and/or the fourth through hole 1200 is ⁇ 5 ⁇ m.
  • the thickness of the support layer 900 is less than 2 ⁇ m, and the area of the support layer 900 accounts for 50% to 80% of the area of the LED chip, so that the electrode reflectivity is 60 % to 95%.
  • the angle of the metal electrode of this layer is required to be 30° to 75°.
  • the material of the support layer 900 may be a metal oxide with better light conductivity, such as indium tin oxide, zinc oxide, and tin oxide.
  • the material of the support layer 900 may be a DBR reflective layer with insulating properties, such as a SiO 2 /TiO 2 DBR reflective layer.
  • the area of the third electrode layer accounts for 30%-55% of the area of the LED chip.
  • the area of the third electrode layer is smaller than the area of the supporting layer 900 .
  • FIG. 6 there is an isolation groove between the second P-type electrode 710 and the second N-type electrode 720, and the width of the isolation groove P3 ⁇ 15 ⁇ m;
  • the distance P4 between the P-type pad 1310 and the N-type pad 1320 is greater than or equal to 50 ⁇ m.
  • the third electrode layer includes a single metal layer of Cr, Ni, Ti, Pt and Au, or a composite layer of several metals and/or alloys.
  • the thickness of Al is The thickness of Pt is The thickness of Ti is The thickness of Ni is The thickness of Au is
  • the third electrode layer is a bump electrode including a Sn component, that is, further, the P-type pad 1310 and the N-type pad 1320 can be bump electrodes.
  • the electrode, the electrode composition is Sn.
  • the bump electrodes can be made by printing, electroplating or vapor deposition and other methods.
  • the height of the bump electrode is greater than or equal to 5 ⁇ m, and the height of the solder paste is greater than or equal to 20 ⁇ m.
  • the third electrode layer there may be one, two or more P-type pads 1310; one, two or more N-type pads 1320 may be Multiple.
  • the embodiment of the present disclosure also provides the method for preparing the LED chip, which specifically includes the following steps:
  • photolithography above the first P-type electrode 510 and the first N-type electrode 520 respectively obtains the first through hole 511 and the second through hole 521, and deposits the second electrode layer; wherein, the second P The type electrode 710 communicates with the first P-type electrode 510 through the first through hole 511, and the second N-type electrode 720 communicates with the first N-type electrode 520 through the second through hole 521;
  • the present disclosure provides an LED chip.
  • the present disclosure by adding a support layer that is not connected to the second electrode layer and the third electrode layer, and an insulating layer that is isolated from the third electrode layer, the second electrode and the third electrode are isolated, thereby avoiding The leakage phenomenon caused by the breakage of the insulating layer is eliminated, and the reliability of the LED chip is increased.

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Abstract

LED芯片及其制备方法，该LED芯片包括：衬底（100）、外延层（200）、电流阻挡层（300）、电流扩展层（400）、第一电极层、第一绝缘层（600）、第二电极层、第二绝缘层（800）、支撑层（900）、第三电极层、第三绝缘层（1000）。该LED芯片，通过增加不与第二电极层和第三电极层相连接的支撑层，以及与第三电极层相隔离的绝缘层，从而起到了隔离第二电极和第三电极的绝缘作用，避免了因绝缘层断裂而导致的漏电现象，增加了LED芯片的可靠性。又通过在芯片中心位置增加的支撑层，实现了防顶针顶破的效果，进一步增加了LED芯片的可靠性。

Description

LED芯片及其制备方法
相关申请的交叉引用
本申请要求于2021年10月14日提交中国专利局的申请号为2021112001857、名称为“LED芯片及其制备方法”的中国专利申请的优先权，以及申请号为2021224844553、名称为“LED芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体制造技术领域，具体而言，涉及LED芯片及其制备方法。
背景技术
LED作为新一代光源，被广泛应用在照明、显示、背光乃至光通信等领域。倒装芯片作为更高光效的产品已经越来越受到市场的青睐，倒装芯片制程结构较多，工艺制程复杂，因此对可靠性有了更高的要求和挑战。
常规的ODR结构，如图1所示，P型金属电极金属层延伸至N型焊盘下方，二者中间通过SiO 2绝缘层相互隔离，形成如虚线方框所示的区域。当绝缘层因为某些原因导致断裂或出现裂痕，均可能导致P型电极和N型焊盘连通，导致漏电的发生，使现有LED使用时的可靠性降低。
发明内容
有鉴于此，本公开的第一目的在于提供一种LED芯片，通过增加不与第二电极层和第三电极层相连接的支撑层，以及与第三电极层相隔离的绝缘层，从而起到了隔离第二电极和第三电极的绝缘作用，从而避免了因绝缘层断裂而导致的漏电现象，增加了LED芯片的可靠性。
本公开的第二目的在于提供如上所述的LED芯片的制备方法。
为了实现本公开的上述目的，特采用以下技术方案：
本公开提供了一种LED芯片，包括：衬底、外延层、电流阻挡层、电流扩展层、第一电极层、第一绝缘层、第二电极层、第二绝缘层、支撑层、第三电极层、第三绝缘层；
其中，所述支撑层设置在所述第二绝缘层和第三电极层之间；
所述第一电极层包括至少一个第一P型电极和至少一个第一N型电极；
所述第二电极层包括至少一个第二P型电极和至少一个第二N型电极；
所述第三电极层包括至少一个P型焊盘和至少一个N型焊盘。
本公开通过增加支撑层和第三绝缘层，使得第三电极层的焊盘与支撑层、支撑层与第二电极层，均不连通，且彼此绝缘，而第三绝缘层与第二电极层通过贯穿第二绝缘层和第三绝缘层的通孔导电连通。并且第三绝缘层与第二绝缘层采用同一光刻进行开孔刻蚀，实现了将支撑层从各个面都包裹在绝缘的SiO 2薄膜中，从而实现了支撑层与各层电极互不相连，起到异性电极的绝缘隔离作用，有效避免因绝缘层断裂导致的LED芯片漏电。
在本公开一种可选的实施方式中，所述支撑层不与任意一电极层电性连接，包括P区支撑层、N区支撑层；
所述P区支撑层覆盖所述第二P型电极的区域；所述N区支撑层覆盖所述第二N型电极的区域；
所述支撑层还包括顶针区支撑层，所述顶针区支撑层设置在所述LED芯片的中心区域，且所述中心区域的下方无任何电极。
在本公开一种可选的实施方式中，所述支撑层的厚度＜2μm。
在本公开一种可选的实施方式中，所述支撑层为金属层或金属氧化物层或者DBR反射层，所述金属层包括Cr、Ni、Ti、Pt和Au的金属单层或者几种金属单层组成的复合金属层。
在本公开一种可选的实施方式中，所述支撑层的侧面距离所述第三通孔和/或所述第四通孔的距离≥5μm。
在本公开一种可选的实施方式中，所述支撑层的面积占所述LED芯片的面积的50％～80％。
在本公开一种可选的实施方式中，所述第三电极层的面积占所述LED芯片的面积的30％～55％。
在本公开一种可选的实施方式中，所述第三电极层的面积小于所述支撑层的面积。
在本公开一种可选的实施方式中，所述第二P型电极和所述第二N型电极之间具有一隔离槽，所隔离槽的宽度≥15μm。
在本公开一种可选的实施方式中，所述P型焊盘和所述N型焊盘之间的距离≥50μm。
在本公开一种可选的实施方式中，所述第三电极层的包括Cr、Ni、Ti、Pt和Au中的金属单层、或者几种金属和/或合金的复合层。
在本公开一种可选的实施方式中，所述第三电极层为包括Sn成分的Bump电极。
本公开还提供了所述的LED芯片的制备方法，包括以下步骤：
(a)、提供一衬底，并在所述衬底上依次沉积N型半导体层、发光层和P型半导体层以形成外延层；
(b)、在所述外延层上沉积SiO 2，并通过光刻得到电流阻挡层，再沉积得到电流扩展层，通过刻蚀得到PN台阶；
(c)、将多个第一P型电极和多个第一N型电极相间分布沉积于芯片表面，然后沉积第一绝缘层；
(d)、在所述第一P型电极和所述第一N型电极上方光刻分别得到第一通孔和第二通孔，沉积第二电极层；其中，第二P型电极通过第一通孔与第一P型电极相连通，第二N型电极通过第二通孔与第一N型电极相连通；
(e)、依次沉积第二绝缘层、支撑层和第三绝缘层，在所述第二P型电极和所述第二N型电极上方无支撑层的区域，刻蚀得到第三通孔和第四通孔；
(f)、沉积第三电极层，其中，P型焊盘通过第三通孔与所述第二P型电极相连接，N型焊盘通过第四通孔与所述第二N型电极相连接。
与现有技术相比，本公开的有益效果为：
(1)本公开所提供的LED芯片，通过增加不与第二电极层和第三电极层相接触的支撑层，以及与第三电极层相隔离的绝缘层，从而起到了隔离第二电极和第三电极的作用，从而避免了因绝缘层断裂而导致的漏电现象，增加了LED芯片的可靠性。
(2)本公开所提供的LED芯片，通过在芯片中心位置增加的支撑层，实现了防顶针顶破的效果，进一步增加了LED芯片的可靠性。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为现有技术中倒装LED芯片ODR结构剖面示意图；
图2为本公开实施例所提供的LED芯片平面示意图；
图3为本公开LED芯片平面示意图的部分局部放大图；
图4为本公开实施例提供的LED芯片的支撑层平面布局示意图；
图5为图4所示的LED芯片的支撑层平面布局示意图对应的第三通孔和第四通孔所平面布局示意图；
图6为本公开实施例所提供的LED芯片第二电极层和第三电极层NP距离示意图；
图7为本公开实施例所提供的LED芯片平面顶针区域局部放大图；
图8为图6按照切割方式A得到的部分剖面示意图；
图9为图6按照切割方式B得到的部分剖面示意图；
图10为图7按照切割方式C得到的部分剖面示意图；
图11为图7按照切割方式D得到的部分剖面示意图；
图12为本申请提供的又一实施例所提供的LED芯片的平面结构示意图。
附图标记：
100-衬底；                 200-外延层；             210-N型半导体层；
211-PN台阶；               220-发光层；             230-P型半导体层；
300-电流阻挡层；           400-电流扩展层；         510-第一P型电极；
511-第一通孔；             520-第一N型电极；        521-第二通孔；
600-第一绝缘层；           710-第二P型电极；        720-第二N型电极；
800-第二绝缘层；           900-支撑层；             910-P区支撑层；
920-N区支撑层；            930-顶针区支撑层；       1000-第三绝缘层；
1100-第三通孔；            1200-第四通孔；          1310-P型焊盘；
1320-N型焊盘。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
图2为本公开实施例所提供的LED芯片平面示意图，图3为本公开LED芯片平面示意图的局部放大图。图4为本公开实施例提供的LED芯片的支撑层900平面布局示意图；图5为图4所示的LED芯片的支撑层900平面布局示意图对应的第三通孔1100和第四通孔1200所平面布局示意图；图6为本公开实施例所提供的LED芯片第二电极层和第三电极层NP距离示意图；图7为本公开实施例所提供的LED芯片平面顶针区域局部放大图；图8为图6按照切割方式A得到的部分剖面示意图；图9为图6按照切割方式B得到的部分剖面示意图；图10为图7按照切割方式C得到的部分剖面示意图；图11为图7按照切割方式D得到的部分剖面示意图。本公开实施例所提供的一种LED芯片，包括：衬底100、 外延层200、电流阻挡层300、电流扩展层400、第一电极层、第一绝缘层600、第二电极层、第二绝缘层800、支撑层900、第三电极层、第三绝缘层1000；
其中，所述支撑层900设置在所述第二绝缘层800和第三电极层之间，且不与任意一电极层电性连接；
所述第一电极层包括至少一个第一P型电极510和至少一个第一N型电极520；
所述第二电极层包括至少一个第二P型电极710和至少一个第二N型电极720；
所述第三电极层包括至少一个P型焊盘1310和至少一个N型焊盘1320。
其他结构如常规LED芯片所设置，具体地，所述外延层200设置于所述衬底100的表面，所述外延层200包括依次层叠设置于所述衬底100表面的N型半导体层210、发光层220和P型半导体层230；
所述外延层200包括PN台阶211，所述PN台阶211的上台阶面为P型半导体层230，下台阶面为N型半导体层210，所述上台阶面和所述下台阶面之间连接形成PN台阶211的侧面；
所述电流阻挡层300和所述电流扩展层400依次设置于所述P型半导体层230的表面；
所述第一电极层包括第一P型电极510和第一N型电极520；所述第一P型电极510与所述电流扩展层400相连接；所述第一N型电极520与所述PN台阶211的所述下台阶面相连接；
所述第一P型电极510与所述第一N型电极520彼此隔离；
所述第一绝缘层600覆盖所述第一N型电极520、所述电流扩展层400、所述PN台阶211的侧面、所述第一P型电极510、以及所述第一N型电极520与所述PN台阶211的侧面之间的所述下台阶面；
所述第一绝缘层600上设置有直通所述第一P型电极510的第一通孔511和直通所述第一N型电极520的第二通孔521；
所述第二电极层包括第二P型电极710和第二N型电极720，所述第二P型电极710和所述第二N型电极720彼此隔离；所述第二P型电极710通过所述第一通孔511与所述第一P型电极510相连接；所述第二N型电极720通过所述第二通孔521与所述第一N型电极520相连接；
所述第二绝缘层800设置于所述第二电极层表面；
所述支撑层900设置于所述第二绝缘层800和第三电极层之间；
所述第三绝缘层完全覆盖所述第二绝缘层800和所述支撑层900形成的表面；
第三通孔1100和第四通孔1200贯穿所述第二绝缘层800和所述第三绝缘层分别直通所述第二P型电极710和第二N型电极720；
所述第三电极层包括至少一个P型焊盘1310和至少一个N型焊盘1320，所述P型焊盘1310和所述N型焊盘1320彼此隔离；所述P型焊盘1310和所述第二P型电极710通过第三通孔1100相连接，所述N型焊盘1320和所述第二N型电极720通过第四通孔1200相连接；
所述支撑层900通过所述第二绝缘层800与所述第二电极层绝缘隔离；并且所述支撑层900通过所述第三绝缘层与所述第三电极层绝缘隔离。
本公开通过增加支撑层900和第三绝缘层，使得第三电极层的焊盘与支撑层900、支撑层900与第二电极层，均不连通，且彼此绝缘，而第三绝缘层与第二电极层通过贯穿第二绝缘层800和第三绝缘层的通孔导电连通。并且第三绝缘层与第二绝缘层800采用同一光刻进行开孔刻蚀，实现了将支撑层900从各个面都包裹在绝缘的SiO2薄膜中，从而实现了支撑层900与各层电极互不相连，起到异性电极的绝缘隔离作用，有效避免因绝缘层断裂导致的LED芯片漏电。
为了进一步提高LED芯片的可靠性，如图4和图12所示，所述支撑层900包括P区支撑层910、N区支撑层920和顶针区支撑层930；
所述P区支撑层910覆盖所述第二P型电极710的区域，起阻挡第二P型电极710的作用；所述N区支撑层920覆盖所述第二N型电极720的区域，起阻挡第二N型电极720的作用；
如图7所示的局部放大图，所述顶针区支撑层930设置在所述LED芯片的中心区域，新增加的支撑层因由金属构成，相比绝缘层具有更强的阻挡力，保护了第二绝缘层不受顶针影响，实现了防顶针顶破的效果。
其中，衬底100可以包括但不限于蓝宝石衬底100。此外，也可以选择图形化的衬底100。其中，N型半导体层210的材质可以为N型掺杂的氮化镓，所述P型半导体层230的材质可以为P型掺杂的氮化镓，但不仅限于这两种半导体类型。
其中，发光层220包括交替层叠设置的量子阱和量子垒，但是不限于此。所述发光层220包括但不限于红光发光层、黄光发光层、绿光发光层或蓝光发光层。所述量子阱包括但不限于InGaN量子阱或AlInGaN量子阱。
其中，电流阻挡层300包括但不限于SiO 2。
其中，电流扩展层400占所述LED芯片的面积的70％～90％，包括但不限于ITO、ZITO、ZIO、GIO、ZTO、FTO、AZO和GZO中的一种。进一步地，所述电流扩展层400包括的厚度为
Figure PCTCN2021138500-appb-000001
例如可以为
Figure PCTCN2021138500-appb-000002
Figure PCTCN2021138500-appb-000003
更进一步地，所述电流扩展层400可以通过磁控溅射或蒸镀的方式进行沉积得到。
其中，第一通孔511和第二通孔521之间互相分离，无任何延伸交叉；如图5所示，第三通孔1100和第四通孔1200之间互相分离，无任何延伸交叉，从而保证上层电极和下层异质电极的分离，切断可能的漏电路径。
本公开实施例中，作为一可选实施例，所述第一绝缘层600为DBR反射层，DBR反射层可以为交替沉积SiO 2和Ti 3O 5形成。更进一步地，所述第一绝缘层600的厚度为2μm～7μm，其中3.5μm～5.5μ最优。
本公开实施例中，作为一可选实施例，所述第二绝缘层800和/或所述第三绝缘层包括氧化硅、氮化硅和氮氧化硅中的至少一种。
本公开实施例中，作为一可选实施例，所述第二绝缘层800和/或所述第三绝缘层的厚度为
Figure PCTCN2021138500-appb-000004
例如为
Figure PCTCN2021138500-appb-000005
本公开实施例中，作为一可选实施例，所述支撑层900可以为任意材质，为保证更好的支撑效果，以及适用于成熟的芯片制备工艺，支撑层900的材质可以为金属层，所述金属层包括Cr、Ni、Ti、Pt和Au的金属单层或者几种金属单层组成的复合金属层。
本公开实施例中，作为一可选实施例，为了保证支撑层900的各个面均以绝缘层包覆，保证无任何面裸露出金属，参考图8所示的剖面示意图，所述支撑层900的侧面距离所述第三通孔1100和/或所述第四通孔1200的距离≥5μm。
本公开实施例中，作为一可选实施例，所述支撑层900的厚度＜2μm，所述支撑层900的面积占所述LED芯片的面积的50％～80％，使得电极反射率在60％～95％，为保证后续薄膜覆盖，该层金属电极角度要求为30°～75°。
本公开实施例中，作为一可选实施例，所述支撑层900的材质可以为导光性较好的金属氧化物，如氧化铟锡、氧化锌、氧化锡。
本公开实施例中，作为一可选实施例，所述支撑层900的材质可以为具有绝缘性质的DBR反射层，如SiO 2/TiO 2DBR反射层。
本公开实施例中，作为一可选实施例，所述第三电极层的面积占所述LED芯片的面积的30％～55％。
本公开实施例中，作为一可选实施例，所述第三电极层的面积小于所述支撑层900的面积。
本公开实施例中，作为一可选实施例，如图6所示，所述第二P型电极710和所述第二N型电极720之间具有一隔离槽，所隔离槽的宽度P3≥15μm；
本公开实施例中，作为一可选实施例，如图6所示，所述P型焊盘1310和所述N型焊盘1320之间的距离P4≥50μm。
本公开实施例中，作为一可选实施例，所述第三电极层的包括Cr、Ni、Ti、Pt和Au 中的金属单层、或者几种金属和/或合金的复合层。更进一步地，Al的厚度为
Figure PCTCN2021138500-appb-000006
Pt的厚度为
Figure PCTCN2021138500-appb-000007
Ti的厚度为
Figure PCTCN2021138500-appb-000008
Ni的厚度为
Figure PCTCN2021138500-appb-000009
Au的厚度为
Figure PCTCN2021138500-appb-000010
本公开实施例中，作为一可选实施例，所述第三电极层为包括Sn成分的Bump电极，即进一步地，所述P型焊盘1310和N型焊盘1320可以为凸点的Bump电极，电极成分为Sn。更进一步地，凸点电极可以采用印刷、电镀或蒸镀等方法制得。所述Bump电极的高度≥5μm，锡膏高度≥20μm。
本公开实施例中，作为一可选实施例，所述第三电极层中，P型焊盘1310可以为1个、2个或者多个；N型焊盘1320可以为1个、2个或者多个。
本公开实施例还提供了所述的LED芯片的制备方法，具体包括以下步骤：
(1)、提供一衬底100，并在所述衬底100上依次沉积N型半导体层210、发光层220和P型半导体层230以形成外延层200；
(2)、在所述外延层200上沉积SiO 2，并通过光刻得到电流阻挡层300，再沉积得到电流扩展层400，利用先腐蚀ITO后刻蚀方式，通过刻蚀得到PN台阶211，为保证ITO与PN台阶距离，去胶前再进行一次ITO腐蚀，去胶后再通过黄光和深刻蚀形成ISO隔离槽。
(3)、将第一P型电极510和第一N型电极520相间分布沉积于芯片表面，然后沉积第一绝缘层600；
(4)、在所述第一P型电极510和所述第一N型电极520上方光刻分别得到第一通孔511和第二通孔521，沉积第二电极层；其中，第二P型电极710通过第一通孔511与第一P型电极510相连通，第二N型电极720通过第二通孔521与第一N型电极520相连通；
(5)、依次沉积第二绝缘层800、支撑层900和第三绝缘层，在所述第二P型电极710和所述第二N型电极720上方无支撑层900的区域，刻蚀得到第三通孔1100和所述第四通孔1200；该刻蚀通孔距离支撑层900边缘的最小距离＞5μm，保证支撑层900各个面完全包裹于第二、第三绝缘层中，隔绝支撑层900与任何金属电极的导电连通；
(6)、沉积第三电极层，其中，P型焊盘1310通过第三通孔1100与所述第二P型电极710相连接，N型焊盘1320通过第四通孔1200与所述第二N型电极720相连接；
(7)、进行研磨、划裂等形成芯粒，其中研磨厚度范围为80μm～300μm。
工业实用性
综上所述，本公开提供了一种LED芯片。本公开通过增加不与第二电极层和第三电极层相连接的支撑层，以及与第三电极层相隔离的绝缘层，从而起到了隔离第二电极和第三电极的绝缘作用，从而避免了因绝缘层断裂而导致的漏电现象，增加了LED芯片的可靠性。

Claims (13)

  1. LED芯片，其特征在于，包括：衬底、具有PN台阶的外延层、电流阻挡层、电流扩展层、第一电极层、第一绝缘层、第二电极层、第二绝缘层、支撑层、第三电极层、第三绝缘层；
    其中，所述支撑层设置在所述第二绝缘层和第三电极层之间；
    所述第一电极层包括至少一个第一P型电极和至少一个第一N型电极；
    所述第二电极层包括至少一个第二P型电极和至少一个第二N型电极；
    所述第三电极层包括至少一个P型焊盘和至少一个N型焊盘。
  2. 根据权利要求1所述的LED芯片，其特征在于，所述支撑层不与任意一电极层电性连接，包括P区支撑层、N区支撑层；
    所述P区支撑层覆盖所述第二P型电极的区域；所述N区支撑层覆盖所述第二N型电极的区域。
  3. 根据权利要求1所述的LED芯片，其特征在于，所述支撑层还包括顶针区支撑层，所述顶针区支撑层设置在所述LED芯片的中心区域。
  4. 根据权利要求1所述的LED芯片，其特征在于，所述支撑层的厚度≤2μm。
  5. 根据权利要求1所述的LED芯片，其特征在于，所述支撑层为金属层或金属氧化物层或者DBR反射层。
  6. 根据权利要求5所述的LED芯片，其特征在于，所述金属层包括Cr、Ni、Ti、Pt和Au的金属单层或者几种金属单层组成的复合金属层。
  7. 根据权利要求5所述的LED芯片，其特征在于，设置有贯穿所述第二绝缘层和所述第三绝缘层的第三通孔和第四通孔；
    所述P型焊盘和所述第二P型电极通过第三通孔电性连接，所述N型焊盘和所述第二N型电极通过第四通孔电性连接；
    其中，所述支撑层的侧面距离所述第三通孔和/或所述第四通孔的距离≥5μm。
  8. 根据权利要求1-7中的任一项所述的LED芯片，其特征在于，所述支撑层的面积占所述LED芯片的面积的50％～80％。
  9. 根据权利要求1所述的LED芯片，其特征在于，所述第三电极层的面积占所述LED芯片的面积的30％～55％。
  10. 根据权利要求9所述的LED芯片，其特征在于，所述第三电极层的面积小于所述支撑层的面积。
  11. 根据权利要求1所述的LED芯片，其特征在于，所述第二P型电极和所述第二 N型电极之间具有一隔离槽，所隔离槽的宽度≥15μm；
    和/或；
    所述P型焊盘和所述N型焊盘之间的距离≥50μm。
  12. 根据权利要求1所述的LED芯片，其特征在于，所述第三电极层的包括Cr、Ni、Ti、Pt和Au中的金属单层、或者几种金属和/或合金的复合层；
    或者；所述第三电极层为包括Sn成分的Bump电极。
  13. 根据权利要求1-12任一项所述的LED芯片的制备方法，其特征在于，包括以下步骤：
    (a)、提供一衬底，并在所述衬底上依次沉积N型半导体层、发光层和P型半导体层以形成外延层；
    (b)、在所述外延层上沉积SiO 2，并通过光刻得到电流阻挡层，再沉积得到电流扩展层，通过刻蚀得到PN台阶；
    (c)、将多个第一P型电极和多个第一N型电极相间分布沉积于芯片表面，然后沉积第一绝缘层；
    (d)、在所述第一P型电极和所述第一N型电极上方光刻分别得到第一通孔和第二通孔，沉积第二电极层；其中，第二P型电极通过第一通孔与第一P型电极相连通，第二N型电极通过第二通孔与第一N型电极相连通；
    (e)、依次沉积第二绝缘层、支撑层和第三绝缘层，在所述第二P型电极和所述第二N型电极上方无支撑层的区域，刻蚀得到第三通孔和第四通孔；
    (f)、沉积第三电极层，其中，P型焊盘通过第三通孔与所述第二P型电极相连接，N型焊盘通过第四通孔与所述第二N型电极相连接。
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CN106206890A (zh) * 2015-05-27 2016-12-07 三星电子株式会社 发光器件封装件及其制造方法
CN109659414A (zh) * 2018-11-22 2019-04-19 华灿光电（浙江）有限公司 一种倒装led芯片及其制作方法
CN209199975U (zh) * 2018-11-22 2019-08-02 华灿光电（浙江）有限公司 一种倒装led芯片
CN111048644A (zh) * 2014-12-16 2020-04-21 晶元光电股份有限公司 发光元件

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CN111048644A (zh) * 2014-12-16 2020-04-21 晶元光电股份有限公司 发光元件
CN106206890A (zh) * 2015-05-27 2016-12-07 三星电子株式会社 发光器件封装件及其制造方法
CN109659414A (zh) * 2018-11-22 2019-04-19 华灿光电（浙江）有限公司 一种倒装led芯片及其制作方法
CN209199975U (zh) * 2018-11-22 2019-08-02 华灿光电（浙江）有限公司 一种倒装led芯片

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