WO2023056744A1 - 一种带宽降速修复方法、装置、电子设备及存储介质 - Google Patents

一种带宽降速修复方法、装置、电子设备及存储介质 Download PDF

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WO2023056744A1
WO2023056744A1 PCT/CN2022/090188 CN2022090188W WO2023056744A1 WO 2023056744 A1 WO2023056744 A1 WO 2023056744A1 CN 2022090188 W CN2022090188 W CN 2022090188W WO 2023056744 A1 WO2023056744 A1 WO 2023056744A1
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module
register
bandwidth
cpld
pcie
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PCT/CN2022/090188
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English (en)
French (fr)
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孔维宾
吴常顺
周加洋
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苏州浪潮智能科技有限公司
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Publication of WO2023056744A1 publication Critical patent/WO2023056744A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present application relates to the technical field of device bandwidth processing, and in particular to a method, device, electronic device, and storage medium for repairing bandwidth deceleration.
  • PCIE Peripheral Component Interconnect Express
  • PCIE5.0 Peripheral Component Interconnect Express
  • the PCIE device in the CPU usually needs to configure the corresponding standard bandwidth, such as configuring the standard bandwidth of X16.
  • the bandwidth configuration of the PCIE device has a bandwidth deceleration problem, such as the bandwidth is reduced from X16 to X1.
  • the CPU generally resets twice to perform bandwidth deceleration repair, but the second reset needs to wait for the PCIE device to stabilize for a period of seconds after the first reset is completed.
  • the stabilization time required between two reset operations is 16 seconds, which takes a long time and the device also has certain requirements for the boot time, so it is urgent to propose a new bandwidth deceleration repair method to improve the timeliness of bandwidth deceleration repair .
  • the technical problem to be solved in the present application is to overcome the time-consuming defect of the existing bandwidth deceleration repair method, thereby providing a bandwidth deceleration repair method, device, electronic equipment and storage medium.
  • the embodiment of the present application discloses a bandwidth deceleration repair method, which is applied to a BIOS module, and the BIOS module is connected to one side of the CPLD module containing a register for communicating with the CPLD module.
  • sending a register connection state control instruction to the CPLD module includes: when the bandwidth deceleration occurs in the PCIE module, performing bandwidth configuration information detection on the PCIE module;
  • the PCIE module is configured with a bandwidth configuration graphics card, and performs an operation of sending a register connection state control command to the CPLD module.
  • the method further includes: The repair result of the bandwidth deceleration of the PCIE module detects; When the bandwidth deceleration still occurs in the PCIE module, repeat the described sending register connection state control instruction to the CPLD module, so that the register is disabled according to the received instruction response and steps to enable join operations until the target number of times is reached.
  • sending a register connection state control command to the CPLD module, so that the register disables and enables connection operations according to the received command response includes: sending a register disable connection control command to the CPLD module, so that the register Responding to the received instruction disables the connection operation; responds to the timing operation, and sends the register enable connection control instruction to the CPLD module when the target time is reached, so that the register enables the connection operation according to the received instruction response.
  • the register connection state control instruction includes: a register disable connection control instruction, a register enable connection control instruction, and an interval duration instruction between register disable and enable connection operations; send the register connection state control instruction to the CPLD module, so that the The register disables and enables the connection operation according to the instruction response received, and also includes: sending the register to disable the connection control instruction to the CPLD module, so that the register disables the connection operation according to the instruction response received; to the CPLD module Sending the register enable connection control instruction and the interval duration instruction between register disable and enable connection operations, so that the register responds to enable connection delay operation according to the received instruction.
  • the method further includes: sending the number of repairs to the bandwidth reduction of the PCIE module and the repair result corresponding to each repair operation to a register of the CPLD module for storage.
  • the method further includes: sending bandwidth deceleration information of the PCIE module to the CPLD module, so that the CPLD module stores the deceleration information in a register.
  • the BIOS module is connected to one side of the CPLD module that contains registers, and is used to communicate with the CPLD module including:
  • the BIOS module is connected to the side of the CPLD module containing registers through the CPU, and the BIOS module communicates with the CPLD module through the IIC bus.
  • the embodiment of the present application also discloses a device for repairing bandwidth speed reduction, which is used for a BIOS module, and the BIOS module is connected to one side of the CPLD module containing a register, and is used to communicate with the CPLD module, The other side of the CPLD module is connected with a PCIE module configured with a target bandwidth, for obtaining the link bandwidth of the PCIE module;
  • the device includes: a link bandwidth acquisition module, for when the device starts, from the CPLD module Obtain the link bandwidth of PCIE module in; Decrease speed and determine module, be used for comparing described link bandwidth and target bandwidth, determine whether bandwidth deceleration occurs in described PCIE module; Instruction sending module, for when described PCIE When bandwidth deceleration occurs in the module, a register connection state control command is sent to the CPLD module, so that the register disables and enables connection operations according to the received command response.
  • the BIOS module is connected to one side of the CPLD module that contains registers, and is used to communicate with the CPLD module including:
  • the BIOS module is connected to the side of the CPLD module containing registers through the CPU, and the BIOS module communicates with the CPLD module through the IIC bus.
  • the embodiment of the present application also discloses an electronic device, including: at least one processor; and a memory connected in communication with the at least one processor; wherein, the memory stores information that can be used by the at least one processor Instructions executed by the processor, the instructions are executed by the at least one processor, so that the at least one processor executes the method for repairing bandwidth slowdown as described in the first aspect or any optional implementation manner of the first aspect step.
  • the embodiment of the present application also discloses a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the first aspect or any optional implementation of the first aspect can be realized.
  • the bandwidth deceleration repair method/device provided by this application is applied to the BIOS module, and the BIOS module is connected to one side of the CPLD module containing registers for communicating with the CPLD module, and the other side of the CPLD module is connected to the PCIE configured with the target bandwidth.
  • Module connection used to obtain the link bandwidth of the PCIE module.
  • the register connection state control command is sent to the CPLD module, so that the register disables and enables the connection operation according to the received command response.
  • the BIOS module When the BIOS module detects the bandwidth deceleration of the PCIE module during the device startup phase, it sends a register connection status control command to the CPLD module, and the control register disables and enables the connection operation according to the received command response, so that the PCIE module link is restarted.
  • the initialization and training operations then realize link bandwidth recovery.
  • the entire process of bandwidth deceleration recovery register disabling and enabling connections only takes milliseconds, which improves the timeliness of bandwidth deceleration recovery and meets the requirements for device startup time.
  • Fig. 1 is a flow chart of a specific example of the bandwidth deceleration repairing method in the embodiment of the present application
  • FIG. 2 is a schematic structural diagram corresponding to a specific example of a bandwidth deceleration repair method in an embodiment of the present application
  • FIG. 3 is a flow chart of a specific example of a bandwidth deceleration repair method in an embodiment of the present application
  • FIG. 4 is a flow chart of a specific example of a bandwidth deceleration repair method in an embodiment of the present application
  • FIG. 5 is a flow chart of a specific example of a bandwidth deceleration repair method in an embodiment of the present application
  • FIG. 6 is a functional block diagram of a specific example of a device for repairing bandwidth speed reduction in an embodiment of the present application
  • FIG. 7 is a diagram of a specific example of electronic equipment in the embodiment of the present application.
  • FIG. 8 is a diagram of a specific example of a storage medium in the embodiment of the present application.
  • BIOS Basic Input Output System
  • BIOS Basic Input Output System
  • CPLD Complex Programmable Logic Device
  • CMOS EPROM CMOS EPROM
  • EEPROM Electrically erasable programmable Logic Device
  • the embodiment of the present application discloses a bandwidth reduction repair method, which is applied to the BIOS module, as shown in Figure 2, the BIOS module is connected to the side of the CPLD module that contains registers through the CPU, and is used to communicate with the CPLD module.
  • the other side of the module is connected to the PCIE module configured with the target bandwidth to obtain the link bandwidth of the PCIE module.
  • the configuration method of the target bandwidth of the PCIE module may be to insert a graphics card with corresponding bandwidth (such as a PEX8733 card) into the equipment chassis to complete the bandwidth configuration.
  • the BIOS module can realize the information interaction between the BIOS module and the CPLD module through the IIC (Inter-Integrated Circuit, integrated circuit bus); at the same time, the PEX8733 card will send the relevant information of the card, such as the card in-position information, reset information, power control information and the current link bandwidth information are sent to the CPLD module.
  • the method includes the following steps:
  • Step 101 when the device starts, obtain the link bandwidth of the PCIE module from the CPLD module.
  • the device startup process may include a device startup or device restart process.
  • the link bandwidth of the PCIE module is obtained from the CPLD module through the BIOS module.
  • the CPLD module can obtain the current link bandwidth from the PCIE module at a certain interval, or the CPLD module obtains the current link bandwidth of the PCIE module when receiving the link bandwidth acquisition request sent by the BIOS module, and then obtains the current link bandwidth through the IIC The received link bandwidth is sent to the BIOS module.
  • Step 102 compare the link bandwidth with the target bandwidth, and determine whether the bandwidth deceleration occurs in the PCIE module.
  • step 103 is performed.
  • the target bandwidth may be the bandwidth initially configured for the PCIE module.
  • the target bandwidth is X16.
  • Step 103 sending the register connection state control command to the CPLD module, so that the register can disable and enable the connection operation according to the received command response.
  • the state transition between the disabled connection and the enabled connection of the register can be realized by changing the register address offset bit, such as the register address offset bit can be pre-specified as "when the register is pointed first, the register responds ", nable LINK (enabled connection)" Operation, the register address offset bit is "when the address is offset, the register responds", isable Link (disabled connection)” operation, so the register connection status control instruction sent to the CPLD module can be an instruction for changing the register address offset bit, By sending an instruction to change the register address offset bit, the control register first responds to the operation of disabling the connection and then the operation of enabling the connection.
  • the register address offset bit can be pre-specified as "when the register is pointed first, the register responds ", nable LINK (enabled connection)” Operation, the register address offset bit is "when the address is offset, the register responds", isable Link (disabled connection)” operation, so the register connection status control instruction sent to the CPLD module can be an instruction
  • the embodiment of the present application does not limit the specific representation form of the register address offset bit, and those skilled in the art can determine it according to actual needs, as long as the address offset bit is changed to control the disabling and enabling of the connection operation of the register.
  • the register connection state control instruction can also be to use a pre-agreed communication protocol to send a section of protocol instructions to the CPLD module to express disabling and enabling connections. After receiving the protocol instruction, the CPLD module performs an analysis operation according to the pre-agreed communication protocol. To control the register response to the corresponding connection operation.
  • the bandwidth deceleration repair method provided by the embodiment of the present application sends a register connection state control command to the CPLD module, and the control register responds to disable and enable the connection operation according to the received command, so that the PCIE module link is re-initialized and the training operation is implemented.
  • Link bandwidth repair In the whole process, while the bandwidth deceleration is realized, it only takes milliseconds for the register to disable and enable the connection, which improves the timeliness of the bandwidth deceleration and repair, and meets the requirements for the device's boot time. Under the Linux system, you can use the setpci command to complete the above bandwidth reduction repair operation.
  • step 103 when the bandwidth deceleration occurs in the PCIE module, send the register connection state control command to the CPLD module, including: the PCIE module is carried out bandwidth configuration information detection; when the PCIE module is configured with a bandwidth configuration graphics card, Execute the operation of sending register connection status control instructions to the CPLD module.
  • the bandwidth configuration information detection is performed on the PCIE module first, and when the PCIE module is configured with a bandwidth configuration graphics card (such as a PEX8733 card), the subsequent register connection state control instruction sending operation is performed;
  • the PCIE module is not configured with a bandwidth-configured graphics card, and there is only bandwidth deceleration. Stop sending register connection status control instructions to the CPLD module to avoid invalid bandwidth recovery operations when no card is inserted in the device chassis, which affects the device startup progress. .
  • the method further includes:
  • Step 104 Detect the repair result of bandwidth deceleration of the PCIE module.
  • the detection method of the bandwidth deceleration repair result may be to obtain the link bandwidth of the PCIE module from the CPLD module again, compare the link bandwidth with the target bandwidth, and then determine whether the bandwidth deceleration still occurs in the PCIE module.
  • Step 105 when the bandwidth deceleration still occurs in the PCIE module, repeatedly send the register connection state control instruction to the CPLD module, so that the register responds to the step of disabling and enabling the connection operation according to the received instruction until the target number of times is reached.
  • the embodiment of the present application does not limit the target number of times, and those skilled in the art can determine it according to actual needs.
  • the target number of times is 3 times.
  • step 103 the register connection status control instruction is sent to the CPLD module, so that the register responds to disable and enable connection operations according to the received instruction, including:
  • Step 1031a send the register to disable the connection control command to the CPLD module, so that the register disables the connection operation according to the received command response; for the specific method of controlling the register to disable the connection by sending the command, refer to step 103 in the above-mentioned embodiment, and will not repeat them here .
  • Step 1032a in response to the timing operation, when the target time is reached, send a register enabling connection control command to the CPLD module, so that the register responds to enabling the connection operation according to the received command.
  • a register enabling connection control command to the CPLD module, so that the register responds to enabling the connection operation according to the received command.
  • the interval A certain period of time before the control register responds to enable connection operation can be 40-60ms, and the embodiment of the present application is preferably 50ms.
  • the setting of the target duration is not limited, and those skilled in the art can determine according to actual needs.
  • the register connection state control instruction includes: a register disable connection control instruction, a register enable connection control instruction, and an interval duration instruction between register disable and enable connection operations; as shown in FIG. 5 , in step 103 to The CPLD module sends the register connection state control command, so that the register disables and enables the connection operation according to the received command response, and also includes:
  • Step 1031b send the register to disable the connection control command to the CPLD module, so that the register disables the connection operation according to the received command response; for the specific method of controlling the register to disable the connection by sending the command, refer to step 103 in the above-mentioned embodiment, and will not go into details here .
  • Step 1032b send the register enable connection control instruction and the interval duration instruction between register disable and enable connection operations to the CPLD module, so that the register enables connection delay operation according to the received instruction response.
  • the register connection state control command sent to the CPLD includes three parts of the command: the register disables the connection control command, the register enables the connection control command, and the interval between the register disable and enable connection operations, and first sends the register disable connection to the CPLD module
  • the control command makes the register disable the connection operation according to the received command response, and then sends the register enable connection control command and the register disable and enable connection operation interval instructions to the CPLD module at the same time, so that the register first responds to a certain interval according to the received command Enable the connection after the timing operation, realize the connection delay control on the register, ensure that the PCIE module can reliably complete the initialization and retraining operations, and improve the success rate of bandwidth deceleration recovery.
  • the method further includes: sending the number of repairs for reducing the bandwidth of the PCIE module and the repair result corresponding to each repair operation to a register of the CPLD module for storage.
  • the repair times and repair results corresponding to each repair operation are sent to the register for storage, so that users can use the repair data recorded in the CPLD module to analyze the repair results of bandwidth exceptions.
  • the method further includes: sending the bandwidth reduction information of the PCIE module to the CPLD module, so that the CPLD module stores the bandwidth reduction information in a register.
  • the bandwidth deceleration information may include, but not limited to, the bandwidth abnormal time, the device status when the abnormality occurs, and the abnormal degree of the bandwidth deceleration.
  • the bandwidth deceleration information may include, but not limited to, the bandwidth abnormal time, the device status when the abnormality occurs, and the abnormal degree of the bandwidth deceleration.
  • the problem of bandwidth slowdown in the chip can be repaired in time, which improves the reliability of the chip performance and is convenient for mass promotion and use in various industries.
  • a device for repairing bandwidth speed reduction is also provided, and the device is used to implement the above embodiments and optional implementation manners, and what has been explained will not be repeated.
  • the term "module” may be a combination of software and/or hardware that realizes a predetermined function.
  • the devices described in the following embodiments are preferably implemented in software, implementations in hardware, or a combination of software and hardware are also possible and contemplated.
  • the device is applied to the BIOS module.
  • the BIOS module is connected to one side of the CPLD module for communicating with the CPLD module.
  • the other side of the CPLD module is connected to a PCIE module configured with a target bandwidth for obtaining the PCIE module. link bandwidth; the device includes:
  • the link bandwidth acquisition module 301 is used to obtain the link bandwidth of the PCIE module from the CPLD module when the device starts;
  • the deceleration determination module 302 is used to compare the link bandwidth with the target bandwidth to determine whether the bandwidth deceleration occurs in the PCIE module;
  • the command sending module 303 is configured to send a register connection state control command to the CPLD module when the bandwidth of the PCIE module slows down, so that the register can disable and enable the connection operation according to the received command response.
  • the bandwidth deceleration repairing device when the BIOS module detects that the PCIE module has a bandwidth deceleration during the device startup phase, sends a register connection state control command to the CPLD module, and the control register is disabled according to the received command response. And enable the connection operation, so that the PCIE module link is re-initialized and the training operation is carried out to realize the link bandwidth repair.
  • the entire bandwidth speed reduction repair process register disables and enables the connection to only take milliseconds, which improves the timeliness of bandwidth speed reduction repair performance, which meets the requirements for the duration of device startup.
  • the instruction sending module 303 includes: a bandwidth configuration information detection module, which is used to detect the bandwidth configuration information of the PCIE module when the PCIE module has a bandwidth deceleration; an execution module, which is used when the PCIE module is configured with Bandwidth configures the graphics card, and executes the operation of sending register connection state control instructions to the CPLD module.
  • a bandwidth configuration information detection module which is used to detect the bandwidth configuration information of the PCIE module when the PCIE module has a bandwidth deceleration
  • an execution module which is used when the PCIE module is configured with Bandwidth configures the graphics card, and executes the operation of sending register connection state control instructions to the CPLD module.
  • the device also includes: a repair result detection module, which is used to detect the repair result of the bandwidth deceleration of the PCIE module; Send the register connection state control command to the CPLD module, so that the register responds to the step of disabling and enabling the connection operation according to the received command until the target number of times is reached.
  • a repair result detection module which is used to detect the repair result of the bandwidth deceleration of the PCIE module.
  • the instruction sending module 303 includes: a first instruction sending module, configured to send a register disable connection control instruction to the CPLD module, so that the register disables the connection operation according to the received instruction response; the second instruction sends The module is used to respond to the timing operation, and when the target time is reached, the register enable connection control instruction is sent to the CPLD module, so that the register responds to enable the connection operation according to the received instruction.
  • the register connection state control instruction includes: a register disable connection control instruction, a register enable connection control instruction, and an interval duration instruction between register disable and enable connection operations;
  • the instruction sending module 303 also includes: a third instruction The sending module is used to send the register disable connection control instruction to the CPLD module, so that the register disables the connection operation according to the received instruction response;
  • the fourth instruction sending module is used to send the register enable connection control instruction and the register disable and enable connection to the CPLD module
  • the interval duration instruction of the operation causes the register to enable the connection delay operation according to the received instruction response.
  • the device further includes: a first storage module, configured to send the number of repairs to the bandwidth reduction of the PCIE module and the repair result corresponding to each repair operation to a register of the CPLD module for storage.
  • the device further includes: a second storage module, configured to send the bandwidth reduction information of the PCIE module to the CPLD module, so that the CPLD module stores the bandwidth reduction information in a register.
  • the embodiment of the present application also provides an electronic device.
  • the electronic device may include a processor 401 and a memory 402, wherein the processor 401 and the memory 402 may be connected through a bus or in other ways.
  • FIG. Take the bus connection as an example.
  • the processor 401 may be a central processing unit (Central Processing Unit, CPU).
  • the processor 401 can also be other general processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or Other chips such as programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above-mentioned types of chips.
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array
  • Other chips such as programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above-mentioned types of chips.
  • the memory 402 as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs and modules, such as program instructions/ module.
  • the processor 401 executes various functional applications and data processing of the processor by running the non-transitory software programs, instructions and modules stored in the memory 402 , that is, implements the bandwidth slowdown recovery method in the above method embodiments.
  • the memory 402 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application program required by at least one function; the data storage area may store data created by the processor 401 and the like.
  • the memory 402 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices.
  • the storage 402 may optionally include storages that are remotely located relative to the processor 401, and these remote storages may be connected to the processor 401 through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • the one or more modules are stored in the memory 402 , and when executed by the processor 401 , execute the method for repairing bandwidth slowdown in the embodiment shown in FIGS. 1-5 .
  • the computer program 610 can be stored in a computer-readable In the storage medium 60, when the computer program 610 is executed, it may include the processes of the embodiments of the above-mentioned methods.
  • the computer-readable storage medium 60 can be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a flash memory (Flash Memory) , hard disk (Hard Disk Drive, abbreviation: HDD) or solid-state hard drive (Solid-State Drive, SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

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Abstract

本申请公开了一种带宽降速修复方法、装置、电子设备及存储介质，应用于BIOS模块，BIOS模块与包含有寄存器的CPLD模块一侧连接，用于与CPLD模块进行通信，CPLD模块另一侧与配置有目标带宽的PCIE模块连接，用于获取PCIE模块的链路带宽；方法包括：当设备启动时，从CPLD模块中获取PCIE模块的链路带宽；将链路带宽与目标带宽进行比对，确定PCIE模块是否出现带宽降速；当PCIE模块出现带宽降速，向CPLD模块发送寄存器连接状态控制指令，寄存器根据接收到的指令响应禁用和启用连接操作。

Description

一种带宽降速修复方法、装置、电子设备及存储介质
本申请要求在2021年10月08日提交中国专利局、申请号为202111168572.7、发明名称为“一种带宽降速修复方法、装置及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及设备带宽处理技术领域，具体涉及一种带宽降速修复方法、装置、电子设备及存储介质。
背景技术
PCIE(Peripheral Component Interconnect Express，快速外部设备互联)是一种高速串行计算机扩展总线标准。在PCIE的发展过程中，接口版本已从PCIE1.0发展到PCIE5.0，同时支持的带宽也由X1、X2逐步演变到X16、X32。对于支持PCIE3.0的CPU，CPU中的PCIE设备通常需要配置相应的标准带宽，如配置X16的标准带宽。但是在设备开机或重启过程中发现带宽配置完成的PCIE设备出现带宽降速的问题，如带宽由X16的带宽降到X1。
相关技术中，对于带宽降速的PCIE设备一般通过CPU拉两次复位进行带宽降速修复，但是第二次复位需要等第一次复位完成后PCIE设备稳定一段秒钟级的时长才能执行，一般两次复位操作之间所需的稳定时长为16秒，耗时较长且设备对开机时长也有一定的要求，故亟待提出一种新的带宽降速修复方法以提高带宽降速修复的及时性。
发明内容
因此，本申请要解决的技术问题在于克服现有带宽降速修复方式耗时较长的缺陷，从而提供一种带宽降速修复方法、装置、电子设备及存储介质。
根据第一方面，本申请实施例公开了一种带宽降速修复方法，应用于BIOS模块，所述BIOS模块与包含有寄存器的CPLD模块一侧连接，用于与所述CPLD模块进行通信，所述CPLD模块另一侧与配置有目标带宽的PCIE模块连接，用于获取所述PCIE模块的链路带宽；所述方法包括：当设备启动时，从CPLD模块中获取PCIE模块的链路带宽；将所述链路带宽与目标带宽进行比对，确定所述PCIE模块是否出现带宽降速；当所述PCIE模块出现带宽降速，向所述CPLD模块发送寄存器连接状态控制指令，使得所述寄存器根据接收到的指令响应禁用和启用连接操作。
可选地，当所述PCIE模块出现带宽降速，向所述CPLD模块发送寄存器连接状态控制指令，包括：当所述PCIE模块出现带宽降速，对所述PCIE模块进行带宽配置信息检测；当所述PCIE模块配置有带宽配置显卡，执行向所述CPLD模块发送寄存器连接状态控制指令的操作。
可选地，当所述PCIE模块出现带宽降速，向所述CPLD模块发送寄存器连接状态控制指令，使得所述寄存器根据接收到的指令响应禁用和启用连接操作之后，所述方法还包括：对所述PCIE模块的带宽降速修复结果进行检测；当所述PCIE模块仍出现带宽降速，重复所述向所述CPLD模块发送寄存器连接状态控制指令，使得所述寄存器根据接收到的指令响应禁用和启用连接操作的步骤，直至达到目标次数。
可选地，向所述CPLD模块发送寄存器连接状态控制指令，使得所述寄存器根据接收到的指令响应禁用和启用连接操作，包括：向所述CPLD模块发送寄存器禁用连接控制指令，使得所述寄存器根据接收到的指令响应禁用连接操作；响应计时操作，当达到目标时长向所述CPLD模块发送寄存器启用连接控制指令，使得所述寄存器根据接收到的指令响应启用连接操作。
可选地，所述寄存器连接状态控制指令包括：寄存器禁用连接控制指令、寄存器启用连接控制指令以及寄存器禁用与启用连接操作的间隔时长指令；向所述CPLD模块发送寄存器连接状态控制指令，使得所述寄存器根据接收到的指令响应禁用和启用连接操作，还包括：向所述CPLD模块发送所述寄存器禁 用连接控制指令，使得所述寄存器根据接收到的指令响应禁用连接操作；向所述CPLD模块发送所述寄存器启用连接控制指令以及寄存器禁用与启用连接操作的间隔时长指令，使得所述寄存器根据接收到的指令响应启用连接延时操作。
可选地，所述方法还包括：将对PCIE模块带宽降速的修复次数以及每一次修复操作对应的修复结果发送至所述CPLD模块的寄存器中存储。
可选地，所述方法还包括：将所述PCIE模块的带宽降速信息发送至所述CPLD模块，使得所述CPLD模块将所述降速信息存储在寄存器中。
可选地，所述BIOS模块与包含有寄存器的CPLD模块一侧连接，用于与所述CPLD模块进行通信包括：
所述BIOS模块通过CPU与包含有寄存器的CPLD模块一侧连接，所述BIOS模块通过IIC总线与所述CPLD模块进行通信。
根据第二方面，本申请实施例还公开了一种带宽降速修复装置，用于BIOS模块，所述BIOS模块与包含有寄存器的CPLD模块一侧连接，用于与所述CPLD模块进行通信，所述CPLD模块另一侧与配置有目标带宽的PCIE模块连接，用于获取所述PCIE模块的链路带宽；所述装置包括：链路带宽获取模块，用于当设备启动时，从CPLD模块中获取PCIE模块的链路带宽；降速确定模块，用于将所述链路带宽与目标带宽进行比对，确定所述PCIE模块是否出现带宽降速；指令发送模块，用于当所述PCIE模块出现带宽降速，向所述CPLD模块发送寄存器连接状态控制指令，使得所述寄存器根据接收到的指令响应禁用和启用连接操作。
可选地，所述BIOS模块与包含有寄存器的CPLD模块一侧连接，用于与所述CPLD模块进行通信包括：
所述BIOS模块通过CPU与包含有寄存器的CPLD模块一侧连接，所述BIOS模块通过IIC总线与所述CPLD模块进行通信。根据第三方面，本申请实施例还公开了一种电子设备，包括：至少一个处理器；以及与所述至少一个处理器通信连接的存储器；其中，所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器执 行如第一方面或第一方面任一可选实施方式所述的带宽降速修复方法的步骤。
根据第四方面，本申请实施方式还公开了一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现如第一方面或第一方面任一可选实施方式所述的带宽降速修复方法的步骤。
本申请技术方案，具有如下优点：
本申请提供的带宽降速修复方法/装置，应用于BIOS模块，BIOS模块与包含有寄存器的CPLD模块一侧连接，用于与CPLD模块进行通信，CPLD模块另一侧与配置有目标带宽的PCIE模块连接，用于获取PCIE模块的链路带宽，当设备启动时，从CPLD模块中获取PCIE模块的链路带宽，将链路带宽与目标带宽进行比对，确定PCIE模块是否出现带宽降速，当PCIE模块出现带宽降速，向CPLD模块发送寄存器连接状态控制指令，使得寄存器根据接收到的指令响应禁用和启用连接操作。当在设备启动阶段BIOS模块检测出PCIE模块出现带宽降速的情况时，向CPLD模块发送寄存器连接状态控制指令，控制寄存器根据接收到的指令响应禁用和启用连接操作，使得PCIE模块链路重新进行初始化以及训练操作继而实现链路带宽修复，整个带宽降速修复过程寄存器禁用与启用连接只需毫秒级的耗时，提高了带宽降速修复的及时性，满足了对设备开机时长的要求。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例中带宽降速修复方法的一个具体示例的流程图；
图2为本申请实施例中带宽降速修复方法的一个具体示例对应的结构示意图；
图3为本申请实施例中带宽降速修复方法的一个具体示例的流程图；
图4为本申请实施例中带宽降速修复方法的一个具体示例的流程图；
图5为本申请实施例中带宽降速修复方法的一个具体示例的流程图；
图6为本申请实施例中带宽降速修复装置的一个具体示例的原理框图；
图7为本申请实施例中电子设备的一个具体示例图；
图8为本申请实施例中存储介质的一个具体示例图。
具体实施方式
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，还可以是两个元件内部的连通，可以是无线连接，也可以是有线连接。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
BIOS(Basic Input Output System，基本输入输出系统)是一组固化到计算机内主板上的一个ROM芯片上的程序，其保存计算机最重要的基本输入输出程序，开机后自检程序和系统自启动程序。CPLD(Complex Programmable Logic Device，复杂可编程逻辑器件)是采用CMOS EPROM、EEPROM、快闪存储 器和SRAM等编程技术构成的高密度、高速度和低功耗的数字集成电路。
本申请实施例公开了一种带宽降速修复方法，应用于BIOS模块，如图2所示，该BIOS模块通过CPU与包含有寄存器的CPLD模块一侧连接，用于与CPLD模块进行通信，CPLD模块另一侧与配置有目标带宽的PCIE模块连接，用于获取PCIE模块的链路带宽。PCIE模块目标带宽的配置方式可以是将相应带宽的显卡(如PEX8733卡)插入到设备机箱内完成带宽配置。BIOS模块可以通过IIC(Inter-Integrated Circuit，集成电路总线)实现BIOS模块与CPLD模块之间的信息交互；同时PEX8733卡会把卡的相关信息，如卡的在位信息、复位信息、电源控制信息以及当前链路带宽信息等发送至CPLD模块。如图1所示，该方法包括如下步骤：
步骤101，当设备启动时，从CPLD模块中获取PCIE模块的链路带宽。
示例性地，设备启动过程可以包括设备开机或者设备重启过程，当检测到设备开机或设备重启时，通过BIOS模块从CPLD模块中获取PCIE模块的链路带宽。具体地，CPLD模块可以按照一定间隔时长从PCIE模块中获取当前链路带宽或者是CPLD模块在接收到BIOS模块发送的链路带宽获取请求时获取PCIE模块的当前链路带宽，继而通过IIC将获取到的链路带宽发送至BIOS模块。
步骤102，将链路带宽与目标带宽进行比对，确定PCIE模块是否出现带宽降速。当PCIE模块出现带宽降速，执行步骤103。
示例性地，该目标带宽可以为初始为PCIE模块配置的带宽，如配置PEX8733卡支持X16的带宽，则该目标带宽为X16。将获取到的链路带宽与目标带宽进行比对，当比对结果不一致则表明PCIE模块出现带宽降速情况，需要进行带宽降速恢复操作；当获取到的链路带宽与目标带宽一致，则停止响应带宽降速修复操作。
步骤103，向CPLD模块发送寄存器连接状态控制指令，使得寄存器根据接收到的指令响应禁用和启用连接操作。
示例性地，寄存器禁用连接与启用连接的状态转换可以通过改变寄存器地址偏移位来实现，如可以预先指定寄存器地址偏移位为“先指时，寄存器响应“，nable LINK(启用连接)”操作，寄存器地址偏移位为“址偏时，寄存器响应“，isable Link(禁用连接)”操作，故向CPLD模块发送的寄存器连接状态控制指令可以是用于改变寄存器地址偏移位的指令，通过发送改变寄存器地址偏移位指令，控制寄存器先响应禁用连接操作再响应启用连接操作。本申请实施例对寄存器地址偏移位的具体表征形式不作限定，本领域技术人员可以根据实际需要确定，只要通过改变地址偏移位来控制寄存器的禁用和启用连接操作即可。寄存器连接状态控制指令还可以是使用预先约定的通信协议先后向CPLD模块发送表达禁用和启用连接的一段协议指令，CPLD模块在接收到协议指令后按照预先约定的通信协议进行解析操作，根据解析结果来控制寄存器响应对应的连接操作。
本申请实施例提供的带宽降速修复方法，通过向CPLD模块发送寄存器连接状态控制指令，控制寄存器根据接收到的指令响应禁用和启用连接操作，使得PCIE模块链路重新进行初始化以及训练操作继而实现链路带宽修复。整个过程在实现了带宽降速修复的同时寄存器禁用与启用连接只需毫秒级的耗时，提高了带宽降速修复的及时性，满足了对设备开机时长的要求。当在linux系统下，可以使用setpci命令来完成上述带宽降速修复操作。
作为本申请一个可选实施方式，步骤103中当PCIE模块出现带宽降速，向CPLD模块发送寄存器连接状态控制指令，包括：对PCIE模块进行带宽配置信息检测；当PCIE模块配置有带宽配置显卡，执行向CPLD模块发送寄存器连接状态控制指令的操作。
示例性地，当检测到PCIE模块出现带宽降速，先对PCIE模块进行带宽配置信息检测，当PCIE模块配置有带宽配置显卡(如PEX8733卡)，执行后续的寄存器连接状态控制指令发送操作；当PCIE模块未配置有带宽配置显卡，仅仅存在带宽降速情况，停止向CPLD模块发送寄存器连接状态控制指令的操作，避免在设备机箱无卡插入的情况下执行无效的带宽恢复操作，影响设备开 机进度。
作为本申请一个可选实施方式，如图3所示，步骤103之后，该方法还包括：
步骤104，对PCIE模块的带宽降速修复结果进行检测。示例性地，带宽降速修复结果的检测方式可以是再次从CPLD模块中获取PCIE模块的链路带宽，将链路带宽与目标带宽进行比对，进而确定PCIE模块是否仍出现带宽降速情况。具体参见上述实施例对应步骤，在此不再赘述。
步骤105，当PCIE模块仍出现带宽降速，重复向CPLD模块发送寄存器连接状态控制指令，使得寄存器根据接收到的指令响应禁用和启用连接操作的步骤，直至达到目标次数。示例性地，本申请实施例对该目标次数不作限定，本领域技术人员可以根据实际需要确定。本申请实施例中该目标次数为3次，通过将带宽降速修复的次数设置为3次，在可以保证带宽降速可靠恢复的同时避免了过度重复修复对开机进度造成影响。
作为本申请一个可选实施方式，如图4所示，步骤103中向CPLD模块发送寄存器连接状态控制指令，使得寄存器根据接收到的指令响应禁用和启用连接操作，包括：
步骤1031a，向CPLD模块发送寄存器禁用连接控制指令，使得寄存器根据接收到的指令响应禁用连接操作；具体的通过发送指令来控制寄存器禁用连接的方式参见上述实施例中步骤103，在此不再赘述。
步骤1032a，响应计时操作，当达到目标时长向CPLD模块发送寄存器启用连接控制指令，使得寄存器根据接收到的指令响应启用连接操作。具体的通过发送指令来控制寄存器启用连接的方式参见上述实施例中步骤103，在此不再赘述。
示例性地，在寄存器先响应禁用连接、再响应启用连接的过程中，为了保证PCIE模块可以可靠完成初始化以及重新训练的操作，提高带宽降速恢复的成功率，在寄存器响应禁用连接操作后间隔一定的时长再控制寄存器响应启用连接操作。该目标时长可以为40-60ms，本申请实施例优选为50ms，对该目标 时长的设定不作限定，本领域技术人员可以根据实际需要确定。
作为本申请一个可选实施方式，该寄存器连接状态控制指令包括：寄存器禁用连接控制指令、寄存器启用连接控制指令以及寄存器禁用与启用连接操作的间隔时长指令；如图5所示，步骤103中向CPLD模块发送寄存器连接状态控制指令，使得寄存器根据接收到的指令响应禁用和启用连接操作，还包括：
步骤1031b，向CPLD模块发送寄存器禁用连接控制指令，使得寄存器根据接收到的指令响应禁用连接操作；具体的通过发送指令来控制寄存器禁用连接的方式参见上述实施例中步骤103，在此不再赘述。
步骤1032b，向CPLD模块发送寄存器启用连接控制指令以及寄存器禁用与启用连接操作的间隔时长指令，使得寄存器根据接收到的指令响应启用连接延时操作。具体的通过发送指令来控制寄存器启用连接的方式参见上述实施例中步骤103，在此不再赘述。
示例性地，向CPLD发送的寄存器连接状态控制指令同时包含三部分指令：寄存器禁用连接控制指令、寄存器启用连接控制指令以及寄存器禁用与启用连接操作的间隔时长指令，先向CPLD模块发送寄存器禁用连接控制指令，使得寄存器根据接收到的指令响应禁用连接操作，再同时向CPLD模块发送寄存器启用连接控制指令以及寄存器禁用与启用连接操作的间隔时长指令，使得寄存器根据接收到的指令先响应一定间隔时长的计时操作后再启用连接，实现对寄存器启用连接延时控制，保证PCIE模块可以可靠完成初始化以及重新训练的操作，提高带宽降速恢复的成功率。
作为本申请一个可选实施方式，该方法还包括：将对PCIE模块带宽降速的修复次数以及每一次修复操作对应的修复结果发送至CPLD模块的寄存器中存储。将修复次数和每一次修复操作对应的修复结果发送至寄存器中存储，便于用户利用CPLD模块中记录的修复数据进行带宽异常修复结果分析。
作为本申请一个可选实施方式，该方法还包括：将PCIE模块的带宽降速信息发送至CPLD模块，使得CPLD模块将带宽降速信息存储在寄存器中。
示例性地，带宽降速信息可以包括但不限于带宽异常时间、发生异常时的 设备状态以及带宽降速异常程度。通过将带宽降速信息存储在CPLD模块的寄存器中，便于用户对带宽异常情况进行统计分析的同时也利于其他与CPLD模块连接的器件模块从CPLD中及时获知PCIE模块的带宽情况。
通过上述实施例记载的方法，可以及时对芯片中出现的带宽降速问题进行修复，提升了芯片性能的可靠性，便于在各行各业批量推广使用。
在本申请实施例中还提供了一种带宽降速修复装置，该装置用于实现上述实施例及可选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
如图6所示，该装置应用于BIOS模块，BIOS模块与CPLD模块一侧连接，用于与CPLD模块进行通信，CPLD模块另一侧与配置有目标带宽的PCIE模块连接，用于获取PCIE模块的链路带宽；该装置包括：
链路带宽获取模块301，用于当设备启动时，从CPLD模块中获取PCIE模块的链路带宽；
降速确定模块302，用于将链路带宽与目标带宽进行比对，确定PCIE模块是否出现带宽降速；
指令发送模块303，用于当PCIE模块出现带宽降速，向CPLD模块发送寄存器连接状态控制指令，使得寄存器根据接收到的指令响应禁用和启用连接操作。
本申请实施例提供的带宽降速修复装置，当在设备启动阶段BIOS模块检测出PCIE模块出现带宽降速的情况时，向CPLD模块发送寄存器连接状态控制指令，控制寄存器根据接收到的指令响应禁用和启用连接操作，使得PCIE模块链路重新进行初始化以及训练操作继而实现链路带宽修复，整个带宽降速修复过程寄存器禁用与启用连接只需毫秒级的耗时，提高了带宽降速修复的及时性，满足了对设备开机时长的要求。
作为本申请一个可选实施方式，指令发送模块303包括：带宽配置信息检测模块，用于当PCIE模块出现带宽降速，对PCIE模块进行带宽配置信息检测；执行模块，用于当PCIE模块配置有带宽配置显卡，执行向CPLD模块发送寄存器连接状态控制指令的操作。
作为本申请一个可选实施方式，该装置还包括：修复结果检测模块，用于对PCIE模块的带宽降速修复结果进行检测；指令重复发送模块，用于当PCIE模块仍出现带宽降速，重复向CPLD模块发送寄存器连接状态控制指令，使得寄存器根据接收到的指令响应禁用和启用连接操作的步骤，直至达到目标次数。
作为本申请一个可选实施方式，指令发送模块303，包括：第一指令发送模块，用于向CPLD模块发送寄存器禁用连接控制指令，使得寄存器根据接收到的指令响应禁用连接操作；第二指令发送模块，用于响应计时操作，当达到目标时长向CPLD模块发送寄存器启用连接控制指令，使得寄存器根据接收到的指令响应启用连接操作。
作为本申请一个可选实施方式，寄存器连接状态控制指令包括：寄存器禁用连接控制指令、寄存器启用连接控制指令以及寄存器禁用与启用连接操作的间隔时长指令；指令发送模块303，还包括：第三指令发送模块，用于向CPLD模块发送寄存器禁用连接控制指令，使得寄存器根据接收到的指令响应禁用连接操作；第四指令发送模块，用于向CPLD模块发送寄存器启用连接控制指令以及寄存器禁用与启用连接操作的间隔时长指令，使得寄存器根据接收到的指令响应启用连接延时操作。
作为本申请一个可选实施方式，该装置还包括：第一存储模块，用于将对PCIE模块带宽降速的修复次数以及每一次修复操作对应的修复结果发送至CPLD模块的寄存器中存储。
作为本申请一个可选实施方式，该装置还包括：第二存储模块，用于将PCIE模块的带宽降速信息发送至CPLD模块，使得CPLD模块将带宽降速信息存储在寄存器中。
本申请实施例还提供了一种电子设备，如图7所示，该电子设备可以包括 处理器401和存储器402，其中处理器401和存储器402可以通过总线或者其他方式连接，图7中以通过总线连接为例。
处理器401可以为中央处理器(Central Processing Unit，CPU)。处理器401还可以为其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等芯片，或者上述各类芯片的组合。
存储器402作为一种非暂态计算机可读存储介质，可用于存储非暂态软件程序、非暂态计算机可执行程序以及模块，如本申请实施例中的带宽降速修复方法对应的程序指令/模块。处理器401通过运行存储在存储器402中的非暂态软件程序、指令以及模块，从而执行处理器的各种功能应用以及数据处理，即实现上述方法实施例中的带宽降速修复方法。
存储器402可以包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需要的应用程序；存储数据区可存储处理器401所创建的数据等。此外，存储器402可以包括高速随机存取存储器，还可以包括非暂态存储器，例如至少一个磁盘存储器件、闪存器件、或其他非暂态固态存储器件。在一些实施例中，存储器402可选包括相对于处理器401远程设置的存储器，这些远程存储器可以通过网络连接至处理器401。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
所述一个或者多个模块存储在所述存储器402中，当被所述处理器401执行时，执行如图1-图5所示实施例中的带宽降速修复方法。
上述电子设备具体细节可以对应参阅图1-图5所示的实施例中对应的相关描述和效果进行理解，此处不再赘述。
本领域技术人员可以理解，实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，如图8所示，所述计算机程序610可存储于一计算机可读存储介质60中，该计算机程序610在执行时，可包括如上述各方法的实施例的流程。其中，所述计算机可读存储介质60可为磁碟、 光盘、只读存储记忆体(Read-Only Memory，ROM)、随机存储记忆体(Random Access Memory，RAM)、快闪存储器(Flash Memory)、硬盘(Hard Disk Drive，缩写：HDD)或固态硬盘(Solid-State Drive，SSD)等；所述存储介质还可以包括上述种类的存储器的组合。
虽然结合附图描述了本申请的实施例，但是本领域技术人员可以在不脱离本申请的精神和范围的情况下作出各种修改和变型，这样的修改和变型均落入由所附权利要求所限定的范围之内。

Claims (12)

  1. 一种带宽降速修复方法，其特征在于，应用于BIOS模块，所述BIOS模块与包含有寄存器的CPLD模块一侧连接，用于与所述CPLD模块进行通信，所述CPLD模块另一侧与配置有目标带宽的PCIE模块连接，用于获取所述PCIE模块的链路带宽；所述方法包括：
    当设备启动时，从CPLD模块中获取PCIE模块的链路带宽；
    将所述链路带宽与目标带宽进行比对，确定所述PCIE模块是否出现带宽降速；
    当所述PCIE模块出现带宽降速，向所述CPLD模块发送寄存器连接状态控制指令，使得所述寄存器根据接收到的指令响应禁用和启用连接操作。
  2. 根据权利要求1所述的方法，其特征在于，当所述PCIE模块出现带宽降速，向所述CPLD模块发送寄存器连接状态控制指令，包括：
    当所述PCIE模块出现带宽降速，对所述PCIE模块进行带宽配置信息检测；
    当所述PCIE模块配置有带宽配置显卡，执行向所述CPLD模块发送寄存器连接状态控制指令的操作。
  3. 根据权利要求1所述的方法，其特征在于，当所述PCIE模块出现带宽降速，向所述CPLD模块发送寄存器连接状态控制指令，使得所述寄存器根据接收到的指令响应禁用和启用连接操作之后，所述方法还包括：
    对所述PCIE模块的带宽降速修复结果进行检测；
    当所述PCIE模块仍出现带宽降速，重复所述向所述CPLD模块发送寄存器连接状态控制指令，使得所述寄存器根据接收到的指令响应禁用和启用连接操作的步骤，直至达到目标次数。
  4. 根据权利要求1所述的方法，其特征在于，向所述CPLD模块发送寄存器连接状态控制指令，使得所述寄存器根据接收到的指令响应禁用和启用连接操作，包括：
    向所述CPLD模块发送寄存器禁用连接控制指令，使得所述寄存器根据接收到的指令响应禁用连接操作；
    响应计时操作，当达到目标时长向所述CPLD模块发送寄存器启用连接控制指令，使得所述寄存器根据接收到的指令响应启用连接操作。
  5. 根据权利要求1所述的方法，其特征在于，所述寄存器连接状态控制指令包括：寄存器禁用连接控制指令、寄存器启用连接控制指令以及寄存器禁用与启用连接操作的间隔时长指令；
    向所述CPLD模块发送寄存器连接状态控制指令，使得所述寄存器根据接收到的指令响应禁用和启用连接操作，还包括：
    向所述CPLD模块发送所述寄存器禁用连接控制指令，使得所述寄存器根据接收到的指令响应禁用连接操作；
    向所述CPLD模块发送所述寄存器启用连接控制指令以及寄存器禁用与启用连接操作的间隔时长指令，使得所述寄存器根据接收到的指令响应启用连接延时操作。
  6. 根据权利要求3所述的方法，其特征在于，所述方法还包括：
    将对PCIE模块带宽降速的修复次数以及每一次修复操作对应的修复结果发送至所述CPLD模块的寄存器中存储。
  7. 根据权利要求1至6中任一项所述的方法，其特征在于，所述方法还包括：
    将所述PCIE模块的带宽降速信息发送至所述CPLD模块，使得所述CPLD模块将所述降速信息存储在寄存器中。
  8. 根据权利要求1所述的方法，其特征在于，所述BIOS模块与包含有寄存器的CPLD模块一侧连接，用于与所述CPLD模块进行通信包括：
    所述BIOS模块通过CPU与包含有寄存器的CPLD模块一侧连接，所述BIOS模块通过IIC总线与所述CPLD模块进行通信。
  9. 一种带宽降速修复装置，其特征在于，用于BIOS模块，所述BIOS模块与包含有寄存器的CPLD模块一侧连接，用于与所述CPLD模块进行通信，所述CPLD模块另一侧与配置有目标带宽的PCIE模块连接，用于获取所述PCIE模块的链路带宽；所述装置包括：
    链路带宽获取模块，用于当设备启动时，从CPLD模块中获取PCIE模块的链路带宽；
    降速确定模块，用于将所述链路带宽与目标带宽进行比对，确定所述PCIE模块是否出现带宽降速；
    指令发送模块，用于当所述PCIE模块出现带宽降速，向所述CPLD模块发送寄存器连接状态控制指令，使得所述寄存器根据接收到的指令响应禁用和启用连接操作。
  10. 根据权利要求9所述的装置，其特征在于，所述BIOS模块与包含有寄存器的CPLD模块一侧连接，用于与所述CPLD模块进行通信包括：
    所述BIOS模块通过CPU与包含有寄存器的CPLD模块一侧连接，所述BIOS模块通过IIC总线与所述CPLD模块进行通信。
  11. 一种电子设备，其特征在于，包括：至少一个处理器；以及与所述至少一个处理器通信连接的存储器；其中，所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器执行如权利要求1至8中任一所述的带宽降速修复方法的步骤。
  12. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求1至8中任一项所述的带宽降速修复方法的步骤。
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