WO2017088531A1 - TigerSharc系列DSP启动管理芯片及方法 - Google Patents

TigerSharc系列DSP启动管理芯片及方法 Download PDF

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WO2017088531A1
WO2017088531A1 PCT/CN2016/095295 CN2016095295W WO2017088531A1 WO 2017088531 A1 WO2017088531 A1 WO 2017088531A1 CN 2016095295 W CN2016095295 W CN 2016095295W WO 2017088531 A1 WO2017088531 A1 WO 2017088531A1
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Prior art keywords
code segment
dsp
chip
tigersharc
management
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PCT/CN2016/095295
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English (en)
French (fr)
Inventor
李震
孙国斌
张小松
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中车青岛四方车辆研究所有限公司
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Priority claimed from CN201610183445.7A external-priority patent/CN105786527B/zh
Priority claimed from CN201620246409.6U external-priority patent/CN205540691U/zh
Application filed by 中车青岛四方车辆研究所有限公司 filed Critical 中车青岛四方车辆研究所有限公司
Priority to US15/549,661 priority Critical patent/US10203962B2/en
Priority to JP2017546838A priority patent/JP6334831B2/ja
Priority to RU2017127786A priority patent/RU2641465C1/ru
Priority to EP16867758.1A priority patent/EP3236350B1/en
Publication of WO2017088531A1 publication Critical patent/WO2017088531A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4406—Loading of operating system

Definitions

  • the invention belongs to the technical field of digital signal processing, and relates to a startup management chip applied to a TigerSharc series DSP chip and a startup management method thereof.
  • the TigerSharc series DSP chip is a high-performance DSP chip of ADI. It has powerful computing processing capability, its execution efficiency is up to 4800MMACS, the processor frequency is up to 600Mhz, and the on-chip RAM is up to 24Mbits. The chip contains two independent computing cores. Up to four instructions can be executed in one clock cycle. This series of chips has multi-DSP co-processing capability, up to 8 DSP co-processing, suitable for high-speed and high-performance signal processing applications.
  • the TS20x does not have on-chip non-volatile program memory, the chip can only be imported externally.
  • PROM boot is more commonly used, but the confidentiality is poor;
  • LinkPort boot is mainly used for downloading programs between DSP chips, and the versatility is poor;
  • No boot is mainly used for debugging, and is generally not recommended;
  • Host boot has its own unique in the common bus system.
  • the advantage is that the host can be started by the external bus through the external bus. This method can achieve good compatibility between the TigerSharc series DSP chip and other systems.
  • Host boot starts during the boot process, the write timing of the DSP is stricter, the boot process is more error-prone, and the boot mode is slower for longer boot code.
  • the boot mode of the traditional TigerSharc series DSP chip is: use the external bus of the DSP to send the startup program to the AUTODMA port (fixed address) of the DSP.
  • the startup program is received using the AUTODMA port, and the host host has control of the bus during startup.
  • This startup mode can be more flexible to implement DSP startup from the external bus, and is more suitable for downloading programs to the TigerSharc series DSP through a common external bus using an FPGA or other processor.
  • the traditional Host boot startup mode needs to add a delay after the boot loader and the first five Words of the last session are written into the TigerSharc series DSP chip.
  • the DSP After each Word is written, it is necessary to wait for the DSP to process the currently written Word before writing the next Word, and the processing time of the non-zero code segment and the zero code segment is different. If the write speed is too fast, it will easily cause the chip to fail to start. Since the code content download of the code segment accounts for the vast majority of the download process time of the entire program, each Word write needs to wait for the response of the TigerSharc series DSP. This will affect the quick start of the TigerSharc family of DSPs. The longer the code, the longer the boot time.
  • the write data is also subject to the acknowledgment signal ACK, the bus lock signal BUSLOCK, and the bus enable signal HBG.
  • the acknowledgment signal ACK, the bus lock signal BUSLOCK, and the bus enable signal HBG signal must be stable, in accordance with the startup logic, TigerSharc series It can be written only when the DSP is ready. Otherwise, if there is 1 data loss, the TigerSharc series DSP will not start.
  • the purpose of the present invention is to design an improved Host boot boot management chip and a boot method for the original Host boot boot method with long startup time and poor stability, that is, the TigerSharc series DSP management based on the improved Host boot startup method.
  • the chip enables fast start-up of multiple TigerSharc series DSP chips.
  • the technical scheme of the invention is: TigerSharc series DSP startup management chip, including interface unit, dual port RAM unit, management unit and DSP download management unit; interface unit is respectively connected with dual port RAM unit and management unit; management unit is connected by control line To the external control system, the management unit is also connected to the dual port RAM unit and the DSP download management unit respectively; the DSP download management unit is connected to at least one TigerSharc series DSP chip via the parallel bus, and the TigerSharc series DSP chip does not exceed 8 pieces, that is, one piece is started.
  • the management chip drives up to 8 DSP chips; it also includes a Flash driver unit and a NOR Flash chip; the management unit is connected to the Flash driver unit; the dual-port RAM unit is connected to the NOR Flash chip via the Flash driver unit; the NOR Flash chip is driven by the Flash driver unit and the DSP. Download snap-in communication.
  • the interface unit comprises a PCI bus interface, a CAN bus interface and an RS232 bus interface, all connected to the management unit and the dual port RAM unit.
  • it also includes a watchdog management circuit that is connected to each of the TigerSharc series DSP chips.
  • the TigerSharc series DSP startup management chip is used to start the TigerSharc series DSP startup management method, and the startup mode is selected by the management unit;
  • the management unit controls the selection to download the DSP startup program via the interface unit, or selects to be started by the NOR Flash chip or started via the external bus;
  • the external bus is the external bus connected to the interface unit. Therefore, the download mode of the DSP startup program is that the management unit controls the interface to download the TigerSharc series DSP startup program via the external bus, or selects to start the NOR Flash chip, and downloads the TigerSharc series startup program;
  • the management unit drives the NOR Flash chip to download the startup program through the Flash driver unit, the DSP startup program is stored in the NOR Flash chip, and the TigerSharc series DSP chip reads the startup in the TigerSharc series DSP chip via the DSP download management unit. program;
  • the external bus is an external bus connected by the interface unit, including but not limited to a PCI bus, a CAN bus, an RS232 bus, and the management unit is used for controlling the operation of the interface unit, the dual port RAM unit, and the DSP download management unit.
  • the DSP startup program includes a code segment portion and a Bootloader portion of 256words, and the code segment portion includes N segments of code segments that are sequentially connected end to end, and the number of N is the same as the number of TigerSharc series DSP chips.
  • the code segment portion includes a non-zero code segment, a zero code segment, and a final code segment.
  • the non-zero code segment contains: (1) non-zero code segment header information, (2) non-zero code segment storage address, and (3) non-zero code segment content.
  • the non-zero code segment header information includes: (1) the code segment identification category information (non-zero code segment, zero code segment, final code segment), and (2) the ID number of the TigerSharc series DSP chip to which the non-zero code segment belongs , (3) the content length of this non-zero code segment.
  • the zero code segment contains: (1) zero code segment header information, and (2) zero code segment storage address.
  • the zero code segment header information includes: (1) the code segment identification category information (non-zero code segment, zero code segment, final code segment), and (2) the ID number of the TigerSharc series DSP chip to which the zero code segment belongs, ( 3) The content length of this zero code segment.
  • the final code segment contains: (1) the final code segment header information, (2) the final code segment storage address, and (3) the final code segment content.
  • the final code segment header information includes: (1) the code segment identification category information (non-zero code segment, zero code segment, final code segment), and (2) the ID number of the TigerSharc series DSP chip to which the final code segment belongs. (3) Final code information for 256words.
  • the Boot loader part is a program before the startup kernel runs, used for initialization, establishing a memory space mapping, and adjusting the operating environment of the software and hardware.
  • the code segment is not the final code segment, according to the size information and address information of this code segment, the content of this code segment is written into the corresponding DSP memory through the DSP parallel bus by means of the 1-stage pipeline reading and writing.
  • the final code segment is written into the DSP memory to complete the startup of the DSP.
  • the update program is re-downloaded to the NOR Flash chip.
  • the code segment includes a non-zero code segment, a zero code segment, and a final code segment;
  • the non-zero code segment includes the ID information of the TigerSharc series DSP chip to which the code segment belongs, the address information stored in the code segment, the size of the code segment, and the code.
  • Paragraph Non-zero content information the zero code segment contains the ID information of the TigerSharc series DSP chip to which the code segment belongs, the address information stored in the code segment and the size of the code segment;
  • the final code segment contains the ID information of the TigerSharc series DSP chip and the 256Words of the code segment.
  • Final code information is included in the code segment, the code segment includes a non-zero code segment, a zero code segment, and a final code segment;
  • the non-zero code segment includes the ID information of the TigerSharc series DSP chip to which the code segment belongs, the address information stored in the code segment, the size of the code segment, and the code.
  • Paragraph Non-zero content information
  • the invention proposes an improved design method of the Host boot, which improves the startup speed of the TigerSharc series DSP chip while improving the stability of the startup process.
  • the TigerSharc series DSP startup management chip is designed. On the one hand, it reduces the difficulty of using the TigerSharc series DSP chip, on the other hand, it improves the startup speed and stability of the TigerSharc series DSP chip.
  • the invention can effectively manage the startup of multiple TigerSharc series DSPs. Reduce the difficulty of using the TigerSharc series of DSPs.
  • the TigerSharc family of DSPs can be started via PCI, CAN, RS232, and parallel buses. Provides connectivity to the TigerSharc family of DSPs for many incompatible systems.
  • the invention has a watchdog function, which can manage multiple pieces of TigerSharc series DSP at the same time.
  • the DSP can be reset and the program download of the DSP can be re-implemented.
  • the invention provides two startup modes, one is started by a NOR Flash chip, and the program directly stores the program in the NOR Flash chip, the NOR Flash chip is used as a temporary storage area of the startup program, and the subsequent startup can be directly in the NOR Flash.
  • the startup program is called in the chip. It only needs to re-download the startup program when the program is updated. It does not need to read the startup program from the outside every time.
  • Figure 1 is a schematic view of the structure of the present invention.
  • Figure 2 is a schematic diagram of the structure of the startup program code.
  • FIG. 3 is a flowchart of a host boot startup procedure according to the present invention.
  • the TigerSharc series DSP boot management chip is a boot management chip built using FPGA, including Interface unit, dual port RAM unit, management unit and DSP download management unit.
  • the interface unit includes a PCI bus interface, a CAN bus interface and an RS232 bus interface, all connected to the management unit and the dual port RAM unit, and provides various interfaces to the external system through the PCI communication module, the CAN communication module and the RS232 communication module.
  • the PCI communication module is responsible for the PCI bus access via the PCI bus interface
  • the CAN communication module is responsible for the CAN bus access via the CAN bus interface
  • the RS232 communication module is responsible for the RS232 bus access via the RS232 bus interface.
  • the dual port RAM is used as a temporary receiving code as a temporary storage unit for the boot program.
  • the management unit is connected to the external control system via the control line, and the control system is the controller of the FPGA startup management chip, and the startup control command is issued.
  • the management unit is also connected to the dual port RAM unit and the DSP download management unit respectively; the DSP download management unit is connected to at least one TigerSharc series DSP chip via the parallel bus, and the TigerSharc series DSP chip does not exceed 8 pieces, that is, one boot management chip drives up to 8 The TigerSharc series of DSP chips.
  • the number of DSP chips that can be driven is mainly limited by the FPGA driver interface.
  • the utility model also includes a flash driving unit and a NOR flash chip; the management unit is connected to the flash driving unit; the dual port RAM unit is connected to the NOR flash chip via the flash driving unit; the NOR flash chip communicates with the DSP download management unit via the flash driving unit.
  • the NOR Flash chip is used as a memory chip for the boot program to store the downloaded boot program.
  • This structure of the management chip provides two startup programs to the startup program channel of the TigerSharc series DSP chip.
  • One is to download the startup program from the external bus through the interface unit, and pass it to the to-be-launched via the dual-port RAM and DSP download management unit.
  • TigerSharc series DSP chip this way needs to re-download the boot program from the external bus every time; one is to directly download the boot program in the NOR Flash chip, each time directly read the boot program from the NOR Flash chip, and when booting
  • the program is updated, the updated startup program is downloaded to the NOR Flash chip again.
  • the updated startup program is directly read from the NOR Flash chip.
  • the way and path to download the launcher can be controlled through the snap-in control.
  • the system also includes a watchdog management circuit that interfaces with each TigerSharc family of DSP chips to enable watchdog management and monitoring of multiple TigerSharc series DSPs.
  • the DSP accesses the registers of the watchdog management circuit in the management chip through the external bus.
  • the TigerSharc series DSP works abnormally, the TigerSharc series DSP can be reset and the program re-download can be re-implemented.
  • the TigerSharc series DSP startup management chip is used to start the TigerSharc series DSP startup management method, and the startup mode needs to be selected by the management unit;
  • the management unit controls the selection to download the DSP startup program via the interface unit, or selects to start or go through the NOR Flash chip. Part bus start;
  • the DSP startup program is stored in the NOR Flash chip, and the TigerSharc series DSP chip reads the startup program in the TigerSharc series DSP chip via the DSP download management module;
  • the DSP startup program is passed to the TigerSharc series DSP chip via the interface unit, dual port RAM, and DSP download management unit.
  • the DSP startup program includes a code segment portion and a Bootloader portion of 256words.
  • the code segment portion includes N segments of code segments that are sequentially connected end to end. The number of N is the same as the number of TigerSharc series DSP chips.
  • the segment contains the ID information of the TigerSharc series DSP chip to which the code segment belongs, the address information stored in the code segment, and the code information.
  • the code segment includes 8 code segments, DSP1 code segment, DSP2 code segment... DSP8 code segment.
  • the specific structure of each code segment includes a non-zero code segment, a zero code segment, and a final code segment, specifically:
  • the non-zero code segment contains: (1) non-zero code segment header information, (2) non-zero code segment storage address, and (3) non-zero code segment content.
  • the non-zero code segment header information includes: (1) the code segment identification category information (non-zero code segment, zero code segment, final code segment), and (2) the ID number of the DSP to which the non-zero code segment belongs (ie, TigerSharc) Series DSP1, TigerSharc series DSP2...TigerSharc series DSP 8), (3) The content length of this non-zero code segment.
  • the zero code segment contains: (1) zero code segment header information, and (2) zero code segment storage address.
  • the zero code segment header information includes: (1) the code segment identification category information (non-zero code segment, zero code segment, final code segment), (2) the ID number of the DSP to which the zero code segment belongs, (3) The length of the content of the zero code segment.
  • the final code segment contains: (1) the final code segment header information, (2) the final code segment storage address, and (3) the final code segment content.
  • the final code segment header information includes: (1) the code segment identifies the category information (non-zero code segment, zero code segment, final code segment), and (2) the ID number of the DSP to which the final code segment belongs. (3) Final code information for 256words.
  • the specific format of the N-segment code segment that is connected end to end is that the non-zero code segment, the zero code segment and the final code segment are sequentially connected; wherein the non-zero code segment includes the non-zero code segments.
  • Zero code segment 1, non-zero code segment 2, non-zero code segment 3... non-zero code segment n1 zero code segment including sequentially connected zero code segment 1, zero code segment 2, zero code segment 3... Zero code segment n2, where n1 and n2 are both equal to N.
  • the code segment header information includes: 1, the ID information of the DSP; 2. the attribute of the code segment (non-zero code segment, zero code segment or final code segment); 3 code The length of the segment.
  • non-zero code segment 1, non-zero code segment 2, non-zero code segment 3, non-zero code segment n1 are sequentially read sequentially.
  • the zero code segment 1, the zero code segment 2, the zero code segment 3, the non-zero code segment n2 are sequentially read until Whether the ID number of the DSP in the zero code segment matches the TigerSharc series DSP N to be started, and finally reads the final code segment.
  • the code segment is not the final code segment, that is, if the code segment read is a non-zero code segment or a zero code segment, according to the size information and the address information of the code segment, the first-level pipeline writing method is adopted.
  • the DSP parallel bus writes the contents of this code segment into the corresponding TigerSharc series DSP memory, which is the TigerSharc series DSP to be started.
  • code segment is the final code segment
  • the process of reading the code segment header information is performed after a delay of 10 ⁇ s; the process of writing the final code segment into the DSP memory is to first write the first 5 Words, delay 10 ⁇ s, and then write the remaining 252Words.
  • the improved Host boot applies the pipelined mechanism of the TigerSharc family of DSPs to the standard Host boot process.
  • the pipeline write mechanism is used instead of the AutoDMA write mechanism.
  • the TigerSharc family of DSPs uses a common external bus design, and on-chip memory can be read and written via the external bus.
  • Using a 1-stage pipeline write has a very high write speed, and a Word write can be completed in one DSP clock cycle. This method greatly reduces the write time of the code content relative to the AutoDMA mode, thus reducing the download time of the entire program.

Abstract

TigerSharc系列DSP启动管理芯片及管理方法，其启动管理芯片包括接口单元、双口RAM单元、管理单元及DSP下载管理单元；还包括Flash驱动单元和NOR Flash芯片；管理单元与Flash驱动单元相连；双口RAM单元经Flash驱动单元连接至NOR Flash芯片；NOR Flash芯片经Flash驱动单元与DSP下载管理单元通信。管理芯片提供了NOR Flash芯片和外部总线启动两种启动模式，并改进了Host boot启动方法，提供两种启动程序下载方式，可极大的提高TigerSharc系列DSP芯片的启动速度。

Description

TigerSharc系列DSP启动管理芯片及方法 技术领域
本发明属于数字信号处理技术领域，涉及一种应用于TigerSharc系列DSP芯片的启动管理芯片及其启动管理方法。
背景技术
TigerSharc系列DSP芯片是ADI公司的高性能DSP芯片，具有超强的运算处理能力，其执行效率高达4800MMACS，处理器主频高达600Mhz，片内RAM高达24Mbits；芯片内部含有两个独立的运算核心，最高可以在一个时钟周期内执行4条指令。此系列芯片具有多DSP协同处理能力，最多可达8片DSP协同处理，适合在高速高性能信号处理领域应用。
由于TS20x没有片内非可易失程序存储器，因此芯片只能通过外部导入程序。其启动程序下载的模式共有4种：PROM boot，Host boot，LinkPort boot和No boot。其中PROM boot较为常用，但保密性差；LinkPort boot主要用于DSP芯片间程序的下载，通用性较差；No boot主要用于调试，一般不推荐使用；Host boot在共总线系统中有其独到的优势，可使用主机通过外部总线实现芯片启动，这种方法可以实现TigerSharc系列DSP芯片和其它系统之间良好的兼容。而Host boot启动在启动过程中对DSP的写入时序要求较为严格，启动过程比较容易出错，同时对较长的启动代码，Host boot模式启动较慢。
传统的TigerSharc系列DSP芯片的Host boot的启动方式为：利用DSP的外总线，向DSP的AUTODMA端口(固定地址)发送启动程序。其启动程序使用AUTODMA端口接收，Host主机在启动过程中具有总线的控制权。这种启动模式可以较为灵活的实现从外总线上实现DSP的启动，比较适合使用FPGA或者其他处理器通过常用的外部总线向TigerSharc系列DSP进行程序下载。
但传统的Host boot启动方式还存在以下不足：
(1)为了保证启动的稳定性，传统的Host boot启动方式在boot loader以及最后一个session的头5个Words写入TigerSharc系列DSP芯片之后，需要加入延时。同时在每一个Word写入之后都需要等待DSP处理完当前写入的Word以后才可以写入下一个Word，且非零代码段和零代码段的处理时间不同。如果写入速度过快，极易造成芯片无法启动。由于代码段的代码内容下载占整个程序下载过程时间的绝大多数，每一个Word的写入，都需要的等待TigerSharc系列DSP的响应。这将影响TigerSharc系列DSP的快速启动，代码的长度越长，启动时间就越长。
(2)写入数据还受到确认信号ACK、总线锁死信号BUSLOCK、总线允许信号HBG的制约，必须在确认信号ACK、总线锁死信号BUSLOCK、总线允许信号HBG信号稳定，符合启动逻辑，TigerSharc系列DSP准备好的情况下才可以写入。否则如果有1个数据丢失都将导致TigerSharc系列DSP无法启动。
发明内容
本发明的目的在于针对原有Host boot启动方法的启动时间过长、稳定性差的不足，设计一种改进的Host boot启动管理芯片，及启动方法，即基于改进Host boot启动方法的TigerSharc系列DSP管理芯片，实现多片TigerSharc系列DSP芯片的快速启动。
本发明的技术方案为：TigerSharc系列DSP启动管理芯片，包括接口单元、双口RAM单元、管理单元及DSP下载管理单元；接口单元分别与双口RAM单元和管理单元相连；管理单元经控制线连接至外部控制系统，管理单元还分别与双口RAM单元及DSP下载管理单元相连；DSP下载管理单元经并行总线连接至至少一片TigerSharc系列DSP芯片，且TigerSharc系列DSP芯片不超过8片，即一片启动管理芯片最多驱动8片DSP芯片；还包括Flash驱动单元和NOR Flash芯片；管理单元与Flash驱动单元相连；双口RAM单元经Flash驱动单元连接至NOR Flash芯片；NOR Flash芯片经Flash驱动单元与DSP下载管理单元通信。
优选的是：接口单元包括PCI总线接口、CAN总线接口和RS232总线接口，均与管理单元及双口RAM单元相连。
优选的是：还包括看门狗管理电路，分别与每个TigerSharc系列DSP芯片相接。
采用TigerSharc系列DSP启动管理芯片进行TigerSharc系列DSP启动管理的方法，先经管理单元选择启动模式；
管理单元控制选择经接口单元下载DSP启动程序，或选择经NOR Flash芯片启动或经外部总线启动；
外部总线即接口单元所接的外部总线，因此，DSP启动程序的下载方式为管理单元控制经接口单元经外部总线下载TigerSharc系列DSP启动程序，或选择经NOR Flash芯片启动，下载TigerSharc系列启动程序；
若选择经NOR Flash芯片启动，管理单元经Flash驱动单元驱动NOR Flash芯片下载启动程序，DSP启动程序存储到NOR Flash芯片中，TigerSharc系列DSP芯片经DSP下载管理单元读取TigerSharc系列DSP芯片中的启动程序；
若选择经外部总线启动，DSP启动程序经双口RAM、DSP下载管理单元传递到TigerSharc 系列DSP芯片。所述的外部总线即为接口单元连接的外部总线，包括但不限于PCI总线、CAN总线、RS232总线，管理单元用于控制接口单元、双口RAM单元及DSP下载管理单元的工作。
优选的是：DSP启动程序包括代码段部分和256words的Boot loader部分，代码段部分包括顺次首尾相接的N段代码段，N的数量与TigerSharc系列DSP芯片的数量相同。
代码段部分包括非零代码段、零代码段和最终代码段。
非零代码段包含：(1)非零代码段标头信息，(2)非零代码段的存放地址，(3)非零代码段的内容。其中非零代码段标头信息包含：(1)本代码段标识类别信息(非零代码段、零代码段、最终代码段)，(2)非零代码段所属的TigerSharc系列DSP芯片的ID号，(3)本非零代码段的内容长度。
零代码段包含：(1)零代码段标头信息，(2)零代码段的存放地址。其中零代码段标头信息包含：(1)本代码段标识类别信息(非零代码段、零代码段、最终代码段)，(2)零代码段所属的TigerSharc系列DSP芯片的ID号，(3)本零代码段的内容长度。
最终代码段包含：(1)最终代码段标头信息，(2)最终代码段的存放地址，(3)最终代码段的内容。其中最终代码段标头信息包含：(1)本代码段标识类别信息(非零代码段、零代码段、最终代码段)，(2)最终代码段所属的TigerSharc系列DSP芯片的ID号。(3)256words的最终代码信息。
其中Boot loader部分为启动程序内核运行前的一段程序，用于初始化，建立内存空间映射，调整软硬件的运行环境。
将Boot loader部分写入TigerSharc系列DSP芯片的AutoDAM地址；
读取代码段中TigerSharc系列DSP芯片的ID信息；
判断代码段中TigerSharc系列DSP芯片的ID信息是否与当前下载该程序的TigerSharc系列DSP芯片的ID号相等；若不相等则顺序向下读取下一段代码段；若相等，则判断本段代码段是否为最终代码段；
若本代码段非最终代码段，根据本代码段的大小信息和地址信息，使用1级流水线读写的方式，通过DSP并行总线，将本代码段内容写入相应的DSP内存中。
若本代码段是最终代码段，则将最终代码段写入DSP内存中，完成本DSP的启动。
更进一步的：DSP启动程序更新时，将更新程序重新下载到NOR Flash芯片中。
更进一步的：代码段包括非零代码段、零代码段和最终代码段；非零代码段中包含代码段所属TigerSharc系列DSP芯片的ID信息，代码段存放的地址信息、代码段的大小和代码段 非零的内容信息；零代码段包含代码段所属TigerSharc系列DSP芯片的ID信息，代码段存放的地址信息和代码段的大小；最终代码段包含代码段所属TigerSharc系列DSP芯片的ID信息和256Words的最终代码信息。
更进一步的：Boot loader部分写入后，延时10μs再执行读取代码段标头信息的流程；最终代码段写入DSP内存的流程为首先写入开头5个Words，延时10μs，再写入剩下的252Words。
本发明的有益效果为：
本发明提出了一种改进的Host boot的设计方法，在提高TigerSharc系列DSP芯片启动速度的同时，提高了启动过程的稳定性。在改进的Host boot的设计方法基础上，设计了TigerSharc系列DSP启动管理芯片，一方面降低了TigerSharc系列DSP芯片的使用难度，另一方面提高了TigerSharc系列DSP芯片的启动速度和稳定性。
本发明可以有效的管理多片TigerSharc系列DSP的启动。降低TigerSharc系列DSP的使用难度。相对外部系统而言，可以通过PCI、CAN、RS232、并行总线启动TigerSharc系列DSP。为很多不兼容的系统提供和TigerSharc系列DSP的连接方案。
本发明具有看门狗功能，此功能可同时管理多片TigerSharc系列DSP，当某DSP运行异常时，可复位DSP，并重新实现DSP的程序下载。
本发明提供了两种启动方式，一种是通过NOR Flash芯片启动，这种方式直接将程序存储到NOR Flash芯片中，NOR Flash芯片作为启动程序的暂存区，随后的启动可直接在NOR Flash芯片中调用启动程序，仅仅需要在启动程序更新的时候重新下载启动程序，不需要每次都从外界读取启动程序；一种是通过外部总线直接接收启动程序，这种方式具有更高的保密性；可通过管理单元设定启动方式，灵活多样。
提供了PCI总线、CAN总线、RS232总线等多种外部总线，可接受多种总线数据格式。
附图说明
图1为本发明结构示意图。
图2为启动程序代码结构示意图。
图3为本发明Host boot启动程序流程图。
具体实施方式
以下结合附图对本发明的具体实施方式进行进一步的描述。
如图1所示，TigerSharc系列DSP启动管理芯片是使用FPGA构建的启动管理芯片，包括 接口单元、双口RAM单元、管理单元及DSP下载管理单元。
接口单元包括PCI总线接口、CAN总线接口和RS232总线接口，均与管理单元及双口RAM单元相连，通过PCI通讯模块、CAN通讯模块和RS232通讯模块提供多种形式的对外部系统的接口。
PCI通讯模块负责PCI总线经PCI总线接口的接入，CAN通讯模块负责CAN总线经CAN总线接口的接入，RS232通讯模块负责RS232总线经RS232总线接口的接入。其中双口RAM作为临时接收代码使用，作为启动程序的临时存储单元。
管理单元经控制线连接至外部控制系统，控制系统为FPGA启动管理芯片的控制器，下达启动控制指令。管理单元还分别与双口RAM单元及DSP下载管理单元相连；DSP下载管理单元经并行总线连接至至少一片TigerSharc系列DSP芯片，且TigerSharc系列DSP芯片不超过8片，即一片启动管理芯片最多驱动8片TigerSharc系列DSP芯片。所能驱动的DSP芯片的数量，主要是受FPGA驱动接口的限制。
还包括Flash驱动单元和NOR Flash芯片；管理单元与Flash驱动单元相连；双口RAM单元经Flash驱动单元连接至NOR Flash芯片；NOR Flash芯片经Flash驱动单元与DSP下载管理单元通信。NOR Flash芯片作为启动程序的存储芯片，用来存储下载的启动程序。
管理芯片的这种结构提供了两种启动程序到TigerSharc系列DSP芯片的启动程序通道，一种是通过接口单元从外部总线下载启动程序，并经双口RAM和DSP下载管理单元传递到待启动的TigerSharc系列DSP芯片，这种方式需要每次都从外部总线重新下载启动程序；一种是直接将启动程序下载在NOR Flash芯片中，每次直接从NOR Flash芯片中读取启动程序，而当启动程序更新时，重新将更新的启动程序下载到NOR Flash芯片中，芯片启动时，直接从NOR Flash芯片中读取更新后的启动程序。可以通过管理单元控制选择下载启动程序的方式和通路。
系统还包括还包括看门狗管理电路，分别与每个TigerSharc系列DSP芯片相接，实现多片TigerSharc系列DSP的看门狗管理和监控。DSP通过外部总线访问管理芯片中看门狗管理电路的寄存器，当TigerSharc系列DSP工作异常时，可复位TigerSharc系列DSP并重新实现程序的重新下载。
采用TigerSharc系列DSP启动管理芯片进行TigerSharc系列DSP启动管理的方法，需要先经管理单元选择启动模式；
管理单元控制选择经接口单元下载DSP启动程序，或选择经NOR Flash芯片启动或经外 部总线启动；
若选择经NOR Flash芯片启动，DSP启动程序存储到NOR Flash芯片中，TigerSharc系列DSP芯片经DSP下载管理模块读取TigerSharc系列DSP芯片中的启动程序；
若选择经外部总线启动，DSP启动程序经接口单元、双口RAM、DSP下载管理单元传递到TigerSharc系列DSP芯片。
如图2所示，DSP启动程序包括代码段部分和256words的Boot loader部分，代码段部分包括顺次首尾相接的N段代码段，N的数量与TigerSharc系列DSP芯片的数量相同，每段代码段中包含代码段所属TigerSharc系列DSP芯片的ID信息、代码段存放的地址信息和代码信息。
以启动管理芯片同时驱动8片TigerSharc系列DSP芯片为例，代码段部分包括8段代码段，DSP1代码段、DSP2代码段……DSP8代码段。每个代码段的具体结构包括非零代码段、零代码段和最终代码段，具体为：
如图2所示，非零代码段包含：(1)非零代码段标头信息，(2)非零代码段的存放地址，(3)非零代码段的内容。其中非零代码段标头信息包含：(1)本代码段标识类别信息(非零代码段、零代码段、最终代码段)，(2)非零代码段所属的DSP的ID号(即TigerSharc系列DSP1、TigerSharc系列DSP2……TigerSharc系列DSP 8)，(3)本非零代码段的内容长度。
零代码段包含：(1)零代码段标头信息，(2)零代码段的存放地址。其中零代码段标头信息包含：(1)本代码段标识类别信息(非零代码段、零代码段、最终代码段)，(2)零代码段所属的DSP的ID号，(3)本零代码段的内容长度。
最终代码段包含：(1)最终代码段标头信息，(2)最终代码段的存放地址，(3)最终代码段的内容。其中最终代码段标头信息包含：(1)本代码段标识类别信息(非零代码段、零代码段、最终代码段)，(2)最终代码段所属的DSP的ID号。(3)256words的最终代码信息。
如图2所示，前述的首尾相接的N段代码段的具体格式为，非零代码段、零代码段和最终代码段顺次相接；其中非零代码段包括顺次相接的非零代码段1、非零代码段2、非零代码段3……非零代码段n1，零代码段包括顺次相接的零代码段1、零代码段2、零代码段3……非零代码段n2，其中n1和n2均等于N。
将该启动管理芯片用于TigerSharc系列DSP芯片启动管理的方法流程如图3所示：
将Boot loader部分写入TigerSharc系列DSP芯片的AutoDAM地址，进行启动程序下载初始化；
读取代码段中TigerSharc系列DSP芯片的ID信息；代码段标头信息包括：1、DSP的ID信息；2、代码段的属性(非零代码段、零代码段或者最终代码段)；3代码段的长度。
判断代码段中DSP芯片的ID信息是否与当前下载该程序的TigerSharc系列DSP芯片的ID号相等，即代码段N是否与TigerSharc系列DSP N相匹配；若不相等则顺序向下读取下一段代码段，直至代码段中包含的DSP的ID号与当前下载该程序的TigerSharc系列DSP的ID号相等；若相等，则判断本段代码段是否为最终代码段。
结合图2，更具体的说，在进行代码段读取和判断的过程中，首先顺次读取非零代码段1、非零代码段2、非零代码段3……非零代码段n1直至非零代码段中的所属DSP的ID号与待启动的TigerSharc系列DSP N是否匹配，再顺次读取零代码段1、零代码段2、零代码段3……非零代码段n2直至零代码段中的所属DSP的ID号与待启动的TigerSharc系列DSP N是否匹配，最后读取最终代码段。
若本代码段非最终代码段，即读取到的代码段为非零代码段或零代码段的情况下，根据本代码段的大小信息和地址信息，使用1级流水写入的方式，通过DSP并行总线，将本代码段内容写入相应的TigerSharc系列DSP内存中，即待启动的TigerSharc系列DSP中。
若本代码段是最终代码段，则将最终代码段写入相应待启动的TigerSharc系列DSP内存中；下载启动程序。
Boot loader部分写入后，延时10μs再执行读取代码段标头信息的流程；最终代码段写入DSP内存的流程为首先写入开头5个Words，延时10μs，再写入剩下的252Words。
改进的Host boot将TigerSharc系列DSP的流水线机制应用于标准Host boot过程中。在代码段下载过程中，使用流水线写入机制代替AutoDMA的写入机制。由于TigerSharc系列DSP采用公用的外总线设计，并且片内内存可以通过外总线读写。使用1级流水线写入具有很高的写入速度，在一个DSP时钟周期可以完成一个Word的写入。这种方式相对于AutoDMA模式而言极大得减少了代码内容的写入时间，因而降低了整个程序的下载时间。

Claims (8)

  1. TigerSharc系列DSP启动管理芯片，其特征在于：包括接口单元、双口RAM单元、管理单元及DSP下载管理单元；所述接口单元分别与双口RAM单元和管理单元相连；所述管理单元经控制线连接至外部控制系统，还分别与双口RAM单元及DSP下载管理单元相连；所述DSP下载管理单元经并行总线连接至至少一片TigerSharc系列DSP芯片；还包括Flash驱动单元和NOR Flash芯片；管理单元与Flash驱动单元相连；双口RAM单元经Flash驱动单元连接至NOR Flash芯片；NOR Flash芯片经Flash驱动单元与DSP下载管理单元通信。
  2. 如权利要求1所述的TigerSharc系列DSP启动管理芯片，其特征在于：所述接口单元包括PCI总线接口、CAN总线接口和RS232总线接口，均与管理单元及双口RAM单元相连。
  3. 如权利要求1所述的TigerSharc系列DSP启动管理芯片，其特征在于：还包括看门狗管理电路，分别与每个TigerSharc系列DSP芯片相接。
  4. 采用权利要求1所述的TigerSharc系列DSP启动管理芯片进行TigerSharc系列DSP启动管理的方法，其特征在于：
    管理单元控制经接口单元下载DSP启动程序，选择经NOR Flash芯片启动或经外部总线启动；即管理单元控制经接口单元经外部总线下载TigerSharc系列DSP启动程序，或选择经NOR Flash芯片启动，下载TigerSharc系列启动程序；
    若选择经NOR Flash芯片启动，DSP启动程序存储到NOR Flash芯片中，TigerSharc系列DSP芯片经DSP下载管理模块读取TigerSharc系列DSP芯片中的启动程序；
    若选择经外部总线启动，DSP启动程序经双口RAM、DSP下载管理单元传递到TigerSharc系列DSP芯片。
  5. 如权利要求4所述的TigerSharc系列DSP下载管理芯片进行TigerSharc系列DSP启动管理的方法，其特征在于：
    DSP启动程序包括代码段部分和256words的Boot loader部分，所述代码段部分包括顺次首尾相接的N段代码段，N的数量与TigerSharc系列DSP芯片的数量相同，每段代码段中包含代码段所属TigerSharc系列DSP芯片的ID信息、代码段存放的地址信息和256words的最终代码信息；
    将Boot loader部分写入TigerSharc系列DSP芯片的AutoDAM地址；
    读取代码段中TigerSharc系列DSP芯片的ID信息；
    判断代码段中TigerSharc系列DSP芯片的ID信息是否与当前下载该程序的TigerSharc系列DSP芯片的ID号相等；若不相等则顺序向下读取下一段代码段；若相等，则判断本段代码段是否为最终代码段；
    若本代码段非最终代码段，根据本代码段的大小信息和地址信息，使用1级流水线写入的方式，通过DSP并行总线，将本代码段内容写入相应的DSP内存中；
    若本代码段是最终代码段，则将最终代码段写入DSP内存中。
  6. 如权利要求4或5所述的TigerSharc系列DSP下载管理芯片进行TigerSharc系列DSP启动管理的方法，其特征在于：DSP启动程序更新时，将更新程序重新下载到NOR Flash芯片中。
  7. 如权利要求4或5所述的TigerSharc系列DSP下载管理芯片进行TigerSharc系列DSP启动管理的方法，其特征在于：所述代码段包括非零代码段、零代码段和最终代码段；
    非零代码段包含：(1)非零代码段标头信息，(2)非零代码段的存放地址，(3)非零代码段的内容；其中非零代码段标头信息包含：(1)本代码段标识类别信息，(2)非零代码段所属的TigerSharc系列DSP芯片的ID号，(3)本非零代码段的内容长度；
    零代码段包含：(1)零代码段标头信息，(2)零代码段的存放地址；其中零代码段标头信息包含：(1)本代码段标识类别信息，(2)零代码段所属的TigerSharc系列DSP芯片的ID号，(3)本零代码段的内容长度；
    最终代码段包含：(1)最终代码段标头信息，(2)最终代码段的存放地址，(3)最终代码段的内容。其中最终代码段标头信息包含：(1)本代码段标识类别信息，(2)最终代码段所属的TigerSharc系列DSP芯片的ID号，(3)256words的最终代码信息；
    所述代码段标识类别信息包括：非零代码段、零代码段和最终代码段。
  8. 如权利要求7所述的TigerSharc系列DSP下载管理芯片进行TigerSharc系列DSP下载管理的方法，其特征在于：Boot loader部分写入后，延时10μs再执行读取代码段标头信息的 流程；最终代码段写入DSP内存的流程为首先写入开头5个Words，延时10μs，再写入剩下的252Words。
PCT/CN2016/095295 2016-03-28 2016-08-15 TigerSharc系列DSP启动管理芯片及方法 WO2017088531A1 (zh)

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