WO2016101177A1 - 计算机设备内存的检测方法和计算机设备 - Google Patents

计算机设备内存的检测方法和计算机设备 Download PDF

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Publication number
WO2016101177A1
WO2016101177A1 PCT/CN2014/094823 CN2014094823W WO2016101177A1 WO 2016101177 A1 WO2016101177 A1 WO 2016101177A1 CN 2014094823 W CN2014094823 W CN 2014094823W WO 2016101177 A1 WO2016101177 A1 WO 2016101177A1
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Prior art keywords
memory
detection unit
cpu
detection
memory detection
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PCT/CN2014/094823
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English (en)
French (fr)
Inventor
莫良伟
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华为技术有限公司
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Priority to CN201480065448.XA priority Critical patent/CN106030544B/zh
Priority to PCT/CN2014/094823 priority patent/WO2016101177A1/zh
Publication of WO2016101177A1 publication Critical patent/WO2016101177A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K5/00—Methods or arrangements for verifying the correctness of markings on a record carrier; Column detection devices

Definitions

  • the present invention relates to the field of information technology, in particular to a method for detecting the memory of a computer device and a computer device.
  • the random access memory (hereinafter referred to as RAM) used in computer equipment has a larger capacity.
  • RAM random access memory
  • the current conventional practice is not to do memory testing at startup; however, in a business-critical system, it is necessary to check in order to ensure the reliability of the system, which will consume a lot of time.
  • the test time for a memory module is T. If the computer device has N memory modules, the total test time is N*T.
  • the memory self-test time is too long, which affects the timeliness of the system from power-on to normal operation.
  • the embodiment of the present invention provides a method for detecting a memory of a computer device and a computer device to solve the problem of excessively long memory detection time in the prior art.
  • an embodiment of the present invention provides a method for detecting the memory of a computer device, including:
  • At least one memory detection unit receives a memory detection instruction sent by the central processing unit CPU of the computer device, and performs memory detection on at least two of the at least two memory modules of the computer device at the same time; wherein, the at least one memory detection unit The unit connects the CPU and at least two memory modules of the computer device, so that the CPU communicates with the at least two memory modules through the at least one memory detection unit;
  • the at least one memory detection unit sends the detection results of the at least two memory modules to the CPU according to the detection result acquisition request sent by the CPU.
  • the memory detection unit is located in each memory module, or the memory detection unit is located between the CPU and at least two memory modules.
  • the method further includes:
  • the memory detection unit When the memory detection unit communicates with the CPU, the memory detection unit cuts off the connection with the at least two memory modules; or, when the memory detection unit detects the memory module, the memory detection unit Cut off the connection with the CPU.
  • each memory module when the memory detection unit is located in each memory module, each memory module includes a memory detection unit. Unit, the memory detection unit is connected to all RAM Chips in each memory module; or,
  • Each RAM Chip of the memory module includes one memory detection unit.
  • the at least one memory detection unit receives the CPU of the computer device Before sending the memory detection instruction, the method further includes:
  • the second method also provides a method for detecting the memory of a computer device, including:
  • the central processing unit CPU of the computer device sends a memory detection instruction to at least one memory detection unit, where the memory detection instruction is used to instruct the at least one memory detection unit to start the detection of the memory module, and the CPU passes the at least one memory detection
  • the unit communicates with at least two memory modules;
  • the CPU obtains a detection result of the memory module from the at least one memory detection unit, and the detection result is that after the at least one memory detection unit performs memory detection on at least two of the at least two memory modules simultaneously The test results.
  • the method further includes:
  • the CPU obtains instructions from the basic input output BIOS program, and sends a memory detection instruction to the at least one memory detection unit.
  • the CPU obtains the detection of the memory module from the at least one memory detection unit
  • the results include:
  • the CPU obtains the detection result of the memory module from the memory detection unit in a polling manner, or the CPU receives the detection result of the memory module reported by the memory detection unit in an interrupt manner.
  • an embodiment of the present invention also provides a computer device, including a central processing unit (CPU) and at least two memory modules, and the computer device further includes at least one memory detection unit; wherein,
  • the CPU is configured to send a memory detection instruction to the at least one memory detection unit
  • the at least one memory detection unit is configured to receive a memory detection instruction sent by the CPU, and perform memory detection on at least two of the at least two memory modules at the same time according to the received memory detection instruction, and according to The acquisition of the detection result by the CPU indicates that the detection result is sent to the CPU or the detection result is sent to the CPU in an interrupt manner.
  • the CPU communicates with the at least two memory modules through the at least one memory detection unit.
  • the memory detection unit includes:
  • a detection control unit configured to receive a memory detection instruction sent by the CPU, and simultaneously perform memory detection on at least two of the at least two memory modules according to the received memory detection instruction;
  • the detection result storage unit is used to store the detection results of at least two memory modules detected by the detection control unit, and send the detection results to the CPU or pass the detection results through the interruption Method to the CPU.
  • the memory detection unit further includes a switch, and the switch is used In order to realize the connection switching between the memory detection unit and the CPU and the memory module, when the memory detection unit communicates with the CPU, the connection between the memory detection unit and the memory module is cut off, when the When the memory detection unit communicates with the memory module, the connection between the memory detection unit and the CPU is cut off.
  • the at least one memory detection unit is located in the memory module to be detected, Or the at least one memory detection unit is located between the CPU and the memory module to be tested.
  • each memory module when the memory detection unit is located in each memory module, each memory module includes a memory detection unit , The memory detection unit is connected to all RAM Chips in each memory module; or,
  • Each RAM Chip of the memory module includes one memory detection unit.
  • At least two memory modules are detected simultaneously through at least one memory detection unit, so that the purpose of parallel detection of memory modules is realized, and at least two memory modules can be detected at the same time , Shorten the memory module To The detection time improves the detection efficiency.
  • FIG. 1 is a schematic flowchart of a method for detecting memory of a computer device according to an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of another method for detecting memory of a computer device according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of the first specific implementation structure of a computer device memory detection method according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a second specific implementation structure of a computer device memory detection method according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a third specific implementation structure of a computer device memory detection method according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the internal structure of a memory detection unit in an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a computer device 700 according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a second implementation manner of a computer device 700 according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a third implementation manner of a computer device 700 according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a first implementation manner of the memory detection unit 703 of the computer device 700 according to an embodiment of the present invention
  • FIG. 11 is a schematic structural diagram of a second implementation manner of the memory detection unit 703 of the computer device 700 according to an embodiment of the present invention.
  • FIG. 1 is a schematic flowchart of a method for detecting memory of a computer device according to an embodiment of the present invention, including:
  • Step 101 At least one memory detection unit receives a memory detection instruction sent by the CPU of the computer device, and performs memory detection on at least two of the at least two memory modules of the computer device at the same time; wherein, the at least one memory detection unit The unit connects the CPU and at least two memory modules of the computer device, so that the CPU communicates with the at least two memory modules through the at least one memory detection unit;
  • the memory module may be a memory module, or a RAM Chip in a memory module.
  • one memory detection unit may be connected to at least two memory modules, and the one memory detection unit simultaneously detects at least two memory modules in parallel; or one memory detection unit is connected to one memory module, and the other One memory detection unit is connected to another memory module, and the two memory detection units simultaneously detect the connected memory modules in parallel; it can also be that one memory detection unit is connected to one memory module, and the other memory detection unit is connected to two or more other memory modules. Two memory modules are connected, and the two memory detection units simultaneously detect the connected memory modules in parallel. As long as the parallel detection of the memory modules at the same time can be realized, it is all included in the protection scope of the embodiment of the present invention, and examples are not given one by one.
  • Step 102 The at least one memory detection unit sends the detection results of the at least two memory modules to the CPU according to the detection result acquisition request sent by the CPU.
  • the memory detection unit may receive the polling request of the CPU and set To The detection result is sent to the CPU; the memory detection unit may also report the detection result to the CPU through interrupts and other methods.
  • the above method uses at least one memory detection unit to detect at least two memory modules at the same time, achieving the purpose of parallel detection of memory modules, being able to detect at least two memory modules at the same time, and shortening the time for detecting memory modules. Improve the efficiency of detection.
  • the method before step 101, further includes: modifying a basic input and output BIOS program, so that the CPU sends to the at least one BIOS program according to the program in the BIOS.
  • the memory detection unit sends a memory detection instruction.
  • a program may be added to the BIOS, and the CPU in the computer device reads the added program from the BIOS, and sends a memory detection instruction to the at least one memory detection unit.
  • the CPU in the computer device may send a memory detection instruction to the at least one memory detection unit.
  • the detection of the memory module by the at least one memory detection unit may be implemented in the following manner: each memory detection unit writes first data to the memory module connected to it, and reads the first data from the memory module that stores the first data. Read the second data from the space, compare the first data with the second data, and determine whether the memory is faulty according to the comparison result.
  • the specific judgment method may be: if the first data is the same as the second data, the memory module is determined to be normal, and if the first data is inconsistent with the second data, the memory module is determined to be abnormal Or malfunction.
  • any memory detection unit can write and read data to a memory module multiple times, and determine whether the memory module is abnormal or malfunctioning after multiple judgments.
  • the at least one memory detection unit is located in the memory module to be tested, or the at least one memory detection unit is located between the CPU and the memory to be tested.
  • the at least one memory detection unit is located in the memory module to be tested. It may be that the at least one memory detection unit is located in a memory bank and is connected to each RAM Chip, or in each RAM Chip of a memory bank. All set up a memory detection unit.
  • the specific implementation manner in which the at least one memory detection unit is located between the CPU and the memory to be detected may be implemented by arranging at least one memory detection unit on the channel between the memory module and the CPU; for example, it may be a computer device A chip set on the main board of the computer is used to realize the function of the memory detection unit.
  • the memory detection unit cuts off the connection with the memory module; or, when each memory detection unit detects the memory module, cuts off the connection with the CPU. That is, the memory detection unit is only connected to the CPU or only the memory module at the same time, so that when the memory detection unit detects the memory module, it will not receive commands from the CPU and will not cause conflicts.
  • FIG. 2 is a schematic flowchart of another computer device memory detection method according to an embodiment of the present invention, including:
  • Step 201 The central processing unit CPU of the computer device sends a memory detection instruction to at least one memory detection unit, where the memory detection instruction is used to instruct the at least one memory detection unit to start the detection of the memory module, and the CPU passes the at least one memory detection unit.
  • One memory detection unit communicates with at least two memory modules;
  • the memory module may be a memory module, or a RAM Chip in a memory module.
  • Step 202 The CPU obtains a detection result of the memory module from the at least one memory detection unit, and the detection result is that the at least one memory detection unit performs simultaneous detection on at least two of the at least two memory modules. The test result after the memory test.
  • the CPU can poll each memory detection unit, and the CPU can repeatedly poll the detection results of each memory module until the detection results of all the memories are obtained; or the memory detection unit can pass interrupts, etc. Report the test results to the CPU in other ways.
  • the CPU of the computer device detects at least two memory modules at the same time through at least one memory detection unit, which achieves the purpose of parallel detection of memory modules, can detect at least two memory modules at the same time, and shortens the number of memory modules.
  • the detection time improves the detection efficiency.
  • the method before step 101, the method further includes:
  • a program may be added to the BIOS, and the CPU in the computer device reads the added program from the BIOS, and sends a memory detection instruction to the at least one memory detection unit.
  • the CPU in the computer device may send a memory detection instruction to the at least one memory detection unit.
  • the detection of the memory module by the at least one memory detection unit may be implemented in the following manner: each memory detection unit writes the first data into the memory module connected to it, and reads the second data from the space storing the first data. Data, comparing the first data with the second data, and judging whether the memory is faulty according to the result of the comparison.
  • the specific judgment method may be: if the first data is the same as the second data, the memory module is determined to be normal, and if the first data is inconsistent with the second data, the memory module is determined to be abnormal Or malfunction.
  • any memory detection unit can write and read data to a memory module multiple times, and determine whether the memory module is abnormal or malfunctioning after multiple judgments.
  • FIG. 3 is a schematic diagram of the first specific implementation structure of a computer device memory detection method according to an embodiment of the present invention.
  • the memory detection unit is located in a memory bank, and each memory bank includes a memory detection unit ,
  • the CPU communicates with each internal memory through the memory detection unit in each memory module To Deposit link.
  • the memory detection units in multiple memory modules can simultaneously detect the memory modules and send the detection results to the central processing unit.
  • the memory detection unit in the memory 1 and the memory detection unit in the memory 2 can detect the memory at the same time, realize parallel detection of the memory, and achieve the purpose of saving memory detection time and improving memory detection efficiency.
  • FIG. 4 is a schematic diagram of the second specific implementation structure of a computer device memory detection method according to an embodiment of the present invention.
  • the memory detection unit is located outside the memory bank, and the CPU passes through the memory detection unit and each memory bank. connection.
  • the memory detection units in multiple memory modules can simultaneously detect the memory modules and send the detection results to the central processing unit.
  • the memory 1 to the memory are detected by the memory detection unit 1 at the same time, thereby realizing parallel detection of the memory, achieving the purpose of saving memory detection time and improving memory detection efficiency.
  • the memory detection unit 2 detects other memories at the same time to realize more parallel memory detection, so as to save more memory detection time and improve memory detection efficiency.
  • FIG. 5 is a schematic diagram of a third specific implementation structure of a computer device memory detection method according to an embodiment of the present invention.
  • the memory detection unit is located in each RAM Chip of the memory bank, and the CPU passes through each memory chip.
  • the memory detection unit in each RAM Chip in the bank is connected to the RAM Chip of each memory bank.
  • the memory detection units in multiple memory modules can simultaneously detect the memory modules and send the detection results to the central processing unit. For example, the memory detection unit in each RAM Chip in the memory 1 simultaneously detects the respective RAM Chip in the memory 1, thereby realizing parallel memory detection, saving memory detection time and improving memory detection efficiency.
  • the memory detection unit in each RAM Chip in memory 2 detects its corresponding RAM Chip in memory 2 at the same time to achieve more parallel memory detection, save more memory detection time, and improve memory detection.
  • the RAM chip has a built-in memory detection unit, which can further increase the speed of self-checking and reduce the design complexity of the memory detection unit.
  • Fig. 3 The above-mentioned memory detection unit in Fig. 3, Fig. 4 or Fig. 5 may be an integrated chip, and its internal structure is shown in Fig. 6: To
  • the memory detection unit takes over the memory bus for the CPU to access the memory, and the CPU can read and write the registers of the memory detection unit by accessing a specific physical address.
  • the memory space (Memory space) under the switch in the memory detection unit is 0x00000000-0x01000000, and an address space outside of this range (such as 0x01000000-0x10000010) is selected as the register, and the CPU accesses the register by accessing the address space of the register.
  • Memory detection unit The switcher in the memory detection unit realizes switching memory to the CPU access or the detection engine access of the memory detection unit. When the CPU issues a detection instruction to the memory detection unit, the switcher cuts off the connection between the search engine and the memory; when the detection engine starts, the memory is accessed.
  • the switch cuts off the connection with the CPU.
  • the conversion of the switch is realized by a controller that can be written into the register; the detection trigger instruction of the memory detection unit and the interrogator for inquiring the detection status are all stored in this register.
  • the central processing unit CPU issues an instruction to start the memory detection to the memory detection unit through the register.
  • the switch in the memory detection unit cuts off the connection between the detection engine and the memory.
  • the register completes the memory detection instruction issued by the CPU and starts the detection of the memory
  • the switch cuts off the connection between the register and the switch, that is, cuts off the connection between the memory detection unit and the CPU, and the address is 0x00000000-0x01000000 by the search engine
  • the memory space is tested. You can write data multiple times and read data to determine whether the read data is consistent with the written data to determine whether the memory space to be tested is normal, whether there is a fault, etc.
  • the detection engine When the detection engine completes the detection of the memory, it saves the detection result in the register.
  • the CPU obtains the detection result from the register by polling, it reads the saved detection result from the register; or the register sends the detection result to the CPU by means of an interrupt.
  • FIG. 7 is a schematic structural diagram of a computer device 700 according to an embodiment of the present invention.
  • the computer device 700 includes a central processing unit CPU701, at least two memory modules 702, and at least one memory detection unit 703; the CPU701 passes At least one memory detection unit 703 is connected to the at least one memory module 702;
  • the CPU 701 is configured to send a memory detection instruction to the at least one memory detection unit 703;
  • the at least one memory detection unit 703 is configured to receive a memory detection instruction sent by the CPU 701, and perform memory detection on at least two of the at least two memory modules 702 at the same time according to the received memory detection instruction, And according to the instruction of obtaining the detection result of the CPU 701, the detection result is sent to the CPU 701 or the detection result is sent to the CPU 701 in an interrupt mode.
  • the above-mentioned computer equipment detects at least two memory modules 702 through at least one memory detection unit 703 at the same time, so as to achieve the purpose of parallel detection of memory modules. At least two memory modules can be detected at the same time, which reduces the number of memory modules. The detection time improves the detection efficiency.
  • the memory module 702 may be a memory module, or a RAM Chip in a memory module.
  • the CPU 701 sends an instruction to obtain the detection result to the memory detection unit 703 in a polling manner.
  • one memory detection unit 703 may be connected to at least two memory modules 702, and the one memory detection unit 703 detects at least two memory modules 702 in parallel at the same time, as shown in FIG. 7.
  • one memory detection unit 703 is connected to one memory module 702
  • another memory detection unit 703 is connected to another memory module 702
  • the two memory detection units 703 are parallel to the connected memory modules 702 at the same time.
  • Detection It can also be that one memory detection unit 703 is connected to one memory module 702, and the other memory detection unit 703 is connected to other two or more memory modules 702, and the two memory detection units simultaneously detect their connected memory modules in parallel, as shown in the figure 9 shown.
  • the parallel detection of the memory modules at the same time can be realized, it is all included in the protection scope of the embodiment of the present invention, and examples are not given one by one.
  • FIGS. 7-9 For the sake of simplicity and clarity of the drawings, multiple memory detection units 703 and memory modules 702 are not shown, that is, for "at least one memory detection module 703 "Only one memory detection module 703 is displayed, for "At least two memory modules 702" only two memory modules 702 are displayed, and so on. For more than two memory detection modules To 703 or more than three memory modules 702, etc., are all within the protection scope of the embodiment of the present invention.
  • One memory detection unit 703 or two memory modules 702 in FIGS. 7-9 should not constitute a limitation to the embodiment of the present invention. .
  • any one of the at least one memory detection unit 703 includes:
  • the detection control unit 7031 is configured to receive a memory detection instruction sent by the CPU 701, and perform memory detection on at least two of the at least two memory modules 702 at the same time according to the received memory detection instruction;
  • the detection result storage unit 7032 is configured to store the detection results of the detection control unit 7031 on at least two memory modules 702, and send the detection results to the CPU 701 or send the detection results to the CPU 701 according to the CPU 701 obtaining the detection result instruction It is sent to the CPU 701 in an interrupt mode.
  • the detection control unit 7031 detects the memory module 702 in the following manner: the detection control unit 7031 writes the first data to the memory module connected to it, and reads the first data from the memory module that stores the first data. Read the second data from the space, compare the first data with the second data, and determine whether the memory is faulty according to the comparison result.
  • the specific judgment method may be: if the first data is the same as the second data, the memory module is determined to be normal, and if the first data is inconsistent with the second data, the memory module is determined to be abnormal Or malfunction.
  • the memory detection unit 703 further includes a switch 7033 for switching the connection between the memory detection unit and the CPU 701 and the memory module 702.
  • a switch 7033 for switching the connection between the memory detection unit and the CPU 701 and the memory module 702.
  • the at least one memory detection unit 703 may be located in the memory module 702 to be tested, or the at least one memory detection unit 703 is located between the CPU 701 and the memory module 702 to be tested. In a specific implementation, the at least one memory detection unit 703 is located in the memory module to be tested. It may be that the at least one memory detection unit 703 is located in a memory bank and is connected to each RAM Chip, or a memory module. Each RAM Chip is equipped with a memory detection unit.
  • the specific implementation manner in which the at least one memory detection unit 703 is located between the CPU 701 and the memory 702 to be detected can be implemented by arranging at least one memory detection unit 703 on the channel between the memory module 702 and the CPU 701; for example, It may be a chip provided on the motherboard of a computer device to implement the function of the memory detection unit 703.
  • the computer device 700 of the embodiment of the present invention may be implemented with reference to the implementation manner in the embodiment shown in FIG. 1 to FIG. 6 above, and details are not described herein again.
  • the disclosed system, device, and method can be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the units is only a logical function division, and it is actually practical.
  • there can be other ways of dividing for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may also be electrical, mechanical or other forms of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments of the present invention.
  • the functional units in the various embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of the present invention is essentially or a part that contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium. It includes a number of instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present invention.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes. .

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Abstract

本发明实施例提供的内存检测方法和计算机设备，以解决现有技术中，内存检测时间过长，影响计算机设备正常工作及时性的问题。本发明实施例提供的内存检测的方法和计算机设备，通过至少一个内存检测单元对至少两个内存模块同时进行检测，实现了并行检测内存模块的目的，能够在同一时间对至少两个内存模块进行检测，缩短了对内存模块进行检测的时间，提高了检测的效率。

Description

计算机设备内存的检测方法和计算机设备 技术领域
本发明涉及信息技术领域，特别涉及计算机设备内存的检测方法和计算机设备。
背景技术
目前计算机设备使用的随机存取存贮器(以下简称内存，即RAM)，容量起来越大，系统启动时为了保证内存的功能完整，要对其进行检测，这个检测过程因容量越来越大而变得越来越长。现在的常规做法是在启动时不做内存检测；但是在关键业务的系统中，为了保证系统的可靠性还是要检查，将会耗费大量时间。例如，对一个内存模块的测试时间是T，如果计算机设备有N个内存模块，则总的检测时间就是N*T，内存自检时间太长，影响系统从上电至正常工作及时性。
发明内容
本发明实施例提供一种计算机设备内存检测的方法和计算机设备，以解决现有技术中内存检测时间过长的问题。
第一方面，本发明实施例提供了一种计算机设备内存检测的方法，包括：
至少一个内存检测单元接收所述计算机设备的中央处理器CPU发送的内存检测指示，对所述计算机设备的至少两个内存模块中的至少两个同时进行内存检测；其中，所述至少一个内存检测单元连接所述CPU与所述计算机设备的至少两个内存模块，使得所述CPU通过所述至少一个内存检测单元与所述至少两个内存模块进行通信；
所述至少一个内存检测单元根据所述CPU发送的检测结果获取请求，将所述至少两个内存模块的检测结果发送给所述CPU。
结合第一方面，在第一方面的第一种可能的实现方式中，所述内存检测单元位于每个内存模块中，或所述内存检测单元位于所述CPU与至少两个内存模块之间。
结合第一方面或第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，所述方法还包括：
在所述内存检测单元与所述CPU通信时，所述内存检测单元切断与所述至少两个内存模块的连接；或者，当所述内存检测单元对内存模块进行检测时，所述内存检测单元切断与所述CPU的连接。
结合第一方面的第一种可能的实现方式，在第一方面的第三种可能的实现方式中，当所述内存检测单元位于每个内存模块中时，每个内存模块中包括一个内存检测单元，所述内存检测单元与每个内存模块中的所有RAM Chip相连；或，
所述内存模块的每个RAM Chip中包含一个所述内存检测单元。
结合第一方面，以及第一方面的第一至第三种可能的实现方式，在第一方面的第四种可能的实现方式中，在所述至少一个内存检测单元接收所述计算机设备的CPU发送的内存检测指示之前，所述方法还包括：
修改基本输入输出BIOS程序，使得所述CPU根据所述BIOS中的程序，向所述至少一个内存检测单元发送内存检测的指示。
第二方法，本发明实施例还提供了一种计算机设备内存检测的方法，包括：
计算机设备的中央处理器CPU向至少一个内存检测单元发送内存检测指示，所述内存检测指示用于指示所述至少一个内存检测单元启动对内存模块的检测，所述CPU通过所述至少一个内存检测单元与至少两个内存模块进行通信；
所述CPU从所述至少一个内存检测单元获取所述内存模块的检测结果，所述检测结果是所述至少一个内存检测单元对所述至少两个内存模块中的至少两个同时进行内存检测后的检测结果。
结合第二方面，在第二方面的第一种可能的实现方式中，在所述计算机设备的中央处理器CPU向至少一个内存检测单元发送内存检测指示之前，所述方法还包括：
所述CPU从基本输入输出BIOS程序中获取指令，向所述至少一个内存检测单元发送内存检测的指示。
结合第二方面，以及第二方面的第一种可能的实现方式，在第二方面的第二种可能的实现方式中，所述CPU从所述至少一个内存检测单元获取所述内存模块的检测结果包括：
所述CPU通过轮询的方式，从所述内存检测单元获取所述内存模块的检测结果，或所述CPU接收所述内存检测单元通过中断的方式上报的所述内存模块的检测结果。
第三方面，本发明实施例还提供了一种计算机设备，包括中央处理器CPU和至少两个内存模块，所述计算机设备还包括至少一个内存检测单元；其中，
所述CPU，用于向所述至少一个内存检测单元发送内存检测指示；
所述至少一个内存检测单元，用于接收所述CPU发送的内存检测指示，并根据接收到的所述内存检测指示对所述至少两个内存模块中的至少两个同时进行内存检测，并依据所述CPU的获取检测结果指示将检测结果发送给所述CPU或将检测结果通过中断的方式发送给所述CPU。
结合第三方面，在第三方面的第一种可能的实现方式中，所述CPU通过所述至少一个内存检测单元与所述至少两个内存模块通信。
结合第三方面，以及第三方面的第一种可能的实现方式，在第三方面 的第二种可能的实现方式中，所述内存检测单元包括：
检测控制单元，用于接收所述CPU发送的内存检测指示，并根据接收到的所述内存检测指示对所述至少两个内存模块中的至少两个同时进行内存检测；
检测结果存储单元，用于存储所述检测控制单元对至少两个内存模块检测后的检测结果，并依据所述CPU的获取检测结果指示将检测结果发送给所述CPU或将检测结果通过中断的方式发送给所述CPU。
结合第三方面，以及第三方面的第一至第二种可能的实现方式，在第三方面的第三种可能的实现方式中，所述内存检测单元还包括切换开关，所述切换开关用于实现所述内存检测单元与所述CPU与内存模块之间的连接切换，当内存检测单元与所述CPU通信时，切断所述内存检测单元与所述内存模块之间的连接，当所述内存检测单元与所述内存模块通信时，切断所述内存检测单元与所述CPU的连接。
结合第三方面，以及第三方面的第一至第三种可能的实现方式，在第三方面的第四种可能的实现方式中，所述至少一个内存检测单元位于待检测的内存模块中，或所述至少一个内存检测单元位于所述CPU与待检测的内存模块之间。
结合第三方面第四种可能的实现方式，在第三方面的第五种可能的实现方式中，当所述内存检测单元位于每个内存模块中时，每个内存模块中包括一个内存检测单元，所述内存检测单元与每个内存模块中的所有RAM Chip相连；或，
所述内存模块的每个RAM Chip中包含一个所述内存检测单元。
本发明实施例提供的内存检测方法和计算机设备，通过至少一个内存检测单元对至少两个内存模块同时进行检测，实现了并行检测内存模块的目的，能够在同一时间对至少两个内存模块进行检测，缩短了对内存模块 进行检测的时间，提高了检测的效率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例一种计算机设备内存检测方法的流程示意图；
图2为本发明实施例另一种计算机设备内存检测方法的流程示意图；
图3为本发明实施例一种计算机设备内存检测方法的第一种具体实现结构示意图；
图4为本发明实施例一种计算机设备内存检测方法的第二种具体实现结构示意图；
图5为本发明实施例一种计算机设备内存检测方法的第三种具体实现结构示意图；
图6为本发明实施例中内存检测单元内部结构示意图；
图7为本发明实施例一种计算机设备700的结构示意图；
图8为本发明实施例一种计算机设备700第二种实现方式的结构示意图；
图9为本发明实施例一种计算机设备700第三种实现方式的结构示意图；
图10为本发明实施例一种计算机设备700的内存检测单元703的第一种实现方式的结构示意图；
图11为本发明实施例一种计算机设备700的内存检测单元703的第二种实现方式的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都应属于本发明保护的范围。
参考图1，图1为本发明实施例一种计算机设备内存检测方法的流程示意图，包括：
步骤101：至少一个内存检测单元接收所述计算机设备的CPU发送的内存检测指示，对所述计算机设备的至少两个内存模块中的至少两个同时进行内存检测；其中，所述至少一个内存检测单元连接所述CPU与所述计算机设备的至少两个内存模块，使得所述CPU通过所述至少一个内存检测单元与所述至少两个内存模块进行通信；
其中，所述内存模块可以是一个内存条，或一个内存条中的一个RAM Chip。
在具体实现中，可以是一个内存检测单元与至少两个内存模块相连，所述一个内存检测单元同时对至少两个内存模块并行进行检测；也可以是一个内存检测单元与一个内存模块相连，另一个内存检测单元与另一内存模块相连，两个内存检测单元同时对各自相连的内存模块并行检测；还可以是一个内存检测单元与一个内存模块相连，另一个内存检测单元与另外两个或多个内存模块相连，两个内存检测单元同时对各自相连的内存模块并行检测。只要能够实现对内存模块在同一时间的并行检测，都包含在本发明实施例的保护范围内，不再一一举例。
步骤102：所述至少一个内存检测单元根据所述CPU发送的检测结果获取请求，将所述至少两个内存模块的检测结果发送给所述CPU。
在具体实现时，可以是所述内存检测单元接收所述CPU的轮询请求并将 检测结果发送给所述CPU；也可以由内存检测单元通过中断等其它方式将检测结果上报至CPU。
上述方法通过至少一个内存检测单元对至少两个内存模块同时进行检测，实现了并行检测内存模块的目的，能够在同一时间对至少两个内存模块进行检测，缩短了对内存模块进行检测的时间，提高了检测的效率。
作为一种可选的实现方式，本发明实施例中，在步骤101之前，所述方法还包括：修改基本输入输出BIOS程序，使得所述CPU根据所述BIOS中的程序，向所述至少一个内存检测单元发送内存检测的指示。具体实现中，可以在BIOS中增加程序，所述计算机设备中的CPU从所述BIOS中读取增加的程序，并向所述至少一个内存检测单元发送内存检测的指示。
相应的，可以在所述计算机设备启动并完成内存的初始化后，由所述计算机设备中的CPU向所述至少一个内存检测单元发送内存检测的指示。
本发明实施例中，所述至少一个内存检测单元对内存模块检测可以通过如下方式实现：每个内存检测单元向其连接的内存模块中写入第一数据，并从存放所述第一数据的空间中读出第二数据，比较所述第一数据与所述第二数据，根据比较的结果判断所述内存是否存在故障。
具体的判断方式可以是：如果所述第一数据与所述第二数据相同，则认定所述内存模块正常，如果所述第一数据与所述第二数据不一致，则认定所述内存模块异常或故障。
作为一种可选的实现方式，任一一个内存检测单元可以对一个内存模块进行多次的数据写入和读出，在进行多次的判断后才确定内存模块是否异常或故障。
可选的，所述至少一个内存检测单元位于待检测的内存模块中，或所述至少一个内存检测单元位于所述CPU与待检测的内存之间。在具体实现 中，所述至少一个内存检测单元位于待检测的内存模块中，可以是所述至少一个内存检测单元位于一个内存条中并分别与每个RAM Chip相连，或者一个内存条的每个RAM Chip中都设置一个内存检测单元。所述至少一个内存检测单元位于所述CPU与待检测的内存之间的具体实现方式，可以通过在内存条与CPU之间的通道上设置至少一个内存检测单元来实现；例如，可以是计算机设备的主板设置的一个芯片，用于实现该内存检测单元的功能。
可选的，在每个内存检测单元与所述CPU通信时，内存检测单元切断与内存模块的连接；或者，当每个内存检测单元对内存模块进行检测时，切断与所述CPU的连接。即内存检测单元在同一时间只与CPU相连，或只与内存模块相连，使得内存检测单元在对内存模块进行检测时，不会接收CPU的命令，不会出现冲突的情况。
参考图2，图2为本发明实施例另一种计算机设备内存检测方法的流程示意图，包括：
步骤201：计算机设备的中央处理器CPU向至少一个内存检测单元发送内存检测指示，所述内存检测指示用于指示所述至少一个内存检测单元启动对内存模块的检测，所述CPU通过所述至少一个内存检测单元与至少两个内存模块进行通信；
其中，所述内存模块可以是一个内存条，或一个内存条中的一个RAM Chip。
步骤202：所述CPU从所述至少一个内存检测单元获取所述内存模块的检测结果，所述检测结果是所述至少一个内存检测单元对所述至少两个内存模块中的至少两个同时进行内存检测后的检测结果。
在具体实现时，可以由所述CPU轮询每个内存检测单元，所述CPU可以反复轮询每个内存模块的检测结果，直至获得所有内存的检测结果；也可以由内存检测单元通过中断等其它方式将检测结果上报至CPU。
上述方法，计算机设备的CPU通过至少一个内存检测单元对至少两个内存模块同时进行检测，实现了并行检测内存模块的目的，能够在同一时间对至少两个内存模块进行检测，缩短了对内存模块进行检测的时间，提高了检测的效率。
作为一种可选的实现方式，本发明实施例中，在步骤101之前，所述方法还包括：
修改基本输入输出BIOS程序，使得所述CPU根据所述BIOS中的程序，向所述至少一个内存检测单元发送内存检测的指示。具体实现中，可以在BIOS中增加程序，所述计算机设备中的CPU从所述BIOS中读取增加的程序，并向所述至少一个内存检测单元发送内存检测的指示。
相应的，可以在所述计算机设备是在启动并完成内存的初始化后，所述计算机设备中的CPU向所述至少一个内存检测单元发送内存检测的指示。所述至少一个内存检测单元对内存模块检测可以通过如下方式实现：每个内存检测单元向其连接的内存模块中写入第一数据，并从存放所述第一数据的空间中读出第二数据，比较所述第一数据与所述第二数据，根据比较的结果判断所述内存是否存在故障。
具体的判断方式可以是：如果所述第一数据与所述第二数据相同，则认定所述内存模块正常，如果所述第一数据与所述第二数据不一致，则认定所述内存模块异常或故障。
作为一种可选的实现方式，任一一个内存检测单元可以对一个内存模块进行多次的数据写入和读出，在进行多次的判断后才确定内存模块是否异常或故障。
参考图3，图3为本发明实施例一种计算机设备内存检测方法的第一种具体实现结构示意图，在图3中，内存检测单元位于内存条中，每个内存条中包含一个内存检测单元，CPU通过每个内存条中的内存检测单元与每个内 存条连接。多个内存条中的内存检测单元能够同时对内存条检测，并将检测结果发送给中央处理器。例如内存1中的内存检测单元与内存2中的内存检测单元可以同时检测内存，实现内存的并行检测，达到节省内存检测时间，提高内存检测效率的目的。
参考图4，图4为本发明实施例一种计算机设备内存检测方法的第二种具体实现结构示意图，在图4中，内存检测单元位于内存条外，CPU通过内存检测单元与每个内存条连接。多个内存条中的内存检测单元能够同时对内存条检测，并将检测结果发送给中央处理器。例如内存1至内存由内存检测单元1同时进行检测，从而实现内存的并行检测，达到节省内存检测时间，提高内存检测效率的目的。还可以进一步的，内存检测单元2同时检测其它内存，实现更多的内存并行检测，达到节省更多内存检测时间，提高内存检测效率的目的。
参考图5，图5为本发明实施例一种计算机设备内存检测方法的第三种具体实现结构示意图，在图4中，内存检测单元位于内存条的每个RAM Chip中，CPU通过每个内存条中每个RAM Chip中的内存检测单元与每个内存条的RAM Chip连接。多个内存条中的内存检测单元能够同时对内存条检测，并将检测结果发送给中央处理器。例如内存1中的每个RAM Chip中的内存检测单元同时对内存1中各自对应的RAM Chip进行检测，从而实现内存的并行检测，达到节省内存检测时间，提高内存检测效率的目的。还可以进一步的，内存2中的每个RAM Chip中的内存检测单元同时对内存2中各自对应的RAM Chip进行检测，实现更多的内存并行检测，达到节省更多内存检测时间，提高内存检测效率的目的。并且，RAM Chip中内置内存检测单元，能够进一步提升自检速度，并降低内存检测单元的设计复杂度。
上述图3、图4或图5中的内存检测单元可以是一个集成芯片，其内部结构如图6所示：
内存检测单元接管了CPU访问内存的内存总线，CPU通过访问特定的物理地址可以读写内存检测单元的寄存器。例如内存检测单元中的切换器下挂的内存空间(Memory space)是0x00000000-0x01000000，选取一个不在此范围的地址空间(如0x01000000-0x10000010)作为寄存器，CPU通过访问该寄存器的地址空间来访问该内存检测单元。内存检测单元中的切换器实现切换内存给CPU访问或者内存检测单元的检测引擎访问，当CPU向内存检测单元下发检测指示时，切换器切断检索引擎与内存的连接；当检测引擎启动对内存模块的检测时，切换器切断与CPU的连接。其中，切换器的变换，由一个可写入寄存器的控制器来实现；内存检测单元的检测触发指令，以及查询检测状态的查询器都存于这个寄存器中。
当计算机设备启动并完成内存的初始化后，中央处理器CPU通过寄存器向内存检测单元下发启动内存检测的指示，这时，内存检测单元中的切换器切断检测引擎与内存的连接。当寄存器完成CPU下发的内存检测指示，启动对内存的检测时，所述切换器切断寄存器与切换器的连接，即切断了内存检测单元与CPU的连接，由检索引擎对地址为0x00000000-0x01000000内存空间进行检测，可以通过多次写入数据并读出数据，判断读出的数据与写入的数据是否一致来判定要检测的内存空间是否正常，是否存在故障等。当检测引擎完成对内存的检测，将检测结果保存在寄存器中。当CPU通过轮询的方式向寄存器获取检测结果时，从该寄存器读取保存的检测结果；或者寄存器通过中断的方式将检测结果发送给CPU。
参考图7，图7为本发明实施例一种计算机设备700的结构示意图，该计算机设备700包括，中央处理器CPU701，至少两个内存模块702，以及至少一个内存检测单元703；所述CPU701通过至少一个内存检测单元703与所述至少一个内存模块702相连；
所述CPU701，用于向所述至少一个内存检测单元703发送内存检测指示；
所述至少一个内存检测单元703，用于接收所述CPU701发送的内存检测指示，并根据接收到的所述内存检测指示对所述至少两个内存模块702中的至少两个同时进行内存检测，并依据所述CPU701的获取检测结果指示将检测结果发送给所述CPU701或将检测结果通过中断的方式发送给所述CPU701。
上述计算机设备，通过至少一个内存检测单元703对至少两个内存模块702同时进行检测，实现了并行检测内存模块的目的，能够在同一时间对至少两个内存模块进行检测，缩短了对内存模块进行检测的时间，提高了检测的效率。
其中，所述内存模块702可以是一个内存条，或一个内存条中的一个RAM Chip。所述CPU701通过轮询的方式，向所述内存检测单元703发送获取检测结果的指示。
在具体实现中，可以是一个内存检测单元703与至少两个内存模块702相连，所述一个内存检测单元703同时对至少两个内存模块702并行进行检测，如图7所示。也可以如图8所示，由一个内存检测单元703与一个内存模块702相连，另一个内存检测单元703与另一内存模块702相连，两个内存检测单元703同时对各自相连的内存模块702并行检测。还可以是一个内存检测单元703与一个内存模块702相连，另一个内存检测单元703与另外两个或多个内存模块702相连，两个内存检测单元同时对各自相连的内存模块并行检测，如图9所示。只要能够实现对内存模块在同一时间的并行检测，都包含在本发明实施例的保护范围内，不再一一举例。
需要说明的是，上述图7-图9的附图中，出于简化、清楚展示附图的考虑，没有显示出多个内存检测单元703和内存模块702，即对于“至少一个内存检测模块703”只显示出一个内存检测模块703，对于“至少两个内存模块702”只显示出两个内存模块702等等。对于两个以上的内存检测模块 703或三个以上的内存模块702等等，都在本发明实施例的保护范围内，图7-图9中一个内存检测单元703，或两个内存模块702不应构成对本发明实施例的限制。
在具体实现中，如图10所示，所述至少一个内存检测单元703中的任意一个内存检测单元703包括：
检测控制单元7031，用于接收所述CPU701发送的内存检测指示，并根据接收到的所述内存检测指示对所述至少两个内存模块702中的至少两个同时进行内存检测；
检测结果存储单元7032，用于存储所述检测控制单元7031对至少两个内存模块702检测后的检测结果，并依据所述CPU701的获取检测结果指示将检测结果发送给所述CPU701或将检测结果通过中断的方式发送给所述CPU701。
在具体实现时，所述检测控制单元7031对内存模块702检测可以通过如下方式实现：所述检测控制单元7031向其连接的内存模块中写入第一数据，并从存放所述第一数据的空间中读出第二数据，比较所述第一数据与所述第二数据，根据比较的结果判断所述内存是否存在故障。具体的判断方式可以是：如果所述第一数据与所述第二数据相同，则认定所述内存模块正常，如果所述第一数据与所述第二数据不一致，则认定所述内存模块异常或故障。
作为一种可选的实现方式，如图11所述，所述内存检测单元703还包括切换开关7033，用于实现所述内存检测单元与所述CPU701与内存模块702之间的连接切换，当内存检测单元703与所述CPU701通信时，切断内存检测单元703与内存模块702的连接，当内存检测单元703与内存模块702通信时，切断内存检测单元703与所述CPU701的连接。使得内存检测单元703在同一时间只与CPU701相连，或只与内存模块702相连。这样，内存检测单元703 在对内存模块702进行检测时，不会接收CPU701的命令，不会出现冲突的情况。
可选的，所述至少一个内存检测单元703可以位于待检测的内存模块702中，或所述至少一个内存检测单元703位于所述CPU701与待检测的内存模块702之间。在具体实现中，所述至少一个内存检测单元703位于待检测的内存模块中，可以是所述至少一个内存检测单元703位于一个内存条中并分别与每个RAM Chip相连，或者一个内存条的每个RAM Chip中都设置一个内存检测单元。所述至少一个内存检测单元703位于所述CPU701与待检测的内存702之间的具体实现方式，可以通过在内存模块702与CPU701之间的通道上设置至少一个内存检测单元703来实现；例如，可以是计算机设备的主板设置的一个芯片，用于实现该内存检测单元703的功能。
本发明实施例的计算机设备700，可以参考上述图1-图6所示的实施例中的实现方式来实现，不再赘述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实 现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本发明实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (14)

  1. 一种计算机设备内存检测的方法，其特征在于，包括：
    至少一个内存检测单元接收所述计算机设备的中央处理器CPU发送的内存检测指示，对所述计算机设备的至少两个内存模块中的至少两个同时进行内存检测；其中，所述至少一个内存检测单元连接所述CPU与所述计算机设备的至少两个内存模块，使得所述CPU通过所述至少一个内存检测单元与所述至少两个内存模块进行通信；
    所述至少一个内存检测单元根据所述CPU发送的检测结果获取请求，将所述至少两个内存模块的检测结果发送给所述CPU。
  2. 根据权利要求1所述的方法，其特征在于：
    所述内存检测单元位于每个内存模块中，或所述内存检测单元位于所述CPU与至少两个内存模块之间。
  3. 根据权利要求1或2所述的方法，其特征在于，所述方法还包括：
    在所述内存检测单元与所述CPU通信时，所述内存检测单元切断与所述至少两个内存模块的连接；或者，当所述内存检测单元对内存模块进行检测时，所述内存检测单元切断与所述CPU的连接。
  4. 根据权利要求2所述的方法，其特征在于：
    当所述内存检测单元位于每个内存模块中时，每个内存模块中包括一个内存检测单元，所述内存检测单元与每个内存模块中的所有RAM Chip相连；或，
    所述内存模块的每个RAM Chip中包含一个所述内存检测单元。
  5. 根据权利要求1‐4中任一所述的方法，其特征在于，在所述至少一个内存检测单元接收所述计算机设备的CPU发送的内存检测指示之前，所述方法还包括：
    修改基本输入输出BIOS程序，使得所述CPU根据所述BIOS中的程序，向所述至少一个内存检测单元发送内存检测的指示。
  6. 一种计算机设备内存检测的方法，其特征在于，包括：
    计算机设备的中央处理器CPU向至少一个内存检测单元发送内存检测指示，所述内存检测指示用于指示所述至少一个内存检测单元启动对内存模块的检测，所述CPU通过所述至少一个内存检测单元与至少两个内存模块进行通信；
    所述CPU从所述至少一个内存检测单元获取所述内存模块的检测结果，所述检测结果是所述至少一个内存检测单元对所述至少两个内存模块中的至少两个同时进行内存检测后的检测结果。
  7. 根据权利要求6中所述的方法，其特征在于，在所述计算机设备的中央处理器CPU向至少一个内存检测单元发送内存检测指示之前，所述方法还包括：
    所述CPU从基本输入输出BIOS程序中获取指令，向所述至少一个内存检测单元发送内存检测的指示。
  8. 根据权利要求6或7所述的方法，其特征在于，所述CPU从所述至少一个内存检测单元获取所述内存模块的检测结果包括：
    所述CPU通过轮询的方式，从所述内存检测单元获取所述内存模块的检测结果，或所述CPU接收所述内存检测单元通过中断的方式上报的所述内存模块的检测结果。
  9. 一种计算机设备，包括中央处理器CPU和至少两个内存模块，其特征在于，所述计算机设备还包括至少一个内存检测单元；其中，
    所述CPU，用于向所述至少一个内存检测单元发送内存检测指示；
    所述至少一个内存检测单元，用于接收所述CPU发送的内存检测指示，并根据接收到的所述内存检测指示对所述至少两个内存模块中的至少两个同时进行内存检测，并依据所述CPU的获取检测结果指示将检测结果发送给所述CPU或将检测结果通过中断的方式发送给所述CPU。
  10. 根据权利要求9所述的计算机设备，其特征在于，所述CPU通过所述至少一个内存检测单元与所述至少两个内存模块通信。
  11. 根据权利要求9或10所述的计算机设备，其特征在于，所述内存检测单元包括：
    检测控制单元，用于接收所述CPU发送的内存检测指示，并根据接收到的所述内存检测指示对所述至少两个内存模块中的至少两个同时进行内存检测；
    检测结果存储单元，用于存储所述检测控制单元对至少两个内存模块检测后的检测结果，并依据所述CPU的获取检测结果指示将检测结果发送给所述CPU或将检测结果通过中断的方式发送给所述CPU。
  12. 根据权利要求9-11任一所述的计算机设备，其特征在于，所述内存检测单元还包括切换开关，所述切换开关用于实现所述内存检测单元与所述CPU与内存模块之间的连接切换，当内存检测单元与所述CPU通信时，切断所述内存检测单元与所述内存模块之间的连接，当所述内存检测单元与所述内存模块通信时，切断所述内存检测单元与所述CPU的连接。
  13. 根据权利要求9-12任一所述的计算机设备，其特征在于，所述至少一个内存检测单元位于待检测的内存模块中，或所述至少一个内存检测单元位于所述CPU与待检测的内存模块之间。
  14. 根据权利要求13任一所述的计算机设备，其特征在于，当所述内存检测单元位于每个内存模块中时，每个内存模块中包括一个内存检测单元，所述内存检测单元与每个内存模块中的所有RAM Chip相连；或，
    所述内存模块的每个RAM Chip中包含一个所述内存检测单元。
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