WO2020233435A1 - 数据处理方法、装置和系统 - Google Patents

数据处理方法、装置和系统 Download PDF

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Publication number
WO2020233435A1
WO2020233435A1 PCT/CN2020/089605 CN2020089605W WO2020233435A1 WO 2020233435 A1 WO2020233435 A1 WO 2020233435A1 CN 2020089605 W CN2020089605 W CN 2020089605W WO 2020233435 A1 WO2020233435 A1 WO 2020233435A1
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Prior art keywords
data
storage device
built
data processing
external storage
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PCT/CN2020/089605
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English (en)
French (fr)
Inventor
李峰
龙欣
张振祥
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阿里巴巴集团控股有限公司
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Publication of WO2020233435A1 publication Critical patent/WO2020233435A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Definitions

  • This application relates to the computer field, and specifically, to a data processing method, device, and system.
  • the existing scheme for accelerating PFGA is mainly to input data at the network port of the FPGA board to accelerate the cache system.
  • DDR Double Data Rate
  • NVMe Non-Volatile Memory Express, Non-Volatile Memory Host Controller Interface Specification
  • NVMe is installed on the FPGA board.
  • SSD Solid State Drives
  • NVMe NVMe
  • the direct connection of SSD and FPGA board will affect the structure and heat dissipation performance of FPGA board.
  • the position of the FPGA board in the cache system makes it difficult for the FPGA board to use high-performance large-scale chips for memory expansion, and it is impossible to perform fine-grained memory acceleration when the capacity is expanded.
  • the embodiments of the present application provide a data processing method, device, and system to at least solve the technical problem of poor performance of the FPGA board caused by the direct connection of the FPGA board and the external storage device to expand the built-in storage device in the related technology.
  • a data processing method including: storing first data in a built-in storage device of a field programmable gate array FPGA board, and storing the first data in an external storage device of the FPGA board. 2. Data, where the FPGA board is connected to the external storage device through the built-in high-speed peripheral component interconnection switch card PCIe switch; obtains data processing instructions, and performs operations corresponding to the data processing instructions on the built-in storage device and/or the external storage device .
  • a data processing device including: a storage module for storing first data in a built-in storage device of a field programmable gate array FPGA board, and The second data is stored in the external storage device, where the FPGA board is connected to the external storage device through the built-in high-speed peripheral component interconnection switch card PCIe switch; the processing module is used to obtain data processing instructions, and the built-in storage device and/ Or the external storage device executes the operation corresponding to the data processing instruction.
  • a storage medium includes a stored program, wherein the device where the storage medium is located is controlled to execute the data processing method when the program runs.
  • a processor is also provided, the processor is configured to run a program, wherein the data processing method is executed when the program is running.
  • a data processing system including: a processor; and a memory, connected to the processor, and configured to provide the processor with instructions for processing the following processing steps:
  • the first data is stored in the built-in storage device of the FPGA board of the array, and the second data is stored in the external storage device of the FPGA board.
  • the FPGA board connects the switch card PCIe switch and the external memory through the built-in high-speed peripheral components. Device connection; obtain data processing instructions, and perform operations corresponding to the data processing instructions on the built-in storage device and/or the external storage device.
  • a data processing method including: storing data in an external storage device of a field programmable gate array FPGA board, wherein the FPGA board uses a built-in high-speed peripheral component
  • the PCIe switch of the interconnection switch card is connected to an external storage device; obtains data processing instructions, and performs operations corresponding to the data processing instructions on the built-in storage device and/or the external storage device.
  • a high-speed peripheral component interconnection exchange card is used to connect the FPGA board to an external storage device, and the first data is stored in the built-in storage device of the field programmable gate array FPGA board and stored in the FPGA
  • the external storage device of the board card stores the second data, and after obtaining the data processing instruction, an operation corresponding to the data processing instruction is performed on the built-in storage device and/or the external storage device.
  • the built-in high-speed peripheral component interconnection exchange card is set to connect the FPGA board to the external storage device. Not only can the FPGA board be expanded, but the external storage device is not directly connected to the FPGA board. It affects the structure and heat dissipation performance of the FPGA board, thereby achieving the purpose of expanding the FPGA board and achieving the technical effect of ensuring the performance of the FPGA board.
  • data with different access frequencies are stored in the built-in storage device and the external storage device. When accessing the stored data in the built-in storage device and/or the external storage device, the data access rate can be further increased.
  • Fig. 1 is a block diagram of the hardware structure of a computer terminal according to an embodiment of the present application
  • Fig. 2 is a flowchart of a data processing method according to an embodiment of the present application
  • Fig. 3 is a schematic diagram of an optional data processing system according to an embodiment of the present application.
  • Fig. 4 is a schematic diagram of an optional data processing system according to an embodiment of the present application.
  • Fig. 5 is a schematic diagram of an optional data processing system according to an embodiment of the present application.
  • Fig. 6 is a schematic diagram of a data processing device according to an embodiment of the present application.
  • Fig. 7 is a structural block diagram of a computer terminal according to an embodiment of the present application.
  • Fig. 8 is a flowchart of a data processing method according to an embodiment of the present application.
  • an embodiment of a data processing method is also provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and, Although a logical sequence is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than here.
  • FIG. 1 shows a block diagram of the hardware structure of a computer terminal (or mobile device) for implementing a data processing method.
  • the computer terminal 10 may include one or more (shown as 102a, 102b, ..., 102n in the figure) processor 102 (the processor 102 may include, but is not limited to, a micro A processing device such as a processor MCU or a programmable logic device FPGA), a memory 104 for storing data, and a transmission device 106 for communication functions.
  • a micro A processing device such as a processor MCU or a programmable logic device FPGA
  • memory 104 for storing data
  • a transmission device 106 for communication functions.
  • the computer terminal 10 can also include: display, input/output interface (I/O interface), universal serial bus (USB) port (can be included as one of the ports of I/O interface), network interface, power supply And/or camera.
  • I/O interface input/output interface
  • USB universal serial bus
  • FIG. 1 is only for illustration, and does not limit the structure of the above electronic device.
  • the computer terminal 10 may also include more or fewer components than those shown in FIG. 1, or have a different configuration from that shown in FIG.
  • the aforementioned one or more processors 102 and/or other data processing circuits may generally be referred to as "data processing circuits" herein.
  • the data processing circuit can be embodied in whole or in part as software, hardware, firmware or any other combination.
  • the data processing circuit may be a single independent processing module, or be fully or partially integrated into any one of the other elements in the computer terminal 10 (or mobile device).
  • the data processing circuit is used as a kind of processor control (for example, selection of a variable resistance terminal path connected to an interface).
  • the memory 104 may be used to store software programs and modules of application software, such as program instructions/data storage devices corresponding to the data processing method in the embodiment of the present application.
  • the processor 102 executes the software programs and modules stored in the memory 104 by running Various functional applications and data processing, namely to achieve the above data processing methods.
  • the memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory 104 may further include a memory remotely provided with respect to the processor 102, and these remote memories may be connected to the computer terminal 10 via a network. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
  • the transmission device 106 is used to receive or send data via a network.
  • the above-mentioned specific examples of the network may include a wireless network provided by the communication provider of the computer terminal 10.
  • the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station to communicate with the Internet.
  • the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet in a wireless manner.
  • RF radio frequency
  • the display may be, for example, a touch screen liquid crystal display (LCD), which may enable a user to interact with the user interface of the computer terminal 10 (or mobile device).
  • LCD liquid crystal display
  • the computer device (or mobile device) shown in FIG. 1 may include hardware elements (including circuits) and software elements (including computer-readable media stored on a computer-readable medium). Code), or a combination of hardware and software components.
  • FIG. 1 is only an example of a specific specific example, and is intended to show the types of components that may be present in the above-mentioned computer device (or mobile device).
  • FIG. 2 is a flowchart of the data processing method according to Embodiment 1 of the present application. As shown in Figure 2, the method at least includes the following steps:
  • Step S202 store the first data in the built-in storage device of the FPGA board of the field programmable gate array, and store the second data in the external storage device of the FPGA board, where the FPGA board interacts with each other through the built-in high-speed peripheral components.
  • the PCIe switch is connected to an external storage device, and the access frequency of the first data is higher than the access frequency of the second data.
  • the built-in storage device is a double-rate synchronous dynamic random access memory DDR
  • the external storage device is a non-volatile built-in storage device host controller interface specification NVMe storage unit.
  • the first data is hot data
  • the second data is cold data.
  • the first data and the second data are determined by the access frequency of the data.
  • the PFGA chip set on the FPGA board is performing data processing.
  • FIG. 3 shows a schematic diagram of a data processing system.
  • the data processing system includes an NIC (Network Interface Card, network adapter), an FPGA board, a CPU (processor), and The external storage device NVMe directly connected to the FPGA board.
  • the FPGA board includes a high-speed peripheral component interconnection switch card PCIe switch, an FPGA chip, and a built-in storage device DDR.
  • the FPGA chip is connected to the processor of the server through the PCIe switch, and receives and processes key-value storage data writing and reading Command, the FPGA chip is directly connected to the built-in storage device DDR.
  • the FPGA chip and the external storage device NVMe are only interconnected through the PCIe switch on the FPGA board.
  • the PCIe switch is configured to control the point-to-point communication of data between the NVMe and the FPGA chip, avoiding the data passing through the server motherboard.
  • the PCIe switch or the Root Complex (root component) of the CPU affects the bandwidth of the system PCIe, which improves the performance of the FPGA board.
  • Step S204 Obtain a data processing instruction, and perform an operation corresponding to the data processing instruction on the built-in storage device and/or the external storage device.
  • the data processing instruction may include, but is not limited to, a write data instruction and a read data instruction, where the write data instruction is used to write data to the built-in storage device and/or the external storage device, and the read data instruction Used to read data from built-in storage devices and/or external storage devices.
  • the built-in storage device and the external storage device store data with different access frequencies. In the process of writing and reading data, the data can be accessed according to the frequency. Reading or writing data from a built-in storage device or an external storage device can improve data access efficiency. In addition, the built-in storage device stores data with a higher access frequency, and the FPGA chip directly reads data from the built-in storage device or writes data to the built-in storage device, which further improves the efficiency of data access.
  • the high-speed peripheral component interconnection switch card is used to connect the FPGA board to the external storage device, and the built-in storage device of the field programmable gate array FPGA board Store the first data, and store the second data in the external storage device of the FPGA board. After obtaining the data processing instruction, perform operations corresponding to the data processing instruction on the built-in storage device and/or the external storage device, where the first The access frequency of the data is higher than the access frequency of the second data.
  • the FPGA board determines the data to be written according to the write data instruction, wherein, when the storage data capacity of the built-in storage device is lower than the first preset When the threshold is set, the data to be written is written into the built-in storage device; when the storage data capacity of the built-in storage device is equal to or higher than the first preset threshold, first the first data in the first data whose access frequency is lower than the second preset threshold Three parts of data are migrated to the external storage device, and then the data to be written is written into the built-in storage device.
  • the storage data capacity of the built-in storage device may be the number of bytes occupied by data in the built-in storage device.
  • the FPGA board detects the current storage data capacity of the built-in storage device DDR. If the storage data of the built-in storage device DDR is detected The capacity is less than the first preset threshold, indicating that the capacity of the data stored in the built-in storage device DDR is sufficient, and the data to be written is directly written into the built-in storage device DDR. It is easy to notice that the processing speed of the FPGA chip for the built-in storage device is greater than the processing speed for the external storage device. If the storage capacity of the built-in storage device is sufficient, storing it in the built-in storage device can improve Data processing speed of FPGA board.
  • the FPGA board transfers the less frequently accessed data in the built-in storage device to the external storage device, and then writes the data to be written into the built-in storage device.
  • the processing speed of the FPGA chip for the built-in storage device is greater than the processing speed for the external storage device. Therefore, storing the data with lower access frequency into the external storage device can also increase the processing speed of the FPGA board. .
  • the above-mentioned second preset threshold may be a pre-defined value, or a value that dynamically changes according to the access frequency of the data stored in the built-in storage device.
  • the FPGA board sorts all data in the current built-in storage device according to the access frequency from small to large, and migrates the first N data with the smallest access frequency to the external storage device.
  • the FPGA board calculates the average value of the access frequency of all data in the current built-in storage device, and migrates the data whose access frequency is less than the average value to the external storage device.
  • the FPGA board determines the data to be read according to the read data instruction. Among them, if the data to be read is found in the built-in storage device, the data to be read is obtained from the built-in storage device; if the data to be read is not found in the built-in storage device, the data to be read is first accessed by accessing the external storage device. Read the data and import the found data to be read into the built-in storage device, and then obtain the data to be read from the built-in storage device.
  • the FPGA board When the server receives a data read instruction (get in Figure 3), the FPGA board first detects whether there is data to be read in the built-in storage device DDR, and if so, Then read the data directly from the built-in storage device DDR; if there is no data to be read in the built-in storage device DDR, initiate an access request to access the external storage device NVMe, and search for the data to be read from the external storage device NVMe, and then Import the data to be read into the built-in storage device DDR, and directly read the data from the built-in storage device DDR.
  • the built-in storage device stores data with a higher access frequency, in the process of reading data, first search for the data to be read in the built-in storage device, and the probability of obtaining the data to be read is higher. High, and the rate of reading data from the built-in storage device is faster.
  • the solution provided by this application can realize simultaneous processing of multiple pairs of data storage instances.
  • the FPGA board When there are multiple data storage instances to be processed in the FPGA board, separate built-in storage devices and external storage devices are set for each data storage instance to be processed.
  • Each storage instance corresponds to the storage in the built-in storage device DDR.
  • Each storage uses multiple external storage devices NVMe to achieve the capacity of the built-in storage device.
  • the aforementioned storage instance may be a key-value storage instance, for example, memcache, which is a cache system with high performance and distributed built-in storage devices.
  • a traditional physical server can be virtualized into multiple virtual servers, and each virtual server runs an independent operating system.
  • each tenant has one of multiple virtual servers and/or a group of virtual servers, and each tenant has an independent virtual network topology and an independent identifier in a virtual resource environment.
  • each tenant is isolated from each other and can interoperate conditionally under certain network strategy deployment.
  • the external storage device NVMe is directly connected to the FPGA card board, and the external storage device NVMe must be installed on the FPGA card board to limit the structure of the FPGA board.
  • the FPGA board is connected to the external storage device NVMe through PCIe switch, and the external storage device NVMe is used to achieve the expansion of the built-in storage device of the FPGA board, which will not affect the structure and heat dissipation performance of the FPGA board.
  • the FPGA multi-tenant approach to fine-grained it can adapt to the needs of different customers and avoid waste of resources.
  • the data processing method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases The former is a better implementation.
  • the technical solution of this application essentially or the part that contributes to the existing technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, The optical disc) includes several instructions to enable a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the method described in each embodiment of the present application.
  • the device 60 includes a storage module 601 and a processing module 603.
  • the storage module 601 is used to store the first data in the built-in storage device of the field programmable gate array FPGA board and the second data in the external storage device of the FPGA board.
  • the PCIe switch of the high-speed peripheral component interconnection switch card is connected to the external storage device, and the access frequency of the first data is higher than the access frequency of the second data;
  • the processing module 603 is used to obtain data processing instructions, and connects the internal storage device and/or external The storage device performs operations corresponding to the data processing instructions.
  • the built-in storage device is a double-rate synchronous dynamic random access memory DDR
  • the external storage device is a non-volatile built-in storage device host controller interface specification NVMe storage unit.
  • the storage module 601 and the processing module 603 described above correspond to steps S202 to S204 in Embodiment 1.
  • the two modules and the corresponding steps implement the same examples and application scenarios, but are not limited to the above implementations.
  • Example one disclosed content It should be noted that, as a part of the device, the above-mentioned modules can run in the computer terminal 10 provided in the first embodiment.
  • the processing module when the data processing instruction is a write data instruction, includes: a first determining module, a first processing module, and a second processing module.
  • the first determining module is used to determine the data to be written according to the write data instruction;
  • the first processing module is used to write the data to be written when the storage data capacity of the built-in storage device is lower than a first preset threshold Into the built-in storage device;
  • the second processing module is used for when the storage data capacity of the built-in storage device is equal to or higher than the first preset threshold, first the third part of the first data whose access frequency is lower than the second preset threshold The data is migrated to the external storage device, and then the data to be written is written to the built-in storage device.
  • the processing module when the data processing instruction is a read data instruction, includes: a second determining module, a third processing module, and a fourth processing module.
  • the second determination module is used to determine the data to be read according to the read data instruction;
  • the third processing module is used to obtain the data to be read from the built-in storage device if the data to be read is found in the built-in storage device ;
  • the fourth processing module is used to if the data to be read is not found in the built-in storage device, first access the external storage device to find the data to be read and import the found data to the built-in storage device, and then Then obtain the data to be read from the built-in storage device.
  • the data processing device further includes: a fourth processing module, which is used to set mutual data storage instances for each data storage instance to be processed when there are multiple data storage instances to be processed in the FPGA board.
  • a fourth processing module which is used to set mutual data storage instances for each data storage instance to be processed when there are multiple data storage instances to be processed in the FPGA board.
  • the system includes a processor and a memory.
  • the memory is connected with the processor to provide the processor with instructions for processing the following processing steps: storing the first data in the built-in storage device of the field programmable gate array FPGA board, and in the external storage device of the FPGA board Store the second data, where the FPGA board is connected to the external storage device through the built-in high-speed peripheral component interconnection switch card PCIe switch, the access frequency of the first data is higher than the access frequency of the second data; the data processing instruction is obtained, The built-in storage device and/or the external storage device perform operations corresponding to the data processing instruction.
  • the high-speed peripheral component interconnection exchange card is used to connect the FPGA board and the external storage device.
  • the first data is stored in the built-in storage device of the field programmable gate array FPGA board, and the first data is stored in the FPGA board.
  • the second data is stored in the external storage device, and after the data processing instruction is obtained, an operation corresponding to the data processing instruction is performed on the built-in storage device and/or the external storage device, wherein the access frequency of the first data is higher than that of the second data frequency.
  • the embodiments of the present application may provide a computer terminal, and the computer terminal may be any computer terminal device in a computer terminal group.
  • the above-mentioned computer terminal may also be replaced with a terminal device such as a mobile terminal.
  • the foregoing computer terminal may be located in at least one network device among multiple network devices in the computer network.
  • the above-mentioned computer terminal can execute the program code of the following steps in the data processing method: store the first data in the built-in storage device of the field programmable gate array FPGA board, and store the first data in the external storage device of the FPGA board Store the second data, where the FPGA board is connected to the external storage device through the built-in high-speed peripheral component interconnection switch card PCIe switch, the access frequency of the first data is higher than the access frequency of the second data; the data processing instruction is obtained, The built-in storage device and/or the external storage device perform operations corresponding to the data processing instruction.
  • FIG. 7 is a structural block diagram of a computer terminal according to an embodiment of the present application.
  • the computer terminal 10 may include: one or more (only one is shown in the figure) processor 702, memory 704, and transmission device 706.
  • the memory can be used to store software programs and modules, such as program instructions/modules corresponding to the data processing method and device in the embodiments of the present application.
  • the processor executes various functional applications by running the software programs and modules stored in the memory. And data processing, that is, to realize the above-mentioned data processing method.
  • the memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memories.
  • the memory may further include a memory remotely provided with respect to the processor, and these remote memories may be connected to the terminal 10 via a network. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
  • the processor can call the information and application programs stored in the memory through the transmission device to perform the following steps: store the first data in the built-in storage device of the field programmable gate array FPGA board, and in the external storage device of the FPGA board Store the second data, where the FPGA board is connected to the external storage device through the built-in high-speed peripheral component interconnection switch card PCIe switch, the access frequency of the first data is higher than the access frequency of the second data; the data processing instruction is obtained, The built-in storage device and/or the external storage device perform operations corresponding to the data processing instruction.
  • the foregoing processor may also execute the program code of the following steps: determine the data to be written according to the write data instruction; when the storage data capacity of the built-in storage device is lower than the first preset threshold, write the data to be written Into the built-in storage device.
  • the above-mentioned processor may also execute the program code of the following steps: determine the data to be written according to the write data instruction; when the storage data capacity of the built-in storage device is equal to or higher than the first preset threshold, the first The third part of the data whose access frequency is lower than the second preset threshold is migrated to the external storage device, and then the data to be written is written into the built-in storage device.
  • the above-mentioned processor may also execute the program code of the following steps: determine the data to be read according to the read data instruction; if the data to be read is found in the built-in storage device, obtain the data to be read from the built-in storage device .
  • the above-mentioned processor may also execute the program code of the following steps: determine the data to be read according to the read data instruction; if the data to be read is not found in the built-in storage device, first access the external storage device to search The data to be read and the found data to be read are imported into the built-in storage device, and then the data to be read is obtained from the built-in storage device.
  • the above-mentioned processor may also execute the program code of the following steps: when there are multiple data storage instances to be processed in the FPGA board, separate built-in storage devices and independent built-in storage devices and External storage device.
  • the built-in storage device is a double-rate synchronous dynamic random access memory DDR
  • the external storage device is a non-volatile built-in storage device host controller interface specification NVMe storage unit.
  • the structure shown in Fig. 7 is only for illustration, and the computer terminal can also be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, an applause computer, and a mobile Internet Device (MID). ), PAD and other terminal equipment.
  • FIG. 7 does not limit the structure of the above electronic device.
  • the computer terminal 10 may also include more or fewer components (such as a network interface, a display device, etc.) than those shown in FIG. 7, or have a configuration different from that shown in FIG.
  • the program can be stored in a computer-readable storage medium, which can be Including: flash disk, read-only memory (Read-Only Memory, ROM), random access device (Random Access Memory, RAM), magnetic disk or optical disk, etc.
  • the embodiment of the present application also provides a storage medium.
  • the aforementioned storage medium may be used to store the program code executed by the data processing method provided in the aforementioned first embodiment.
  • the foregoing storage medium may be located in any computer terminal in a computer terminal group in a computer network, or located in any mobile terminal in a mobile terminal group.
  • the storage medium is configured to store the program code for executing the following steps: store the first data in the built-in storage device of the FPGA board of the field programmable gate array, and The external storage device stores the second data, where the FPGA board is connected to the external storage device through the built-in high-speed peripheral component interconnection switch card PCIe switch, the access frequency of the first data is higher than the access frequency of the second data; the data is obtained Processing instructions, to perform operations corresponding to the data processing instructions on the built-in storage device and/or the external storage device.
  • the storage medium is configured to store the program code for executing the following steps: determine the data to be written according to the write data instruction; when the storage data capacity of the built-in storage device is lower than the first preset When the threshold is reached, write the data to be written into the built-in storage device.
  • the storage medium is configured to store the program code for performing the following steps: determine the data to be written according to the write data instruction; when the storage data capacity of the built-in storage device is equal to or higher than the first When the threshold is preset, the third part of the first data whose access frequency is lower than the second preset threshold is first migrated to the external storage device, and then the data to be written is written into the built-in storage device.
  • the storage medium is configured to store the program code for executing the following steps: determine the data to be read according to the read data instruction; if the data to be read is found in the built-in storage device, then Obtain the data to be read from the built-in storage device.
  • the storage medium is configured to store program code for performing the following steps: determine the data to be read according to the read data instruction; if the data to be read is not found in the built-in storage device, Then, first access the external storage device to find the data to be read and import the found data to be read into the built-in storage device, and then obtain the data to be read from the built-in storage device.
  • the built-in storage device is a double-rate synchronous dynamic random access memory DDR
  • the external storage device is a non-volatile built-in storage device host controller interface specification NVMe storage unit.
  • the storage medium is configured to store the program code used to perform the following steps: when there are multiple data storage instances to be processed in the FPGA board, each data to be processed is stored separately
  • the example sets up independent internal storage devices and external storage devices.
  • an embodiment of a data processing method is also provided. As shown in FIG. 8, the method includes the following steps:
  • Step S802 storing data in an external storage device of the FPGA board of the field programmable gate array, where the FPGA board is connected to the external storage device through the built-in high-speed peripheral component interconnection switch card PCIe switch.
  • the external storage device may be a non-volatile built-in storage device host controller interface specification NVMe storage unit.
  • NVMe non-volatile built-in storage device host controller interface specification
  • the PCIe switch is configured to control the point-to-point communication of data between the NVMe and the FPGA chip, avoiding the data passing through the server
  • the PCIe switch in the motherboard or the Root Complex (root component) of the CPU affects the bandwidth of the system PCIe, which improves the performance of the FPGA board.
  • Step S804 Obtain a data processing instruction, and perform an operation corresponding to the data processing instruction on the built-in storage device and/or the external storage device.
  • the FPGA board includes an external storage device and a built-in storage device.
  • the data stored in the external storage device is the first data
  • the data stored in the built-in storage device is the second data.
  • the access frequency is higher than that of the second data.
  • the built-in storage device may be a double-rate synchronous dynamic random access memory DDR
  • the data processing instructions may include, but are not limited to, write data instructions and read data instructions, where the write data instructions are used to connect to the built-in storage device and/or externally Write data in the storage device, and read data instructions are used to read data from the built-in storage device and/or the external storage device.
  • the built-in storage device and the external storage device store data with different access frequencies. In the process of writing and reading data, the data can be accessed according to the frequency. Reading or writing data from a built-in storage device or an external storage device can improve data access efficiency. In addition, the built-in storage device stores data with a higher access frequency, and the FPGA chip directly reads data from the built-in storage device or writes data to the built-in storage device, which further improves the efficiency of data access.
  • the high-speed peripheral component interconnection switch card is used to connect the FPGA board and the external storage device, and the data is stored in the external storage device of the FPGA board. After the data processing instruction, an operation corresponding to the data processing instruction is performed on the built-in storage device and/or the external storage device.
  • the FPGA board determines the data to be written according to the write data instruction, wherein, when the storage data capacity of the built-in storage device is lower than the first preset When the threshold is set, the data to be written is written into the built-in storage device; when the storage data capacity of the built-in storage device is equal to or higher than the first preset threshold, first the first data in the first data whose access frequency is lower than the second preset threshold Three parts of data are migrated to the external storage device, and then the data to be written is written into the built-in storage device.
  • the FPGA board determines the data to be read according to the read data instruction. Among them, if the data to be read is found in the built-in storage device, the data to be read is obtained from the built-in storage device; if the data to be read is not found in the built-in storage device, the data to be read is first accessed by accessing the external storage device. Read the data and import the found data to be read into the built-in storage device, and then obtain the data to be read from the built-in storage device.
  • the solution provided by this application can realize simultaneous processing of multiple data storage instances.
  • multiple data storage instances to be processed in the FPGA board separate built-in storage devices and external storage devices are set for each data storage instance to be processed.
  • the external storage device NVMe is directly connected to the FPGA card board, and the external storage device NVMe must be installed on the FPGA card board to limit the structure of the FPGA board.
  • the FPGA board is connected to the external storage device NVMe through PCIe switch, and the external storage device NVMe is used to achieve the expansion of the built-in storage device of the FPGA board, which will not affect the structure and heat dissipation performance of the FPGA board.
  • the FPGA multi-tenant approach to fine-grained it can adapt to the needs of different customers and avoid waste of resources.
  • the disclosed technical content can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • multiple units or components may be combined or may be Integrate into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of units or modules, and may be in electrical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program code .

Abstract

一种数据处理方法、装置和系统，该方法包括：在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在FPGA板卡的外接存储器件中存储第二数据（S202），其中，FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与外接存储器件连接；获取数据处理指令，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作（S204）。本方法解决了相关技术中，FPGA板卡与外接存储器件直连对内置存储器件进行扩展导致FPGA板卡性能差的技术问题。

Description

数据处理方法、装置和系统
本申请要求2019年05月21日递交的申请号为201910424272.7、发明名称为“数据处理方法、装置和系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机领域，具体而言，涉及一种数据处理方法、装置和系统。
背景技术
现有的对PFGA(A Field-Programmable Gate Array，现场可编程门阵列)进行加速的方案主要是在FPGA板卡的网口输入数据，以实现对缓存系统的加速。相关技术中，还采用通过FPGA板卡的接口与NVMe(Non-Volatile Memory Express，非易失性内存主机控制器接口规范)连接来进行DDR(Double Data Rate双倍速率)扩展。其中，相关产品中，NVMe安装在FPGA板卡上。
虽然SSD(Solid State Drives，固态硬盘)通过NVMe直接安装在FPGA板卡可以实现对缓存系统的扩展，但SSD与FPGA板卡直接连接会影响FPGA板卡的结构和散热性能。另外，FPGA板卡在缓存系统中的位置使得FPGA板卡不易采用高性能大规格芯片进行内存扩展，而且在容量扩大的情况下无法进行细粒度的内存加速。
针对上述的问题，目前尚未提出有效的解决方案。
发明内容
本申请实施例提供了一种数据处理方法、装置和系统，以至少解决相关技术中，FPGA板卡与外接存储器件直连对内置存储器件进行扩展导致FPGA板卡性能差的技术问题。
根据本申请实施例的一个方面，提供了一种数据处理方法，包括：在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在FPGA板卡的外接存储器件中存储第二数据，其中，FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与外接存储器件连接；获取数据处理指令，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作。
根据本申请实施例的另一方面，还提供了一种数据处理装置，包括：存储模块，用于在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在FPGA板卡 的外接存储器件中存储第二数据，其中，FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与外接存储器件连接；处理模块，用于获取数据处理指令，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作。
根据本申请实施例的另一方面，还提供了一种存储介质，该存储介质包括存储的程序，其中，在程序运行时控制存储介质所在设备执行数据处理方法。
根据本申请实施例的另一方面，还提供了一种处理器，该处理器用于运行程序，其中，程序运行时执行数据处理方法。
根据本申请实施例的另一方面，还提供了一种数据处理系统，包括：处理器；以及存储器，与处理器连接，用于为处理器提供处理以下处理步骤的指令：在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在FPGA板卡的外接存储器件中存储第二数据，其中，FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与外接存储器件连接；获取数据处理指令，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作。
根据本申请实施例的另一方面，还提供了一种数据处理方法，包括：在现场可编程门阵列FPGA板卡的外接存储器件中存储数据，其中，FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与外接存储器件连接；获取数据处理指令，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作。
在本申请实施例中，采用高速外设组件互连交换卡连接FPGA板卡与外接存储器件的方式，通过在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，并在FPGA板卡的外接存储器件中存储第二数据，在获取数据处理指令之后，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作。
在上述过程中，设置内置的高速外设组件互连交换卡使得FPGA板卡与外接存储器件连接，不仅可以实现对FPGA板卡的扩容，而且外接存储器件不与FPGA板卡直接连接，不会对FPGA板卡的结构和散热性能造成影响，从而达到了对FPGA板卡进行扩容的目的，实现了保证FPGA板卡的性能的技术效果。另外，在内置存储器件和外接存储器件中分别存储不同访问频率的数据，在对内置存储器件和/或外接存储器件中的存储数据进行访问的时候，可以进一步地提高数据的访问速率。
由此可见，本申请所提供的方案解决了相关技术中，FPGA板卡与外接存储器件直连对内置存储器件进行扩展导致FPGA板卡性能差的技术问题。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1是根据本申请实施例的一种计算机终端的硬件结构框图；
图2是根据本申请实施例的一种数据处理方法的流程图；
图3是根据本申请实施例的一种可选的数据处理系统的示意图；
图4是根据本申请实施例的一种可选的数据处理系统的示意图；
图5是根据本申请实施例的一种可选的数据处理系统的示意图；
图6是根据本申请实施例的一种数据处理装置的示意图；
图7是根据本申请实施例的一种计算机终端的结构框图；以及
图8是根据本申请实施例的一种数据处理方法的流程图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
实施例1
根据本申请实施例，还提供了一种数据处理方法的实施例，需要说明的是，在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行，并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
本申请实施例一所提供的方法实施例可以在移动终端、计算机终端或者类似的运算装置中执行。图1示出了一种用于实现数据处理方法的计算机终端(或移动设备)的硬件结构框图。如图1所示，计算机终端10(或移动设备10)可以包括一个或多个(图中采用102a、102b，……，102n来示出)处理器102(处理器102可以包括但不限于微处理器MCU或可编程逻辑器件FPGA等的处理装置)、用于存储数据的存储器104、以及用于通信功能的传输装置106。除此以外，还可以包括：显示器、输入/输出接口(I/O接口)、通用串行总线(USB)端口(可以作为I/O接口的端口中的一个端口被包括)、网络接口、电源和/或相机。本领域普通技术人员可以理解，图1所示的结构仅为示意，其并不对上述电子装置的结构造成限定。例如，计算机终端10还可包括比图1中所示更多或者更少的组件，或者具有与图1所示不同的配置。
应当注意到的是上述一个或多个处理器102和/或其他数据处理电路在本文中通常可以被称为“数据处理电路”。该数据处理电路可以全部或部分的体现为软件、硬件、固件或其他任意组合。此外，数据处理电路可为单个独立的处理模块，或全部或部分的结合到计算机终端10(或移动设备)中的其他元件中的任意一个内。如本申请实施例中所涉及到的，该数据处理电路作为一种处理器控制(例如与接口连接的可变电阻终端路径的选择)。
存储器104可用于存储应用软件的软件程序以及模块，如本申请实施例中的数据处理方法对应的程序指令/数据存储装置，处理器102通过运行存储在存储器104内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的数据处理方法。存储器104可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器104可进一步包括相对于处理器102远程设置的存储器，这些远程存储器可以通过网络连接至计算机终端10。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输装置106用于经由一个网络接收或者发送数据。上述的网络具体实例可包括计算机终端10的通信供应商提供的无线网络。在一个实例中，传输装置106包括一个网络适配器(Network Interface Controller，NIC)，其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中，传输装置106可以为射频(Radio Frequency，RF)模块，其用于通过无线方式与互联网进行通讯。
显示器可以例如触摸屏式的液晶显示器(LCD)，该液晶显示器可使得用户能够与计算机终端10(或移动设备)的用户界面进行交互。
此处需要说明的是，在一些可选实施例中，上述图1所示的计算机设备(或移动设备)可以包括硬件元件(包括电路)、软件元件(包括存储在计算机可读介质上的计算机代码)、或硬件元件和软件元件两者的结合。应当指出的是，图1仅为特定具体实例的一个实例，并且旨在示出可存在于上述计算机设备(或移动设备)中的部件的类型。
在上述运行环境下，本申请提供了如图2所示的数据处理方法，图2是根据本申请实施例一的数据处理方法的流程图。由图2可知，该方法至少包括如下步骤：
步骤S202，在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在FPGA板卡的外接存储器件中存储第二数据，其中，FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与外接存储器件连接，第一数据的访问频率高于第二数据的访问频率。
在步骤S202中，内置存储器件为双倍速率同步动态随机存储器DDR，外接存储器件为非易失性内置存储器件主机控制器接口规范NVMe存储单元。另外，第一数据为热数据，第二数据为冷数据，可选的，第一数据和第二数据通过数据的访问频率来确定，例如，设置在FPGA板卡上的PFGA芯片在对数据进行存储时，首先检测该待存储数据的访问频率，如果访问频率大于预设频率，则将待存储数据存储至内置存储器件中，否则继续检测内置存储器件中的存储容量，如果存储容量大于预设存储容量，则将待存储数据存储至外接存储器件中；如果存储容量不大于预设存储容量，则将待存储数据存储至内置存储器件。
在一种可选的实施例中，图3示出了数据处理系统的示意图，由图3可知，数据处理系统包括NIC(Network Interface Card，网络适配器)、FPGA板卡、CPU(处理器)以及与FPGA板卡直连的外接存储器件NVMe。其中，FPGA板卡包括高速外设组件互连交换卡PCIe switch、FPGA芯片以及内置存储器件DDR，FPGA芯片通过PCIe switch与服务器的处理器连接，接收并处理键值存储的数据写入和读取命令，FPGA芯片与内置存储器件DDR直连。
需要说明的是，通过PCIe switch与外接存储器件连接，将外接存储器件作为FPGA芯片的键值存储容量的扩展，可以实现对FPGA板卡内置存储器件的键值存储的内置存储器件的扩展。
另外，FPGA芯片和外接存储器件NVMe之间仅通过FPGA板卡上的PCIe switch互连，通过配置PCIe switch来控制NVMe和FPGA芯片之间的数据的点对点的通信，避免了数据经过服务器的主板中的PCIe switch或者CPU的Root Complex(根组件)对系统PCIe 的带宽造成影响，提高了FPGA板卡的性能。
步骤S204，获取数据处理指令，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作。
在步骤S204中，数据处理指令可以包括但不限于写入数据指令和读取数据指令，其中，写入数据指令用于向内置存储器件和/或外接存储器件中写入数据，读取数据指令用于从内置存储器件和/或外接存储器件中读取数据。
容易注意到的是，内置存储器件和外接存储器件中存储有不同访问频率的数据，在对数据进行写入和读取操作的过程中，可根据数据的访问频率。从内置存储器件或外接存储器件中读取或写入数据，可以提高数据的访问效率。另外，内置存储器件中存储访问频率较高的数据，FPGA芯片直接从内置存储器件读取数据，或者向内置存储器件写入数据，进一步提高了数据的访问效率。
基于上述步骤S202至步骤S204所限定的方案，可以获知，采用高速外设组件互连交换卡连接FPGA板卡与外接存储器件的方式，通过在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，并在FPGA板卡的外接存储器件中存储第二数据，在获取数据处理指令之后，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作，其中，第一数据的访问频率高于第二数据的访问频率。
容易注意到的是，设置内置的高速外设组件互连交换卡使得FPGA板卡与外接存储器件连接，不仅可以实现对FPGA板卡的扩容，而且外接存储器件不与FPGA板卡直接连接，不会对FPGA板卡的结构和散热性能造成影响，从而达到了对FPGA板卡进行扩容的目的，实现了保证FPGA板卡的性能的技术效果。另外，在内置存储器件和外接存储器件中分别存储不同访问频率的数据，在对内置存储器件和/或外接存储器件中的存储数据进行访问的时候，可以进一步地提高数据的访问速率。
由此可见，本申请所提供的方案解决了相关技术中，FPGA板卡与外接存储器件直连对内置存储器件进行扩展导致FPGA板卡性能差的技术问题。
在一种可选的实施例中，当数据处理指令为写入数据指令时，FPGA板根据写入数据指令确定待写入数据，其中，当内置存储器件的存储数据容量低于第一预设阈值时，将待写入数据写入内置存储器件；当内置存储器件的存储数据容量等于或高于第一预设阈值时，先将第一数据中访问频率低于第二预设阈值的第三部分数据迁移至外接存储器件，再将待写入数据写入内置存储器件。
可选的，内置存储器件的存储数据容量可以为内置存储器件中数据所占用的字节数。 以图3为例进行说明，服务器在接收到写入数据指令(如图3中的set)时，FPGA板卡检测内置存储器件DDR当前的存储数据容量，如果检测到内置存储器件DDR的存储数据容量小于第一预设阈值，说明内置存储器件DDR中存储数据的容量充足，直接将待写入数据直接写入内置存储器件DDR中。容易注意到的是，FPGA芯片对内置存储器件的处理速度要大于对外接存储器件的处理速度，在内置存储器件中存储数据的容量充足的情况下，将其存入内置存储器件中，可以提高FPGA板卡对数据的处理速度。
另外，如果检测到内置存储器件DDR的存储数据容量大于等于第一预设阈值，说明内置存储器件DDR中存储数据的容量不足，如果继续向内置存储器件中存储数据，可能会造成内置存储器件溢出的问题。为防止内置存储器件溢出，FPGA板卡将内置存储器件中访问频率较低的数据迁移至外接存储器件中，然后再将待写入数据写入内置存储器件中。同样的，FPGA芯片对内置存储器件的处理速度要大于对外接存储器件的处理速度，因此，将访问频率较低的数据存入至外接存储器件中，同样可以提高FPGA板卡对数据的处理速度。
需要说明的是，上述第二预设阈值可以为预先定义的数值，也可以根据内置存储器件所存储数据的访问频率动态变化的数值。例如，FPGA板卡按照的访问频率从小到大对当前内置存储器件中所有数据进行排序，并将前N个访问频率最小的数据迁移至外接存储器件中。又例如，FPGA板卡计算当前内置存储器件中所有数据的访问频率的平均值，并将访问频率小于平均值的数据迁移至外接存储器件中。
在一种可选的实施例中，当数据处理指令为读取数据指令时，FPGA板根据读取数据指令确定待读取数据。其中，如果在内置存储器件中查找到待读取数据，则从内置存储器件获取待读取数据；如果在内置存储器件中未查找到待读取数据，则先通过访问外接存储器件以查找待读取数据并将查找到的待读取数据导入内置存储器件，然后再从内置存储器件获取待读取数据。
可选的，以图3为例进行说明，服务器在接收到读取数据指令(如图3中的get)时，FPGA板卡首先检测内置存储器件DDR中是否存在待读取数据，如果存在，则直接从内置存储器件DDR中读取数据；如果内置存储器件DDR中不存在待读取数据，则发起访问外接存储器件NVMe的访问请求，并从外接存储器件NVMe中查找待读取数据，然后将待读取数据导入到内置存储器件DDR中，并直接从内置存储器件DDR中读取数据。
需要说明的是，由于内置存储器件中存储的是访问频率较高的数据，因此，在读取数据的过程中，首先在内置存储器件中查找待读取数据，得到待读取数据的概率较高， 并且，从内置存储器件中读取数据的速率较快。
在另一种可选的方案中，本申请所提供的方案可实现同时多对个数据存储实例进行处理。当FPGA板卡中存在多个待处理的数据存储实例时，分别为每个待处理的数据存储实例设置相互独立的内置存储器件和外接存储器件。如图4和图5所示，FPGA芯片中具有四个存储实例，每个存储实例分别与内置存储器件DDR中的存储相对应，每个存储通过多个外接存储器件NVMe实现内置存储器件容量的扩容。其中，上述存储实例可以为键值存储实例，例如，memcache，memcache为具有高性能、分布式内置存储器件的缓存系统。
需要说明的是，上述过程通过PFGA多租户的方式细粒度使用FPGA对内置存储器件进行加速，可适应不同客户的需求，保障了客户数据的安全，避免了资源的浪费。
此外，还需要说明的是，在多租户的方式中，可将传统的物理服务器虚拟化为多个虚拟服务器，每个虚拟服务器运行独立的操作系统。其中，每个租户具有多个虚拟服务器中的一个和/或一组虚拟服务器，且每个租户具有独立的虚拟网络拓扑，在虚拟资源环境下具有独立的标识。另外，每个租户相互隔离，并可在一定的网络策略部署下有条件的互通。
由上述内容可知，相较于现有技术中，将外接存储器件NVMe直接连接FPGA卡板上，并要求外接存储器件NVMe必须安装在FPGA卡板上限制FPGA板卡的结构，本申请所提供的方案中，通过PCIe switch的方式使得FPGA板卡与外接存储器件NVMe连接，用外接存储器件NVMe来实现对FPGA卡板的内置存储器件的扩容，对FPGA卡板的结构以及散热性能不会产生影响。另外，通过FPGA多租户的方式来细粒度，能够适应不同的客户的需求，避免了资源浪费。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本申请所必须的。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的数据处理方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储 在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
实施例2
根据本申请实施例，还提供了一种用于实施上述数据处理方法的数据处理装置，如图6所示，该装置60包括：存储模块601以及处理模块603。
其中，存储模块601，用于在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在FPGA板卡的外接存储器件中存储第二数据，其中，FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与外接存储器件连接，第一数据的访问频率高于第二数据的访问频率；处理模块603，用于获取数据处理指令，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作。
可选的，内置存储器件为双倍速率同步动态随机存储器DDR，外接存储器件为非易失性内置存储器件主机控制器接口规范NVMe存储单元。
此处，需要说明的是，上述存储模块601以及处理模块603对应于实施例1中的步骤S202至步骤S204，两个模块与对应的步骤所实现的实例和应用场景相同，但不限于上述实施例一所公开的内容。需要说明的是，上述模块作为装置的一部分可以运行在实施例一提供的计算机终端10中。
在一种可选的方案中，当数据处理指令为写入数据指令时，处理模块包括：第一确定模块、第一处理模块以及第二处理模块。其中，第一确定模块，用于根据写入数据指令确定待写入数据；第一处理模块，用于当内置存储器件的存储数据容量低于第一预设阈值时，将待写入数据写入内置存储器件；第二处理模块，用于当内置存储器件的存储数据容量等于或高于第一预设阈值时，先将第一数据中访问频率低于第二预设阈值的第三部分数据迁移至外接存储器件，再将待写入数据写入内置存储器件。
在一种可选的方案中，当数据处理指令为读取数据指令时，处理模块包括：第二确定模块、第三处理模块以及第四处理模块。其中，第二确定模块，用于根据读取数据指令确定待读取数据；第三处理模块，用于如果在内置存储器件中查找到待读取数据，则从内置存储器件获取待读取数据；第四处理模块，用于如果在内置存储器件中未查找到待读取数据，则先通过访问外接存储器件以查找待读取数据并将查找到的待读取数据导入内置存储器件，然后再从内置存储器件获取待读取数据。
在一种可选的方案中，数据处理装置还包括：第四处理模块，用于当FPGA板卡中存在多个待处理的数据存储实例时，分别为每个待处理的数据存储实例设置相互独立的内 置存储器件和外接存储器件。
实施例3
根据本申请实施例，还提供了一种用于实施上述数据处理方法的数据处理系统，该系统包括：处理器以及存储器。
其中，存储器与处理器连接，用于为处理器提供处理以下处理步骤的指令：在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在FPGA板卡的外接存储器件中存储第二数据，其中，FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与外接存储器件连接，第一数据的访问频率高于第二数据的访问频率；获取数据处理指令，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作。
由上可知，采用高速外设组件互连交换卡连接FPGA板卡与外接存储器件的方式，通过在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，并在FPGA板卡的外接存储器件中存储第二数据，在获取数据处理指令之后，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作，其中，第一数据的访问频率高于第二数据的访问频率。
容易注意到的是，设置内置的高速外设组件互连交换卡使得FPGA板卡与外接存储器件连接，不仅可以实现对FPGA板卡的扩容，而且外接存储器件不与FPGA板卡直接连接，不会对FPGA板卡的结构和散热性能造成影响，从而达到了对FPGA板卡进行扩容的目的，实现了保证FPGA板卡的性能的技术效果。另外，在内置存储器件和外接存储器件中分别存储不同访问频率的数据，在对内置存储器件和/或外接存储器件中的存储数据进行访问的时候，可以进一步地提高数据的访问速率。
由此可见，本申请所提供的方案解决了相关技术中，FPGA板卡与外接存储器件直连对内置存储器件进行扩展导致FPGA板卡性能差的技术问题。
需要说明的是，本实施例所提供的数据处理系统可执行实施例1中的数据处理方法，相关内容已在实施例1中进行说明，在此不再赘述。
实施例4
本申请的实施例可以提供一种计算机终端，该计算机终端可以是计算机终端群中的任意一个计算机终端设备。可选地，在本实施例中，上述计算机终端也可以替换为移动终端等终端设备。
可选地，在本实施例中，上述计算机终端可以位于计算机网络的多个网络设备中的至少一个网络设备。
在本实施例中，上述计算机终端可以执行数据处理方法中以下步骤的程序代码：在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在FPGA板卡的外接存储器件中存储第二数据，其中，FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与外接存储器件连接，第一数据的访问频率高于第二数据的访问频率；获取数据处理指令，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作。
可选地，图7是根据本申请实施例的一种计算机终端的结构框图。如图7所示，该计算机终端10可以包括：一个或多个(图中仅示出一个)处理器702、存储器704以及传输装置706。
其中，存储器可用于存储软件程序以及模块，如本申请实施例中的数据处理方法和装置对应的程序指令/模块，处理器通过运行存储在存储器内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的数据处理方法。存储器可包括高速随机存储器，还可以包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器可进一步包括相对于处理器远程设置的存储器，这些远程存储器可以通过网络连接至终端10。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
处理器可以通过传输装置调用存储器存储的信息及应用程序，以执行下述步骤：在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在FPGA板卡的外接存储器件中存储第二数据，其中，FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与外接存储器件连接，第一数据的访问频率高于第二数据的访问频率；获取数据处理指令，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作。
可选的，上述处理器还可以执行如下步骤的程序代码：根据写入数据指令确定待写入数据；当内置存储器件的存储数据容量低于第一预设阈值时，将待写入数据写入内置存储器件。
可选的，上述处理器还可以执行如下步骤的程序代码：根据写入数据指令确定待写入数据；当内置存储器件的存储数据容量等于或高于第一预设阈值时，先将第一数据中访问频率低于第二预设阈值的第三部分数据迁移至外接存储器件，再将待写入数据写入内置存储器件。
可选的，上述处理器还可以执行如下步骤的程序代码：根据读取数据指令确定待读取数据；如果在内置存储器件中查找到待读取数据，则从内置存储器件获取待读取数据。
可选的，上述处理器还可以执行如下步骤的程序代码：根据读取数据指令确定待读 取数据；如果在内置存储器件中未查找到待读取数据，则先通过访问外接存储器件以查找待读取数据并将查找到的待读取数据导入内置存储器件，然后再从内置存储器件获取待读取数据。
可选的，上述处理器还可以执行如下步骤的程序代码：当FPGA板卡中存在多个待处理的数据存储实例时，分别为每个待处理的数据存储实例设置相互独立的内置存储器件和外接存储器件。
可选的，内置存储器件为双倍速率同步动态随机存储器DDR，外接存储器件为非易失性内置存储器件主机控制器接口规范NVMe存储单元。
本领域普通技术人员可以理解，图7所示的结构仅为示意，计算机终端也可以是智能手机(如Android手机、iOS手机等)、平板电脑、掌声电脑以及移动互联网设备(Mobile Internet Devices，MID)、PAD等终端设备。图7其并不对上述电子装置的结构造成限定。例如，计算机终端10还可包括比图7中所示更多或者更少的组件(如网络接口、显示装置等)，或者具有与图7所示不同的配置。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令终端设备相关的硬件来完成，该程序可以存储于一计算机可读存储介质中，存储介质可以包括：闪存盘、只读存储器(Read-Only Memory，ROM)、随机存取器(Random Access Memory，RAM)、磁盘或光盘等。
实施例5
本申请的实施例还提供了一种存储介质。可选地，在本实施例中，上述存储介质可以用于保存上述实施例一所提供的数据处理方法所执行的程序代码。
可选地，在本实施例中，上述存储介质可以位于计算机网络中计算机终端群中的任意一个计算机终端中，或者位于移动终端群中的任意一个移动终端中。
可选地，在本实施例中，存储介质被设置为存储用于执行以下步骤的程序代码：在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在FPGA板卡的外接存储器件中存储第二数据，其中，FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与外接存储器件连接，第一数据的访问频率高于第二数据的访问频率；获取数据处理指令，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作。
可选地，在本实施例中，存储介质被设置为存储用于执行以下步骤的程序代码：根据写入数据指令确定待写入数据；当内置存储器件的存储数据容量低于第一预设阈值时，将待写入数据写入内置存储器件。
可选地，在本实施例中，存储介质被设置为存储用于执行以下步骤的程序代码：根据写入数据指令确定待写入数据；当内置存储器件的存储数据容量等于或高于第一预设阈值时，先将第一数据中访问频率低于第二预设阈值的第三部分数据迁移至外接存储器件，再将待写入数据写入内置存储器件。
可选地，在本实施例中，存储介质被设置为存储用于执行以下步骤的程序代码：根据读取数据指令确定待读取数据；如果在内置存储器件中查找到待读取数据，则从内置存储器件获取待读取数据。
可选地，在本实施例中，存储介质被设置为存储用于执行以下步骤的程序代码：根据读取数据指令确定待读取数据；如果在内置存储器件中未查找到待读取数据，则先通过访问外接存储器件以查找待读取数据并将查找到的待读取数据导入内置存储器件，然后再从内置存储器件获取待读取数据。
可选地，内置存储器件为双倍速率同步动态随机存储器DDR，外接存储器件为非易失性内置存储器件主机控制器接口规范NVMe存储单元。
可选地，在本实施例中，存储介质被设置为存储用于执行以下步骤的程序代码：当FPGA板卡中存在多个待处理的数据存储实例时，分别为每个待处理的数据存储实例设置相互独立的内置存储器件和外接存储器件。
实施例6
根据本申请实施例，还提供了一种数据处理方法的实施例，如图8所示，该方法包括如下步骤：
步骤S802，在现场可编程门阵列FPGA板卡的外接存储器件中存储数据，其中，FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与外接存储器件连接。
在步骤S802中，外接存储器件可以为非易失性内置存储器件主机控制器接口规范NVMe存储单元。通过PCIe switch与外接存储器件连接，将外接存储器件作为FPGA芯片的键值存储容量的扩展，可以实现对FPGA板卡内置存储器件的键值存储的内置存储器件的扩展。
需要说明的是，FPGA芯片和外接存储器件NVMe之间仅通过FPGA板卡上的PCIe switch互连，通过配置PCIe switch来控制NVMe和FPGA芯片之间的数据的点对点的通信，避免了数据经过服务器的主板中的PCIe switch或者CPU的Root Complex(根组件)对系统PCIe的带宽造成影响，提高了FPGA板卡的性能。
步骤S804，获取数据处理指令，对内置存储器件和/或外接存储器件执行与数据处 理指令对应的操作。
需要说明的是，FPGA板卡包括外接存储器件和内置存储器件，其中，外接存储器件存储的数据为第一数据，内置存储器件中存储的数据为第二数据，可选的，第一数据的访问频率高于第二数据的访问频率。另外，内置存储器件可以为双倍速率同步动态随机存储器DDR，数据处理指令可以包括但不限于写入数据指令和读取数据指令，其中，写入数据指令用于向内置存储器件和/或外接存储器件中写入数据，读取数据指令用于从内置存储器件和/或外接存储器件中读取数据。
容易注意到的是，内置存储器件和外接存储器件中存储有不同访问频率的数据，在对数据进行写入和读取操作的过程中，可根据数据的访问频率。从内置存储器件或外接存储器件中读取或写入数据，可以提高数据的访问效率。另外，内置存储器件中存储访问频率较高的数据，FPGA芯片直接从内置存储器件读取数据，或者向内置存储器件写入数据，进一步提高了数据的访问效率。
基于上述步骤S802至步骤S804所限定的方案，可以获知，采用高速外设组件互连交换卡连接FPGA板卡与外接存储器件的方式，通过在FPGA板卡的外接存储器件中存储数据，在获取数据处理指令之后，对内置存储器件和/或外接存储器件执行与数据处理指令对应的操作。
容易注意到的是，设置内置的高速外设组件互连交换卡使得FPGA板卡与外接存储器件连接，不仅可以实现对FPGA板卡的扩容，而且外接存储器件不与FPGA板卡直接连接，不会对FPGA板卡的结构和散热性能造成影响，从而达到了对FPGA板卡进行扩容的目的，实现了保证FPGA板卡的性能的技术效果。
由此可见，本申请所提供的方案解决了相关技术中，FPGA板卡与外接存储器件直连对内置存储器件进行扩展导致FPGA板卡性能差的技术问题。
在一种可选的实施例中，当数据处理指令为写入数据指令时，FPGA板根据写入数据指令确定待写入数据，其中，当内置存储器件的存储数据容量低于第一预设阈值时，将待写入数据写入内置存储器件；当内置存储器件的存储数据容量等于或高于第一预设阈值时，先将第一数据中访问频率低于第二预设阈值的第三部分数据迁移至外接存储器件，再将待写入数据写入内置存储器件。
在另一种可选的实施例中，当数据处理指令为读取数据指令时，FPGA板根据读取数据指令确定待读取数据。其中，如果在内置存储器件中查找到待读取数据，则从内置存储器件获取待读取数据；如果在内置存储器件中未查找到待读取数据，则先通过访问外 接存储器件以查找待读取数据并将查找到的待读取数据导入内置存储器件，然后再从内置存储器件获取待读取数据。
此外，本申请所提供的方案可实现同时多对个数据存储实例进行处理。当FPGA板卡中存在多个待处理的数据存储实例时，分别为每个待处理的数据存储实例设置相互独立的内置存储器件和外接存储器件。
由上述内容可知，相较于现有技术中，将外接存储器件NVMe直接连接FPGA卡板上，并要求外接存储器件NVMe必须安装在FPGA卡板上限制FPGA板卡的结构，本申请所提供的方案中，通过PCIe switch的方式使得FPGA板卡与外接存储器件NVMe连接，用外接存储器件NVMe来实现对FPGA卡板的内置存储器件的扩容，对FPGA卡板的结构以及散热性能不会产生影响。另外，通过FPGA多租户的方式来细粒度，能够适应不同的客户的需求，避免了资源浪费。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
在本申请的上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的技术内容，可通过其它的方式实现。其中，以上所描述的装置实施例仅仅是示意性的，例如所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，单元或模块的间接耦合或通信连接，可以是电性或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式 体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (13)

  1. 一种数据处理方法，其特征在于，包括：
    在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在所述FPGA板卡的外接存储器件中存储第二数据，其中，所述FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与所述外接存储器件连接；
    获取数据处理指令，对所述内置存储器件和/或所述外接存储器件执行与所述数据处理指令对应的操作。
  2. 根据权利要求1所述的方法，其特征在于，当所述数据处理指令为写入数据指令时，获取所述数据处理指令，对所述内置存储器件执行与所述数据处理指令对应的操作包括：
    根据所述写入数据指令确定待写入数据；
    当所述内置存储器件的存储数据容量低于第一预设阈值时，将所述待写入数据写入所述内置存储器件。
  3. 根据权利要求1所述的方法，其特征在于，当所述数据处理指令为写入数据指令时，获取所述数据处理指令，对所述内置存储器件和所述外接存储器件执行与所述数据处理指令对应的操作包括：
    根据所述写入数据指令确定待写入数据；
    当所述内置存储器件的存储数据容量等于或高于第一预设阈值时，先将所述第一数据中访问频率低于第二预设阈值的第三部分数据迁移至所述外接存储器件，再将所述待写入数据写入所述内置存储器件。
  4. 根据权利要求1所述的方法，其特征在于，当所述数据处理指令为读取数据指令时，获取所述数据处理指令，对所述内置存储器件执行与所述数据处理指令对应的操作包括：
    根据所述读取数据指令确定待读取数据；
    如果在所述内置存储器件中查找到所述待读取数据，则从所述内置存储器件获取所述待读取数据。
  5. 根据权利要求1所述的方法，其特征在于，当所述数据处理指令为读取数据指令时，获取所述数据处理指令，对所述内置存储器件和所述外接存储器件执行与所述数据处理指令对应的操作包括：
    根据所述读取数据指令确定待读取数据；
    如果在所述内置存储器件中未查找到所述待读取数据，则先通过访问所述外接存储器件以查找所述待读取数据并将查找到的所述待读取数据导入所述内置存储器件，然后再从所述内置存储器件获取所述待读取数据。
  6. 根据权利要求1至5中任一项所述的方法，其特征在于，所述内置存储器件为双倍速率同步动态随机存储器DDR，所述外接存储器件为非易失性内置存储器件主机控制器接口规范NVMe存储单元。
  7. 根据权利要求1至5中任一项所述的方法，其特征在于，当所述FPGA板卡中存在多个待处理的数据存储实例时，分别为每个待处理的数据存储实例设置相互独立的所述内置存储器件和所述外接存储器件。
  8. 根据权利要求1至5中任一项所述的方法，其特征在于，所述第一数据的访问频率高于所述第二数据的访问频率。
  9. 一种数据处理装置，其特征在于，包括：
    存储模块，用于在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在所述FPGA板卡的外接存储器件中存储第二数据，其中，所述FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与所述外接存储器件连接；
    处理模块，用于获取数据处理指令，对所述内置存储器件和/或所述外接存储器件执行与所述数据处理指令对应的操作。
  10. 一种存储介质，其特征在于，所述存储介质包括存储的程序，其中，在所述程序运行时控制所述存储介质所在设备执行权利要求1至8中任意一项所述的数据处理方法。
  11. 一种处理器，其特征在于，所述处理器用于运行程序，其中，所述程序运行时执行权利要求1至8中任意一项所述的数据处理方法。
  12. 一种数据处理方法，其特征在于，包括：
    在现场可编程门阵列FPGA板卡的外接存储器件中存储数据，其中，所述FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与所述外接存储器件连接；
    获取数据处理指令，对内置存储器件和/或所述外接存储器件执行与所述数据处理指令对应的操作。
  13. 一种数据处理系统，其特征在于，包括：
    处理器；以及
    存储器，与所述处理器连接，用于为所述处理器提供处理以下处理步骤的指令：
    在现场可编程门阵列FPGA板卡的内置存储器件中存储第一数据，以及在所述FPGA板卡的外接存储器件中存储第二数据，其中，所述FPGA板卡通过内置的高速外设组件互连交换卡PCIe switch与所述外接存储器件连接；
    获取数据处理指令，对所述内置存储器件和/或所述外接存储器件执行与所述数据处理指令对应的操作。
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