WO2016037503A1 - PCIe拓扑的配置方法和装置 - Google Patents

PCIe拓扑的配置方法和装置 Download PDF

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Publication number
WO2016037503A1
WO2016037503A1 PCT/CN2015/081069 CN2015081069W WO2016037503A1 WO 2016037503 A1 WO2016037503 A1 WO 2016037503A1 CN 2015081069 W CN2015081069 W CN 2015081069W WO 2016037503 A1 WO2016037503 A1 WO 2016037503A1
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Prior art keywords
pcie
switch chip
configuration
connection relationship
current
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PCT/CN2015/081069
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English (en)
French (fr)
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战岳祥
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华为技术有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/12—Discovery or management of network topologies

Definitions

  • the embodiments of the present invention relate to data communication technologies, and in particular, to a method and an apparatus for configuring a PCIe topology.
  • the scalability of the server is an important performance of the server.
  • the scalability of the server means that the hardware configuration of the server can be flexibly configured according to requirements, such as memory, adapter, solid state disk (SSD), processor, and the like.
  • the scalability of the server can be achieved by adding a Peripheral Component Interconnect Express (PCIe) slot on the board.
  • PCIe Peripheral Component Interconnect Express
  • Each PCIe slot can be plugged into a PCIe card, and the PCIe card can be connected.
  • Different PCIe devices can meet the requirements of different users and different application scenarios. For example, plugging in a graphics processing unit (GPU) in the PCIe slot can expand the video processing capability of the server and insert SSD in the PCIe slot. , can expand the storage capacity of the server.
  • GPU graphics processing unit
  • PCIE slots When designing a scalable server, the more PCIE slots the server has, the better the cost and the server's architectural space allow. However, the number of CPUs (CPUs) on the board is limited. As PCIe slots increase, PCIe devices and limited CPU connections will cause PCIE topology design.
  • PCIe topology refers to PCIe. The connection between the device and the CPU on the board. In different application scenarios, the PCIe device is connected to different interfaces of the CPU to form different PCIe topologies. The PCIe topology of different application scenarios is different. The more application scenarios that can be supported, the better.
  • the board when designing a server, firstly, according to the application scenario, the board is designed to meet the application scenarios of the server in the hardware design of the server.
  • the design is designed. Two boards are used to support all application scenarios. When two boards cannot support all application scenarios, you need to design three boards.
  • the PCIE topology of the hardware design planning is difficult to meet the requirements of all application scenarios. Therefore, redundant boards need to be added to meet different application scenarios, resulting in increased server costs.
  • the PCIe topology is designed. Ok, the subsequent changes cannot be made. When a new application scenario occurs, the board needs to be redesigned, which also increases the server cost.
  • the embodiment of the present invention provides a method and a device for configuring a PCIe topology.
  • a board has multiple PCie topologies.
  • the corresponding function is implemented by changing the PCIe topology relationship. Reduce server costs.
  • a first aspect of the present invention provides a method for configuring a PCIe topology, including:
  • the configuration of the PCIe switch chip is modified according to the current connection relationship between each PCIe device and each PCIe slot, including :
  • the determining whether the current configuration of the PCIe switch chip matches the current connection relationship including:
  • the identifier of each PCIe slot includes The bus number and the device number of each PCIe device, and the device information of each PCIe device includes: a device identifier and a vendor identifier of each PCIe device.
  • the current connection relationship between each PCIe device and each PCIe slot is After modifying the configuration of the PCIe switch chip, the method further includes:
  • the baseboard management controller BMC on the server or the basic input/output system BIOS of the server.
  • a second aspect of the present invention provides a device for configuring a PCIe topology, including:
  • the obtaining module is configured to obtain identification information of each fast peripheral component interconnecting standard PCIe slot connected to the board of the server, and device information of the PCIe device connected to each PCIe slot;
  • a determining module configured to determine, according to the identifier information of each PCIe slot and the device information of each PCIe device, a current connection relationship between each PCIe device and each PCIe slot;
  • a modification module configured to modify a configuration of the PCIe switch chip according to a current connection relationship between each PCIe device and each PCIe slot.
  • the modifying module includes:
  • An obtaining unit configured to acquire a current configuration of the PCIe switch chip
  • a determining unit configured to determine whether a current configuration of the PCIe switch chip is connected to the current one
  • the plurality of configurations of the PCIe switch chip are in one-to-one correspondence with the plurality of connection relationships between the PCIe devices and the PCIe slots;
  • a modifying unit configured to modify a current state of the PCIe switch chip stored in the erasable programmable read only memory (EPROM) of the PCIe switch chip when the current configuration of the PCIe switch chip does not match the current connection relationship
  • EPROM erasable programmable read only memory
  • the determining unit is specifically configured to:
  • the identifier of each PCIe slot includes The bus number and the device number of each PCIe device, and the device information of each PCIe device includes: a device identifier and a vendor identifier of each PCIe device.
  • a notification module configured to notify the server of the basic input/output system BIOS to restart the server.
  • the apparatus is The baseboard management controller BMC or the basic input/output system BIOS of the server.
  • a third aspect of the present invention provides a PCIe topology configuration apparatus, including: a processor, a memory, a communication interface, and a system bus, wherein the memory and the communication interface are connected to the processor through the system bus and complete each other Communication;
  • the memory for storing computer executable instructions
  • the processor is configured to execute the computer executable instructions to perform the method as follows:
  • the processor modifies a configuration of a PCIe switch chip according to a current connection relationship between each PCIe device and each PCIe slot ,include:
  • the processor determines whether a current configuration of the PCIe switch chip is connected to the current connection. Relationship matching, including:
  • the identifier of each PCIe slot includes: a bus number and a device number of each PCIe slot, and device information of each PCIe device The device identifier and the vendor identifier of each PCIe device are included.
  • the processor is further configured to:
  • the device is The baseboard management controller BMC or the basic input/output system BIOS of the server.
  • the method and device for configuring a PCIe topology in the embodiment of the present invention when a new application scenario occurs, the user adjusts the PCIe device connected to each PCIe slot on the board as needed, thereby changing the PCIe device and the PCIe insertion.
  • the BMC obtains the identification information of each PCIe slot connected to the board and the device information of the PCIe device connected to each PCIe slot, according to the PCIe insertion.
  • the identification information of the slot and the device information of the PCIe device determine the current connection relationship between the PCIe devices and the PCIe slots.
  • the user adjusts the connection relationship between the PCIe devices and the PCIe slots, resulting in PCIe.
  • the current configuration of the switch chip does not match the current connection relationship, and the BMC modifies the current configuration of the PCIe switch chip to a target configuration that matches the current connection relationship according to the current connection relationship, thereby completing configuration of the PCIe topology. .
  • FIG. 1 is a schematic structural diagram of an X86 server to which embodiments of the present invention are applied;
  • FIG. 2 is a schematic diagram of a configuration of a PCIe switch chip
  • FIG. 3 is a flowchart of a method for configuring a PCIE topology according to an embodiment of the present disclosure
  • FIG. 4 is a flowchart of a method for modifying a configuration of a PCIe switch chip according to Embodiment 2 of the present invention
  • FIG. 5 is a schematic structural diagram of a device for configuring a PCIe topology according to Embodiment 3 of the present invention.
  • FIG. 6 is a schematic structural diagram of a device for configuring a PCIe topology according to Embodiment 4 of the present invention.
  • FIG. 7 is a schematic structural diagram of a device for configuring a PCIe topology according to Embodiment 5 of the present invention.
  • FIG. 1 is a schematic structural diagram of an X86 server according to various embodiments of the present invention.
  • a board (not shown in FIG. 1 ) of the server is provided with two central processing units (Central Processing Units, CPU): CPU1 and CPU2, Baseboard Management Controller (BMC), and PCIe switch chip.
  • CPU Central Processing Unit
  • BMC Baseboard Management Controller
  • PCIe switch chips are used to connect CPUs and PCIe devices.
  • PCIe switch chips include uplink interfaces and downlinks.
  • the interface is connected to the PCIe interface of the CPU, and the downlink interface is connected to the PCIe slot.
  • the PCIe device can be connected to multiple PCIe devices.
  • the PCIe device can be a GPU, a network card, or an SSD.
  • FIG. 1 is only an example.
  • the CPU may also include more CPUs.
  • a plurality of PCIe switch chips may be disposed between the CPU and the PCIe settings, which is not limited in the embodiment of the present invention.
  • the PCIe switch chip needs to have a virtual switch function, that is, one PCIe switch chip can be virtualized into multiple virtual switch chips, and the uplink interface of each virtual switch chip is used to connect one CPU, and each virtual switch chip is downlinked.
  • the interface is connected to the PCIe slot, and the PCIe slot is inserted into the PCIe slot.
  • the uplink interface and the downlink interface of the PCIe switch chip have a unique correspondence.
  • the correspondence between the uplink interface and the downlink interface of the PCIe switch chip is referred to as the configuration of the PCIe switch chip.
  • 2 is a schematic diagram of a configuration of a PCIe switch chip. As shown in FIG.
  • the PCIe switch chip 1 is a switch chip supporting a 96X bandwidth
  • the PCIe switch chip 2 is a switch chip supporting a 24X bandwidth.
  • CPU: CPU1 and CPU2 the board has a total of 6 PCIe slots.
  • the uplink interface of the PCIe switch chip 1 occupies a bandwidth of 32X.
  • the downlink interface of the PCIe switch chip occupies 64X bandwidth.
  • the uplink interface of the PCIe switch chip 2 occupies 8X bandwidth.
  • the downlink interface of the PCIe switch chip occupies the X16 bandwidth.
  • the PCIe switch chip 1 has two uplink interfaces: uplink interface 1 and uplink interface 2, each uplink interface occupies 16X bandwidth, and PCIe switch chip 1 has 5 downlink interfaces, wherein downlink interfaces 1, 2, and 3 respectively occupy The bandwidth of 16X, the downlink interfaces 4 and 5 occupy 8X bandwidth respectively.
  • the uplink interface 1 of the PCIe switch chip 1 is connected to the interfaces 3A, 3B, 3C, and 3C of the CPU 1, and the uplink interface 2 of the PCIe switch chip 1 is connected to the interfaces 3A, 3B, 3C, and 3C of the CPU 2, and the downlink interface 1 of the PCIe switch chip 1 is MEZZ4 connection, PCIE switch chip 1 downlink interface 2 and PCIe slot 1 connection, PCIe switch chip 1 downlink interface 3 and PCIe slot 2 connection, PCIe switch chip 1 downlink interface 4 and PCIe slot 5 connection, PCIe switch chip 1 downlink The interface 5 is connected to the PCIe slot 6.
  • the uplink interface 1 of the PCIe switch chip 1 corresponds to the downlink interfaces 1, 2, and 3, and the uplink interface 2 of the PCIe switch chip 1 corresponds to the downlink interfaces 5 and 6, that is, the PCIe switch chip 1
  • the data received by the uplink interface 1 can only be sent to the downlink interfaces 1, 2, and 3.
  • the data received from the uplink interface 2 of the PCIe switch chip 1 can only be sent to the downlink interfaces 5 and 6.
  • the PCIe switch chip 2 has an uplink interface and two downlink interfaces.
  • the uplink interface of the PCIe switch chip 2 is connected to the interfaces 1A and 1B of the CPU 1, the downlink interface 1 of the PCIe switch chip 2 is connected to the PCIE slot 4, and the PCIe switch chip 2 is connected.
  • the downlink interface 2 is connected to the MEZZ3, and the PCIe switch chip 2 does not have a virtual switching function.
  • CPU1 and CPU2 are connected to the PCIe device through the PCIe switch chip, and the CPU1 and the CPU2 can be directly connected to the PCIe device or the PCIe slot.
  • the interfaces 2C and 2D of the CPU1 are connected to the PCIe slot 3 in FIG.
  • the interfaces 2A and 2B of the CPU 1 are connected to the MEZZ2, the interfaces 2A, 2B, 2C, and 2D of the CPU 2 are connected to the MEZZ1, and the interfaces 1A and 1B of the CPU 2 are connected to the Redundant Arrays of Independent Disks (RAID), and the interfaces of the CPU 1 and the CPU 2 are connected.
  • 0 is mainly used for management information transmission.
  • the hardware connection relationship of all the devices on the board is as follows:
  • the PCIe topology of the board includes the following four hardware connection relationships: (1) the PCIe device connected to the board and the PCIe of the board. a connection relationship of the slot; (2) a connection relationship between the PCIe slot and a downlink interface of the PCIe switch chip; (3) a connection relationship between the PCIe device and a PCIe interface of the CPU; and (4) the PCIe exchange The connection relationship between the uplink interface of the chip and the PCIe interface of the CPU.
  • the PCIe devices connected to the PCIe slots are different in different application scenarios, that is, the first connection relationship is Variable, the other three; the connection relationship is fixed.
  • the user can change the PCIe topology of the board by changing the PCIe device connected to the PCIe slot.
  • a server can only support one application scenario.
  • the user can only purchase one new server, which is costly for the user, and needs to be different for the server manufacturer.
  • the requirements of the application scenario design different boards, which increases the cost of the server.
  • FIG. 3 is a flowchart of a method for configuring a PCIE topology according to an embodiment of the present invention.
  • the method of this embodiment may include the following steps:
  • Step 101 Obtain identification information of each PCIe slot connected to the board of the server, and device information of each PCIe device connected to each PCIe slot, according to the identification information of each PCIe slot and the PCIe.
  • the device information of the device determines the current connection relationship between the PCIe devices and the PCIe slots.
  • the BMC can obtain the identification information of the PCIe slots and the device information of the PCIe devices connected to the PCIe slots in the following two ways: In one manner, the BMC collects the identifiers of the PCIe slots by itself. Information and device information of PCIe devices connected to the respective PCIe slots. In another aspect, the BMC receives the identification information of each PCIe slot sent by the BIOS of the server and the device information of the PCIe device connected to each PCIe slot. After the server is started, the BIOS starts scanning all the PCIe devices connected to the board, and obtains device information of the PCIe devices and identification information of the PCIe slots, and the PCIe slots are The identification information and the device information of the PCIe device are sent to the BMC. Specifically, the BIOS may send the each to the BMC through an Intelligent Platform Management Interface (IPMI) message. Identification information of the PCIe slot and device information of the PCIe device connected to each PCIe slot.
  • IPMI Intelligent Platform Management Interface
  • the identification information of each PCIe slot includes: a bus number and a device number of each PCIe slot.
  • the identifier information of the PCIe device may further include the PCIe.
  • the function number of the slot is automatically allocated according to the connection relationship of the PCIe slots in the PCIe configuration phase.
  • the PCIe protocol specifies that each PCIe slot is allocated during the PCIe configuration process. A unique bus number, device number, and function number are provided to determine the location of each PCIe slot based on the bus number, device number, and function number of each PCIe slot.
  • the device information of each PCIe device includes: a device ID and a vendor ID of each PCIe device, where the device identifier and the vendor identifier of each PCIe device are saved in each PCIe
  • the device identifier and the vendor identifier may uniquely identify the PCIe device
  • the vendor identifier is specified by a Peripheral Component Interconnect Special Interest Group (PCI-SIG), such as The manufacturer ID of Intel is 8086.
  • PCI-SIG Peripheral Component Interconnect Special Interest Group
  • the device identification is defined by the manufacturer itself and is used to distinguish different products.
  • the location of the PCIe slot can be determined by the bus number and device number of the PCIe slot. However, it is not possible to determine which PCIe device is connected to the PCIe slot.
  • the PCIe slot needs to be determined according to the device identifier and vendor ID of the PCIe device. Which PCIe device is specifically connected to obtain the current connection relationship between each PCIe device and each PCIe slot
  • the BMC determines, according to the identifier information of each PCIe slot and the device information of each PCIe device, that the current connection relationship between each PCIe device and each PCIe slot is prior art, and does not do too much here. description.
  • Step 102 Modify the configuration of the PCIe switch chip according to the current connection relationship between each PCIe device and each PCIe slot.
  • Each PCIe device is connected to a plurality of CPUs through the PCIe switch chip, and an uplink interface of the PCIe switch chip is connected to a PCIe interface of the multiple CPUs, and a downlink interface of the PCIe switch chip and the PCIe plug
  • the configuration of the PCIe switch chip is specifically the correspondence between the uplink interface and the downlink interface of the PCIe switch chip.
  • the connection relationship between each PCIe device and each PCIe slot changes when the PCIe device connected to the PCIe slot changes.
  • the board can support multiple application scenarios, and each application scenario corresponds to a PCIe topology.
  • each PCIe topology the PCIe slot and PCIe connected to the board are used.
  • the device has a connection relationship, and each connection relationship corresponds to a configuration of the PCIe switch chip. Therefore, when the connection relationship between the PCIe device and the PCIe slot changes, the configuration of the PCIe switch chip also needs to be changed accordingly. Modifying, by the BMC, the configuration of the PCIe switch chip according to the current connection relationship between the PCIe devices and the PCIe slots, so that the modified configuration of the PCIe switch chip and the PCIe devices and the The current connection relationship of the PCIe slot corresponds.
  • the user adjusts the connection relationship between each PCIe slot connected to the PCIe device on the server board as needed, and after the server is started, the BMC on the server passes.
  • Obtaining identification information of each PCIe slot connected to the board and device information of the PCIe device connected to each PCIe slot, according to the identifier information of each PCIe slot and device information of each PCIe device Determining the current connection relationship between the PCIe devices and the PCIe slots.
  • the current configuration of the PCIe switch chip does not match the current connection relationship because the user adjusts the connection relationship between the PCIe devices and the PCIe slots.
  • the BMC modifies the current configuration of the PCIe switch chip to a target configuration that matches the current connection relationship according to the current connection relationship, thereby completing the configuration of the PCIe topology.
  • FIG. 4 is a flowchart of a method for modifying the configuration of the PCIe switch chip according to the second embodiment of the present invention. As shown in FIG. 4, the method provided in this embodiment may include the following steps:
  • Step 201 Obtain identification information of each PCIe slot connected to the board of the server, and device information of the PCIe device connected to each PCIe slot, according to the identification information of each PCIe slot and the PCIe device. Device information, determining a current connection relationship between each PCIe device and each PCIe slot.
  • Step 202 Obtain a current configuration of the PCIe switch chip.
  • the current configuration of the PCIe switch chip is specifically the correspondence between the uplink interface and the downlink interface of the PCIe switch chip at the current time.
  • the uplink interface of the PCIe switch chip is connected to multiple CPUs, and the downlink interface of the PCIe switch chip is Connected to each PCIe slot.
  • the connection relationship between the uplink interface and the downlink interface of the PCIe switch chip can be changed by changing the configuration of the PCIe switch chip, thereby changing the connection relationship between the PCIe devices and the CPU.
  • the BMC and the PCIe switch chip are connected by an Inter-Integrated Circuit (I 2 C) bus.
  • I 2 C Inter-Integrated Circuit
  • the configuration information of the current configuration of the PCIe switch chip is usually saved in the PCIe.
  • the BMC reads the configuration information of the current configuration of the PCIe switch chip from the register of the PCIe switch chip through the I 2 C bus.
  • Step 203 Determine whether the current configuration of the PCIe switch chip matches the current connection relationship, where multiple configurations of the PCIe switch chip and multiple connection relationships between the PCIe devices and the PCIe slots are performed. One-to-one correspondence.
  • Each PCIe device has multiple connection relationships with the PCIe slots.
  • the PCIe switch chip has multiple configurations, and various configurations of the PCIe switch chip and the PCIe devices and the PCIe plugs are inserted.
  • the various connection relationships of the slots correspond one-to-one.
  • the connection relationship between the PCIe slot and the PCIe device connected to the board and the configuration of the PCIe switch chip may be pre-stored in the memory of the BMC.
  • the BMC determines whether the current configuration of the PCIe switch chip matches the current PCIe topology relationship of the board, specifically:
  • the BMC determines, according to the configuration information of the PCIe switch chip corresponding to the current connection relationship, the configuration of the PCIe switch chip corresponding to the current connection relationship. Then, the BMC determines the PCIe. Whether the current configuration of the switch chip is the same as the current configuration of the PCIe switch chip corresponding to the current connection relationship. If they are the same, it is determined that the current configuration of the PCIe switch chip matches the current connection relationship. If not, the BMC determines that the current configuration of the PCIe switch chip does not match the current connection relationship.
  • HPC-Dual a general-Purpose computation on GPU
  • HPC-Dual the connection between the PCIe slot and the PCIe device is as follows: GPGPU is installed on PCIE slot 1 and PCIE slot 2, and is installed on Mezz2.
  • IB Interconnect structure
  • GPGPU and IB constitute Remote Direct Memory Access (RDMA)
  • RDMA Remote Direct Memory Access
  • Mezz1/3/4 is unlimited, that is, you can install PCIe devices on Mezz1/3/4. If the PCIe device is not installed, the remaining PCIe slots have no space to be installed.
  • connection between the PCIe slot and the PCIe device corresponds to the PCIe topology 2.
  • the connection between the PCIe slot and the PCIe device is as follows: PCIe slot
  • the GPU is installed on the 1/2
  • the Mezz1/3/4 is unlimited
  • the Mess2 is not installed
  • the remaining PCIe slots have no space to be installed.
  • the connection between the PCIe slot and the PCIe device here corresponds to the PCIe topology 1.
  • Mezz1/3/4 is also a PCIe slot.
  • the Mezz slot is usually a slot set by a specific server manufacturer. It is not as versatile as a PCIe slot. All PCIe devices can be used with PCIe slots. Connected, and the Mezz slot can only be connected to PCIe devices produced by the specific service provider.
  • connection relationships between the PCIe slot and the PCIe device and the configuration of the PCIe switch chip corresponding to each connection relationship are pre-stored in the BMC.
  • the BMC determines the PCIe switch chip configuration corresponding to the current connection relationship according to the correspondence between the configuration of the plurality of the PCIe switch chips and the connection relationship between the PCIe slot and the PCIe device connected to the board. Specifically, the BMC can compare the current connection relationship with each of the pre-stored multiple correspondences to determine the current connection of the board. And then, according to the correspondence, find a configuration of the PCIe switch chip corresponding to the current connection relationship.
  • the BMC compares and analyzes the connection relationship between multiple PCIe slots and PCIe devices in advance, finds the difference between various connection relationships, and then, according to the difference between the various connection relationships,
  • the current connection relationship is found in a plurality of pre-saved connection relationships. For example, in the PCIe topology 2, an IB card is inserted in the MESS2 in the current connection relationship between the PCIe slot and the PCIe device, and the current PCIe slot and the current PCIe device in the PCIe topology 1 In the connection relationship, the IB card is not inserted in the MESS2, then the BMC can use the card type at the MEZZ2 as a difference point.
  • the card in the MEZZ2 is an IB card. If the card in the MEZZ2 is an IB card, the BMC determines that the current connection relationship between the PCIe slot and the PCIe device is the connection relationship of the PCIe topology 2, if MEZZ2 The BMC is not an IB card, and the BMC determines that the current connection of the PCIe slot and the PCIe device is a connection relationship corresponding to the PCIe topology 1. After the current connection relationship is found from the multiple correspondences, the configuration of the PCIe switch chip corresponding to the current connection relationship is found according to the correspondence.
  • Step 204 If the current configuration of the PCIe switch chip does not match the current connection relationship, modify the current configuration of the PCIe switch chip stored in the EPROM of the PCIe switch chip, and the modified PCIe switch chip. The configuration matches the current connection relationship.
  • the PCIe switch chip has a plurality of registers, and address information and configuration information of each register are stored in an Erasable Programmable Read Only Memory (EPROM) of the PCIe switch chip.
  • EPROM Erasable Programmable Read Only Memory
  • the BMC may modify the current configuration configuration information of the PCIe switch chip of the register in the EPROM of the PCIe switch chip to the PCIe switch chip that matches the current connection relationship. Configuration information for the configuration.
  • the BMC modifies the EPROM, the BMC notifies the BIOS to rewrite the boot server.
  • each register of the PCIe switch chip reads the modified configuration from the EPROM, and then, The current configuration is modified to the modified configuration, and the modified configuration takes effect.
  • the method of the first embodiment and the second embodiment may also be performed by the BIOS of the server.
  • the difference is that when the BIOS is executed, the PCIe devices connected to the board and the PCIe slots are connected.
  • the correspondence with the configuration of the PCIe switch chip is stored in the memory of the server.
  • FIG. 5 is a schematic structural diagram of a device for configuring a PCIe topology according to Embodiment 3 of the present invention.
  • the device for configuring a PCIe topology may be a baseboard management controller BMC on the server or a basic input/output system BIOS of the server.
  • the apparatus for configuring a PCIe topology provided by this embodiment includes: an obtaining module 11, a determining module 12, and a modifying module 13.
  • the obtaining module 11 is configured to obtain identification information of each PCIe slot connected to the board of the server and device information of the PCIe device connected to each PCIe slot;
  • a determining module 12 configured to determine, according to the identifier information of each PCIe slot and the device information of each PCIe device, a current connection relationship between each PCIe device and each PCIe slot;
  • the modification module 13 is configured to modify the configuration of the PCIe switch chip according to the current connection relationship between each PCIe device and each PCIe slot.
  • the identifier of each PCIe slot includes: a bus number and a device number of each PCIe slot
  • the device information of each PCIe device includes: a device identifier and a vendor identifier of each PCIe device.
  • the device for configuring the PCIe topology provided in this embodiment may be used to implement the technical solution provided by the method embodiment 1.
  • the implementation principle and technical effects are similar, and details are not described herein again.
  • FIG. 6 is a schematic structural diagram of a device for configuring a PCIe topology according to Embodiment 4 of the present invention.
  • the device in this embodiment is based on the device structure shown in FIG. 5, and further, the modification module is 13 may include: an obtaining unit 131, a determining unit 132, and a modifying unit 133.
  • the obtaining unit 131 is configured to acquire a current configuration of the PCIe switch chip.
  • the determining unit 132 is configured to determine whether a current configuration of the PCIe switch chip matches the current connection relationship, where multiple configurations of the PCIe switch chip and the PCIe device and the PCIe slot are One-to-one correspondence of various connection relationships;
  • the modifying unit 133 is configured to modify the PCIe exchange stored in the erasable programmable read only memory EPROM of the PCIe switch chip when the current configuration of the PCIe switch chip does not match the current connection relationship.
  • the current configuration of the chip, the modified configuration of the PCIe switch chip matches the current connection relationship.
  • the obtaining unit 131 is specifically configured to: read the currently configured configuration information from a register of the PCIe switch chip.
  • the determining unit 132 is specifically configured to: determine, according to the configuration information of the PCIe switch chip corresponding to the current connection relationship, the configuration of the PCIe switch chip corresponding to the current connection relationship; and determine the PCIe switch.
  • the current configuration of the chip is the same as the configuration of the PCIe switch chip corresponding to the current connection relationship; if the same, determining that the current configuration of the PCIe switch chip matches the current connection relationship; if not, determining The current configuration of the PCIe switch chip does not match the current connection relationship.
  • the method may further include: a notification module 14 configured to notify the basic input/output system BIOS of the server to restart the server.
  • the device in this embodiment may be used to implement the technical solution provided in the second embodiment of the method.
  • the specific implementation manner and technical effects are similar, and details are not described herein again.
  • FIG. 7 is a schematic structural diagram of a device for configuring a PCIe topology according to Embodiment 5 of the present invention.
  • the device is a baseboard management controller BMC on the server or a basic input/output system BIOS of the server.
  • the apparatus 200 of the present embodiment includes a processor 21, a memory 22, a communication interface 23, and a system bus 24, and the memory 22 and the communication interface 23 pass through the system bus 24 and the processor. 21, connecting and completing communication with each other; the memory 22 for storing computer executable instructions 221; the communication interface 23 for communicating with the server or other network device, the processor 21, for operating
  • the computer executable instructions 221 are executed to perform the methods described below:
  • the processor 21 modifies the configuration of the PCIe switch chip according to the current connection relationship between the PCIe device and the PCIe slot, and specifically includes: acquiring a current configuration of the PCIe switch chip; determining a current state of the PCIe switch chip. Whether the configuration is matched with the current connection relationship, wherein the plurality of configurations of the PCIe switch chip and the plurality of connection relationships between the PCIe devices and the PCIe slots are in one-to-one correspondence; if the PCIe switch chip If the current configuration does not match the current connection relationship, modify the current configuration of the PCIe switch chip stored in the erasable programmable read only memory EPROM of the PCIe switch chip, and modify the configuration of the PCIe switch chip. Matches the current connection relationship.
  • Determining, by the processor 21, whether the current configuration of the PCIe switch chip matches the current connection relationship specifically: determining, according to configuration information of the PCIe switch chip corresponding to the current connection relationship saved in advance a configuration of the PCIe switch chip corresponding to the connection relationship; determining whether the current configuration of the PCIe switch chip is the same as the configuration of the PCIe switch chip corresponding to the current connection relationship; if the same, determining the PCIe switch chip The current configuration matches the current connection relationship; if not, it is determined that the current configuration of the PCIe switch chip does not match the current connection relationship.
  • the identifier of each PCIe slot includes: a bus number and a device number of each PCIe slot
  • the device information of each PCIe device includes: a device identifier and a vendor identifier of each PCIe device.
  • processor 21 is further configured to: notify the basic input and output system BIOS of the server to restart the server.
  • the device in this embodiment may be used to implement the technical solutions provided in the first embodiment and the second embodiment.
  • the specific implementations and technical effects are similar, and details are not described herein again.
  • the aforementioned program can be stored in a computer readable storage medium.
  • the program when executed, performs the steps including the foregoing method embodiments; and the foregoing storage medium includes various media that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

Abstract

本发明实施例提供一种PCIe拓扑的配置方法和装置，包括：获取服务器的单板上连接的各PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息，根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息，确定所述各PCIe设备与所述各PCIe插槽的当前连接关系；根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置。当有新的应用场景出现时，用户只需要调整所述各PCIe设备与所述各PCIe插槽的连接关系，所述装置会根据调整后的连接关系自动修改所述PCIe交换芯片的配置，以完成PCIe拓扑的配置，而不需要增加一块单板，从而降低了服务器的成本。另外，通过改变PCIe拓扑使得一块单板能够支持多种应用场景。

Description

PCIe拓扑的配置方法和装置
本申请要求于2014年09月10日提交中国专利局、申请号为201410457793.X、发明名称为“PCIe拓扑的配置方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及数据通信技技术，尤其涉及一种PCIe拓扑的配置方法和装置。
背景技术
服务器的可扩展性是服务器的一个重要性能，服务器的可扩展性是指服务器的硬件配置可以根据需要灵活配置，如内存、适配器、固态硬盘(Solid State Disk，简称SSD)、处理器等。服务器的可扩展性可以通过增加单板上的快速外围部件互连标准(Peripheral Component Interconnect express，简称PCIe)插槽实现，每个PCIe插槽上可以插一张PCIe卡，PCIe卡上可以连接多个不同的PCIe设备来满足不同用户和不同应用场景的要求，例如，在PCIe插槽插上图形处理器(Graphic Processing Unit，简称GPU)，可以扩展服务器的视频处理能力，在PCIe插槽插SSD，可以扩展服务器的存储能力。在设计一款可扩展型服务器时，在成本和服务器的结构空间允许的情况下，服务器的PCIE插槽越多越好。但是，单板上的CPU中央处理器(Central Processing Unit，简称CPU)的数量有限，随着PCIe插槽增多，PCIe设备与有限的CPU连接会带来PCIE拓扑的设计问题，PCIe拓扑是指PCIe设备与单板上的CPU的连接关系，在不同的应用场景下，PCIe设备会被连接到CPU的不同接口上，从而形成不同的PCIe拓扑，不同应用场景对应的PCIe拓扑不同，通常希望单板能支持的应用场景越多越好。
现有技术中，在设计服务器时，首先，根据应用场景进行分析，在服务器的硬件设计时让单板尽量满足多的应用场景，当一块单板的PCIe拓扑无法满足所有应用场景要求时，设计两块单板来支持所有的应用场景，当两块单板也不能支持所有的应用场景要求时，就需要设计三块单板。
因为应用场景一般会相互冲突，硬件设计规划的PCIE拓扑很难满足所有应用场景的要求，因此，需要增加多余的单板来满足不同应用场景要求，导致服务器的成本增加，另外，PCIe拓扑一旦设计好，后续将无法更改，当出现新的应用场景时，需要重新设计单板，也会增加服务器成本。
发明内容
本发明实施例提供一种PCIe拓扑的配置方法和装置，一块单板具有多种PCie拓扑关系，当有新的应用场景时，通过改变PCIe拓扑关系实现相应的功能，不需要增加单板，从而降低服务器成本。
本发明第一方面提供一种PCIe拓扑的配置方法，包括：
获取服务器的单板上连接的各快速外围部件互连标准PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息，根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息，确定所述各PCIe设备与所述各PCIe插槽的当前连接关系；
根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置。
结合本发明第一方面，在本发明第一方面的第一种可能的实现方式中，所述根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置，包括：
获取所述PCIe交换芯片的当前配置；
确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，其中，所述PCIe交换芯片的多种配置与所述各PCIe设备与所述各PCIe插槽的多种连接关系一一对应；
若所述PCIe交换芯片的当前配置与所述当前连接关系不匹配，则修改所述PCIe交换芯片的可擦除可编程只读存储器EPROM中存储的所述PCIe交换芯片的当前配置，修改后的所述PCIe交换芯片的配置与所述当前连接关系匹配。
结合本发明第一方面的第一种可能的实现方式，在本发明第一方面的第二种可能的实现方式中，所述确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，包括：
根据预先保存的所述当前连接关系对应的所述PCIe交换芯片的配置信息，确定所述当前连接关系对应的所述PCIe交换芯片的配置；
判断所述PCIe交换芯片的当前配置，是否与所述当前连接关系对应的所述PCIe交换芯片的配置相同；
如果相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系匹配；
如果不相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系不匹配。
结合本发明第一方面以及本发明第一方面的第一种和第二种可能的实现方式，在本发明第一方面的第三种可能的实现方式中，所述各PCIe插槽的标识包括：所述各PCIe插槽的总线号和设备号，所述各PCIe设备的设备信息包括：所述各PCIe设备的设备标识和厂商标识。
结合本发明第一方面的第三种可能的实现方式，在本发明第一方面的第四种可能的实现方式中，所述根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置之后，所述方法还包括：
通知所述服务器的基本输入输出系统BIOS重新启动所述服务器。
结合本发明第一方面以及本发明第一方面的第一种至和第二种可能的实现方式，在本发明第一方面的第五种可能的实现方式中，所述方法的执行主体为所述服务器上的基板管理控制器BMC或所述服务器的基本输入输出系统BIOS。
本发明第二方面提供一种PCIe拓扑的配置装置，包括：
获取模块，用于获取服务器的单板上连接的各快速外围部件互连标准PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息；
确定模块，用于根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息，确定所述各PCIe设备与所述各PCIe插槽的当前连接关系；
修改模块，用于根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置。
结合本发明第二方面，在本发明第二方面的第一种可能的实现方式中，所述修改模块包括：
获取单元，用于获取所述PCIe交换芯片的当前配置；
确定单元，用于确定所述PCIe交换芯片的当前配置是否与所述当前连 接关系匹配，其中，所述PCIe交换芯片的多种配置与所述各PCIe设备与所述各PCIe插槽的多种连接关系一一对应；
修改单元，用于当所述PCIe交换芯片的当前配置与所述当前连接关系不匹配时，修改所述PCIe交换芯片的可擦除可编程只读存储器EPROM中存储的所述PCIe交换芯片的当前配置，修改后的所述PCIe交换芯片的配置与所述当前连接关系匹配。
结合本发明第二方面的第一种可能的实现方式，在本发明第二方面的第二种可能的实现方式中，所述确定单元具体用于：
根据预先保存的所述当前连接关系对应的所述PCIe交换芯片的配置信息，确定所述当前连接关系对应的所述PCIe交换芯片的配置；
判断所述PCIe交换芯片的当前配置，是否与所述当前连接关系对应的所述PCIe交换芯片的配置相同；
如果相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系匹配；
如果不相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系不匹配。
结合本发明第二方面以及本发明第二方面的第一种和第二种可能的实现方式，在本发明第二方面的第三种可能的实现方式中，所述各PCIe插槽的标识包括：所述各PCIe插槽的总线号和设备号，所述各PCIe设备的设备信息包括：所述各PCIe设备的设备标识和厂商标识。
结合本发明第二方面的第三种可能的实现方式，在本发明第二方面的第四种可能的实现方式中，还包括：
通知模块，用于通知所述服务器的基本输入输出系统BIOS重新启动所述服务器。
结合本发明第二方面以及本发明第二方面的第一种和第二种可能的实现方式，在本发明第二方面的第五种可能的实现方式中，所述装置为所述服务器上的基板管理控制器BMC或所述服务器的基本输入输出系统BIOS。
本发明第三方面提供一种PCIe拓扑的配置装置，包括：处理器、存储器、通信接口和系统总线，所述存储器和所述通信接口通过所述系统总线与所述处理器连接并完成相互间的通信；
所述存储器，用于存储计算机可执行指令；
所述处理器，用于运行所述计算机可执行指令，以执行如下所述方法：
获取服务器的单板上连接的各快速外围部件互连标准PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息，根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息，确定所述各PCIe设备与所述各PCIe插槽的当前连接关系；
根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置。
结合本发明第三方面，在本发明第三方面的第一种可能的实现方式中，所述处理器根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置，包括：
获取所述PCIe交换芯片的当前配置；
确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，其中，所述PCIe交换芯片的多种配置与所述各PCIe设备与所述各PCIe插槽的多种连接关系一一对应；
若所述PCIe交换芯片的当前配置与所述当前连接关系不匹配，则修改所述PCIe交换芯片的可擦除可编程只读存储器EPROM中存储的所述PCIe交换芯片的当前配置，修改后的所述PCIe交换芯片的配置与所述当前连接关系匹配。
结合本发明第三方面的第一种可能的实现方式，在本发明第三方面的第二种可能的实现方式中，所述处理器确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，包括：
根据预先保存的所述当前连接关系对应的所述PCIe交换芯片的配置信息，确定所述当前连接关系对应的所述PCIe交换芯片的配置；
判断所述PCIe交换芯片的当前配置，是否与所述当前连接关系对应的所述PCIe交换芯片的配置相同；
如果相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系匹配；
如果不相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系不匹配。
结合本发明第三方面以及本发明第三方面的第一种和第二种可能的实 现方式，在本发明第三方面的第三种可能的实现方式中，所述各PCIe插槽的标识包括：所述各PCIe插槽的总线号和设备号，所述各PCIe设备的设备信息包括：所述各PCIe设备的设备标识和厂商标识。
结合本发明第三方面的第三种可能的实现方式，在本发明第三方面的第四种可能的实现方式中，所述处理器还用于：
通知所述服务器的基本输入输出系统BIOS重新启动所述服务器。
结合本发明第三方面以及本发明第三方面的第一种和第二种可能的实现方式，在本发明第三方面的第五种可能的实现方式中，所述装置为所述服务器上的基板管理控制器BMC或所述服务器的基本输入输出系统BIOS。
本发明实施例PCIe拓扑的配置方法和装置，当一种新应用场景出现时，用户根据需要调整单板上的各PCIe插槽所连接的PCIe设备，从而改变各PCIe设备与所述各PCIe插槽的连接关系，所述BMC在服务器启动后，获取所述单板上连接的各PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息，根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息确定所述各PCIe设备与所述各PCIe插槽的当前连接关系，由于用户调整了各PCIe设备与所述各PCIe插槽连接关系，导致PCIe交换芯片的当前配置与所述当前连接关系不匹配，所述BMC根据所述当前连接关系修改所述PCIe交换芯片的当前配置为与所述当前连接关系匹配的目标配置，从而完成PCIe拓扑的配置。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明各实施例适用的一种X86服务器的结构示意图；
图2为PCIe交换芯片的一种配置的示意图；
图3为本发明实施例提供的一种PCIE拓扑的配置方法的流程图；
图4为本发明实施例二提供的修改PCIe交换芯片的配置的方法的流程图；
图5为本发明实施例三提供的一种PCIe拓扑的配置装置的结构示意图；
图6为本发明实施例四提供的一种PCIe拓扑的配置装置的结构示意图；
图7为本发明实施例五提供的一种PCIe拓扑的配置装置的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例的方法可以应用在各种服务器中，例如X86服务器、高级精简指令集机器(Advanced RISC Machine，简称ARM)服务器、性能优化增强的RISC(Performance Optimized With Enhanced RISC，简称POWER)服务器。图1为本发明各实施例适用的一种X86服务器的结构示意图，如图1所示，该服务器的单板(图1中未示出)上设置有两个中央处理单元(Central Processing Unit，简称CPU)：CPU1和CPU2、基板控制器(Baseboard Management Controller，简称BMC)、PCIe交换芯片，BMC用于管理单板，PCIe交换芯片用于连接CPU和PCIe设备，PCIe交换芯片包括上行接口和下行接口，上行接口用于和CPU的PCIe接口连接，下行接口与PCIe插槽连接，PCIE插槽上可以连接多个PCIe设备，PCIe设备具体可以为GPU、网卡、SSD等。图1只是举例说明，服务器中还可以包括更多的CPU，CPU和PCIe设置之间也可以设置有多个PCIe交换芯片，本发明实施例并不对此进行限制。
本发明实施例中，PCIe交换芯片需要具有虚拟交换功能，即一个PCIe交换芯片可以虚拟为多个虚拟交换芯片，每个虚拟交换芯片的上行接口用于连接一个CPU，每个虚拟交换芯片的下行接口和PCIe插槽连接，PCIe插槽上插有PCIe设备。在将PCIe交换芯片虚拟为多个虚拟交换芯片后， PCIe交换芯片的上行接口和下行接口具有唯一的对应关系，将PCIe交换芯片的上行接口和下行接口的对应关系称为PCIe交换芯片的配置。图2为PCIe交换芯片的一种配置的示意图，如图2所示，PCIe交换芯片1为一个支持96X带宽的交换芯片，PCIe交换芯片2为一个支持24X带宽的交换芯片，单板上有两个CPU：CPU1和CPU2，单板共有6个PCIe插槽。PCIe交换芯片1的上行接口共占用32X的带宽，PCIe交换芯片的下行接口共占用64X的带宽，PCIe交换芯片2的上行接口共占用8X的带宽，PCIe交换芯片的下行接口共占用X16的带宽。图2中PCIe交换芯片1共有两个上行接口：上行接口1和上行接口2，每个上行接口占用16X的带宽，PCIe交换芯片1共有5个下行接口，其中下行接口1、2、3分别占用16X的带宽，下行接口4、5分别占用8X的带宽。PCIe交换芯片1的上行接口1与CPU1的接口3A、3B、3C、3C连接，PCIe交换芯片1的上行接口2与CPU2的接口3A、3B、3C、3C连接，PCIe交换芯片1下行接口1与MEZZ4连接，PCIE交换芯片1下行接口2与PCIe插槽1连接，PCIe交换芯片1下行接口3与PCIe插槽2连接，PCIe交换芯片1下行接口4与PCIe插槽5连接，PCIe交换芯片1下行接口5与PCIe插槽6连接，PCIe交换芯片1的上行接口1分别对应下行接口1、2、3，PCIe交换芯片1的上行接口2对应下行接口5、6，也就是说从PCIe交换芯片1的上行接口1接收到的数据只能发送给下行接口1、2、3，从PCIe交换芯片1的上行接口2接收到的数据只能发送给下行接口5、6。PCIe交换芯片2具有一个上行接口和两个下行接口，PCIe交换芯片2的上行接口与CPU1的接口1A和1B连接，PCIe交换芯片2的下行接口1与PCIE插槽4连接，PCIe交换芯片2的下行接口2与MEZZ3连接，PCIe交换芯片2不具有虚拟交换功能。图2中，CPU1和CPU2除了通过PCIe交换芯片与PCIE设备连接外，CPU1和CPU2也可以直接与PCIe设备或PCIe插槽连接，如图2中CPU1的接口2C和2D与PCIe插槽3连接，CPU1的接口2A和2B与MEZZ2连接，CPU2的接口2A、2B、2C、2D与MEZZ1连接，CPU2的接口1A和1B与磁盘阵列(Redundant Arrays of independent Disks，简称RAID)连接，CPU1和CPU2的接口0主要用于管理信息的传输。
现有技术中，一台服务器的单板设计好后，PCIe交换芯片在配置完成后将被固定，因此，所述单板的PCIe拓扑固定不变。所述单板的PCIe拓 扑指所述单板上的所有设备的硬件连接关系，所述单板的PCIe拓扑具体包括以下四种硬件连接关系：(1)所述单板上连接的PCIe设备与所述单板的PCIe插槽的连接关系；(2)所述PCIe插槽与所述PCIe交换芯片的下行接口的连接关系；(3)所述PCIe设备与CPU的PCIe接口的连接关系；(4)所述PCIe交换芯片的上行接口与所述CPU的PCIe接口的连接关系。由于所述各PCIe插槽上连接的PCIe设备是可拔插的，因此，在不同应用场景下，所述各PCIe插槽上连接的PCIe设备是不同的，也就是说第一种连接关系是可变的，其他三种；连接关系时固定不变的。当用户有新的业务需求时，用户可以通过改变PCIe插槽上连接的PCIe设备改变所述单板的PCIe拓扑。现有技术中，通常一台服务器只能支持一种应用场景，当用户有新的业务需求时，用户只能购买一台新的服务器，对用户来说成本高，对于服务器厂商来说需要根据不同的应用场景的需求设计不同的单板，增加了服务器的成本。
针对现有技术的问题，本发明实施例提供一种PCIe拓扑的配置方法，图3为本发明实施例提供的一种PCIE拓扑的配置方法的流程图，本实施例中以BMC为执行主体为例进行说明，如图3所示，本实施例的方法可以包括以下步骤：
步骤101、获取服务器的单板上连接的各PCIe插槽的标识信息以及所述各PCIe插槽上连接的各PCIe设备的设备信息，根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息确定所述各PCIe设备与所述各PCIe插槽的当前连接关系。
BMC可以通过以下两种方式获取所述各PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息：一种方式，所述BMC自己收集所述各PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息。另一种方式，所述BMC接收所述服务器的BIOS发送的所述各PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息。所述服务器启动后，所述BIOS开始扫描所述单板上连接的所有PCIe设备，得到所述各PCIe设备的设备信息以及所述各PCIe插槽的标识信息，并将所述各PCIe插槽的标识信息以及所述各PCIe设备的设备信息发送给所述BMC，具体地，所述BIOS可以通过智能平台管理接口(Intelligent Platform Management Interface，简称IPMI)消息向所述BMC发送所述各 PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息。
所述各PCIe插槽的标识信息包括：所述各PCIe插槽的总线号(bus number)和设备号(device number)，可选地，所述PCIe设备的标识信息还可以包括所述各PCIe插槽的功能号(function number),所述标识信息是在PCIe配置阶段根据所述各PCIe插槽的连接关系自动分配的，PCIe协议规定在PCIe配置过程中，每个PCIe插槽都会被分配到一个唯一的总线号、设备号和功能号，以便于根据所述各PCIe插槽的总线号、设备号和功能号确定所述各PCIe插槽的位置。所述各PCIe设备的设备信息包括：所述各PCIe设备的设备标识(device ID)和厂商标识(vendor ID)，所述各PCIe设备的设备标识和所述厂商标识被保存在所述各PCIe设备的配置寄存器中，所述设备标识和所述厂商标识可以唯一标识所述PCIe设备，所述厂商标识由外围部件互连专业组(Peripheral Component Interconnect Special Interest Group，简称PCI-SIG)规定，比如intel公司的厂商标识为8086，设备标识是厂商自己定义的，用于区分不同的产品。通过PCIe插槽的总线号、设备号能够确定PCIe插槽的位置信息，但是并不能确定PCIe插槽上具体连接哪一个PCIe设备，还需要根据PCIe设备的设备标识和厂商标识确定PCIe插槽上具体连接哪个PCIe设备，从而得到所述各PCIe设备与所述各PCIe插槽的当前连接关系。
所述BMC根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息确定所述各PCIe设备与所述各PCIe插槽的当前连接关系为现有技术，此处不做过多描述。
步骤102、根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置。
所述各PCIe设备通过所述PCIe交换芯片与多个CPU连接，所述PCIe交换芯片的上行接口与所述多个CPU的PCIe接口连接，所述PCIe交换芯片的下行接口与所述各PCIe插槽连接，所述PCIe交换芯片的配置具体为所述PCIe交换芯片的上行接口和下行接口的对应关系。当所述PCIe插槽上连接的PCIe设备变化时，所述各PCIe设备与所述各PCIe插槽的连接关系变化。
本实施例中，所述单板可以支持多种应用场景下，每种应用场景对应一种PCIe拓扑，在每种PCIe拓扑中，所述单板上连接的PCIe插槽和PCIe 设备的具有一种连接关系，每种连接关系对应PCIe交换芯片的一种配置。因此，当PCIe设备和PCIe插槽的连接关系变化时，所述PCIe交换芯片的配置也需要相应改变。所述BMC根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改所述PCIe交换芯片的配置，使得修改后的所述PCIe交换芯片的配置与所述各PCIe设备与所述各PCIe插槽的当前连接关系相对应。
本实施例，当一种新应用场景出现时，用户根据需要调整服务器的单板上连接的各PCIe插槽与各PCIe设备的连接关系，在所述服务器启动后，所述服务器上的BMC通过获取所述单板上连接的各PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息，根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息确定所述各PCIe设备与所述各PCIe插槽的当前连接关系，由于用户调整了各PCIe设备与所述各PCIe插槽连接关系，导致PCIe交换芯片的当前配置与所述当前连接关系不匹配，所述BMC根据所述当前连接关系修改所述PCIe交换芯片的当前配置为与所述当前连接关系匹配的目标配置，从而完成PCIe拓扑的配置。
在上述实施例一的基础上，本发明实施例二主要对实施例一中步骤102进行详细说明，图4为本发明实施例二提供的修改PCIe交换芯片的配置的方法的流程图，如图4所示，本实施例提供的方法可以包括以下步骤：
步骤201、获取服务器的单板上连接的各PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息，根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息，确定所述各PCIe设备与所述各PCIe插槽的当前连接关系。
本步骤的具体实现方式可参照实施例一的相关描述，这里不再赘述。
步骤202、获取所述PCIe交换芯片的当前配置。
所述PCIe交换芯片的当前配置具体为所述PCIe交换芯片的上行接口和下行接口在当前时刻的对应关系，所述PCIe交换芯片的上行接口与多个CPU连接，所述PCIe交换芯片的下行接口与所述各PCIe插槽连接。通过改变所述PCIe交换芯片的配置可以改变所述PCIe交换芯片的上行接口和下行接口的连接关系，从而改变所述各PCIe设备与CPU的连接关系。
所述BMC和所述PCIe交换芯片之间通过内置集成电路(Inter－ Integrated Circuit，简称，I2C)总线连接通信，所述PCIe交换芯片的当前配置的配置信息通常情况下保存在所述PCIe交换芯片的寄存器中，所述BMC通过I2C总线从所述PCIe交换芯片的寄存器中读取所述PCIe交换芯片的当前配置的配置信息。
步骤203、确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，其中，所述PCIe交换芯片的多种配置与所述各PCIe设备与所述各PCIe插槽的多种连接关系一一对应。
所述各PCIe设备与所述各PCIe插槽的具有多种连接关系，所述PCIe交换芯片具有多种配置，所述PCIe交换芯片的多种配置与所述各PCIe设备与所述各PCIe插槽的多种连接关系一一对应。所述单板上连接的PCIe插槽和PCIe设备的连接关系，与PCIe交换芯片的配置的对应关系，可以预先保存在所述BMC的存储器中。则所述BMC确定所述PCIe交换芯片的当前配置是否与所述单板的当前PCIe拓扑关系匹配，具体为：
首先，所述BMC根据预先保存的所述当前连接关系对应的所述PCIe交换芯片的配置信息，确定所述当前连接关系对应的所述PCIe交换芯片的配置；然后，所述BMC判断所述PCIe交换芯片的当前配置是否与所述当前连接关系对应的所述PCIe交换芯片的当前配置相同，如果相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系匹配。如果不相同，则所述BMC确定所述PCIe交换芯片的当前配置与所述当前连接关系不匹配。
举例来说，在高性能计算((high performance computing，简称HPC)中通常引入用于通用计算目的的图形处理器(General-Purpose computation on GPU，简称GPGPU)来提高计算性能，以下简称HPC-双GPU场景。仍以图2所示例子为例，在HPC-双GPU场景下，PCIe插槽和PCIe设备的连接关系如下：PCIE插槽1和PCIE插槽2上分别安装有GPGPU，Mezz2上安装有互联结构(Infiniband，简称IB)，GPGPU和IB组成远程直接数据存取(Remote Direct Memory Access，简称RDMA)，Mezz1/3/4无限制，即Mezz1/3/4上可以安装PCIe设备也可以不安装PCIe设备，其余的PCIe插槽没有空间安装，这里的PCIe插槽和PCIe设备的连接关系对应PCIe拓扑2。在桌面云场景下，PCIe插槽和PCIe设备的连接关系如下：PCIe插槽1/2上分别安装有GPU，Mezz1/3/4无限制，Mess2不安装，其余PCIe插槽没有空间安装，这里的PCIe插槽和PCIe设备的连接关系对应PCIe拓扑1。 这里，Mezz1/3/4也为一种PCIe插槽，Mezz插槽通常是特定服务器厂商设置的一种插槽，不像PCIe插槽一样具有通用性，所有的PCIe设备都能与PCIe插槽连接，而Mezz插槽只能与所述特定服务厂商生产的PCIe设备连接。
本实施例中，所述BMC中预先保存PCIe插槽和PCIe设备的各种连接关系，以及每种连接关系对应的PCIe交换芯片的配置。所述BMC根据预先保存的多种所述PCIe交换芯片的配置与所述单板上连接的PCIe插槽和PCIe设备的连接关系的对应关系，确定所述当前连接关系对应的PCIe交换芯片配置时，具体可以通过如下两种方式：一种方式中，所述BMC将所述当前连接关系与预先保存的多种对应关系中的每种连接关系分别进行比较，以确定所述单板的当前连接关系，然后，根据所述对应关系，找到所述当前连接关系对应的PCIe交换芯片的配置。另一种方式中，所述BMC预先对多种PCIe插槽和PCIe设备的连接关系进行比较分析，找到各种连接关系之间的区别点，然后，根据各种连接关系之间的区别点从预先保存的多种连接关系中找到所述当前连接关系。举例来说，在所述PCIe拓扑2中，所述PCIe插槽和PCIe设备的当前连接关系中MESS2中插有IB卡，而所述PCIe拓扑1中，所述PCIe插槽和PCIe设备的当前连接关系中MESS2中不插IB卡，那么所述BMC可以将MEZZ2处的插卡类型作为区别点，所述BMC在从预先保存的多种连接关系中找到所述当前连接关系时，只需要判断MEZZ2中的插卡是不是IB卡，若MEZZ2中的插卡是IB卡，则所述BMC确定所述PCIe插槽和PCIe设备的当前连接关系为所述PCIe拓扑2对应的连接关系，若MEZZ2中的插卡不是IB卡，则所述BMC确定所述PCIe插槽和PCIe设备的当前连接为所述PCIe拓扑1对应的连接关系。在从所述多种对应关系中找到所述当前连接关系后，根据所述对应关系，找到所述当前连接关系对应的PCIe交换芯片的配置。
步骤204、若所述PCIe交换芯片的当前配置与所述当前连接关系不匹配，则修改所述PCIe交换芯片的EPROM中存储的所述PCIe交换芯片的当前配置，修改后的所述PCIe交换芯片的配置与所述当前连接关系匹配。
具体地，所述PCIe交换芯片具有多个寄存器，每个寄存器的地址信息和配置信息都保存在所述PCIe交换芯片的可擦除可编程只读存储器(Erasable Programmable Read Only Memory，简称EPROM)中，在服务器 每次上电后，每个寄存器都会从所述EPROM中读取自己的配置信息，然后，根据读取到的配置信息修改自己的配置。因此，本实施例中，所述BMC可以将所述PCIe交换芯片的EPROM中的寄存器的所述PCIe交换芯片的当前配置的配置信息，修改为与所述当前连接关系匹配的所述PCIe交换芯片的配置的配置信息。在所述BMC修改所述EPROM后，所述BMC通知BIOS重写启动服务器，当所述服务器重新启动后，所述PCIe交换芯片的各寄存器从所述EPROM中读取修改后的配置，然后，将当前配置修改为所述修改后配置，所述修改后的配置生效。
上述实施例一和实施例二的方法，也可以由所述服务器的BIOS执行，区别点在于：当由所述BIOS执行时，所述单板上连接的各PCIe设备和各PCIe插槽连接关系与所述PCIe交换芯片的配置的对应关系保存在所述服务器的存储器中。
图5为本发明实施例三提供的一种PCIe拓扑的配置装置的结构示意图，所述PCIe拓扑的配置装置可以所述服务器上的基板管理控制器BMC或所述服务器的基本输入输出系统BIOS。如图5所示，本实施例提供的PCIe拓扑的配置装置包括：获取模块11、确定模块12和修改模块13。
所述获取模块11，用于获取服务器的单板上连接的各PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息；
确定模块12，用于根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息，确定所述各PCIe设备与所述各PCIe插槽的当前连接关系；
修改模块13，用于根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置。
其中，所述各PCIe插槽的标识包括：所述各PCIe插槽的总线号和设备号，所述各PCIe设备的设备信息包括：所述各PCIe设备的设备标识和厂商标识。
本实施例提供的PCIe拓扑的配置装置，可用于执行方法实施例一提供的技术方案，其实现原理和技术效果类似，这里不再赘述。
图6为本发明实施例四提供的一种PCIe拓扑的配置装置的结构示意图，如图6所示，本实施例的装置在图5所示装置结构的基础上，进一步地，所述修改模块13可以包括：获取单元131、确定单元132和修改单元 133。
其中，所述获取单元131，用于获取所述PCIe交换芯片的当前配置；
所述确定单元132，用于确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，其中，所述PCIe交换芯片的多种配置与所述各PCIe设备与所述各PCIe插槽的多种连接关系一一对应；
所述修改单元133，用于当所述PCIe交换芯片的当前配置与所述当前连接关系不匹配时，修改所述PCIe交换芯片的可擦除可编程只读存储器EPROM中存储的所述PCIe交换芯片的当前配置，修改后的所述PCIe交换芯片的配置与所述当前连接关系匹配。
所述获取单元131具体用于：从所述PCIe交换芯片的寄存器中读取所述当前配置的配置信息。
所述确定单元132具体用于：根据预先保存的所述当前连接关系对应的所述PCIe交换芯片的配置信息，确定所述当前连接关系对应的所述PCIe交换芯片的配置；判断所述PCIe交换芯片的当前配置，是否与所述当前连接关系对应的所述PCIe交换芯片的配置相同；如果相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系匹配；如果不相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系不匹配。
进一步地，还可以包括：通知模块14，用于通知所述服务器的基本输入输出系统BIOS重新启动所述服务器。
本实施例的装置，可用于执行方法实施例二提供的技术方案，具体实现方式和技术效果类似，这里不再赘述。
图7为本发明实施例五提供的一种PCIe拓扑的配置装置的结构示意图，所述装置为所述服务器上的基板管理控制器BMC或所述服务器的基本输入输出系统BIOS。如图7所示，本实施例的装置200包括：处理器21、存储器22、通信接口23和系统总线24，所述存储器22和所述通信接口23通过所述系统总线24与所述处理器21连接并完成相互间的通信；所述存储器22，用于存储计算机可执行指令221；所述通信接口23用于与所述服务器或其他网络设备通信，所述处理器21，用于运行所述计算机可执行指令221，以执行如下所述方法：
获取服务器的单板上连接的各PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息，根据所述各PCIe插槽的标识信息和 所述各PCIe设备的设备信息，确定所述各PCIe设备与所述各PCIe插槽的当前连接关系；
根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置。
所述处理器21根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置，具体包括：获取所述PCIe交换芯片的当前配置；确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，其中，所述PCIe交换芯片的多种配置与所述各PCIe设备与所述各PCIe插槽的多种连接关系一一对应；若所述PCIe交换芯片的当前配置与所述当前连接关系不匹配，则修改所述PCIe交换芯片的可擦除可编程只读存储器EPROM中存储的所述PCIe交换芯片的当前配置，修改后的所述PCIe交换芯片的配置与所述当前连接关系匹配。
所述处理器21确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，具体包括：根据预先保存的所述当前连接关系对应的所述PCIe交换芯片的配置信息，确定所述当前连接关系对应的所述PCIe交换芯片的配置；判断所述PCIe交换芯片的当前配置，是否与所述当前连接关系对应的所述PCIe交换芯片的配置相同；如果相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系匹配；如果不相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系不匹配。
本实施例中，所述各PCIe插槽的标识包括：所述各PCIe插槽的总线号和设备号，所述各PCIe设备的设备信息包括：所述各PCIe设备的设备标识和厂商标识。
进一步地，所述处理器21还用于：通知所述服务器的基本输入输出系统BIOS重新启动所述服务器。
本实施例的装置，可用于执行方法实施例一和实施例二提供的技术方案，具体实现方式和技术效果类似，这里不再赘述。
本领域普通技术人员可以理解：实现上述各方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成。前述的程序可以存储于一计算机可读取存储介质中。该程序在执行时，执行包括上述各方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (18)

  1. 一种PCIe拓扑的配置方法，其特征在于，包括：
    获取服务器的单板上连接的各快速外围部件互连标准PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息，根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息，确定所述各PCIe设备与所述各PCIe插槽的当前连接关系；
    根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置，包括：
    获取所述PCIe交换芯片的当前配置；
    确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，其中，所述PCIe交换芯片的多种配置与所述各PCIe设备与所述各PCIe插槽的多种连接关系一一对应；
    若所述PCIe交换芯片的当前配置与所述当前连接关系不匹配，则修改所述PCIe交换芯片的可擦除可编程只读存储器EPROM中存储的所述PCIe交换芯片的当前配置，修改后的所述PCIe交换芯片的配置与所述当前连接关系匹配。
  3. 根据权利要求2所述的方法，其特征在于，所述确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，包括：
    根据预先保存的所述当前连接关系对应的所述PCIe交换芯片的配置信息，确定所述当前连接关系对应的所述PCIe交换芯片的配置；
    判断所述PCIe交换芯片的当前配置，是否与所述当前连接关系对应的所述PCIe交换芯片的配置相同；
    如果相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系匹配；
    如果不相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系不匹配。
  4. 根据权利要求1-3中任一项所述的方法，其特征在于，所述各PCIe插槽的标识包括：所述各PCIe插槽的总线号和设备号，所述各PCIe设备 的设备信息包括：所述各PCIe设备的设备标识和厂商标识。
  5. 根据权利要求4所述的方法，其特征在于，所述根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置之后，所述方法还包括：
    通知所述服务器的基本输入输出系统BIOS重新启动所述服务器。
  6. 根据权利要求1-3中任一项所述的方法，其特征在于，所述方法是由所述服务器上的基板管理控制器BMC或所述服务器的基本输入输出系统BIOS实现的。
  7. 一种PCIe拓扑的配置装置，其特征在于，包括：
    获取模块，用于获取服务器的单板上连接的各快速外围部件互连标准PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息；
    确定模块，用于根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息，确定所述各PCIe设备与所述各PCIe插槽的当前连接关系；
    修改模块，用于根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置。
  8. 根据权利要求7所述的装置，其特征在于，所述修改模块包括：
    获取单元，用于获取所述PCIe交换芯片的当前配置；
    确定单元，用于确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，其中，所述PCIe交换芯片的多种配置与所述各PCIe设备与所述各PCIe插槽的多种连接关系一一对应；
    修改单元，用于当所述PCIe交换芯片的当前配置与所述当前连接关系不匹配时，修改所述PCIe交换芯片的可擦除可编程只读存储器EPROM中存储的所述PCIe交换芯片的当前配置，修改后的所述PCIe交换芯片的配置与所述当前连接关系匹配。
  9. 根据权利要求8所述的装置，其特征在于，所述确定单元具体用于：
    根据预先保存的所述当前连接关系对应的所述PCIe交换芯片的配置信息，确定所述当前连接关系对应的所述PCIe交换芯片的配置；
    判断所述PCIe交换芯片的当前配置，是否与所述当前连接关系对应的所述PCIe交换芯片的配置相同；
    如果相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系匹配；
    如果不相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系不匹配。
  10. 根据权利要求7-9中任一项所述的装置，其特征在于，所述各PCIe插槽的标识包括：所述各PCIe插槽的总线号和设备号，所述各PCIe设备的设备信息包括：所述各PCIe设备的设备标识和厂商标识。
  11. 根据权利要求10所述的装置，其特征在于，还包括：
    通知模块，用于通知所述服务器的基本输入输出系统BIOS重新启动所述服务器。
  12. 根据权利要求7-9中任一项所述的装置，其特征在于，所述装置为所述服务器上的基板管理控制器BMC或所述服务器的基本输入输出系统BIOS。
  13. 一种PCIe拓扑的配置装置，其特征在于，包括：处理器、存储器、通信接口和系统总线，所述存储器和所述通信接口通过所述系统总线与所述处理器连接并完成相互间的通信；
    所述存储器，用于存储计算机可执行指令；
    所述处理器，用于运行所述计算机可执行指令，以执行如下所述方法：
    获取服务器的单板上连接的各快速外围部件互连标准PCIe插槽的标识信息以及所述各PCIe插槽上连接的PCIe设备的设备信息，根据所述各PCIe插槽的标识信息和所述各PCIe设备的设备信息，确定所述各PCIe设备与所述各PCIe插槽的当前连接关系；
    根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置。
  14. 根据权利要求13所述的装置，其特征在于，所述处理器根据所述各PCIe设备与所述各PCIe插槽的当前连接关系修改PCIe交换芯片的配置，包括：
    获取所述PCIe交换芯片的当前配置；
    确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，其中，所述PCIe交换芯片的多种配置与所述各PCIe设备与所述各PCIe插槽的多种连接关系一一对应；
    若所述PCIe交换芯片的当前配置与所述当前连接关系不匹配，则修改所述PCIe交换芯片的可擦除可编程只读存储器EPROM中存储的所述PCIe 交换芯片的当前配置，修改后的所述PCIe交换芯片的配置与所述当前连接关系匹配。
  15. 根据权利要求14所述的装置，其特征在于，所述处理器确定所述PCIe交换芯片的当前配置是否与所述当前连接关系匹配，包括：
    根据预先保存的所述当前连接关系对应的所述PCIe交换芯片的配置信息，确定所述当前连接关系对应的所述PCIe交换芯片的配置；
    判断所述PCIe交换芯片的当前配置，是否与所述当前连接关系对应的所述PCIe交换芯片的配置相同；
    如果相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系匹配；
    如果不相同，则确定所述PCIe交换芯片的当前配置与所述当前连接关系不匹配。
  16. 根据权利要求13-15中任一项所述的装置，其特征在于，所述各PCIe插槽的标识包括：所述各PCIe插槽的总线号和设备号，所述各PCIe设备的设备信息包括：所述各PCIe设备的设备标识和厂商标识。
  17. 根据权利要求16所述的装置，其特征在于，所述处理器还用于：
    通知所述服务器的基本输入输出系统BIOS重新启动所述服务器。
  18. 根据权利要求13-15中任一项所述的装置，其特征在于，所述装置为所述服务器上的基板管理控制器BMC或所述服务器的基本输入输出系统BIOS。
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