WO2023047229A1 - 半導体装置、記憶装置、及び電子機器 - Google Patents
半導体装置、記憶装置、及び電子機器 Download PDFInfo
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- WO2023047229A1 WO2023047229A1 PCT/IB2022/058440 IB2022058440W WO2023047229A1 WO 2023047229 A1 WO2023047229 A1 WO 2023047229A1 IB 2022058440 W IB2022058440 W IB 2022058440W WO 2023047229 A1 WO2023047229 A1 WO 2023047229A1
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- conductor
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Images
Classifications
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- H10N50/10—Magnetoresistive devices
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- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/82—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of the magnetic field applied to the device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/80—Constructional details
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- One embodiment of the present invention relates to semiconductor devices, memory devices, and electronic devices.
- one aspect of the present invention is not limited to the above technical field.
- TECHNICAL FIELD The technical field of the invention disclosed in this specification and the like relates to a product, an operation method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition of matter. Therefore, the technical fields of one embodiment of the present invention disclosed in this specification more specifically include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, and sensors. , processors, electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for testing them.
- the access time (delay time or latency) of SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) is about several ns to several tens of ns. It is used as memory or main memory.
- SRAM or DRAM is volatile memory, power consumption may be high while data is held. Therefore, storage devices used as cache memories or main memories of computers are required to have large storage capacity and low power consumption.
- An object of one embodiment of the present invention is to provide a memory device with low power consumption.
- an object of one embodiment of the present invention is to provide a storage device with a large storage capacity.
- an object of one embodiment of the present invention is to provide a novel storage device or the like.
- an object of one embodiment of the present invention is to provide an electronic device including the memory device.
- the problem of one embodiment of the present invention is not limited to the problems listed above.
- the issues listed above do not preclude the existence of other issues.
- Still other issues are issues not mentioned in this section, which will be described in the following description.
- Problems not mentioned in this section can be derived from the descriptions in the specification, drawings, or the like by those skilled in the art, and can be appropriately extracted from these descriptions.
- one embodiment of the present invention is to solve at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems.
- One embodiment of the present invention is a semiconductor device including a first conductor, a second conductor, a third conductor, a first transistor, a second transistor, and a memory element.
- a second conductor overlying the first conductor; a memory element overlying the second conductor; a first transistor and a second transistor overlying the memory element;
- a conductor overlies the first transistor and the second transistor.
- the third conductor is located in a region overlapping the first conductor.
- each of the first transistor and the second transistor includes a metal oxide in a channel formation region.
- the memory element may include any one of a resistance change element, a ferroelectric capacitor, an FTJ element, and a phase change memory.
- One embodiment of the present invention is a semiconductor device including a first conductor, a second conductor, a third conductor, a first transistor, a second transistor, and a memory element.
- the memory element has a first magnetic layer, a second magnetic layer, and an insulator.
- the second conductor is positioned above the first conductor
- the first magnetic layer is positioned above the second conductor
- the insulator is positioned above the first magnetic layer
- the second magnetic layer is located above the insulator.
- the first transistor and the second transistor are positioned above the second magnetic layer
- the third conductor is positioned above the first transistor and the second transistor.
- the third conductor is located in a region overlapping the first conductor.
- the first conductor is electrically connected to the second conductor
- the second conductor is electrically connected to the first magnetic layer and the first terminal of the first transistor
- the second magnetic layer is , is electrically connected to the first terminal of the second transistor
- the second terminal of the first transistor is electrically connected to the second terminal of the second transistor and the third conductor.
- each of the first transistor and the second transistor includes a metal oxide in a channel formation region.
- the memory element may function as an MTJ element.
- the first magnetic layer functions as a free layer
- the second magnetic layer functions as a fixed layer
- the insulator functions as a tunnel insulator.
- the second conductor may have a metal material that causes a spin Hall effect when current flows.
- a first conductor, a second conductor, a third conductor, a first transistor, a second transistor, and a memory element which are different from the structure in (3) above
- the memory element has a first magnetic layer, a second magnetic layer, and an insulator.
- a first transistor and a second transistor are located above the third conductor, and a second magnetic layer is located above the first transistor and the second transistor.
- the insulator is positioned above the second magnetic layer, the first magnetic layer is positioned above the insulator, the second conductor is positioned above the first magnetic layer, and the first conductor comprises: Located above the second conductor.
- the first conductor is located in a region overlapping the third conductor.
- the first conductor is electrically connected to the second conductor
- the second conductor is electrically connected to the first magnetic layer and the first terminal of the first transistor
- the second magnetic layer is , is electrically connected to the first terminal of the second transistor
- the second terminal of the first transistor is electrically connected to the second terminal of the second transistor and the third conductor.
- each of the first transistor and the second transistor includes a metal oxide in a channel formation region.
- the memory element may function as an MTJ element.
- the first magnetic layer functions as a free layer
- the second magnetic layer functions as a fixed layer
- the insulator functions as a tunnel insulator.
- the second conductor may have a metal material that causes a spin Hall effect when current flows.
- one embodiment of the present invention is a memory device including the semiconductor device according to any one of (1) to (6) and a layer including a peripheral circuit. Note that the layer is located below the semiconductor device.
- the peripheral circuit has a function of writing data to and reading data from the semiconductor device.
- one embodiment of the present invention is an electronic device including the storage device of (7) and a housing.
- a memory device with low power consumption can be provided.
- a storage device with a large storage capacity can be provided.
- a novel storage device or the like can be provided.
- an electronic device including the above memory device can be provided.
- FIG. 1A is a schematic plan view showing a configuration example of a memory cell
- FIG. 1B is a schematic cross-sectional view showing a configuration example of the memory cell
- 2A and 2B are schematic cross-sectional views showing configuration examples of transistors
- 3A and 3B are schematic cross-sectional views showing configuration examples of transistors
- 4A to 4D are circuit diagrams showing configuration examples of memory cells.
- FIG. 5 is a schematic diagram illustrating a configuration example of a memory element included in a memory cell.
- FIG. 6A is a schematic plan view showing a configuration example of a memory cell
- FIG. 6B is a schematic cross-sectional view showing a configuration example of the memory cell.
- FIG. 1A is a schematic plan view showing a configuration example of a memory cell
- FIG. 1B is a schematic cross-sectional view showing a configuration example of the memory cell.
- FIG. 7 is a schematic cross-sectional view showing a configuration example of a memory cell.
- FIG. 8 is a schematic cross-sectional view showing a configuration example of a memory cell.
- FIG. 9 is a block diagram showing a connection configuration of a plurality of memory cells.
- FIG. 10A is a schematic plan view showing a configuration example of a memory cell, and FIG. 10B is a schematic cross-sectional view showing a configuration example of the memory cell.
- FIG. 11A is a schematic plan view showing a configuration example of a memory cell, and FIG. 11B is a schematic cross-sectional view showing a configuration example of the memory cell.
- FIG. 12A is a schematic plan view showing a configuration example of a memory cell, and FIG.
- FIG. 12B is a schematic cross-sectional view showing a configuration example of the memory cell.
- FIG. 13 is a perspective view schematically showing the configuration of a memory cell.
- FIG. 14 is a perspective view schematically showing the configuration of a memory cell.
- FIG. 15A is a schematic plan view showing a configuration example of a memory cell
- FIG. 15B is a schematic cross-sectional view showing a configuration example of the memory cell.
- 16A and 16B are schematic cross-sectional views showing configuration examples of memory cells.
- FIG. 17 is a block diagram showing a configuration example of a storage device.
- 18A and 18B are block diagrams showing configuration examples of storage devices.
- FIG. 19 is a schematic cross-sectional view showing a configuration example of a storage device.
- FIG. 19 is a schematic cross-sectional view showing a configuration example of a storage device.
- FIG. 20 is a schematic cross-sectional view showing a configuration example of a transistor.
- FIG. 21 is a schematic cross-sectional view showing a configuration example of a storage device.
- FIG. 22 is a block diagram showing a configuration example of a storage device.
- 23A is a perspective view showing an example of a semiconductor wafer
- FIG. 23B is a perspective view showing an example of a chip
- FIGS. 23C and 23D are perspective views showing an example of an electronic component.
- FIG. 24 is a block diagram explaining the CPU.
- 25A to 25J are perspective views or schematic diagrams illustrating examples of electronic devices.
- 26A to 26D are diagrams illustrating configuration examples of electronic devices.
- 27A to 27E are perspective views or schematic diagrams illustrating examples of electronic devices.
- a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide is sometimes called an oxide semiconductor. That is, when a metal oxide can form a channel-forming region of a transistor having one or more selected from an amplifying action, a rectifying action, and a switching action, the metal oxide is called a metal oxide semiconductor. can be called In the case of describing an OS transistor, it can also be referred to as a transistor including a metal oxide or an oxide semiconductor.
- nitrogen-containing metal oxides may also be collectively referred to as metal oxides.
- a metal oxide containing nitrogen may also be referred to as a metal oxynitride.
- the content (or part of the content) described in one embodiment may be combined with another content (or part of the content) described in that embodiment, or one or a plurality of other implementations. can be applied, combined, or replaced with at least one of the contents described in the form of (may be part of the contents).
- figure (may be part of) described in one embodiment refers to another part of that figure, another figure (may be part) described in that embodiment, and one or more other More drawings can be formed by combining at least one of the drawings (or part of them) described in the embodiments.
- plan views may be used to describe the configuration according to each embodiment.
- a plan view is, for example, a diagram showing a state of a plane (cut end) obtained by cutting the configuration in the horizontal direction.
- Hidden lines for example, dashed lines
- the term "plan view” can be replaced with the term "projection view", "top view", or "bottom view”.
- a plane (cut) obtained by cutting the configuration in a direction different from the horizontal direction may be called a plan view instead of a plane (cut) obtained by cutting the configuration in the horizontal direction.
- a line of sight in a direction perpendicular to the plan view may be called a plan view.
- a cross-sectional view is, for example, a diagram showing a state of a plane (cut end) obtained by cutting the configuration in the vertical direction.
- the term "cross-sectional view” can be replaced with the term "front view” or "side view”.
- a cross-sectional view may be a plane (cut) obtained by cutting the structure in a direction different from the vertical direction, rather than a plane (cut) obtained by cutting the configuration in the vertical direction.
- a line of sight in a direction perpendicular to the cross-sectional view may be referred to as a cross-sectional view.
- a semiconductor device is a device that utilizes semiconductor characteristics, and refers to circuits including semiconductor elements (eg, transistors, diodes, and photodiodes), devices having such circuits, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip with an integrated circuit, and an electronic component containing the chip in a package are examples of semiconductor devices.
- memory devices, display devices, light-emitting devices, lighting devices, electronic devices, and the like are themselves semiconductor devices and may include semiconductor devices.
- connection relationships other than the connection relationships shown in the drawings or the text are not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or the text.
- X and Y are electrically connected is an element that enables electrical connection between X and Y (for example, switch, transistor, capacitive element, inductor, resistive element, diode, display devices, light emitting devices, and loads) can be connected between X and Y one or more times.
- the switch has a function of being controlled to be turned on and off. In other words, the switch has the function of being in a conducting state (on state) or a non-conducting state (off state) and controlling whether or not to allow current to flow.
- X and Y are functionally connected is a circuit that enables functional connection between X and Y (e.g., logic circuit (e.g., inverter, NAND circuit, and NOR circuit), Signal conversion circuits (e.g., digital-to-analog conversion circuits, analog-to-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (e.g., power supply circuits such as step-up circuits or step-down circuits, and level shifter circuits that change the potential level of signals), voltage source, current source, switching circuit, amplifier circuit (for example, a circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, and buffer circuit), signal generation circuit, memory circuit, control circuit) can be connected between X and Y one or more times. As an example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.
- logic circuit
- X and Y are electrically connected, it means that X and Y are electrically connected (that is, another element or another circuit is interposed), and the case where X and Y are directly connected (that is, the case where X and Y are connected without another element or another circuit interposed between them). (if any).
- X and Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and X, the source of the transistor (or the 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and are electrically connected in the order of Y.”
- the source (or first terminal, etc.) of the transistor is electrically connected to X
- the drain (or second terminal, etc.) of the transistor is electrically connected to Y
- X is the source of the transistor ( or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.
- X is electrically connected to Y through the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X is the source (or first terminal, etc.) of the transistor; terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.
- the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished by defining the order of connection in the circuit configuration.
- the technical scope can be determined.
- these expression methods are examples, and are not limited to these expression methods.
- X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, and layers).
- circuit diagram shows independent components electrically connected to each other, if one component has the functions of multiple components.
- one component has the functions of multiple components.
- the term "electrically connected" in this specification includes cases where one conductive film functions as a plurality of constituent elements.
- a “resistive element” can be, for example, a circuit element having a resistance value higher than 0 ⁇ , a wiring having a resistance value higher than 0 ⁇ , or the like. Therefore, in this specification and the like, the term “resistive element” includes a wiring having a resistance value, a transistor, a diode, a coil, and the like through which a current flows between a source and a drain. Therefore, the term “resistive element” can be interchanged with terms such as “resistance,””load,” and “region having a resistance value,” and conversely, “resistance,””load,” and “region having a resistance value.” can be interchanged with the term “resistive element”.
- the resistance value can be, for example, preferably 1 m ⁇ or more and 10 ⁇ or less, more preferably 5 m ⁇ or more and 5 ⁇ or less, still more preferably 10 m ⁇ or more and 1 ⁇ or less. Also, for example, it may be 1 ⁇ or more and 1 ⁇ 10 9 ⁇ or less.
- capacitor element refers to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, a transistor can be the gate capacitance of Therefore, in this specification and the like, terms such as “capacitance element”, “parasitic capacitance”, and “gate capacitance” can be replaced with the term “capacitance”. can be translated into terms such as “element”, “parasitic capacitance”, and "gate capacitance”.
- a pair of electrodes in “capacitance” can be rephrased as “a pair of conductors", “a pair of conductive regions", and “a pair of regions”.
- the value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. Also, for example, it may be 1 pF or more and 10 ⁇ F or less.
- a transistor has three terminals called a gate, a source, and a drain.
- a gate is a control terminal that controls the conduction state of a transistor.
- the two terminals functioning as source or drain are the input and output terminals of the transistor.
- One of the two input/output terminals functions as a source and the other as a drain depending on the conductivity type of the transistor (n-channel type, p-channel type) and the level of potentials applied to the three terminals of the transistor. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.
- a transistor may have a back gate in addition to the three terminals described above, depending on the structure of the transistor.
- one of the gate and back gate of the transistor may be referred to as a first gate
- the other of the gate and back gate of the transistor may be referred to as a second gate.
- the terms "gate” and “backgate” may be used interchangeably for the same transistor.
- the respective gates may be referred to as a first gate, a second gate, a third gate, or the like in this specification and the like.
- the circuit element may have a plurality of circuit elements.
- resistor when one resistor is described on the circuit diagram, it includes the case where two or more resistors are electrically connected in series.
- capacitor when one capacitor is described on the circuit diagram includes the case where two or more capacitors are electrically connected in parallel.
- transistor when one transistor is illustrated in a circuit diagram, two or more transistors are electrically connected in series and the gates of the transistors are electrically connected to each other. shall include Similarly, for example, when one switch is described on the circuit diagram, the switch has two or more transistors, and the two or more transistors are electrically connected in series. This includes the case where the gates of the transistors are electrically connected to each other.
- a node can be called a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like, depending on the circuit configuration and device structure. Terminals, wirings, and the like can also be called nodes.
- Voltage is a potential difference from a reference potential.
- the reference potential is ground potential
- “voltage” can be replaced with “potential”. Note that the ground potential does not necessarily mean 0V.
- the potential is relative, and when the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, etc., and the potential output from the circuit etc. also change.
- the terms “high level potential” and “low level potential” do not mean specific potentials.
- the high-level potentials supplied by both wirings do not have to be equal to each other.
- the low-level potentials applied by both wirings need not be equal to each other.
- “Current” refers to the phenomenon of charge transfer (electrical conduction). is happening.” Therefore, in this specification and the like, unless otherwise specified, the term “electric current” refers to a charge transfer phenomenon (electrical conduction) associated with the movement of carriers.
- the carrier here includes, for example, electrons, holes, anions, cations, and complex ions, and the carrier differs depending on the current flow system (eg, semiconductor, metal, electrolyte, and in vacuum).
- the "direction of current” in wiring or the like is the direction in which carriers that become positive charges move, and is described as a positive amount of current. In other words, the direction in which the carriers that become negative charges move is the direction opposite to the direction of the current, and is represented by the amount of negative current.
- the ordinal numbers “first”, “second”, and “third” are added to avoid confusion of constituent elements. Therefore, the number of components is not limited. Also, the order of the components is not limited. For example, the component referred to as “first” in one of the embodiments such as this specification may be the component referred to as “second” in another embodiment or the scope of claims. can also be Further, for example, the component referred to as “first” in one of the embodiments of this specification etc. may be omitted in other embodiments or the scope of claims.
- electrode B on insulating layer A does not require that electrode B be formed on insulating layer A in direct contact with another configuration between insulating layer A and electrode B. Do not exclude those containing elements.
- the terms “film” and “layer” can be interchanged depending on the situation. For example, it may be possible to change the term “conductive layer” to the term “conductive film.” Or, for example, it may be possible to change the term “insulating film” to the term “insulating layer”. Alternatively, in some cases or circumstances, the terms “film” or “layer” can be omitted and replaced with other terms. For example, it may be possible to change the term “conductive layer” or “conductive film” to the term “conductor.” Or, for example, it may be possible to change the term “insulating layer” or “insulating film” to the term “insulator”.
- Electrode may be used as part of a “wiring” and vice versa.
- the term “electrode” or “wiring” also includes the case where one or both of a plurality of “electrodes” and “wiring” are integrally formed.
- terminal may be used as part of one or both of “wiring” and “electrode”, and vice versa.
- terminal also includes cases where a plurality of "electrodes", “wirings”, or “terminals” are integrally formed.
- an “electrode” can be part of a “wiring” or a “terminal”, and a “terminal” can be part of a “wiring” or an “electrode”, for example.
- terms such as “electrode”, “wiring”, or “terminal” may be replaced with terms such as "region” in some cases.
- terms such as “wiring”, “signal line”, and “power line” can be interchanged depending on the case or situation. For example, it may be possible to change the term “wiring” to the term “signal line”. Also, for example, it may be possible to change the term “wiring” to the term “power supply line”. Also, vice versa, it may be possible to change the term “signal line” or “power line” to the term “wiring”. It may be possible to change the term “power line” to the term “signal line”. Also, vice versa, the term “signal line” may be changed to the term “power line”. Also, the term “potential” applied to the wiring can be changed to the term “signal” in some cases or depending on the situation. And vice versa, the term “signal” may be changed to the term “potential”.
- semiconductor impurities refer to, for example, substances other than the main components that constitute the semiconductor layer.
- impurities may cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity.
- impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and elements other than the main component. Transition metals may be mentioned, in particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like.
- a switch is one that has the function of being in a conducting state (on state) or a non-conducting state (off state) and controlling whether or not to allow current to flow.
- a switch has a function of selecting and switching a path through which current flows.
- an electrical switch, a mechanical switch, or the like can be used.
- the switch is not limited to a specific one as long as it can control current.
- Examples of electrical switches include transistors (eg, bipolar transistors, MOS transistors, etc.), diodes (eg, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes , diode-connected transistors, etc.), or a logic circuit combining these.
- transistors eg, bipolar transistors, MOS transistors, etc.
- diodes eg, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes , diode-connected transistors, etc.
- the “on state” of the transistor means a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically short-circuited.
- a “non-conducting state” of a transistor means a state in which a source electrode and a drain electrode of the transistor can be considered to be electrically cut off. Note that the polarity (conductivity type) of the transistor is not particularly limited when the transistor is operated as a simple switch.
- a mechanical switch is a switch using MEMS (Micro Electro Mechanical Systems) technology.
- the switch has an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction by moving the electrode.
- parallel refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of ⁇ 5° or more and 5° or less is also included.
- substantially parallel or “substantially parallel” refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less.
- Perfect means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.
- FIG. 4A shows an example of a memory cell that may be included in a memory device.
- the memory cell MC shown in FIG. 4A can be said to be an example of a SOT-MRAM (Spin Orbit Torque-Magnetoresistive Random Access Memory), which is a three-terminal memory element.
- SOT-MRAM Spin Orbit Torque-Magnetoresistive Random Access Memory
- the memory cell MC of FIG. 4A has, for example, a transistor M3, a transistor M4, and a resistance change device MD.
- an OS transistor can be applied as the transistor M3 and the transistor M4.
- a channel formation region of the OS transistor is preferably an oxide containing one or more selected from indium, gallium, and zinc.
- indium, element M (element M includes, for example, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, one or more selected from cerium, neodymium, hafnium, tantalum, tungsten, or magnesium), and an oxide containing one or more selected from zinc may be used.
- the memory device of one embodiment of the present invention is not limited to this.
- the transistor M3 and the transistor M4 illustrated in FIG. 4A may be configured without a back gate, that is, may be single-gate transistors.
- some of the transistors may have back gates, and some of the transistors may have no back gates.
- each of the transistor M3 and the transistor M4 includes a case of operating as a switching element unless otherwise specified. That is, the gate voltage, the source voltage, and the drain voltage of each transistor described above include cases where the voltage range is such that the transistor operates as a switching element. Also, each of the transistor M3 and the transistor M4 may operate in the linear region or the saturation region when in the ON state. Also, each of the transistor M3 and the transistor M4 may operate in a sub-threshold region.
- the variable resistance device MD has an MTJ (Magnetic Tunnel Junction) element ME. Also, the resistance change device MD has a terminal IT1, a terminal IT2, and a terminal OT. Details of the variable resistance device MD will be described later.
- MTJ Magnetic Tunnel Junction
- a first terminal of the transistor M3 is electrically connected to the terminal IT2 of the resistance change device MD, a second terminal of the transistor M3 is electrically connected to the wiring SL, and a gate of the transistor M3 is electrically connected to the wiring WLa. It is connected to the.
- a first terminal of the transistor M4 is electrically connected to the terminal OT of the resistance change device MD, a second terminal of the transistor M4 is electrically connected to the wiring SL, and a gate of the transistor M4 is electrically connected to the wiring WLb. It is connected to the.
- a terminal IT1 of the resistance change device MD is electrically connected to the wiring BL.
- the wiring BL functions as a write bit line, a read bit line, or a wiring for applying a constant voltage to the memory cell MC.
- the wiring SL functions as a wiring that gives a constant voltage.
- the wiring WLa functions as a write word line for the memory cell MC, for example.
- the wiring WLb functions as a read word line for the memory cell MC, for example.
- back gates are illustrated for the transistor M3 and the transistor M4, and the connection configuration of the back gates is not illustrated, but the electrical connection destination of the back gates should be determined at the design stage. can be done.
- the gate and back gate may be electrically connected in order to increase the on-state current of the transistor. That is, for example, the gate and backgate of the transistor M3 may be electrically connected, or the gate and backgate of the transistor M4 may be electrically connected.
- the back gate of the transistor and an external circuit are electrically connected.
- a wiring for connection may be provided and a potential may be applied to the back gate of the transistor by the external circuit or the like.
- the memory cell MC can be configured as shown in FIG. 4B.
- the memory cell MC in FIG. 4B has a configuration in which a wiring BGE is electrically connected to the back gates of the transistors M3 and M4 included in the memory cell MC in FIG. 4A.
- a predetermined potential By applying a predetermined potential to the wiring BGE, the threshold voltages of the transistors M3 and M4 can be varied.
- variable resistance device MD Next, the variable resistance device MD will be explained.
- FIG. 5 is a block diagram showing an example of the resistance change device MD.
- the resistance change device MD of FIG. 5 has a layer RL, a layer TIS, a layer FL, and a layer CA. Note that the layer RL, the layer TIS, and the layer FL are included in the MTJ element ME.
- the layer CA has, for example, a conductive film.
- the terminal IT1 and the terminal IT2 are electrically connected through the film. Therefore, by applying a voltage between the terminals IT1 and IT2, a current flows between the terminals IT1 and IT2.
- Layer CA may also be referred to as a channel layer.
- the film is made of a material that causes a spin Hall effect when a current flows between the terminals IT1 and IT2.
- the spin Hall effect is a phenomenon in which a spin current is generated in a direction substantially perpendicular to the direction of current flow.
- a current flows in a two-dimensional plane such as a thin film
- electrons with different spin directions are polarized on the upper surface and the lower surface of the thin film, respectively, thereby generating a spin current in a direction substantially perpendicular to the thin film. Occur. Therefore, the layer CA can generate a spin current in the substantially vertical direction of the layer CA by the current flowing between the terminal IT1 and the terminal IT2.
- the layer CA preferably has a metal material that causes the spin Hall effect. Specifically, it is preferable to use a transition metal having a strong spin-orbit interaction as the metal material. Such transition metals include, for example, tungsten, platinum, and tantalum.
- the layer CA may also include a topological insulator that causes a spin Hall effect, in which case, for example, an alloy of bismuth and antimony or an alloy of bismuth and selenium may be used.
- the layer FL functions as a free layer in the MTJ element ME.
- the layer FL has a ferromagnetic material, and the ferromagnetic material can take a magnetic moment parallel or antiparallel to the magnetization direction of the layer RL, which will be described later.
- Layer FL may also be referred to as a magnetic layer.
- the ferromagnetic material contained in the layer FL is preferably, for example, a material in which the magnetization of the ferromagnetic material is reversed by a small spin current.
- the ferromagnetic material contained in the layer FL is a material that is less susceptible to magnetization reversal due to thermal energy.
- the ferromagnetic material for example, one type of metal material selected from iron, cobalt, and nickel, or two or more types of alloy selected from the above materials can be used.
- alloys include cobalt-iron-boron alloys.
- Further examples of other alloys include alloys of manganese and gallium or manganese and germanium.
- the magnetic moment of layer FL receives spin torque due to the spin current generated in layer CA.
- the magnetic moment of the layer FL reverses direction, for example, when the spin torque exceeds a threshold. That is, the magnetization direction of the layer FL can be changed by passing a current through the layer CA (between the terminals IT1 and IT2). Information can be recorded in the MTJ element ME by this operation.
- the layer TIS functions as a layer having a tunnel insulator in the MTJ element ME.
- a voltage is applied between the layer FL and the layer RL (terminal OT)
- a tunnel current can flow through the layer TIS due to the tunnel magnetoresistive effect.
- the electric resistance value of the layer TIS changes depending on the direction of the magnetic moment of the layer FL. Specifically, the electric resistance value of the layer TIS changes depending on whether the magnetization directions of the layers FL and RL are parallel or antiparallel.
- magnesium oxide or aluminum oxide can be used for the tunnel insulator.
- the layer RL functions as a fixed layer in the MTJ element ME.
- Layer RL comprises a ferromagnetic material. Note that the ferromagnetic material of the layer RL has a fixed magnetization direction, unlike the ferromagnetic material of the layer FL. Layer RL, like layer FL, is sometimes referred to as a magnetic layer.
- the ferromagnetic material contained in the layer RL for example, a material that can be applied to the ferromagnetic material contained in the layer FL can be used.
- the ferromagnetic material and the tunnel insulator contained in the MTJ element ME are preferably combined so that the magnetoresistance ratio (MR ratio) of the MTJ element ME is increased.
- the wiring SL is supplied with a low-level potential, for example.
- a high-level potential is applied to the wiring WLa to turn on the transistor M3, and a low-level potential is applied to the wiring WLb to turn off the transistor M4.
- a first potential higher than the low-level potential of the wiring SL is applied from the wiring BL to the terminal IT1.
- a current flows between the terminals IT1 and IT2 according to the potential difference between the first potential and the low-level potential of the wiring SL. Therefore, a current flows through the layer CA of the MTJ element ME, a spin current is generated in the layer CA, and the magnetization direction of the ferromagnetic material of the layer FL is determined by the spin current.
- a high-level potential is applied to the wiring WLa to turn on the transistor M3, and a high-level potential is applied to the wiring WLb to turn on the transistor M4.
- a second potential higher than the low-level potential and lower than the first potential from the wiring BL to the terminal IT1 a current flows through one or both of the terminals IT1 and IT2 and between the terminals IT1 and OT. flows.
- the electric resistance value of the MTJ element ME changes depending on whether the magnetization directions of the layers RL and FL are parallel or antiparallel, so the amount of tunnel current flowing through the layer TIS of the MTJ element ME also change.
- information recorded in the MTJ element ME can be read by measuring the amount of current flowing through the MTJ element ME and the terminal IT1.
- Information recorded in the MTJ element ME can also be read by applying a predetermined potential to the wiring SL, flowing a constant current from the wiring BL to the terminal IT1 of the MTJ element ME, and measuring the potential of the terminal IT1.
- the resistance change device MD may have a circuit element whose resistance changes other than the MTJ element ME.
- the variable resistance device MD is called a variable resistance element utilizing electric field induced giant resistance change (CER effect), a ferroelectric tunnel junction (FTJ) element, or a phase change memory (PCM or PRAM).
- CER effect electric field induced giant resistance change
- FJ ferroelectric tunnel junction
- PCM or PRAM phase change memory
- the resistance change device MD may have a ferroelectric capacitor that induces a current by applying a pulse voltage.
- FIG. 1A and 1B illustrate configuration examples of a memory cell, which is a semiconductor device of one embodiment of the present invention.
- FIG. 1A is a plan view schematically showing a configuration example of the memory cell 600A
- FIG. 1B is a cross-sectional view schematically showing a configuration example of the memory cell 600A included in the layer OSL. is.
- FIG. 1B is a cross-sectional view taken along dashed line A1-A2 shown in FIG. 1A.
- 1A also illustrates conductor 590, conductor 540, conductor 560A, conductor 560B, conductor 542a, conductor 542b, conductor 542c, oxide 530bA, oxide 530bB, memory element 400, conductor 458, Only conductors 450, 448, and 440 are selectively shown.
- memory cell 600A includes memory element 400 and transistors 500A and 500B located above memory element 400.
- transistors 500A and 500B located above memory element 400.
- FIGS. one or both of the transistor 500A and the transistor 500B may be referred to as the transistor 500 in this specification and the like.
- FIG. 2A shows a cross-sectional view of the transistor 500A in the channel length direction
- FIG. 2B shows a cross-sectional view of the transistor 500A in the channel width direction.
- the transistors shown in FIGS. 2A and 2B may partially differ in shape from the transistor shown in FIG. 1B for the sake of explanation.
- the memory cell MC of FIG. 4A is used.
- the transistor 500A corresponds to the transistor M3
- the transistor 500B corresponds to the transistor M4
- the memory element 400 corresponds to the resistance change device MD. Therefore, in the cross-sectional view of FIG. 1, the first terminal of the transistor 500A is electrically connected to the first terminal of the memory element 400 and the conductor 440 (described in detail later) that functions as a wiring. .
- the wiring BL in FIG. 4A can be a conductor 440 electrically connected to the first terminal of the memory element 400, for example.
- the wiring SL in FIG. 4A can be, for example, a conductor 590 (described in detail later) electrically connected to the second terminal of the transistor 500A and the second terminal of the transistor 500B.
- the wiring WLa in FIG. 4A can be, for example, a conductor 560A (details will be described later) corresponding to the gate of the transistor 500A.
- the wiring WLb in FIG. 4A can be, for example, a conductor 560B (details will be described later) corresponding to the gate of the transistor 500B.
- a transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region.
- the transistor 500 has a low off-state current and a small change in field-effect mobility even at high temperatures.
- a transistor included in the above memory device or the like for example, a memory device whose operating performance is less likely to decrease even at high temperatures can be realized.
- the layer OSL has an insulator 434 .
- the insulator 434 functions as an interlayer film, for example.
- the insulator 434 may function as a planarization film that planarizes steps caused by circuit elements, wirings, and the like located below the insulator 434 .
- the top surface of the insulator 434 may be planarized by planarization treatment using a chemical machine polishing (CMP) method to improve planarity.
- CMP chemical machine polishing
- silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used, for example.
- silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
- silicon oxynitride refers to a material whose composition contains more nitrogen than oxygen.
- aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen
- aluminum oxynitride refers to a material whose composition contains more nitrogen than oxygen. indicates
- An insulator 436 is provided over the insulator 434 , a conductor 440 is provided over the insulator 436 , and an insulator 442 is provided over the conductor 440 .
- the insulators 436 and 442 preferably have barrier properties such that impurities such as water, hydrogen, or oxygen do not diffuse.
- the insulators 436 and 442 are added to prevent hydrogen or water from diffusing into the transistor 500 from below the insulators 436 and 442 .
- a barrier film that prevents diffusion of water or hydrogen may be used.
- a barrier film that prevents diffusion of oxygen is used for the insulators 436 and 442 in order to suppress oxidation of the conductor 440 . Just do it.
- a silicon nitride film formed by a CVD (Chemical Vapor Deposition) method can be used as an example of a film having a barrier property against hydrogen.
- a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide for the film having a barrier property against hydrogen.
- aluminum oxide has a high shielding effect that prevents not only impurities such as hydrogen and moisture, which are factors that change the electrical characteristics of transistors, but also oxygen from penetrating through the film.
- the desorption amount of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS).
- TDS thermal desorption spectroscopy
- the amount of hydrogen released from the insulators 436 and 442 was determined by TDS analysis at a film surface temperature range of 50° C. to 500° C. in terms of hydrogen atoms.
- the concentration is 10 ⁇ 10 15 atoms/cm 2 or less, preferably 5 ⁇ 10 15 atoms/cm 2 or less.
- the conductor 440 functions as a wiring electrically connected to the memory cell of one embodiment of the present invention, as described above.
- a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) can be used.
- a metal nitride film titanium nitride film, molybdenum nitride film, tungsten nitride film
- indium tin oxide for example, can be applied to the conductor 440 .
- the conductor 440 includes, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or Conductive materials such as indium tin oxide doped with silicon oxide can also be applied.
- the conductor 440 has a single-layer structure in FIG. 1, it is not limited to this structure, and may have a laminated structure of two or more layers. For example, between a conductor with barrier properties and a conductor with high conductivity, a conductor with barrier properties and a conductor with high adhesion to the conductor with high conductivity may be formed.
- An insulator 443, an insulator 444, and an insulator 446 are provided on the insulator 442 in this order from below.
- the insulators 443 and 444 preferably have a lower dielectric constant than the insulators 436 and 442 .
- the dielectric constants of the insulators 443 and 444 are preferably less than 4, more preferably less than 3.
- the dielectric constants of the insulators 443 and 444 are preferably 0.7 times or less, more preferably 0.6 times or less, that of the insulators 436 and 442 .
- a material that can be applied to the insulator 434 can be used for the insulators 443 and 444, for example.
- the insulator 446 preferably has barrier properties such that impurities such as water, hydrogen, or oxygen do not diffuse. Therefore, for the insulator 446, a material that can be applied to the insulators 436 and 442 can be used, for example. For the insulator 446, a structure applicable to the insulators 436 and 442 can be used, for example.
- a conductor 448 is embedded in the insulator 442 , the insulator 443 , the insulator 444 , and the insulator 446 .
- the conductor 448 functions as a via, plug, or wiring.
- conductors that function as vias, plugs, or wirings may have a plurality of structures collectively given the same reference numerals.
- the wiring and the via or plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a via or plug.
- Conductor 448, conductor 457, conductor 458, conductor 518, and conductor 540 described later include metal materials, alloy materials, metal nitride materials, or A single layer or a stack of conductive materials such as metal oxide materials can be used. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to use a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material. Alternatively, a material that can be applied to the conductor 440 can be used as a material that can be applied to each via, plug, or wiring, for example.
- each via, plug, or wiring includes a conductor having a barrier property against water or hydrogen.
- a conductor having a barrier property against water or hydrogen is preferred.
- a conductor having a barrier property against water or hydrogen is formed on the side surfaces of the openings formed in the insulators 442, 443, 444, and 446 which have a barrier property against hydrogen. is preferred.
- the conductor having a barrier property against hydrogen for example, tantalum nitride may be used.
- tantalum nitride by stacking tantalum nitride and highly conductive tungsten, the diffusion of hydrogen can be suppressed while maintaining the conductivity of the wiring.
- the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulators 442 and 446 having a barrier property against hydrogen.
- a conductor 450 is provided over the insulator 446 and the conductor 448 .
- the conductor 450 functions as a wiring for electrically connecting the first terminal of the memory element 400 and the first terminal of the transistor 500A to the conductor 440.
- a material that can be applied to the conductor 440 can be used for the conductor 450, for example.
- the memory element 400 is the MTJ element ME included in the resistance change device MD of the memory cell MC in FIGS. preferable. Therefore, for the conductor 450, for example, a material that can be applied to the layer CA shown in FIG. 5 can be used.
- the memory element 400 is the MTJ element ME included in the resistance change device MD of the memory cell MC in FIGS. 4A and 4B.
- the memory element 400 is provided in a partial area on the conductor 450 .
- the memory element 400 includes a conductor 401, an insulator 402, a conductor 403, and a conductor 404.
- the conductor 401, the insulator 402, the conductor 403, and the conductor 404 are arranged in this order. area is laminated.
- a conductor 401 is a free layer in the memory element 400 and corresponds to the layer FL of the MTJ element ME in FIG.
- the insulator 402 is a tunnel insulator in the memory element 400 and corresponds to the layer TIS of the MTJ element ME in FIG.
- the conductor 403 is a fixed layer in the memory element 400 and corresponds to the layer RL of the MTJ element ME in FIG. Therefore, materials that can be applied to the conductor 401, the insulator 402, and the conductor 403 can refer to the description of the MTJ element ME in FIG.
- the conductor 404 is provided as a hard mask for forming the conductor 401 , the insulator 402 and the conductor 403 .
- a material that can be applied to the conductor 448 can be used.
- the insulator 452 is provided so as to cover the insulator 446 , the conductor 450 , the conductor 401 , the insulator 402 , the conductor 403 , and the conductor 404 .
- the insulator 452 for example, like the insulators 436, 442, and 446, it is preferable to use a film having barrier properties such that impurities such as water, hydrogen, or oxygen do not diffuse.
- a material that can be used for the insulator 436 is preferably used for the insulator 452 .
- a structure applicable to the insulator 436 can be used for the insulator 452 .
- An insulator 454 is provided on the insulator 452 .
- the insulator 454 functions as a planarization film that planarizes steps caused by the conductor 450 , the memory element 400 , and the insulator 452 , for example.
- the insulator 454 is formed by, for example, planarization treatment by a chemical mechanical polishing (CMP) method after an insulator to be the insulator 454 is formed over the insulator 452 until the conductor 404 is exposed. It can be formed by doing.
- CMP chemical mechanical polishing
- An insulator 456 is provided over the insulator 454 , the insulator 452 , and the conductor 404 .
- the insulator 454 and the insulator 456 it is preferable to use an insulator with a relatively low relative permittivity like the insulator 443 or the insulator 444, for example.
- the insulators 454 and 456 are preferably formed using a material that can be used for the insulators 443 and 444 .
- a conductor 457 is embedded in the insulator 456 .
- a conductor 458 is embedded in the insulator 452 , the insulator 454 , and the insulator 456 . Note that the conductors 457 and 458 function as vias, plugs, or wirings.
- the conductor 457 functions as a wiring for electrically connecting the second terminal of the memory element 400 to the first terminal of the transistor 500B.
- An insulator 510 , an insulator 512 , an insulator 513 , an insulator 514 , and an insulator 516 are stacked in this order over the insulator 456 , the conductor 457 , and the conductor 458 .
- Any of the insulator 510, the insulator 512, the insulator 513, the insulator 514, and the insulator 516 is preferably a substance having a barrier property against water, hydrogen, or oxygen.
- the insulator 510 and the insulator 514 it is preferable to use a film having a barrier property so that an impurity such as water or hydrogen does not diffuse from below the insulator 510 to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 436 can be used for the insulators 510 and 514 .
- a structure that can be applied to the insulator 436 can be used.
- the insulator 513 similarly to the insulators 510 and 514, it is preferable to use a film having barrier properties such that an impurity such as water or hydrogen is not diffused.
- the insulator 513 functions as a film that seals the transistor 500 together with the insulator 576 described later. Therefore, the insulator 513 is preferably made of a material that can be used for the insulator 576 .
- a material that can be used for the insulator 510 or the insulator 514 may be used.
- a material with a relatively low dielectric constant for the insulators 512 and 516 parasitic capacitance generated between wirings can be reduced. Therefore, for the insulators 512 and 516, a material similar to that of the insulators 443 and 444 can be used.
- transistor 500A and the transistor 500B configuration examples of the transistor 500A and the transistor 500B are described. Note that this description refers to transistor 500A shown in FIGS. 2A and 2B. Therefore, the description of the transistor 500A below will be referred to for the transistor 500B, and the differences between the transistors 500A and 500B will be described in addition to the transistor 500A below.
- the transistor 500A is provided above the insulator 514 .
- a conductor included in the transistor 500 (eg, the conductor 503 in FIGS. 2A and 2B) is embedded in the insulator 510, the insulator 512, the insulator 513, the insulator 514, and the insulator 516. .
- a conductor 518 is embedded in the insulator 510, the insulator 512, the insulator 513, the insulator 514, the insulator 516, the insulator 520, and the insulator 522.
- the conductor 518 functions as a via, a plug, or a wiring connected to the memory element 400, the conductor 440, and the conductor 450 described above. Therefore, the conductor 518 can be provided using a material similar to that of the conductor 448, for example.
- a conductor 518 in a region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water.
- the transistor 500A and components below the transistor 500A can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and hydrogen can be prevented from diffusing from below the transistor 500A to the transistor 500A. can be suppressed.
- transistor 500A includes conductor 503 embedded in insulators 514 and 516 and insulator 516 and conductor 503 overlying insulator 503 .
- conductors 542a and 542b spaced apart from each other on oxide 530b; and conductors 542a and 542b between conductors 542a and 542b.
- an insulator 580 in which an opening is formed so as to overlap with the insulator 580 , an oxide 530 c provided on the bottom surface and side surfaces of the opening, an insulator 550 provided on the top surface of the oxide 530 c , and an insulator 550 on the top surface of the insulator 550 ; and a conductor 560 .
- the conductor 542a and the conductor 542b are collectively referred to as the conductor 542 in this specification and the like.
- an insulator 544 is preferably arranged between the conductors 542a and 542b and the insulator 580.
- the conductor 560 includes a conductor 560a provided inside the insulator 550, a conductor 560b provided so as to be embedded inside the conductor 560a, It is preferred to have Insulator 574 is also preferably disposed over insulator 580, conductor 560, and insulator 550, as shown in FIGS. 2A and 2B.
- oxide 530a the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530 below.
- the transistor 500A has a structure in which three layers of the oxide 530a, the oxide 530b, and the oxide 530c are stacked in a region where a channel is formed and in the vicinity thereof, this is one embodiment of the present invention. is not limited to For example, a single layer of the oxide 530b, a two-layer structure of the oxides 530b and 530a, a two-layer structure of the oxides 530b and 530c, or a stacked structure of four or more layers may be employed.
- the conductor 560 has a two-layer structure in the transistor 500A, one embodiment of the present invention is not limited to this.
- the conductor 560 may have a single-layer structure or a laminated structure of three or more layers.
- the transistor 500A illustrated in FIGS. 1, 2A, and 2B is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on the circuit configuration and the driving method.
- the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as source and drain electrodes, respectively.
- the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b.
- the placement of conductor 560 , conductor 542 a and conductor 542 b is selected in a self-aligned manner with respect to the opening in insulator 580 . That is, in the transistor 500A, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, since the conductor 560 can be formed without providing a margin for alignment, the area occupied by the transistor 500A can be reduced. As a result, miniaturization and high integration of the memory device can be achieved.
- the conductor 560 is formed in a region between the conductors 542a and 542b in a self-aligning manner, the conductor 560 does not have a region that overlaps with the conductors 542a or 542b. Accordingly, parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Therefore, the switching speed of the transistor 500A can be improved, and high frequency characteristics can be obtained.
- the conductor 560 may function as a first gate (also called top gate) electrode.
- the conductor 503 functions as a second gate (also referred to as a bottom gate) electrode.
- the potential applied to the conductor 503 is changed independently of the potential applied to the conductor 560, so that the threshold voltage of the transistor 500A can be controlled.
- the threshold voltage of the transistor 500A can be increased and the off current can be reduced. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when no potential is applied.
- the conductor 503 is arranged so as to overlap with the oxide 530 and the conductor 560 . Accordingly, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected to each other, so that the channel formation region formed in the oxide 530 is covered. can be done.
- a transistor structure in which a channel formation region is electrically surrounded by electric fields of a first gate electrode and a second gate electrode is referred to as a surrounded channel (S-channel) structure.
- the conductor 503 has a conductor 503a formed in contact with the inner walls of the openings of the insulators 514 and 516, and a conductor 503b formed inside. Note that although the structure in which the conductors 503a and 503b are stacked is shown in the transistor 500, one embodiment of the present invention is not limited to this.
- the conductor 503 may be provided as a single layer or a laminated structure of three or more layers.
- the conductor 503a it is preferable to use a conductive material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, or copper atoms (the above impurities are difficult to permeate).
- a conductive material that has a function of suppressing the diffusion of oxygen for example, one or both of oxygen atoms and oxygen molecules (the above-mentioned oxygen hardly permeates).
- the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of one or all of the impurities or oxygen.
- the conductor 503a since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 503b from being oxidized and reducing its conductivity.
- the conductor 503b preferably uses a highly conductive material containing tungsten, copper, or aluminum as its main component.
- the conductor 503a is not necessarily provided in the case where high conductivity of the wiring can be maintained. Note that although the conductor 503b is shown as a single layer, it may have a layered structure, for example, a layered structure of titanium or titanium nitride and any of the above conductive materials.
- the insulator 520, the insulator 522, and the insulator 524 function as second gate insulating films.
- the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the stoichiometric composition.
- the insulator 524 preferably has an excess oxygen region.
- V 0 oxygen vacancy
- electrical characteristics are likely to fluctuate and reliability may be degraded.
- hydrogen in the vicinity of the oxygen vacancy (V 0 ) forms a defect (hereinafter sometimes referred to as V OH ) in which hydrogen enters the oxygen vacancy (V 0 ), and generates electrons that serve as carriers.
- V OH defect
- oxygen vacancies are included in the region where the channel is formed in the oxide semiconductor, the transistor has normally-on characteristics (the channel exists even if no voltage is applied to the gate electrode, and current flows through the transistor). flow characteristics).
- impurities, oxygen vacancies, and VOH are preferably reduced as much as possible in a region where a channel is formed in the oxide semiconductor.
- the region in which the channel is formed in the oxide semiconductor preferably has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.
- an oxide material from which part of oxygen is released by heating is preferably used as the insulator having the excess oxygen region.
- the oxide that desorbs oxygen by heating means that the desorption amount of oxygen in terms of oxygen atoms is 1.0 ⁇ 10 18 atoms/cm 3 or more, preferably 1, in TDS (Thermal Desorption Spectroscopy) analysis. 0 ⁇ 10 19 atoms/cm 3 or more, more preferably 2.0 ⁇ 10 19 atoms/cm 3 or more, or 3.0 ⁇ 10 20 atoms/cm 3 or more.
- the surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.
- one or more of heat treatment, microwave treatment, and RF treatment may be performed while the insulator having the excess oxygen region and the oxide 530 are in contact with each other.
- water or hydrogen in the oxide 530 can be removed.
- a reaction that breaks the bond of VoH occurs, in other words, a reaction of “V OH ⁇ V 2 O +H” occurs, and dehydrogenation can be performed.
- Part of the hydrogen generated at this time is combined with oxygen to form H 2 O and removed from the oxide 530 or an insulator near the oxide 530 in some cases. Further, part of the hydrogen might be diffused or trapped (also called gettering) in the conductors 542a and 542b.
- the microwave treatment for example, it is preferable to use an apparatus having a power supply for generating high-density plasma or an apparatus having a power supply for applying RF to the substrate side.
- a gas containing oxygen and using high-density plasma high-density oxygen radicals can be generated.
- the oxygen radicals generated by the high-density plasma can be generated.
- the microwave treatment may be performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher.
- oxygen and argon are used as gases to be introduced into the apparatus for microwave treatment, and the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is 50% or less, preferably 10% or more and 30%. % or less.
- heat treatment is preferably performed with the surface of the oxide 530 exposed during the manufacturing process of the transistor 500 .
- the heat treatment may be performed at, for example, 100° C. to 450° C., more preferably 350° C. to 400° C.
- the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
- heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxide 530 to reduce oxygen vacancies (V 0 ).
- the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen after the heat treatment is performed in a nitrogen gas or inert gas atmosphere. good.
- heat treatment may be continuously performed in a nitrogen gas or inert gas atmosphere.
- oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction “V 2 O +O ⁇ null” can be promoted.
- the supplied oxygen reacts with the hydrogen remaining in the oxide 530, so that the hydrogen can be removed as H 2 O (dehydrated). Accordingly, hydrogen remaining in the oxide 530 can be suppressed from being recombined with oxygen vacancies to form VOH .
- the insulator 522 when the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less permeable).
- oxygen eg, oxygen atoms, oxygen molecules, etc.
- the insulator 522 has a function of suppressing diffusion of oxygen or impurities, oxygen contained in the oxide 530 does not diffuse to the insulator 520 side, which is preferable.
- the conductor 503 can be prevented from reacting with oxygen contained in each of the insulator 524 and the oxide 530 .
- the insulator 522 is, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate ( SrTiO3 ), or It is preferable to use an insulator containing a so-called high-k material such as (Ba, Sr)TiO 3 (BST) in a single layer or a laminated layer. As transistors are miniaturized and highly integrated, thinning of the gate insulating film may cause a problem such as leakage current. By using a high-k material for the insulator functioning as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
- a so-called high-k material such as (Ba, Sr)TiO 3 (BST)
- an insulator containing an oxide of one or both of aluminum and hafnium which is an insulating material that has a function of suppressing the diffusion of impurities and oxygen (the above-described oxygen hardly permeates).
- the insulator containing oxides of one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
- the insulator 522 is a layer that suppresses release of oxygen from the oxide 530 and entry of impurities such as hydrogen into the oxide 530 from the peripheral portion of the transistor 500. function as
- aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
- these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
- the insulator 520 is preferably thermally stable.
- silicon oxide and silicon oxynitride are preferred because they are thermally stable.
- the insulator 520 with a stacked structure that is thermally stable and has a high relative dielectric constant can be obtained.
- the insulator 520, the insulator 522, and the insulator 524 are illustrated as the second gate insulating film having a stacked-layer structure of three layers.
- the gate insulating film may have a single layer, two layers, or a laminated structure of four or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may be used.
- the transistor 500A preferably uses a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region.
- a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region.
- In-M-Zn oxide element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, or magnesium.
- the In-M-Zn oxide that can be applied as the oxide 530 is preferably CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) or CAC-OS (Cloud-Aligned Composite Oxide Semiconductor).
- the oxide 530 may be an In--Ga oxide, an In--Zn oxide, or an In oxide.
- a metal oxide with a low carrier concentration is preferably used for the transistor 500A.
- the impurity concentration in the metal oxide should be lowered to lower the defect level density.
- a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
- impurities in metal oxides include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.
- hydrogen contained in the metal oxide reacts with oxygen bound to the metal atom to form water, which may cause oxygen vacancies in the metal oxide. Further, when hydrogen enters oxygen vacancies in the oxide 530, the oxygen vacancies and hydrogen may combine to form VOH .
- VOH may function as a donor and generate an electron, which is a carrier.
- part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron that is a carrier. Therefore, a transistor using a metal oxide containing a large amount of hydrogen tends to have normally-on characteristics.
- hydrogen in a metal oxide is likely to move due to stress such as heat or an electric field; therefore, when a large amount of hydrogen is contained in the metal oxide, the reliability of the transistor might be deteriorated.
- V OH in oxide 530 it is preferred to reduce V OH in oxide 530 as much as possible to be highly pure intrinsic or substantially highly pure intrinsic.
- impurities such as moisture or hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment).
- oxygenation treatment it is important to supply oxygen to the metal oxide to compensate for oxygen deficiency (sometimes referred to as oxygenation treatment).
- Defects with hydrogen in oxygen vacancies can function as donors for metal oxides. However, it is difficult to quantitatively evaluate the defects. Therefore, metal oxides are sometimes evaluated not by the donor concentration but by the carrier concentration. Therefore, in this specification and the like, instead of the donor concentration, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the metal oxide. In other words, the “carrier concentration” described in this specification and the like may be rephrased as “donor concentration”.
- the hydrogen concentration obtained by secondary ion mass spectrometry is less than 1 ⁇ 10 20 atoms/cm 3 , preferably 1 ⁇ 10 19 atoms/cm It is less than 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , still more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
- the metal oxide is an intrinsic (also referred to as I-type) or substantially intrinsic semiconductor with a large bandgap, and is used for the channel formation region.
- the carrier concentration of the metal oxide is preferably less than 1 ⁇ 10 18 cm ⁇ 3 , more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , further preferably less than 1 ⁇ 10 16 cm ⁇ 3 . It is preferably less than 1 ⁇ 10 13 cm ⁇ 3 , more preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
- the lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but can be set to 1 ⁇ 10 ⁇ 9 cm ⁇ 3 , for example.
- the conductors 542a and 542b are in contact with the oxide 530, whereby oxygen in the oxide 530 diffuses into the conductors 542a and 542b, 542a and conductor 542b may be oxidized.
- the conductivity of the conductors 542a and 542b is highly likely to be reduced by the oxidation of the conductors 542a and 542b. Note that diffusion of oxygen in the oxide 530 to the conductors 542a and 542b can be rephrased as absorption of oxygen in the oxide 530 by the conductors 542a and 542b.
- oxygen in the oxide 530 diffuses into the conductor 542a and the conductor 542b, so that different layers are formed between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b.
- the different layer contains more oxygen than the conductors 542a and 542b, the different layer is presumed to have insulating properties.
- the three-layer structure of the conductor 542a or the conductor 542b, the different layer, and the oxide 530b can be regarded as a three-layer structure of metal-insulator-semiconductor. semiconductor) structure, or a diode junction structure mainly composed of the MIS structure.
- the different layers are not limited to being formed between the conductors 542a and 542b and the oxide 530b. may be formed in
- a metal oxide that functions as a channel formation region in the oxide 530 preferably has a bandgap of 2 eV or more, preferably 2.5 eV or more.
- the oxide 530 can suppress the diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b.
- the oxide 530c over the oxide 530b, diffusion of impurities from a structure formed above the oxide 530c to the oxide 530b can be suppressed.
- the oxide 530 preferably has a laminated structure with a plurality of oxide layers having different atomic ratios of metal atoms.
- the atomic number ratio of the element M among the constituent elements is greater than the atomic number ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. is preferred.
- the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b.
- the atomic ratio of In to the element M in the metal oxide used for the oxide 530b is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.
- the oxide 530c can be a metal oxide that can be used for the oxide 530a or the oxide 530b.
- a metal oxide having a composition close to any one can be used.
- a metal oxide having a composition of 3 to 4.1 and a composition in the vicinity thereof is preferable.
- the above composition indicates the atomic ratio in the oxide formed on the substrate or the atomic ratio in the sputtering target.
- the ratio of In as the composition of the oxide 530b, the on-state current of the transistor, the field-effect mobility, or the like can be increased, which is preferable.
- the energies of the conduction band bottoms of the oxides 530a and 530c be higher than the energies of the conduction band bottoms of the oxide 530b.
- the electron affinities of the oxides 530a and 530c are preferably smaller than that of the oxide 530b.
- the energy level at the bottom of the conduction band changes smoothly at the junction of the oxide 530a, the oxide 530b, and the oxide 530c.
- the energy level of the bottom of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c continuously changes or continuously joins.
- the defect level density of the mixed layers formed at the interface between the oxides 530a and 530b and the interface between the oxides 530b and 530c should be lowered.
- the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) other than oxygen, thereby forming a mixed layer with a low defect level density.
- the oxide 530b is an In--Ga--Zn oxide
- the oxides 530a and 530c may be In--Ga--Zn oxide, Ga--Zn oxide, or gallium oxide.
- the main route of carriers is the oxide 530b.
- the oxides 530a and 530c have the above structure, defect level densities at the interfaces between the oxides 530a and 530b and between the oxides 530b and 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.
- a conductor 542a and a conductor 542b functioning as a source electrode and a drain electrode are provided over the oxide 530b.
- Conductors 542a and 542b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. , iridium, strontium, and lanthanum, or preferably use an alloy containing the above-described metal elements as a component, or use an alloy in which a plurality of the above-described metal elements are combined.
- the conductor 542a and the conductor 542b include, for example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, strontium and ruthenium. It is preferred to use an oxide or an oxide containing lanthanum and nickel.
- tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel do not oxidize. It is more preferable to use such a material for the conductors 542a and 542b because it is a conductive material that is difficult to absorb oxygen or a material that maintains conductivity even after absorbing oxygen. In addition, since a metal nitride such as tantalum nitride has a barrier property against hydrogen or oxygen, it is more preferable to use a metal nitride for the conductors 542a and 542b.
- the conductors 542a and 542b are shown to have a single-layer structure, but they may have a laminated structure of two or more layers.
- a tantalum nitride film and a tungsten film are preferably stacked.
- a titanium film and an aluminum film may be stacked.
- a two-layer structure in which an aluminum film is laminated on a tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a tungsten film
- a two-layer structure in which a copper film is laminated thereon may be employed.
- the conductors 542a and 542b are formed by stacking a titanium film or a titanium nitride film, an aluminum film or a copper film over the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film over the titanium film or the titanium nitride film.
- the conductor 542a and the conductor 542b are formed by stacking a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film over the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film thereover. It may be a three-layer structure that forms a Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used for the conductors 542a and 542b.
- regions 543a and 543b may be formed as low-resistance regions at and near the interfaces of the oxide 530 with the conductors 542a and 542b, respectively.
- the region 543a functions as one of the source region and the drain region
- the region 543b functions as the other of the source region and the drain region.
- a channel formation region is formed in a region sandwiched between the regions 543a and 543b.
- the oxygen concentration of the region 543a may be reduced.
- a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the component of the oxide 530 is formed in the region 543a (region 543b). In such a case, the carrier concentration of the region 543a (region 543b) increases and the region 543a (region 543b) becomes a low resistance region.
- the insulator 544 is provided so as to cover the conductors 542a and 542b, and suppresses oxidation of the conductors 542a and 542b. At this time, the insulator 544 may be provided so as to cover side surfaces of the oxide 530 and the insulator 524 and be in contact with the insulator 522 .
- the insulator 544 is a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, and magnesium. can be used. Silicon nitride oxide or silicon nitride can also be used for the insulator 544 .
- an insulator containing one or both oxides of aluminum and hafnium such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) can be used.
- hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is less likely to be crystallized in heat treatment in a later step.
- the insulator 544 is not essential when the conductors 542a and 542b are made of an oxidation-resistant material or when the conductivity does not significantly decrease even when oxygen is absorbed. It may be appropriately designed depending on the required transistor characteristics.
- impurities such as water and hydrogen contained in the insulator 580 can be prevented from diffusing into the oxide 530b.
- oxidation of the conductor 560 due to excess oxygen in the insulator 580 can be suppressed.
- the insulator 550 functions as a first gate insulating film.
- the insulator 550 is preferably placed in contact with the inside (top and side surfaces) of the oxide 530c.
- the insulator 550 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similarly to the insulator 524 described above.
- silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and vacancies are used.
- silicon oxide and silicon oxynitride are preferable because they are stable against heat.
- the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced.
- the thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.
- a metal oxide may be provided between the insulator 550 and the conductor 560 in order to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530 .
- the metal oxide preferably suppresses diffusion of oxygen from the insulator 550 to the conductor 560 .
- diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, reduction in the amount of excess oxygen supplied to the oxide 530 can be suppressed.
- oxidation of the conductor 560 due to excess oxygen can be suppressed.
- a material that can be used for the insulator 544 may be used.
- the insulator 550 may have a stacked structure similarly to the second gate insulating film. As transistors are miniaturized and highly integrated, thinning of the gate insulating film may cause problems such as leakage current.
- By forming a laminated structure with a material that is relatively stable it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Moreover, it is possible to obtain a laminated structure that is thermally stable and has a high dielectric constant.
- the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 2A and 2B, it may have a single-layer structure or a laminated structure of three or more layers.
- the conductor 560a is a conductor having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (eg, N 2 O, NO, and NO 2 ), and copper atoms. It is preferable to use a flexible material. Alternatively, it is preferable to use a conductive material that has a function of suppressing diffusion of oxygen (for example, one or both of oxygen atoms, acid, and oxygen molecules). Since the conductor 560a has a function of suppressing diffusion of oxygen, oxygen contained in the insulator 550 can suppress oxidation of the conductor 560b and a decrease in conductivity.
- impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (eg, N 2 O, NO, and NO 2 ), and copper atoms. It is preferable to use a flexible material. Alternatively, it is preferable to use a conductive material that has a function of suppressing diffusion
- an oxide semiconductor that can be used for the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b by a sputtering method, the electric resistance value of the conductor 560a can be lowered to make the conductor 560a a conductor. This can be called an OC (Oxide Conductor) electrode.
- a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 560b.
- a conductor with high conductivity is preferably used.
- a conductive material whose main component is tungsten, copper, or aluminum can be used.
- the conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and any of the above conductive materials.
- the insulator 580 is provided over the conductors 542a and 542b with the insulator 544 interposed therebetween.
- Insulator 580 preferably has excess oxygen regions.
- the insulator 580 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or oxide with vacancies. It preferably contains silicone or resin.
- silicon oxide and silicon oxynitride are preferable because they are thermally stable.
- silicon oxide and silicon oxide having vacancies are preferable because an excess oxygen region can be easily formed in a later step.
- the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably low.
- the opening of the insulator 580 is formed so as to overlap a region between the conductors 542a and 542b.
- the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b.
- the conductor 560 is formed in a self-aligned manner, so the transistor 500 is sometimes called a TGSA (Top Gate Self Align) type FET.
- the conductor 560 can have a shape with a high aspect ratio.
- the conductor 560 since the conductor 560 is embedded in the opening of the insulator 580, the conductor 560 can be formed without collapsing during the process even if the conductor 560 has a high aspect ratio. can be done.
- the insulator 574 is preferably provided in contact with the top surface of the insulator 580 , the top surface of the conductor 560 , and the top surface of the insulator 550 .
- excess oxygen regions can be provided in the insulators 550 and 580 . Accordingly, oxygen can be supplied into the oxide 530 from the excess oxygen region.
- the insulator 574 is a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like. be able to.
- aluminum oxide has a high barrier property, and even a thin film of 0.5 nm or more and 3.0 nm or less can suppress the diffusion of hydrogen and nitrogen. Therefore, the aluminum oxide film formed by the sputtering method can function not only as an oxygen supply source but also as a barrier film against impurities such as hydrogen.
- insulator 574, insulator 580, insulator 544, insulator 522, insulator 520, insulator 516, and insulator 514 is removed to surround transistor 500A and to expose insulator 513.
- An insulator 576 having a high barrier property against hydrogen or water is formed. Therefore, each side surface of insulator 574 , insulator 580 , insulator 544 , insulator 522 , insulator 520 , insulator 516 , and insulator 514 is in contact with insulator 576 . Accordingly, moisture and hydrogen can be prevented from entering the transistor 500 from the outside.
- the insulator 513 and the insulator 576 preferably have a high function of suppressing diffusion of hydrogen (eg, one or both of hydrogen atoms and hydrogen molecules) or water molecules.
- the insulators 513 and 576 are preferably made of silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties. Accordingly, hydrogen can be prevented from diffusing into the oxide 530, so deterioration of the characteristics of the transistor 500 can be prevented. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.
- An insulator 581 functioning as an interlayer film and a planarization film is preferably provided over the insulator 576 .
- the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.
- insulators 552 are provided on side surfaces of openings formed in the insulators 581 , 576 , 574 , 580 , and 544 .
- a conductor 540 is provided so as to be in contact with the side surface of the insulator 552 and the bottom surface of the opening. Note that in FIG. 2A, the conductor 540 is provided in a region that overlaps with the conductor 542b and does not overlap with the oxide 530b. In other words, conductor 540 is provided to be positioned between transistor 500A and transistor 500B in FIG.
- the insulator 552 is provided in contact with the insulator 581, the insulator 576, the insulator 574, the insulator 580, and the insulator 544, for example.
- the insulator 552 preferably has a function of suppressing diffusion of hydrogen or water molecules.
- an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide, which is a material with a high hydrogen barrier property, is preferably used.
- silicon nitride is a material with high hydrogen barrier properties, it is preferable to use it as the insulator 552 .
- the reliability of the semiconductor device of one embodiment of the present invention can be improved.
- the conductor 540 can be provided using a material similar to that of the conductor 448, the conductor 458, the conductor 518, or the conductor 503, for example.
- the conductor 540 has a stacked structure of two or more layers, and the first layer in contact with the insulator 552 has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (see above). It is preferable to use a conductive material that is difficult for impurities to permeate), and to use a conductive material containing tungsten, copper, or aluminum as a main component and having high conductivity for the second and subsequent layers.
- an insulator 582 is provided on the insulator 581 .
- the insulator 582 preferably uses a substance that has barrier properties against one or both of oxygen and hydrogen. Therefore, a material similar to that of the insulator 514 can be used for the insulator 582 .
- the insulator 582 is preferably made of metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.
- aluminum oxide has a high shielding effect of blocking oxygen and impurities such as hydrogen or moisture, which cause changes in the electrical characteristics of the transistor, from penetrating through the film; is more preferred.
- An insulator 584 is provided on the insulator 582 .
- a material similar to that of the insulator 443 or the insulator 444 can be used for the insulator 584 .
- the insulator 584 can be a silicon oxide film or a silicon oxynitride film.
- An insulator 588 is provided on the insulator 584 .
- the insulator 588 preferably has barrier properties such that impurities such as water, hydrogen, or oxygen do not diffuse. Therefore, for the insulator 588, for example, a material that can be applied to the insulators 436 and 442 can be used. For the insulator 588, for example, a structure that can be applied to the insulators 436 and 442 can be used.
- insulator 544, insulator 580, insulator 574, insulator 576, insulator 581, insulator 582, insulator 584, and insulator 588 may include the conductive material described above.
- a body 540 is implanted.
- the conductor 540 functions as a via, plug, or wiring that connects the transistors 500A and 500B and a conductor 590, which will be described later.
- a conductor 590 is provided over the insulator 588 and the conductor 540 .
- the conductor 590 functions as a wiring electrically connected to the memory cell of one embodiment of the present invention, as described above.
- the conductor 590 can be made of a material that can be used for the conductor 440 .
- a structure that can be applied to the conductor 440 can be used.
- An insulator 592 is provided on the conductor 590 .
- the insulator 592 preferably has barrier properties such that impurities such as water, hydrogen, or oxygen do not diffuse. Therefore, for the insulator 592, for example, a material that can be applied to the insulators 436 and 442 can be used. For the insulator 592, for example, a structure applicable to the insulators 436 and 442 can be used.
- An insulator 593 is provided on the insulator 592 .
- a material similar to that of the insulator 443 or the insulator 444 can be used for the insulator 593 .
- the insulator 593 can be a silicon oxide film or a silicon oxynitride film.
- the conductor 440 functioning as the wiring BL and the conductor 590 functioning as the wiring SL preferably have regions that overlap with each other. Accordingly, the area of memory cells included in the memory device can be reduced.
- the wiring width of the conductor 590 functioning as the wiring SL is shown to be shorter than the wiring width of the conductor 440 functioning as the wiring BL in the plan view of FIG. 1A, but the wiring width of the conductor 590 is It may be equal to the wiring width of the conductor 440 or may be longer than the wiring width of the conductor 440 .
- the structure of the transistor in the semiconductor device of one embodiment of the present invention is not limited to the structures in FIGS. 1, 2A, and 2B.
- the transistors illustrated in FIGS. 3A and 3B may be used as the transistors that can be applied to the transistors M3 and M4 illustrated in FIGS. 4A and 4B.
- a transistor 500A shown in FIGS. 3A and 3B is a modification of the transistor 500A shown in FIGS. 2A and 2B.
- FIG. 3A shows a cross-sectional view of the transistor 500A in the channel length direction
- FIG. 500A shows a cross-sectional view in the channel width direction.
- Transistor 500A shown in FIGS. 3A and 3B also differs from transistor 500A shown in FIGS. 2A and 2B in that oxide 530c is not provided. Therefore, the insulator 550 is provided on the bottom and side surfaces of the opening formed between the conductors 542 a and 542 b in the insulator 580 , and the conductor 560 is provided on the top surface of the insulator 550 . are placed.
- the transistor 500A illustrated in FIGS. 3A and 3B does not include the oxide 530c, parasitic capacitance between the oxide 530c and the conductor 560 can be eliminated with the insulator 550 interposed therebetween. Thereby, the operating frequency of the transistor 500A can be increased.
- the structure of the transistor in the semiconductor device of one embodiment of the present invention may be a structure other than the transistors illustrated in FIGS. 1A to 3B.
- a semiconductor device of one embodiment of the present invention can be, for example, a planar transistor, a staggered transistor, or an inverted staggered transistor.
- a top-gate transistor whose gate is provided above the semiconductor layer can be used.
- a bottom-gate transistor whose gate is provided below a semiconductor layer for example, a bottom-gate top-contact (BGTC) transistor can be used.
- BGTC bottom-gate top-contact
- a transistor whose gates are provided above and below a semiconductor layer can be used.
- the configuration of the memory cell 600A shown in FIGS. 1A and 1B may be changed to the configuration of the memory cell shown in FIGS. 6A and 6B.
- the memory cell 600B shown in FIGS. 6A and 6B includes transistors 500A and 500B over conductor 590, memory element 400 over transistors 500A and 500B, and conductor 400 over memory element 400. 440 is provided. That is, the memory cell 600B has a configuration in which the stacking order of each component of the memory cell 600A is reversed.
- the memory cell 600B differs from the memory cell 600A shown in FIGS. 1A and 1B in that the conductor 440 is positioned above the conductor 590.
- the wiring BL is provided above the wiring SL.
- the conductor 518 is provided over the conductor 590, and the conductor 542b is provided over the conductor 518.
- the conductor 540 is provided above the conductor 542b to provide electrical continuity between the conductor 542b and the conductor 590, but FIGS. 6A and 6B.
- the conductor 518 is provided under the conductor 542b so that the conductor 542b and the conductor 590 are electrically connected.
- conductors 540 are provided above the conductors 542a and 542c.
- a conductor 457a is provided above the insulator 446 and the conductor 540 that is electrically connected to the conductor 542a.
- a conductor 457b is provided above the insulator 446 and the conductor 540 that is electrically connected to the conductor 542c. Note that a material that can be used for the conductor 457 can be used for the conductors 457a and 457b. Further, when the same material is used for the conductors 457a and 457b, the conductors 457a and 457b can be formed in the same step.
- a conductor 458A is embedded in the insulator 454.
- the conductor 458A functions as a via, plug, or wiring. Therefore, for the conductor 458A, for example, a material that can be applied to the conductor 458 can be used.
- the memory element 400 included in the memory cell 600B differs in configuration from the memory element 400 of FIGS. 1A and 1B.
- the memory element 400 in FIGS. 1A and 1B has a configuration in which the conductor 401, the insulator 402, the conductor 403, and the conductor 404 are stacked in this order, but the memory element 400 in FIGS. 4 has a structure in which a conductor 403, an insulator 402, a conductor 401, and a conductor 404 are stacked in this order. That is, in memory cell 600B of FIGS. 6A and 6B, the first terminal of memory element 400 is electrically connected to conductor 450, which will be described later, and the second terminal of memory element 400 is electrically connected to conductor 457b. It is configured as
- the conductor 404 is provided as a hard mask.
- the conductor 401 functioning as the free layer of the MTJ element assumes a state of magnetic moment due to the current flowing through the conductor 450, which will be described later.
- a close configuration is preferable.
- it is preferable that the conductor 401 and the conductor 450 are in direct contact with each other without providing the conductor 404 .
- a step of thinning the conductor 404 or a step of exposing the conductor 401 may be performed by planarization treatment after the insulator 454 is formed.
- An insulator 476 is provided on the insulator 454 .
- An opening is provided in a region of the insulator 476 that overlaps with the conductor 458A and the conductor 401 .
- a material that can be used for the insulator 446 can be used for the insulator 476 .
- a conductor 450 is provided on the insulator 476 and on the conductor 458A that is the bottom surface of the opening of the insulator 476 and the conductor 401 .
- the conductor 450 becomes conductive with the conductor 458A and the conductor 401 .
- the conductor 450 preferably comprises a metal material that causes the spin Hall effect, similar to the conductor 450 of FIGS. 1A and 1B. Therefore, for the conductor 450, for example, a material that can be applied to the layer CA shown in FIG. 5 can be used.
- An insulator 478 is provided on the conductor 450 and the insulator 476 .
- a material that can be applied to the insulator 446 can be used.
- An insulator 443 , an insulator 444 and an insulator 436 are provided in this order on the insulator 478 .
- a conductor 448 is embedded in the insulator 443 , the insulator 444 , and the insulator 436 .
- a conductor 440 is provided over the conductor 448 and the insulator 436 . This electrically connects the conductor 440 to the first terminal of the memory element 400 and the first terminal of the transistor 500A.
- the memory cell 600B of FIGS. 6A and 6B can be applied to a memory device, like the memory cell 600A of FIGS. 1A and 1B.
- the semiconductor device of one embodiment of the present invention includes the memory cell 600B in FIGS. 6A and 6B above the memory cell 600A in FIGS. 1A and 1B as a structure in which the conductor 590 is shared with each other, for example. It is good also as a structure provided.
- the semiconductor device of one embodiment of the present invention may have a structure illustrated in FIG. 7, for example.
- FIG. 7 shows a configuration example of a semiconductor device including a layer OSLa including the memory cells 600A of FIGS. 1A and 1B and a layer OSLb including the memory cells 600B of FIGS. 6A and 6B. Note that the layer OSLb is provided above the layer OSLa.
- memory cell 600 A and memory cell 600 B are electrically connected to conductor 590 .
- the conductor 590 functions as a wiring SL for each of the memory cells 600A and 600B.
- the memory cell 600A and the memory cell 600B overlap each other so as to share the conductor 590 functioning as the wiring SL, thereby increasing the storage capacity per unit volume of the semiconductor device. can do.
- FIGS. 6A and 6B show a structure in which the memory cell 600A and the memory cell 600B are electrically connected to the conductor 590, a structure in which the conductor 440 is shared is shown in FIGS. 6A and 6B.
- 1A and 1B may be provided above the memory cell 600B. That is, the memory cell 600A and the memory cell 600B may be electrically connected to the conductor 440 functioning as the wiring BL (see FIG. 8).
- another layer OSLa is further provided above the layer OSLb, and the memory cell 600B in the layer OSLb and the memory cell 600A in the other layer OSLa are electrically connected to the conductor 440 functioning as the wiring BL. (not shown).
- memory cells 600A and memory cells 600B are alternately stacked, and the wiring SL (conductor 590) is shared between the memory cell 600A positioned below and the memory cell 600B positioned above. may be configured.
- memory cells 600A and memory cells 600B are alternately stacked, and the wiring BL (conductor 440) is shared between the lower memory cell 600B and the upper memory cell 600A. It is good also as a structure which carries out.
- the semiconductor device of one embodiment of the present invention may have the structures illustrated in FIGS. 10A and 10B.
- a memory cell 600A shown in FIGS. 10A and 10B is a modification of the memory cell 600A shown in FIGS. 1A and 1B. different.
- the transistor 500A and the transistor 500B are formed so as to share the insulator 524, the oxide 530a, and the oxide 530b.
- the opening to be filled with the conductor 540 is provided in a region between the conductor 560A and the conductor 560B where the insulator 524, the oxide 530a, and the oxide 530b overlap with each other.
- the area where the transistor 500A and the transistor 500B are formed can be made smaller than the area where the transistor 500A and the transistor 500B are separately formed as shown in FIGS. 1A and 1B.
- the area for forming the memory cell 600A can be reduced, so that the area per bit can be reduced as a bit density.
- the semiconductor device of one embodiment of the present invention may have the structures illustrated in FIGS. 11A and 11B.
- a memory cell 600A shown in FIGS. 11A and 11B is a modified example of the memory cell 600A shown in FIGS. 10A and 10B. different.
- the transistors 500A and 500B have a structure in which the conductors 542a to 542c are formed only over the oxide 530b.
- a method for manufacturing the transistors 500A and 500B for example, an insulator 524, an oxide 530a, an oxide 530b, and conductive films to be conductors 542a to 542c are sequentially stacked over an insulator 522. Then, the insulator 524, the oxide 530a, and the oxide 530a are separated by etching treatment or the like so that the side surfaces of the insulator 524, the oxide 530a, and the oxide 530b and the top surface of the insulator 522 are exposed.
- the conductive films to be the conductors 530b and the conductors 542a to 542c may be processed. Thus, conductors 542a to 542c are formed only over the oxide 530b.
- memory cell 600A in FIGS. 11A and 11B part of the structures of the insulators and conductors provided above the transistors 500A and 500B are different from those in the memory cell 600A in FIGS. different.
- memory cell 600A in FIGS. 11A and 11B has insulator 586 over insulator 583 and conductor 585A over insulator 586, conductor 540A, and conductor 540B.
- a conductor 585B is provided over the insulator 586, the conductor 540C, and the conductor 540D
- an insulator 591 is provided over the insulator 586, the conductor 585A, and the conductor 585B.
- an insulator 584 is provided over the insulator 591, which is different from the memory cell 600A in FIGS. 10A and 10B.
- the insulator 586 can be formed in the same process as the insulator 446, for example. Therefore, a material that can be used for the insulator 446 can be used for the insulator 586 .
- the first terminal of the transistor 500A, the first terminal of the memory element 400, and the conductor 440 are electrically connected.
- a conductor 540A and a conductor 540B are embedded in each of them. Specifically, openings are provided in regions of the insulator 580, the insulator 574, the insulator 576, the insulator 581, the insulator 582, the insulator 583, and the insulator 586 described later, which overlap with the conductor 542a.
- a conductor 540A is embedded in the opening.
- the insulator 520, the insulator 522, the insulator 544, the insulator 580, the insulator 574, and the insulator overlapping with the conductor 518 (the conductor 458) electrically connected to the first terminal of the memory element 400 576, the insulator 581, the insulator 582, the insulator 583, and the insulator 586 are provided with openings, and the conductors 540B are embedded in the openings.
- a conductor 540C and a conductor 540D are embedded at predetermined locations. Specifically, openings are provided in regions of the insulators 580, 574, 576, 581, 582, 583, and 586 which overlap with the conductor 542c. A conductor 540C is embedded in the portion. Insulators 520 , 522 , 544 , 544 , 580 , 574 , 576 , and 581 overlap with the conductor 518 electrically connected to the second terminal of the memory element 400 . , the insulator 582, the insulator 583, and the insulator 586 are provided with openings, and the conductors 540D are embedded in the openings.
- the conductors 540A to 540D can be formed in the same process as the conductor 540, for example. Therefore, a material that can be used for the conductor 540 can be used for the conductors 540A to 540D. Insulators 552 may be provided on the side surfaces of the openings provided with the conductors 540A to 540D, similarly to the side surfaces of the openings provided with the conductor 540A.
- a conductor 585A is provided over the insulator 586, the conductor 540A, and the conductor 540B.
- a conductor 585B is provided above the insulator 586, the conductor 540C, and the conductor 540D.
- the conductors 585A and 585B can be formed in the same process as the conductor 450, for example. Therefore, a material that can be used for the conductor 450 can be used for the conductor 585A and the conductor 585B.
- An insulator 591 is provided over the insulator 586, the conductor 585A, and the conductor 585B.
- the insulator 591 can be formed through a process similar to that of the insulator 452, for example. Therefore, a material that can be used for the insulator 452 can be used for the insulator 591 .
- One or more memory cells 600A (or By using the memory cell 600B), the area of the memory cell included in the memory device can be reduced. Accordingly, the memory capacity per unit area of the memory device can be increased.
- the memory cell MC shown in FIG. 4C is a modified example of the memory cell MC shown in FIG. 4A, and the memory cell MC shown in FIG. 4C can also be included in the storage device.
- the memory cell MC in FIG. 4C differs from the memory cell MC in FIG. 4A in that the wiring SL is changed to two wirings WBL and RBL, and that the wiring BL is changed to the wiring SL.
- the second terminal of the transistor M3 is electrically connected to the wiring WBL, and the second terminal of the transistor M4 is electrically connected to the wiring RBL.
- a terminal IT1 of the resistance change device MD is electrically connected to the wiring SL.
- the wiring WBL functions as a write bit line, for example.
- the wiring RBL functions as a read bit line, for example.
- the wiring SL functions as a wiring for applying a constant voltage, for example.
- the wiring SL is supplied with a low-level potential, for example.
- a high-level potential is applied to the wiring WLa to turn on the transistor M3, and a low-level potential is applied to the wiring WLb to turn off the transistor M4.
- a first potential higher than the low-level potential of the wiring SL is applied from the wiring WBL to the terminal IT2.
- a current flows between the terminals IT1 and IT2 according to the potential difference between the first potential and the low-level potential of the wiring SL. Therefore, a current flows through the layer CA of the MTJ element ME, a spin current is generated in the layer CA, and the magnetization direction of the ferromagnetic material of the layer FL is determined by the spin current.
- a low-level potential is applied to the wiring WLa to turn off the transistor M3, and a high-level potential is applied to the wiring WLb to turn on the transistor M4.
- a second potential higher than the low-level potential of the wiring SL from the wiring RBL to the terminal OT current flows between the terminal IT1 and the terminal OT.
- the electric resistance value of the MTJ element ME changes depending on whether the magnetization directions of the layers RL and FL are parallel or antiparallel, so the amount of tunnel current flowing through the layer TIS of the MTJ element ME also change. That is, the information recorded in the MTJ element ME can be read by measuring the amount of current flowing through the terminal IT1. Information recorded in the MTJ element ME can also be read out by flowing a constant current between the wiring SL and the wiring RBL and measuring the potential of the terminal OT or the terminal IT1.
- FIG. 12A and 12B show configuration examples of the memory cell MC in FIG. 4C, which is a semiconductor device of one embodiment of the present invention.
- FIG. 12A is a plan view schematically showing a configuration example of the memory cell 600C
- FIG. 12B is a cross-sectional view schematically showing a configuration example of the memory cell 600C included in the layer OSL. is.
- FIG. 12B is a cross-sectional view along the dashed-dotted line A1-A2 shown in FIG. 12A.
- FIG. 12A also illustrates conductor 590, conductor 560A, conductor 560B, conductor 542aA, conductor 542aB, conductor 542bA, conductor 542bB, oxide 530bA, oxide 530bB, memory element 400, conductor 450, Only conductors 518A, 518B, 540A, 540B, and 440 are selectively shown.
- memory cell 600C has transistor 500A, memory element 400 located above transistor 500A, and transistor 500B located above memory element 400.
- transistor 500A and the transistor 500B may be referred to as the transistor 500 in some cases.
- the transistor 500A corresponds to the transistor M3, the transistor 500B corresponds to the transistor M4, and the memory element 400 corresponds to the resistance change device MD.
- the conductor 440 corresponds to the wiring WBL, the conductor 450 corresponds to the wiring SL, and the conductor 590 corresponds to the wiring RBL.
- the conductor 560A corresponds to the wiring WLa, and the conductor 560B corresponds to the wiring WLb.
- An insulator 434, an insulator 436, a conductor 440, an insulator 442, and an insulator 512 are provided in this order below the transistor 500A.
- the transistor 500A includes a conductor 542aA functioning as one of a source and a drain, a conductor 542bA functioning as the other of the source and the drain, an oxide 530bA in which a channel formation region is formed, and a conductor 560A functioning as a gate. , has
- the conductor 542bA is electrically connected to the conductor 440 via the conductor 518A.
- the conductor 542aA is electrically connected to the conductor 450, which will be described later, through the conductor 540A.
- an insulator 582, an insulator 584, and an insulator 446 are provided in this order from bottom to top.
- a conductor 450 is provided on the conductor 540A and the insulator 446 . Furthermore, the memory element 400 is provided on the conductor 450 . 12B, a conductor 401, an insulator 402, a conductor 403, and a conductor 404 are provided in this order from bottom to top.
- the conductor 450 also extends in the channel width direction of the transistors 500A and 500B in the region ARA shown in FIG. 12B (see FIG. 12A).
- An insulator 452, an insulator 454, and an insulator 476 are provided on the conductor 450 and the insulator 446 in this order from bottom to top.
- a conductor 457 c is provided over the insulator 476 and the conductor 404 . Note that the description of the conductors 457a and 457b described in Structural Example 2 can be referred to for the conductor 457c.
- An insulator 478 is provided over the insulator 476 and the conductor 457c. Note that the description of the insulator 478 in Structural Example 2 can be referred to for the insulator 478 .
- a transistor 500B is provided above the insulator 476 .
- the transistor 500B includes a conductor 542aB functioning as one of the source and the drain, a conductor 542bB functioning as the other of the source and the drain, an oxide 530bB in which a channel formation region is formed, and a conductor 560B functioning as the gate. , has
- the conductor 542bB is electrically connected to the conductor 404 via the conductor 518B.
- the conductor 542aB is electrically connected to a conductor 590 described later through the conductor 540B.
- An insulator 588, a conductor 590, an insulator 592, and an insulator 593 are provided in this order from the bottom to the top above the transistor 500B.
- the memory cell 600C illustrated in FIGS. 12A and 12B has a region where the conductor 440 functioning as the wiring WBL and the conductor 590 functioning as the wiring RBL overlap with each other, and function as the gate of the transistor 500A.
- the area of the memory cells included in the memory device can be reduced. Accordingly, the memory capacity per unit area of the memory device can be increased.
- the memory cell 600C in FIGS. 12A and 12B described above has a structure in which the conductor 440 functioning as the wiring WBL and the conductor 590 functioning as the wiring RBL overlap each other.
- a wiring that functions as the wiring SL may also be provided in a region overlapping with the conductor 440 and the conductor 590 .
- FIG. 13 shows a configuration of a memory cell having a region where the conductor 440 functioning as the wiring WBL, the conductor 590 functioning as the wiring RBL, and the wiring SL overlap with each other.
- the conductor 590 since the conductor 590 is positioned above the conductor 440 and the wiring SL, the conductor 590 does not necessarily have to be provided in a region where the conductor 440 and the wiring SL overlap.
- the semiconductor device of one embodiment of the present invention may have a structure in which the conductor 590 does not overlap with the conductor 440 and the wiring SL in the memory cell 600C illustrated in FIG.
- the memory cell 600C shown in FIG. 13 has a three-dimensional structure, arrows indicating the x-direction, y-direction, and z-direction are attached.
- the x-direction, the y-direction, and the z-direction here are shown as directions perpendicular to each other as an example.
- one of the x-direction, y-direction, and z-direction may be referred to as a "first direction” or a "first direction.”
- the other one may be called a "second direction” or a "second direction.”
- the remaining one may be called "third direction” or "third direction”.
- a memory cell 600C in FIG. 13 has layers LY1 to LY6 as an example. Also, in the memory cell 600C of FIG. 13, layers LY1 to LY6 are stacked in order from the bottom. In the memory cell 600C of FIG. 13, the laminate of layers LY1 and LY2 is layer LY1-2, the laminate of layers LY3 and LY4 is layer LY3-4, and the layer LY5 and layer LY6 are stacked. Let the body be layer LY5-6. Therefore, in the memory cell 600C of FIG. 13, layers LY1-2, LY3-4, and LY5-6 are laminated in order from the bottom.
- the layer LY1 includes a transistor 500A.
- Layer LY2 also includes a conductor 440 .
- Layer LY3 also includes conductors 450 and memory elements 400 .
- the layer LY4 includes the wiring SL.
- Layer LY5 also includes transistor 500B.
- Layer LY6 also includes a conductor 590 .
- the memory element 400 is provided on the conductor 450, similar to the memory cell 600C of FIG. 12B.
- a conductor 401, an insulator 402, a conductor 403, and a conductor 404 are formed in this order from below (reference numerals are not shown), as in the memory cell 600C of FIG. 12B.
- each of the conductor 440, the conductor 590, and the wiring SL, which overlap each other, extends in the x direction.
- the transistor 500A and the transistor 500B are arranged so that the channel length direction is the x direction.
- the memory cell 600C in FIG. 13 has a conductor 560A functioning as the gate (wiring WLa) of the transistor 500A and a conductor 560A functioning as the gate (wiring WLb) of the transistor 500B.
- 560B and 560B have areas that overlap each other. Also, each of the conductor 560A and the conductor 560B extends in the y direction.
- each of the transistors 500A and 500B in the memory cell 600C of FIG. 13 may have a conductor 503 corresponding to a back gate.
- vias or plugs are provided between the upper and lower layers.
- conductor 518A that functions as a via or plug between layers LY1 and LY2 to electrically connect one of the sources or drains of transistor 500A in layer LY1 and conductor 440 in layer LY2.
- a conductive material that functions as a via or plug between the layers LY1 and LY3 to electrically connect the other of the source or drain of the transistor 500A in the layer LY1 and the conductor 450 in the layer LY3.
- a body 540A is provided.
- a conductor VA functioning as a via or a plug is provided between the layers LY3 and LY4 in order to electrically connect the conductor 450 of the layer LY3 and the wiring SL of the layer LY4.
- a conductor 450 of the layer LY3 and the wiring SL of the layer LY4.
- An electrical conductor 518B is provided.
- a conductive layer that functions as a via or plug between the layers LY5 and LY6 to electrically connect the other of the source or drain of the transistor 500B in the layer LY5 and the conductor 590 in the layer LY6.
- a body 540B is provided.
- the conductor 440 functioning as the wiring WBL, the conductor 590 functioning as the wiring RBL, and the wiring SL can be overlapped with each other. circuit area can be reduced.
- the stacking order of the layers LY1 to LY6 of the memory cell 600C which is a semiconductor device of one embodiment of the present invention, is not limited to that in FIG.
- the layer LY2 may be provided below the layer LY1
- the layer LY4 may be provided above the layer LY2 and below the layer LY3
- the layer LY6 may be provided above and below the layer LY4. It may be provided below the layer LY5 (not shown in either case).
- the configuration in which the layer LY2 is provided above the layer LY3 and below the layer LY4 is not suitable because the conductor 440 and the conductor VA intersect. Also, the configuration in which the layer LY2 is provided above the layer LY4 is not suitable because the wiring SL and the conductor 518A intersect. Also, the configuration in which the layer LY4 is provided below the layer LY2 is not suitable because the conductor 440 and the conductor VA intersect. A configuration in which the layer LY4 is provided above the layer LY5 and below the layer LY6 is also inappropriate because the wiring SL and the conductor 540B intersect. A configuration in which the layer LY4 is provided above the layer LY6 is also inappropriate because the conductor 590 and the conductor VA intersect. Also, the configuration in which the layer LY6 is provided below the layer LY4 is also inappropriate because the wiring SL and the conductor 540B intersect.
- the layer LY1 can be positioned below or above the layer LY2. Also, in layers LY3-4 of memory cell 600C of FIG. 13, layer LY3 can be located above or below layer LY4. Also, in layers LY5-6 of memory cell 600C of FIG. 13, layer LY5 can be located above or below layer LY6.
- the transistors 500A and 500B are not limited to OS transistors and may be other transistors.
- the transistor 500A when the memory cell 600C is formed on a semiconductor substrate, the transistor 500A can be a transistor formed on the semiconductor substrate when the layer LY1 of the memory cell 600C in FIG. 13 is located below the layer LY2. can.
- the transistor 500A can be a transistor (Si transistor) including silicon in a channel formation region.
- the structures of the transistor 500A and the transistor 500B in the memory cell 600C, which are semiconductor devices of one embodiment of the present invention, are not limited to those in FIG.
- the structures of the transistor 500A and the transistor 500B in the memory cell 600C, which are semiconductor devices of one embodiment of the present invention, may be changed as appropriate.
- the channel length direction of the transistor 500A and the transistor 500B does not have to be the X direction.
- the transistor 500A may be provided with the straight line passing through the conductor 540A and the conductor 518A as the channel length direction of the transistor 500A.
- the transistor 500B may be provided in the layer LY5 so that the channel length direction of the transistor 500B is a straight line passing through the conductor 540B and the conductor 518B.
- FIG. 4D shows an example of a memory cell that can be included in a storage device that differs from FIGS. 4A-4C.
- the memory cell MC shown in FIG. 4D is also an example of SOT-MRAM, like the memory cell MC shown in FIG. 4A.
- a memory cell MC in FIG. 4D has, for example, a transistor M3, a resistance change device MD, and a diode DI.
- the description of the transistor M3 and the resistance change device MD in FIG. 4A can be referred to.
- the diode DI has a rectifying action.
- a semiconductor diode, a constant voltage diode, a tunnel diode, or a Schottky barrier diode can be used for the diode DI, for example.
- a first terminal of the transistor M3 is electrically connected to the terminal IT2 of the resistance change device MD, a second terminal of the transistor M3 is electrically connected to the wiring SL, and a gate of the transistor M3 is electrically connected to the wiring WLa. It is connected to the.
- a cathode of the diode DI is electrically connected to the terminal OT of the resistance change device MD, and an anode of the diode DI is electrically connected to the wiring RAL.
- a terminal IT1 of the resistance change device MD is electrically connected to the wiring BL.
- the wiring RAL functions as a read bit line for the memory cell MC. Specifically, for example, a low-level potential is applied to the wiring RAL when data is written to the memory cell MC, and a high-level potential is applied to the wiring RAL when data is read from the memory cell MC.
- the wiring SL is supplied with a low-level potential, for example.
- the low-level potential is preferably equal to the potential of the terminal IT1 or the potential of the terminal IT2. is preferably a low potential.
- a third potential higher than the low-level potential applied to the wiring SL is applied from the wiring BL to the terminal IT1.
- a current flows between the terminals IT1 and IT2 according to the potential difference between the third potential and the low-level potential of the wiring SL. Therefore, a current flows through the layer CA of the MTJ element ME, a spin current is generated in the layer CA, and the magnetization direction of the ferromagnetic material of the layer FL is determined by the spin current.
- a low-level potential is applied to the wiring WLa to turn off the transistor M3.
- a high-level potential is applied to the wiring RAL.
- a fourth potential lower than the high-level potential applied to the wiring RAL from the wiring BL to the terminal IT1 a current flows between the terminal IT1 and the terminal OT.
- the electric resistance value of the MTJ element ME changes depending on whether the magnetization directions of the layers RL and FL are parallel or antiparallel, so the amount of tunnel current flowing through the layer TIS of the MTJ element ME also change.
- information recorded in the MTJ element ME can be read by measuring the amount of current flowing through the MTJ element ME and the terminal IT1.
- Information recorded in the MTJ element ME can also be read by applying a predetermined potential to the wiring SL, flowing a constant current from the wiring BL to the terminal IT1 of the MTJ element ME, and measuring the potential of the terminal IT1.
- FIG. 15A and 15B show configuration examples of the memory cell MC in FIG. 4D, which is a semiconductor device of one embodiment of the present invention.
- FIG. 15A is a plan view schematically showing a configuration example of the memory cell 600D
- FIG. 15B is a cross-sectional view schematically showing a configuration example of the memory cell 600D included in the layer OSL. is.
- FIG. 15B is a cross-sectional view along the dashed-dotted line A1-A2 shown in FIG. 15A.
- FIG. 15A also illustrates a conductor 590, a conductor 440, a conductor 560A, a conductor 542a, a conductor 542b, an oxide 530bA, a conductor 457e, a memory element 400, a conductor 450, a conductor 448, a conductor 540, and conductors 518 are shown.
- the memory cell 600D has a diode 700, a memory element 400 located above the diode 700, and a transistor 500A located above the memory element 400.
- FIGS. 1-10 the memory cell 600D has a diode 700, a memory element 400 located above the diode 700, and a transistor 500A located above the memory element 400.
- the transistor 500A corresponds to the transistor M3
- the diode 700 corresponds to the diode DI
- the memory element 400 corresponds to the resistance change device MD.
- the conductor 440 corresponds to the wiring BL
- the conductor 590 corresponds to the wiring SL
- the conductor 457e corresponds to the wiring RAL.
- the conductor 560A corresponds to the wiring WLa.
- an insulator 434, an insulator 436, a conductor 440, an insulator 442, an insulator 443, an insulator 444, and an insulator 446 are provided in this order from bottom to top.
- conductors 448 are embedded in the insulators 442 , 443 , 444 , and 446 .
- a conductor 457 d is provided over the insulator 446 and the conductor 448 .
- a conductor 457 e is provided over the insulator 446 . Note that the description of the conductors 457a and 457b in Structure Example 2 can be referred to for the conductors 457d and 457e.
- a diode 700 is provided on the conductor 457e.
- the structure of the diode 700 can be, for example, a laminate of a semiconductor 701 that is a p-type semiconductor and a semiconductor 702 that is an n-type semiconductor.
- the diode 700 may be called a pn junction diode.
- the diode 700 may be a Schottky barrier diode in which the semiconductor 701 is changed to a metal material, for example.
- An insulator 711 and an insulator 712 are provided over the insulator 446, the conductor 457d, and the conductor 457e.
- the insulator 711 can be formed through a process similar to that of the insulator 452 described in Structural Example 1, for example. Therefore, a material that can be used for the insulator 452 can be used for the insulator 711 .
- the insulator 712 can be formed through a process similar to that of the insulator 454 described in Structural Example 1, for example. Therefore, a material that can be used for the insulator 454 can be used for the insulator 712 .
- a conductor 721 is embedded in the insulator 711 and the insulator 712 .
- the description of the conductor 458A in Structural Example 2 can be referred to.
- An insulator 496 is provided on the insulator 711 and the insulator 712 .
- the insulator 496 can be formed through a process similar to that of the insulator 476 described in Structural Example 2, for example. Therefore, a material that can be used for the insulator 476 can be used for the insulator 496 .
- a conductor 457 a is provided over the insulator 496 and the conductor 721 .
- a conductor 457 b is provided over the insulator 496 and the semiconductor 702 .
- a memory element 400 is provided over the conductor 457b. Further, in the memory element 400, the conductor 403, the insulator 402, the conductor 401, and the conductor 404 are stacked in this order over the conductor 457b.
- An insulator 498 and an insulator 454 are provided over the conductor 457 a , the conductor 457 b , and the insulator 496 .
- a conductor 458 A is embedded in the insulator 498 and the insulator 454 .
- An insulator 476 is provided on the insulator 454 .
- An opening is provided in a region of the insulator 476 that overlaps with the conductor 458A and the conductor 401 .
- a conductor 450 is provided over the insulator 476 , the conductor 458 A that is the bottom surface of the opening of the insulator 476 , and the conductor 401 .
- the conductor 450 becomes conductive with the conductor 458A and the conductor 401 .
- the conductor 450 preferably comprises a metal material that causes the spin Hall effect, similar to the conductor 450 of FIGS. 1A and 1B. Therefore, for the conductor 450, for example, a material that can be applied to the layer CA shown in FIG. 5 can be used.
- a transistor 500A is provided above the conductor 450 .
- the transistor 500A includes a conductor 542a functioning as one of a source and a drain, a conductor 542b functioning as the other of the source and the drain, an oxide 530bA in which a channel formation region is formed, and a conductor 560A functioning as a gate. , has
- the conductor 542 b is electrically connected to the conductor 450 via the conductor 518 .
- the conductor 542a is electrically connected to a conductor 590, which will be described later, through the conductor 540.
- An insulator 588, a conductor 590, an insulator 592, and an insulator 593 are provided in this order from the bottom to the top above the transistor 500A.
- a memory cell 600D illustrated in FIGS. 15A and 15B has a region where the conductor 440 functioning as the wiring BL and the conductor 590 functioning as the wiring SL overlap with each other, and functions as the gate of the transistor 500A.
- the area of the memory cell included in the memory device can be reduced. Accordingly, the memory capacity per unit area of the memory device can be increased.
- the memory cell 600D in FIGS. 15A and 15B has a configuration in which the memory element 400 and the diode 700 are provided below the conductor 450. and the transistor 500A.
- the memory element 400 is formed over the conductor 450, and further above the memory element 400 via the conductor 457b. , may form a diode 700 .
- the conductor 457 e functioning as the wiring RAL is formed over the diode 700 .
- the memory element 400 in FIG. 16A differs from the memory element 400 in FIGS. 15A and 15B in that the stacking order of the conductor 401, the insulator 402, and the conductor 403 is reversed.
- the diode 700 in FIG. 16A differs from the diode 700 in FIGS. 15A and 15B in that the stacking order of the semiconductors 701 and 702 is reversed.
- the memory cell 600D in FIGS. 15A to 16A has a structure in which the conductor 590 is provided above the conductor 440; however, the conductor 440 may be provided above the conductor 590. .
- the transistor 500A, the memory element 400, the diode 700, and the conductor 440 may be sequentially provided after the conductor 590 is formed.
- the area of the memory cell included in the storage device can be reduced. Accordingly, the memory capacity per unit area of the memory device can be increased.
- memory cells 600A to 600D retain data using MTJ elements, power required to retain data can be reduced unlike DRAM and SRAM. Therefore, by configuring a memory cell having an MTJ element, a semiconductor device with low power consumption can be configured.
- the insulator, conductor, or semiconductor disclosed in this specification and the like can be formed by a PVD (Physical Vapor Deposition) method or a CVD method.
- PVD methods include, for example, a sputtering method, a resistance heating vapor deposition method, an electron beam vapor deposition method, or a PLD (Pulsed Laser Deposition) method.
- a CVD method a plasma CVD method or a thermal CVD method can be used as a CVD method.
- the thermal CVD method includes, for example, the MOCVD (Metal Organic Chemical Vapor Deposition) method, the ALD (Atomic Layer Deposition) method, and the like.
- the thermal CVD method does not use plasma, so it has the advantage of not generating defects due to plasma damage.
- a raw material gas and an oxidizing agent are sent into a chamber at the same time, the inside of the chamber is made to be under atmospheric pressure or reduced pressure, and a film is formed by reacting near or on the substrate and depositing it on the substrate. .
- the inside of the chamber may be under atmospheric pressure or reduced pressure
- raw material gases for reaction are sequentially introduced into the chamber
- film formation may be performed by repeating the order of gas introduction.
- switching the switching valves also called high-speed valves
- two or more source gases are sequentially supplied to the chamber, and the first source gas is supplied simultaneously with or after the first source gas so as not to mix the two or more source gases.
- An active gas for example, argon or nitrogen
- the inert gas serves as a carrier gas, and the inert gas may be introduced at the same time as the introduction of the second raw material gas.
- the second source gas may be introduced after the first source gas is exhausted by evacuation.
- the first source gas adsorbs on the surface of the substrate to form a first thin layer, which reacts with the second source gas introduced later to form a second thin layer on the first thin layer. is laminated to form a thin film.
- a thin film with excellent step coverage can be formed by repeating this gas introduction sequence several times until a desired thickness is obtained. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, and this method is suitable for manufacturing fine FETs.
- Thermal CVD such as MOCVD or ALD can form various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described above.
- Trimethylindium (In( CH3 ) 3 ), trimethylgallium (Ga( CH3 ) 3 ), and dimethylzinc (Zn( CH3 ) 2 ) are used to form the —O film.
- triethylgallium (Ga(C 2 H 5 ) 3 ) can be used instead of trimethylgallium
- diethylzinc Zn(C 2 H 5 ) 2
- dimethylzinc can also be used.
- a liquid containing a solvent and a hafnium precursor compound for example, hafnium alkoxide or tetrakisdimethylamide hafnium (TDMAH, Hf[N( CH3) ) 2 ] 4
- hafnium precursor compound for example, hafnium alkoxide or tetrakisdimethylamide hafnium (TDMAH, Hf[N( CH3) ) 2 ] 4
- ozone O 3
- Other materials include tetrakis(ethylmethylamido)hafnium.
- a liquid containing a solvent and an aluminum precursor compound for example, trimethylaluminum (TMA, Al(CH 3 ) 3 )
- TMA trimethylaluminum
- H 2 O oxidizing agent
- Other materials also include tris(dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).
- hexachlorodisilane is adsorbed on the film formation surface to generate radicals of an oxidizing gas (for example, O 2 or dinitrogen monoxide). feed to react with the adsorbate.
- an oxidizing gas for example, O 2 or dinitrogen monoxide
- WF 6 gas and B 2 H 6 gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF 6 gas and H The two gases are sequentially and repeatedly introduced to form a tungsten film.
- SiH4 gas may be used instead of B2H6 gas .
- a precursor generally, for example, a precursor or a metal precursor
- an oxidizing agent generally, for example, sometimes referred to as a reactant, a reactant, or a non-metallic precursor
- a precursor In(CH 3 ) 3 gas and an oxidizing agent O 3 gas are introduced to form an In—O layer, and then a precursor Ga(CH 3 ) 3 gas and An oxidant O 3 gas is introduced to form a GaO layer, and then a precursor Zn(CH 3 ) 2 gas and an oxidant O 3 gas are introduced to form a ZnO layer.
- a precursor In(CH 3 ) 3 gas and an oxidizing agent O 3 gas are introduced to form an In—O layer
- a precursor Ga(CH 3 ) 3 gas and An oxidant O 3 gas is introduced to form a GaO layer
- a precursor Zn(CH 3 ) 2 gas and an oxidant O 3 gas are introduced to form a ZnO layer.
- mixed oxide layers such as an In--Ga--O layer, an In--Zn--O layer, and a Ga--Zn--O layer may be formed using these gases.
- H 2 O gas obtained by bubbling water with an inert gas such as Ar may be used instead of O 3 gas, it is preferable to use O 3 gas that does not contain H.
- In(C 2 H 5 ) 3 gas may be used instead of In(CH 3 ) 3 gas.
- Ga(C 2 H 5 ) 3 gas may be used instead of Ga(CH 3 ) 3 gas.
- Zn(CH 3 ) 2 gas may be used.
- FIG. 17 shows the structure of a storage device of one embodiment of the present invention.
- the memory device MDV has a peripheral circuit PHL and a memory cell array MCA.
- the peripheral circuit PHL has a row decoder 2621 , a word line driver circuit 2622 , a bit line driver circuit 2630 , an output circuit 2640 and a control logic circuit 2660 .
- the bit line driver circuit 2630 has a column decoder 2631, a precharge circuit 2632, a sense amplifier 2633, and a write circuit 2634.
- the precharge circuit 2632 has a function of precharging a wiring (not shown in FIG. 17) electrically connected to a memory cell MC, which will be described later, to a predetermined potential.
- the sense amplifier 2633 has a function of acquiring the potential (or current) read from the memory cell MC as a data signal and amplifying the data signal. The amplified data signal is output to the outside of the memory device MDV via the output circuit 2640 as a digital data signal RDATA.
- the memory device MDV is externally supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit PHL, and a power supply voltage (VIL) for the memory cell array MCA as power supply voltages.
- VSS low power supply voltage
- VDD high power supply voltage
- VIL power supply voltage
- control signals CE, WE, RE
- an address signal ADDR a data signal WDATA
- CE, WE, RE control signals
- ADDR an address signal
- WDATA data signal
- the control logic circuit 2660 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 2621 and column decoder 2631 .
- CE is a chip enable signal
- WE is a write enable signal
- RE is a read enable signal.
- the signal processed by the control logic circuit 2660 is not limited to this, and other control signals may be input as necessary.
- the configuration example of the present embodiment is not limited to the configuration of FIG.
- the configuration may be appropriately changed such that all or part of the peripheral circuit PHL is provided in the lower layer of the memory cell array MCA.
- the memory device MDV may have a configuration in which the peripheral circuit PHL is provided in the lower layer and the memory cell array MCA is provided above the peripheral circuit PHL.
- the memory cell array MCA has m ⁇ n memory cells MC as an example.
- the memory cells MC are arranged in a matrix of m rows and n columns. Note that in FIG. 18A, of the plurality of memory cells MC, memory cell MC[1,1], memory cell MC[m,1], memory cell MC[1,n], and memory cell MC[m,n] are It is shown as an excerpt.
- the peripheral circuit PHL has a circuit WD, a circuit BD, a circuit SD, a circuit CLC, and a circuit OPC.
- Peripheral circuit PHL does not include all of circuit WD, circuit BD, circuit SD, circuit CLC, and circuit OPC. , the circuit OPC, and one or more circuits selected from.
- the circuit WD can be, for example, a circuit corresponding to the word line driver circuit 2622 in FIG. Further, for example, the circuit WD is electrically connected to the wirings WL[1] to WL[m]. The circuit WD functions to transmit selection signals to the memory cells MC included in the memory cell array MCA through the wirings WL[1] to WL[m].
- FIG. 18A shows an example in which one wiring WL[1] to WL[m] is provided for each row of the memory cell array MCA, a plurality of wirings are provided for one row of the memory cell array MCA. Wiring may be provided.
- the circuit BD can be, for example, a circuit corresponding to the bit line driver circuit 2630 in FIG. Further, for example, the circuit BD is electrically connected to the wirings BL[1] to BL[n].
- the circuit BD functions as a circuit for transmitting a write signal to the memory cells MC included in the memory cell array MCA through the wirings BL[1] to BL[n].
- the circuit BD functions as a circuit that applies a predetermined voltage or current during reading to the memory cells MC included in the memory cell array MCA through the wirings BL[1] to BL[n]. .
- FIG. 18A shows an example in which one wiring BL[1] to one wiring BL[n] is provided for each column of the memory cell array MCA, a plurality of wirings are provided for one column of the memory cell array MCA. wiring may be provided. For example, a wiring for transmitting a write signal and a wiring for transmitting a read signal may be provided for one column of the memory cell array MCA.
- the circuit SD can be, for example, a voltage generation circuit for applying a predetermined voltage to the plurality of memory cells MC of the memory cell array MCA. Further, the circuit SD is electrically connected to the wirings SL[1] to SL[n], for example. Note that the memory device MDV in FIG. 18A may have a configuration in which the power supply voltage (VIL) for the memory cell array MCA shown in FIG. 17 is directly input without providing the circuit SD.
- VIL power supply voltage
- FIG. 18A shows an example in which one wiring SL[1] to SL[n] is provided for each column of the memory cell array MCA, a plurality of wirings SL[1] to SL[n] are provided for one column of the memory cell array MCA. wiring may be provided.
- the circuit CLC can be, for example, a circuit corresponding to the control logic circuit 2660 in FIG.
- the circuit OPC can be, for example, a circuit corresponding to the output circuit 2640 in FIG.
- the peripheral circuit PHL can be formed on a semiconductor substrate, for example. That is, the circuit WD, the circuit BD, the circuit SD, the circuit OPC, and the circuit CLC can be formed over a semiconductor substrate. Further, by using a substrate made of silicon as a semiconductor substrate, for example, a transistor including silicon in a channel formation region (hereinafter referred to as a Si transistor) can be formed on the substrate. Therefore, a Si transistor can be applied as a transistor included in the peripheral circuit PHL.
- a Si transistor a transistor including silicon in a channel formation region
- the semiconductor substrate for example, a substrate made of germanium may be used.
- the peripheral circuit PHL may be formed on a compound semiconductor substrate, and the compound semiconductor substrate may be a substrate made of a material such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. is mentioned.
- the peripheral circuit PHL may be formed on a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.
- SOI Silicon On Insulator
- the peripheral circuit PHL can be formed on an insulator substrate, for example.
- the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (for example, an yttria stabilized zirconia substrate), or a resin substrate.
- the peripheral circuit PHL can be formed on, for example, a conductor substrate.
- the conductor substrate include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates.
- an insulator substrate and a conductor substrate cannot form a channel formation region in the substrate itself, so a transistor cannot be formed directly on the insulator substrate and the conductor substrate. Therefore, in order to form a transistor over an insulator substrate or a conductor substrate, it is necessary to separately provide a semiconductor film over the insulator substrate or the conductor substrate.
- the memory cell array MCA can be provided above the semiconductor substrate and the peripheral circuit PHL by applying the OS transistor as a transistor included in the memory cell array MCA. can be done.
- FIG. 19 is a cross-sectional view schematically showing a configuration example of the memory device MDV of FIG. 18A including the memory cell MC of FIG. 4A.
- the memory device MDV shown in FIG. 19 has a layer SIL and a layer OSL provided above the layer SIL.
- the layer OSL has, for example, the memory cell array MCA described above.
- a memory cell 600 illustrated in FIG. 19 corresponds to one or more selected from memory cells MC[1,1] to MC[m,n] in FIG. 18A.
- a layer SIL shown in FIG. 19 includes a semiconductor substrate and a peripheral circuit PHL formed on the semiconductor substrate.
- Peripheral circuit PHL has, for example, circuit WD, circuit BD, circuit SD, circuit CLC, and circuit OPC as in the configuration of memory device MDV in FIG. 18A.
- transistor 300 may be a transistor included in circuit WD, circuit BD, circuit SD, circuit CLC, or circuit OPC.
- the transistor 300 has a conductor 316, an element isolation layer 312, an insulator 315, a semiconductor region 313 made of part of the substrate 310, and low resistance regions 314a and 314b functioning as source or drain regions.
- a semiconductor substrate for example, can be applied as the substrate 310 .
- the semiconductor substrate include a substrate made of silicon and a substrate made of germanium, as described above.
- a compound semiconductor substrate can be applied as the substrate 310.
- the compound semiconductor substrate include substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, as described above.
- the transistor 300 As shown in FIG. 20, the upper surface and side surfaces in the channel width direction of the semiconductor region 313 are covered with the conductor 316 with the insulator 315 interposed therebetween.
- the transistor 300 Fin-type By making the transistor 300 Fin-type in this manner, the effective channel width is increased, so that the on-characteristics of the transistor 300 can be improved. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 300 can be improved.
- the transistor 300 may be either p-channel type or n-channel type.
- a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low-resistance region 314a and a low-resistance region 314b that serve as a source region or a drain region preferably contain a silicon-based semiconductor. preferably contains monocrystalline silicon. Alternatively, it may be formed using a material including germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), aluminum gallium arsenide (GaAlAs), gallium nitride (GaN), or the like. Alternatively, a structure using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide.
- HEMT High Electron Mobility Transistor
- the low-resistance region 314a and the low-resistance region 314b are composed of elements imparting n-type conductivity such as arsenic or phosphorus, or p-type conductivity such as boron or aluminum. Contains elements that impart n-type conductivity such as arsenic or phosphorus, or p-type conductivity such as boron or aluminum. Contains elements that impart n-type conductivity such as arsenic or phosphorus, or p-type conductivity such as boron or aluminum. Contains elements that impart
- the conductor 316 functioning as a gate electrode is a semiconductor material such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus, an element imparting p-type conductivity such as boron or aluminum, or a metal material. , alloy materials, or metal oxide materials can be used.
- the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, a material such as titanium nitride or tantalum nitride is preferably used for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.
- the element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310 from each other.
- the element isolation layer 312 can be formed using, for example, a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a mesa isolation method, or the like.
- LOCOS Local Oxidation of Silicon
- STI Shallow Trench Isolation
- the transistor 300 illustrated in FIGS. 19 and 20 is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on the circuit configuration and driving method.
- the transistor 300 shown in FIGS. 19 and 20 may be a planar transistor.
- an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.
- the insulator 320, the insulator 322, the insulator 324, and the insulator 326 include, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride. You can use it.
- the insulator 322 may function as a planarization film that planarizes steps caused by the insulator 320 and the transistor 300 covered with the insulator 322 .
- the top surface of insulator 322 may be planarized using a chemical mechanical polishing (CMP) process to improve planarity.
- CMP chemical mechanical polishing
- the insulator 324 it is preferable to use a film having a barrier property that prevents impurities such as water or hydrogen from diffusing from the substrate 310, the transistor 300, or the like to the region where the transistor 500 is provided.
- a film having a barrier property against hydrogen for example, silicon nitride formed by a CVD method can be used.
- diffusion of hydrogen into a semiconductor element including an oxide semiconductor such as the transistor 500 might degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses diffusion of hydrogen between the transistor 500 and the transistor 300 .
- the film that suppresses diffusion of hydrogen is a film from which the amount of desorption of hydrogen is small.
- the insulator 326 preferably has a lower dielectric constant than the insulator 324 .
- the dielectric constant of insulator 326 is preferably less than 4, more preferably less than 3.
- the dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, that of the insulator 324 .
- a conductor 328 and a conductor 330 are embedded in the insulator 320 , the insulator 322 , the insulator 324 and the insulator 326 .
- the conductors 328 and 330 function as vias, plugs, or wirings.
- conductors that function as vias, plugs, or wirings may have a plurality of structures collectively given the same reference numerals.
- the wiring and the via or plug connected to the wiring may be integrated. That is, part of the conductor may function as wiring, and part of the conductor may function as via or plug.
- the conductors 328 and 330 include the conductors 448, 450, 457, 458, and 458 as materials that can be applied to vias, plugs, and wirings. Any material applicable to body 518 or conductor 540 can be used.
- a wiring layer may be provided over the insulator 326 and the conductor 330 .
- an insulator 350 , an insulator 352 , and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330 .
- a conductor 356 is formed over the insulators 350 , 352 , and 354 .
- the conductor 356 functions as a via, a plug, or a wiring connected to the transistor 300, for example.
- the conductor 356 can be provided using a material similar to that of the conductors 328 and 330 .
- An insulator 360 is formed over the insulator 354 and the conductor 356 .
- an insulator having a barrier property against impurities such as water or hydrogen is preferably used similarly to the insulator 324.
- an insulator with a relatively low dielectric constant is preferably used in order to reduce parasitic capacitance between wirings, like the insulator 326.
- the conductor 356 preferably contains a conductor having barrier properties against water or hydrogen.
- a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen.
- the conductor 356 is preferably made of tantalum nitride as a conductor having a barrier property against hydrogen, for example.
- the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while the conductivity of the wiring is maintained.
- FIG. 18A illustrates the structure in which one memory cell array MCA is provided above the peripheral circuit PHL
- the memory device of one embodiment of the present invention is not limited to this.
- the memory device of one embodiment of the present invention may include a plurality of stacked memory cell arrays MCA above the peripheral circuit PHL.
- FIG. 18B shows the configuration of a memory device in which memory cell arrays MCA[1] to MCA[p] (where p is an integer of 2 or more) are stacked above the peripheral circuit PHL.
- FIG. 21 shows a schematic cross-sectional view of the memory device MDV of FIG. 18B.
- the memory device MDV shown in FIG. 21 has a configuration in which a plurality of layers OSL are provided above the layer SIL in the memory device MDV shown in FIG.
- the memory device MDV illustrated in FIG. 21 includes a layer SIL and layers OSL[1] to OSL[p] provided above the layer SIL (here, p is an integer of 1 or more). have. Also, the memory cell arrays MCA[1] to MCA[p] shown in FIG. 18B are included in the layers OSL[1] to OSL[p] shown in FIG. 21 respectively. With such a configuration, the memory device MDV can be manufactured.
- FIG. 22 shows a configuration example in which the memory cell 600 of FIG. 19 is applied to the memory device MDV of FIG. 18A.
- each component is shown on a plane for easy viewing, but the memory cell array MCA is provided above the peripheral circuit PHL as in the case of the memory device MDV in FIG. 18A, as in FIG. shall be provided.
- Any one of the memory cells MC[1,1] to MC[m,n] shown in FIG. 22 corresponds to the memory cell 600 in FIG.
- the peripheral circuit PHL has a circuit WD, a circuit BD, and a circuit SD.
- the circuit WD, the circuit BD, and the circuit SD the description of the memory device MDV in FIG. 18A can be referred to.
- the memory device MDV in FIG. 22 differs from the memory device MDV in FIG. 18A in that the wirings SL[1] to SL[n] are provided in the column direction rather than in the row direction. As described above, in the memory device MDV, the direction in which the wiring extends is not particularly limited.
- the circuit WD includes the wirings WLa[1] to WLa[m] and the wirings WLb[1] to WLb[m] as the wirings WL[1] to WL[m] in the memory device MDV in FIG. 18A. is electrically connected to That is, the wiring WLa and the wiring WLb are provided for each row of the memory cell array MCA.
- the circuit WD preferably has a configuration in which different voltages are input to the wirings WLa and WLb when writing information to the memory cell MC and when reading information from the memory cell MC. .
- the configuration example in which the memory cell 600 of FIG. 19 is applied to the memory device MDV of FIG. 18A is not limited to the configuration of the memory device MDV of FIG.
- the circuit configuration of the memory device MDV of FIG. 22 may be changed according to the situation.
- a memory cell using the MTJ element ME functions as a non-volatile memory, so power for holding data can be reduced. Therefore, by applying the above structure to a memory device, a memory device with low power consumption can be provided. Further, by using an OS transistor or the like as a transistor of the memory cell, the memory cell array can be manufactured in a semiconductor process; therefore, the memory cell array can be stacked above the peripheral circuit. By stacking a plurality of memory cell arrays, a memory device with a large memory capacity can be provided.
- a metal oxide used for an OS transistor preferably contains at least indium or zinc, and more preferably contains indium and zinc.
- metal oxides include indium and M (where M is gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium). , hafnium, tantalum, tungsten, magnesium, and cobalt) and zinc.
- M is preferably one or more selected from gallium, aluminum, yttrium and tin, more preferably gallium.
- a metal oxide can be formed by a chemical vapor deposition (CVD) method such as a sputtering method, a metalorganic chemical vapor deposition (MOCVD) method, or an atomic layer deposition (ALD) method.
- CVD chemical vapor deposition
- MOCVD metalorganic chemical vapor deposition
- ALD atomic layer deposition
- oxides containing indium (In), gallium (Ga), and zinc (Zn) will be described as examples of metal oxides. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) is sometimes called an In--Ga--Zn oxide.
- Crystal structures of oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystal. (poly crystal) and the like.
- the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum.
- XRD X-ray diffraction
- it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement.
- GIXD Gram-Incidence XRD
- the GIXD method is also called a thin film method or a Seemann-Bohlin method.
- the XRD spectrum obtained by the GIXD measurement may be simply referred to as the XRD spectrum.
- the shape of the peak of the XRD spectrum is almost bilaterally symmetrical.
- the shape of the peak of the XRD spectrum is left-right asymmetric.
- the asymmetric shape of the peaks in the XRD spectra demonstrates the presence of crystals in the film or substrate. In other words, the film or substrate cannot be said to be in an amorphous state unless the shape of the peaks in the XRD spectrum is symmetrical.
- the crystal structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a nano beam electron diffraction pattern) observed by nano beam electron diffraction (NBED).
- a diffraction pattern also referred to as a nano beam electron diffraction pattern
- NBED nano beam electron diffraction
- a halo is observed in the diffraction pattern of a quartz glass substrate, and it can be confirmed that the quartz glass is in an amorphous state.
- a spot-like pattern is observed instead of a halo. For this reason, it is presumed that it cannot be concluded that the In-Ga-Zn oxide deposited at room temperature is in an intermediate state, neither single crystal nor polycrystal, nor amorphous state, and is in an amorphous state. be done.
- oxide semiconductors may be classified differently from the above when their structures are focused. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors.
- Non-single-crystal oxide semiconductors include, for example, the above CAAC-OS and nc-OS.
- Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.
- CAAC-OS is an oxide semiconductor that includes a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction to the formation surface of the CAAC-OS film, or the normal direction to the surface of the CAAC-OS film.
- a crystalline region is a region having periodicity in atomic arrangement. If the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement.
- CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and the region may have strain.
- the strain refers to a portion where the orientation of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and has no obvious orientation in the ab plane direction.
- each of the plurality of crystal regions is composed of one or more microcrystals (crystals having a maximum diameter of less than 10 nm).
- the maximum diameter of the crystalline region is less than 10 nm.
- the maximum diameter of the crystal region may be about several tens of nanometers.
- the CAAC-OS includes a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn) and oxygen (
- an In layer a layer containing indium (In) and oxygen
- Ga gallium
- Zn zinc
- oxygen it tends to have a layered crystal structure (also referred to as a layered structure) in which (Ga, Zn) layers are laminated.
- the (Ga, Zn) layer may contain indium.
- the In layer may contain gallium.
- the In layer may contain zinc.
- the layered structure is observed as a lattice image in, for example, a high-resolution TEM (Transmission Electron Microscope) image.
- a plurality of bright points are observed in the electron beam diffraction pattern of the CAAC-OS film.
- a certain spot and another spot are observed at point-symmetrical positions with respect to the spot of the incident electron beam that has passed through the sample (also referred to as a direct spot) as the center of symmetry.
- the lattice arrangement in the crystal region is basically a hexagonal lattice, but the unit cell is not always a regular hexagon and may be a non-regular hexagon. Moreover, the distortion may have a lattice arrangement of pentagons, heptagons, or the like. Note that in CAAC-OS, no clear crystal grain boundary can be observed even near the strain. That is, it can be seen that the distortion of the lattice arrangement suppresses the formation of grain boundaries. This is because the CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction, the bond distance between atoms changes due to the substitution of metal atoms, and the like. It is considered to be for
- a crystal structure in which clear grain boundaries are confirmed is called a polycrystal.
- a grain boundary becomes a recombination center, and there is a high possibility that carriers are trapped and cause a decrease in the on-state current of a transistor, a decrease in field-effect mobility, and the like. Therefore, a CAAC-OS in which no clear grain boundaries are observed is one of crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor.
- a structure containing Zn is preferable for forming a CAAC-OS.
- In--Zn oxide and In--Ga--Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.
- CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the decrease in electron mobility due to grain boundaries is less likely to occur in CAAC-OS.
- the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor including CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including CAAC-OS is resistant to heat and has high reliability.
- CAAC-OS is also stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS for the OS transistor can increase the degree of freedom in the manufacturing process.
- nc-OS has periodic atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
- the nc-OS has minute crystals.
- the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also called a nanocrystal.
- nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
- an nc-OS may be indistinguishable from an a-like OS and an amorphous oxide semiconductor depending on the analysis method.
- an nc-OS film is subjected to structural analysis using an XRD apparatus, out-of-plane XRD measurement using ⁇ /2 ⁇ scanning does not detect a peak indicating crystallinity.
- an nc-OS film is subjected to electron beam diffraction (also referred to as selected area electron beam diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is obtained. Observed.
- an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than the nanocrystal size (for example, 1 nm or more and 30 nm or less)
- electron diffraction also referred to as nanobeam electron diffraction
- an electron beam with a probe diameter close to or smaller than the nanocrystal size for example, 1 nm or more and 30 nm or less
- An a-like OS is an oxide semiconductor having a structure between an nc-OS and an amorphous oxide semiconductor.
- An a-like OS has void or low density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. In addition, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.
- CAC-OS relates to material composition.
- CAC-OS is, for example, one structure of a material in which elements constituting a metal oxide are unevenly distributed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
- the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof.
- the mixed state is also called mosaic or patch.
- CAC-OS is a structure in which the material is separated into a first region and a second region to form a mosaic shape, and the first region is distributed in the film (hereinafter, also referred to as a cloud shape). ). That is, CAC-OS is a composite metal oxide in which the first region and the second region are mixed.
- the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In--Ga--Zn oxide are denoted by [In], [Ga], and [Zn], respectively.
- the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film.
- the second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film.
- the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
- the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
- the first region is a region whose main component is indium oxide, indium zinc oxide, or the like.
- the second region is a region containing gallium oxide, gallium zinc oxide, or the like as a main component. That is, the first region can be rephrased as a region containing In as a main component. Also, the second region can be rephrased as a region containing Ga as a main component.
- a clear boundary between the first region and the second region may not be observed.
- the CAC-OS in the In—Ga—Zn oxide means a region containing Ga as a main component and a region containing In as a main component in a material structure containing In, Ga, Zn, and O. Each region is a mosaic, and refers to a configuration in which these regions exist randomly. Therefore, CAC-OS is presumed to have a structure in which metal elements are unevenly distributed.
- the CAC-OS can be formed, for example, by sputtering under the condition that the substrate is not heated.
- an inert gas typically argon
- an oxygen gas typically a nitrogen gas
- a nitrogen gas may be used as a deposition gas.
- the flow rate ratio of the oxygen gas to the total flow rate of the film forming gas during film formation is preferably as low as possible.
- the flow ratio of the oxygen gas to the total flow rate of the film forming gas during film formation is 0% or more and less than 30%, preferably 0% or more and 10% or less.
- an EDX mapping obtained using energy dispersive X-ray spectroscopy shows that a region containing In as a main component It can be confirmed that the (first region) and the region (second region) containing Ga as the main component are unevenly distributed and have a mixed structure.
- the first region is a region with higher conductivity than the second region. That is, when carriers flow through the first region, conductivity as a metal oxide is developed. Therefore, by distributing the first region in the form of a cloud in the metal oxide, a high field effect mobility ( ⁇ ) can be realized.
- the second region is a region with higher insulation than the first region.
- the leakage current can be suppressed by distributing the second region in the metal oxide.
- CAC-OS when used for a transistor, the conductivity caused by the first region and the insulation caused by the second region act complementarily to provide a switching function (turning on/off). functions) can be given to the CAC-OS.
- a part of the material has a conductive function
- a part of the material has an insulating function
- the whole material has a semiconductor function.
- CAC-OS is most suitable for various semiconductor devices including display devices.
- Oxide semiconductors have a variety of structures, each with different characteristics.
- An oxide semiconductor of one embodiment of the present invention includes two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS. may
- an oxide also referred to as "IGZO" containing indium (In), gallium (Ga), and zinc (Zn)
- IGZO oxide containing indium (In), gallium (Ga), and zinc (Zn)
- IAZO oxide containing indium (In), aluminum (Al), and zinc (Zn)
- IAGZO oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn)
- an oxide semiconductor with low carrier concentration is preferably used for a transistor.
- the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm ⁇ 3 or less, preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ 10 13 cm ⁇ 3 or less, more preferably 1 ⁇ 10 11 cm ⁇ 3 or less . 3 or less, more preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more.
- the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
- a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
- an oxide semiconductor with a low carrier concentration is sometimes referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
- a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect level density, so the trap level density may also be low.
- the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor whose channel formation region is formed in an oxide semiconductor with a high trap level density might have unstable electrical characteristics.
- Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.
- the impurities in the oxide semiconductor refer to, for example, substances other than the main components of the oxide semiconductor. For example, an element whose concentration is less than 0.1 atomic percent can be said to be an impurity.
- the concentration of silicon or carbon in the oxide semiconductor is 2 ⁇ 10 atoms/cm or less, preferably 2 ⁇ 10 17 atoms/cm 3 or less.
- the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
- the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms/cm 3 , preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less. , more preferably 5 ⁇ 10 17 atoms/cm 3 or less.
- Hydrogen contained in an oxide semiconductor reacts with oxygen that bonds to a metal atom to form water, which may cause oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
- This embodiment mode shows an example of a semiconductor wafer on which the memory device and the like described in the above embodiment are formed, and an electronic component in which the memory device is incorporated.
- a semiconductor wafer 4800 shown in FIG. 23A has a wafer 4801 and a plurality of circuit sections 4802 provided on the upper surface of the wafer 4801 .
- the portion without the circuit portion 4802 is the spacing 4803, which is the area for dicing.
- a semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of a wafer 4801 through a pre-process. After that, the wafer 4801 may be thinned by grinding the opposite surface of the wafer 4801 on which the plurality of circuit portions 4802 are formed. By this process, warping of the wafer 4801 can be reduced, and miniaturization as a component can be achieved.
- the next step is the dicing process. Dicing is performed along a scribe line SCL1 and a scribe line SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by dashed lines.
- the spacing 4803 is provided so that a plurality of scribe lines SCL1 are parallel, and a plurality of scribe lines SCL2 are provided so that the scribe lines SCL1 and SCL2 are parallel. It is preferable to provide it vertically.
- a chip 4800a as shown in FIG. 23B can be cut out from the semiconductor wafer 4800 by performing the dicing process.
- the chip 4800a has a wafer 4801a, a circuit portion 4802, and a spacing 4803a.
- the spacing 4803a is preferably made as small as possible. In this case, it is sufficient that the width of the spacing 4803 between the adjacent circuit portions 4802 is substantially equal to the width of the scribe line SCL1 or the width of the scribe line SCL2.
- the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 23A.
- the shape of the element substrate can be appropriately changed according to the manufacturing process of the element and the apparatus for manufacturing the element.
- FIG. 23C shows a perspective view of electronic component 4700 and a substrate (mounting substrate 4704) on which electronic component 4700 is mounted.
- Electronic component 4700 shown in FIG. 23C has chip 4800 a in mold 4711 .
- the chip 4800a shown in FIG. 23C has a structure in which the circuit portion 4802 is stacked. That is, the memory device described in the above embodiment can be applied to the circuit portion 4802 .
- FIG. 23C is partially omitted to show the inside of electronic component 4700 .
- Electronic component 4700 has lands 4712 outside mold 4711 . Land 4712 is electrically connected to electrode pad 4713 , and electrode pad 4713 is electrically connected to chip 4800 a by wire 4714 .
- Electronic component 4700 is mounted on printed circuit board 4702, for example.
- a mounting board 4704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed board 4702 .
- FIG. 23D A perspective view of the electronic component 4730 is shown in FIG. 23D.
- Electronic component 4730 is an example of SiP (System in package) or MCM (Multi Chip Module).
- An electronic component 4730 includes an interposer 4731 provided over a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 provided over the interposer 4731 .
- the electronic component 4730 has a semiconductor device 4710 .
- the semiconductor device 4710 can be, for example, the memory device described in any of the above embodiments, a high bandwidth memory (HBM), or the like.
- HBM high bandwidth memory
- an integrated circuit semiconductor device such as a CPU, GPU, FPGA, or memory device can be used.
- a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732 .
- a silicon interposer, a resin interposer, or the like can be used as the interposer 4731 .
- the interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. A plurality of wirings are provided in a single layer or multiple layers. In addition, the interposer 4731 has a function of electrically connecting the integrated circuit provided over the interposer 4731 to electrodes provided over the package substrate 4732 . For these reasons, the interposer is sometimes called a "rewiring board” or an "intermediate board". In some cases, through electrodes are provided in the interposer 4731 and the integrated circuit and the package substrate 4732 are electrically connected using the through electrodes. Also, in a silicon interposer, a TSV (Through Silicon Via) can be used as a through electrode.
- TSV Three Silicon Via
- a silicon interposer is preferably used as the interposer 4731 . Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with the resin interposer.
- HBM In HBM, it is necessary to connect many wires in order to achieve a wide memory bandwidth. Therefore, an interposer for mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts the HBM.
- SiP or MCM using a silicon interposer is unlikely to deteriorate in reliability due to the difference in coefficient of expansion between the integrated circuit and the interposer.
- the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur.
- a 2.5D package 2.5-dimensional packaging in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
- a heat sink may be provided overlapping with the electronic component 4730 .
- a heat sink it is preferable that the heights of the integrated circuits provided over the interposer 4731 be uniform.
- the semiconductor device 4710 and the semiconductor device 4735 have the same height.
- Electrodes 4733 may be provided on the bottom of the package substrate 4732 in order to mount the electronic component 4730 on another substrate.
- FIG. 23D shows an example in which the electrodes 4733 are formed from solder balls.
- BGA Bend Grid Array
- the electrodes 4733 may be formed of conductive pins.
- PGA Peripheral Component Interconnect
- the electronic component 4730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA.
- a mounting method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) be able to.
- FIG. 24 is a block diagram showing an example configuration of a CPU partially using the storage device described in the above embodiment.
- the CPU shown in FIG. 24 includes an ALU (Arithmetic Logic Unit) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198 (Bus I/ F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I/F).
- a semiconductor substrate, an SOI substrate, or a glass substrate is used as the substrate 1190 .
- the ROM 1199 and ROM interface 1189 may be provided on separate chips.
- the CPU shown in FIG. 24 is merely an example of a simplified configuration, and actual CPUs have a wide variety of configurations depending on their uses.
- a configuration including a CPU or an arithmetic circuit shown in FIG. 24 may be used as one core, a plurality of such cores may be included, and the cores may operate in parallel, that is, a configuration like a GPU.
- the number of bits that the CPU can handle in its internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits or more.
- Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.
- the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on decoded instructions. Specifically, ALU controller 1192 generates signals for controlling the operation of ALU 1191 . In addition, the interrupt controller 1194 judges and processes an interrupt request from an external input/output device or a peripheral circuit from its priority or mask state while the CPU is executing a program. A register controller 1197 generates an address for the register 1196 and reads or writes the register 1196 according to the state of the CPU.
- the timing controller 1195 generates signals for controlling the timing of the operations of the ALU 1191 , ALU controller 1192 , instruction decoder 1193 , interrupt controller 1194 and register controller 1197 .
- the timing controller 1195 has an internal clock generator that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits described above.
- the register 1196 is provided with memory cells.
- the register 1196 may have, for example, the storage devices described in the previous embodiments.
- the register controller 1197 selects a holding operation in the register 1196 according to instructions from the ALU 1191 . That is, in the memory cells included in the register 1196, it is selected whether data is held by a flip-flop or a capacitor. When data holding by the flip-flop is selected, power supply voltage is supplied to the memory cells in the register 1196 . When data retention in the capacitor is selected, data is rewritten in the capacitor, and supply of power supply voltage to the memory cells in the register 1196 can be stopped.
- FIGS. 27A to 27E illustrate how electronic components 4700 having the storage device are included in each electronic device.
- An information terminal 5500 shown in FIG. 25A is a mobile phone (smartphone), which is a type of information terminal.
- the information terminal 5500 includes a housing 5510 and a display portion 5511.
- the display portion 5511 is provided with a touch panel, and the housing 5510 is provided with buttons.
- the information terminal 5500 can hold temporary files generated when an application is executed (for example, a cache when using a web browser).
- FIG. 25B illustrates an information terminal 5900 that is an example of a wearable terminal.
- An information terminal 5900 includes a housing 5901, a display portion 5902, operation buttons 5903, an operator 5904, a band 5905, and the like.
- the wearable terminal like the information terminal 5500 described above, can hold temporary files generated when an application is executed by applying the storage device described in the above embodiment.
- a desktop information terminal 5300 is also illustrated in FIG. 25C.
- the desktop information terminal 5300 has an information terminal main body 5301 , a display 5302 and a keyboard 5303 .
- the desktop information terminal 5300 can hold temporary files generated when an application is executed by applying the storage device described in the above embodiment.
- a smartphone, a wearable terminal, and a desktop information terminal are illustrated as examples of electronic devices in FIGS. be able to.
- Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), laptop information terminals, and workstations.
- FIG. 25D also illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance.
- the electric freezer-refrigerator 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and the like.
- the electric refrigerator-freezer 5800 can be used as, for example, IoT (Internet of Things).
- IoT Internet of Things
- the electric freezer-refrigerator 5800 can transmit and receive information such as the foodstuffs stored in the electric freezer-refrigerator 5800 and the expiration date of the foodstuffs to and from the above-described information terminal or the like via the Internet or the like. can.
- the electric refrigerator-freezer 5800 can hold the information as a temporary file in the storage device.
- an electric refrigerator/freezer was explained as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Appliances, washing machines, dryers, audiovisual equipment, etc.
- FIG. 25E also illustrates a portable game machine 5200, which is an example of a game machine.
- a portable game machine 5200 includes a housing 5201 , a display portion 5202 , and buttons 5203 .
- FIG. 25F illustrates a stationary game machine 7500, which is an example of a game machine.
- a stationary game machine 7500 has a main body 7520 and a controller 7522 .
- a controller 7522 can be connected to the main body 7520 wirelessly or by wire.
- the controller 7522 includes one or more selected from a display unit for displaying game images, a touch panel serving as an input interface other than buttons, a stick, a rotating knob, and a sliding knob. be able to.
- the shape of the controller 7522 is not limited to that shown in FIG. 25F, and the shape of the controller 7522 may be varied according to the genre of the game.
- a button can be used as a trigger and a controller shaped like a gun can be used.
- a controller shaped like a musical instrument, music equipment, or the like can be used.
- the stationary game machine may not use a controller, but may instead have a camera, depth sensor, microphone, etc., and may be operated by the game player's gestures and/or voice.
- the video of the game machine described above can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
- a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
- the low power consumption can reduce the heat generated from the circuit, so that the influence of the heat on the circuit itself, the peripheral circuits, and the module can be reduced.
- FIGS. 25E and 25F illustrate a portable game machine and a stationary game machine as examples of game machines
- the electronic device of one embodiment of the present invention is not limited to these.
- Examples of electronic devices of one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.
- the storage devices described in the above embodiments can be applied to automobiles, which are moving bodies, and to the vicinity of the driver's seat of automobiles.
- FIG. 25G An automobile 5700, which is an example of a mobile object, is illustrated in FIG. 25G.
- a display device for displaying such information may be provided around the driver's seat.
- the display device can compensate for the blind spots in the driver's seat and the visibility blocked by pillars, etc., and enhance safety. be able to.
- the storage device described in the above embodiment can temporarily hold information
- the storage device can be used for an automatic driving system of the automobile 5700, and the storage device can be used for road guidance, danger prediction, etc. can be used to hold necessary temporary information in
- the display device may be configured to display temporary information such as road guidance and danger prediction. Further, a configuration may be adopted in which images of a driving recorder installed in automobile 5700 are held.
- mobile objects include trains, monorails, ships, and flying objects (eg, helicopters, unmanned aerial vehicles (drone), airplanes, and rockets).
- flying objects eg, helicopters, unmanned aerial vehicles (drone), airplanes, and rockets.
- FIG. 25H illustrates a digital camera 6240 as an example of an imaging device.
- the digital camera 6240 has a housing 6241, a display unit 6242, an operation button 6243, or a shutter button 6244, and a detachable lens 6246 is attached to the digital camera 6240.
- the digital camera 6240 has a configuration in which the lens 6246 can be removed from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated.
- the digital camera 6240 may have a configuration in which a strobe device or a viewfinder can be attached separately.
- the digital camera 6240 with low power consumption can be realized.
- the low power consumption can reduce the heat generated from the circuit, so that the influence of the heat on the circuit itself, the peripheral circuits, and the module can be reduced.
- Video camera The storage devices described in the above embodiments can be applied to video cameras.
- FIG. 25I illustrates a video camera 6300 as an example of an imaging device.
- a video camera 6300 has a first housing 6301 , a second housing 6302 , a display portion 6303 , operation keys 6304 , a lens 6305 , and a connection portion 6306 .
- the operation keys 6304 and the lens 6305 are provided on the first housing 6301, and the display portion 6303 is provided on the second housing 6302.
- the first housing 6301 and the second housing 6302 are connected by a connecting portion 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting portion 6306. be.
- the image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 on the connection unit 6306 .
- the video camera 6300 can hold temporary files generated during encoding.
- ICD implantable cardioverter defibrillator
- FIG. 25J is a cross-sectional schematic diagram showing an example of an ICD.
- the ICD main body 5400 has at least a battery 5401, an electronic component 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.
- the ICD body 5400 is surgically placed in the body, and two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body, with one wire tip placed in the right ventricle and the other wire tip placed in the right atrium. be done.
- the ICD main body 5400 functions as a pacemaker, and paces the heart when the heart rate deviates from the prescribed range. Also, if pacing does not improve heart rate (eg, rapid ventricular tachycardia or ventricular fibrillation), treatment with electric shocks is given.
- heart rate eg, rapid ventricular tachycardia or ventricular fibrillation
- the ICD main body 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting heart rate. In addition, the ICD main body 5400 can store heart rate data acquired by the sensor or the like, the number of pacing treatments, time, and the like in the electronic component 4700 .
- the ICD main body 5400 having a plurality of batteries can enhance safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the rest of the batteries can still function, so the ICD also functions as an auxiliary power source.
- an antenna capable of transmitting physiological signals may be provided.
- a system may be configured to monitor various cardiac activity.
- the storage devices described in the above embodiments can be applied to electronic devices for XR (Extended Reality or Cross Reality) such as AR (Augmented Reality) or VR (Virtual Reality).
- XR Extended Reality or Cross Reality
- AR Augmented Reality
- VR Virtual Reality
- FIGS. 26A to 26C are diagrams showing the appearance of an electronic device 8300 that is a head mounted display.
- An electronic device 8300 illustrated in FIGS. 26A to 26C includes a housing 8301, a display portion 8302, a band-like fixture 8304, a fixture 8304a attached to the head, and a pair of lenses 8305.
- FIG. Note that the electronic device 8300 may be provided with operation buttons.
- the user can visually recognize the displayed image on the display unit 8302 through the lens 8305 .
- the display portion 8302 it is preferable to arrange the display portion 8302 in a curved manner because the user can feel a high presence.
- three-dimensional display or the like using parallax can be performed.
- the configuration is not limited to the configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided and one display portion may be arranged for one eye of the user.
- the display unit 8302 for example, it is preferable to use a display device with extremely high definition.
- a display device with extremely high definition By using a high-definition display device for the display portion 8302, even if the display image is enlarged using the lens 8305 in the electronic device 8300 in FIG. It can display high quality images.
- the head-mounted display which is an electronic device of one embodiment of the present invention, may have the structure of an electronic device 8200 that is a glass-type head-mounted display illustrated in FIG. 26D.
- the electronic device 8200 has a mounting section 8201, a lens 8202, a main body 8203, a display section 8204, and a cable 8205.
- a battery 8206 is built in the mounting portion 8201 .
- a cable 8205 supplies power from a battery 8206 to the main body 8203 .
- a main body 8203 includes a wireless receiver or the like, and can display received video information on a display portion 8204 .
- the main body 8203 is equipped with a camera, and information on the movement of the user's eyeballs or eyelids can be used as input means.
- the mounting section 8201 may be provided with a plurality of electrodes capable of detecting a current flowing along with the movement of the user's eyeballs at a position where it touches the user, and may have a function of recognizing the line of sight. Moreover, it may have a function of monitoring the user's pulse based on the current flowing through the electrode.
- the mounting unit 8201 may have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, etc., and has a function of displaying biological information of the user on the display unit 8204, In addition, a function of changing an image displayed on the display portion 8204 may be provided.
- Extension device for PC The storage devices described in the above embodiments can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.
- FIG. 27A shows an expansion device 6100 externally attached to a PC, mounted with a portable chip capable of storing information, as an example of the expansion device.
- the expansion device 6100 can store information by the chip, for example, by connecting to a PC via a USB (Universal Serial Bus) or the like.
- FIG. 27A illustrates the portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this. It may also be an expansion device in a larger form.
- the expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103 and a substrate 6104.
- a substrate 6104 is housed in a housing 6101 .
- the substrate 6104 is provided with a circuit for driving the memory device or the like described in the above embodiment mode.
- substrate 6104 has electronic components 4700 and controller chip 6106 mounted thereon.
- a USB connector 6103 functions as an interface for connecting with an external device.
- SD card The storage devices described in the above embodiments can be applied to SD cards that can be attached to electronic devices such as information terminals and digital cameras.
- FIG. 27B is a schematic diagram of the appearance of the SD card
- FIG. 27C is a schematic diagram of the internal structure of the SD card.
- the SD card 5110 has a housing 5111 , a connector 5112 and a substrate 5113 .
- a connector 5112 functions as an interface for connecting with an external device.
- a substrate 5113 is housed in a housing 5111 .
- a substrate 5113 is provided with a memory device and a circuit for driving the memory device.
- an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113 .
- the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate according to circumstances.
- a write circuit, a row driver, a read circuit, and the like included in electronic components may be incorporated in the controller chip 5115 instead of the electronic component 4700 .
- the capacity of the SD card 5110 can be increased by providing the electronic component 4700 on the back side of the substrate 5113 as well.
- a wireless chip having a wireless communication function may be provided over the substrate 5113 .
- wireless communication can be performed between the external device and the SD card 5110, and data can be read from and written to the electronic component 4700.
- SSD Solid State Drives
- electronic devices such as information terminals.
- FIG. 27D is a schematic diagram of the appearance of the SSD
- FIG. 27E is a schematic diagram of the internal structure of the SSD.
- the SSD 5150 has a housing 5151 , a connector 5152 and a substrate 5153 .
- a connector 5152 functions as an interface for connecting with an external device.
- a substrate 5153 is housed in a housing 5151 .
- a substrate 5153 is provided with a memory device and a circuit for driving the memory device.
- substrate 5153 has electronic component 4700, memory chip 5155, and controller chip 5156 mounted thereon. By providing the electronic component 4700 also on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased.
- the memory chip 5155 incorporates a work memory.
- the memory chip 5155 may be a DRAM chip.
- the controller chip 5156 incorporates a processor, an ECC circuit, and the like. Note that the circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and the circuit configurations may be changed as appropriate according to circumstances.
- the controller chip 5156 may also be provided with a memory functioning as a work memory.
- a novel electronic device can be provided by applying the storage device described in the above embodiment to the storage device included in the electronic device described above.
- MDV memory device
- MCA memory cell array
- MCA[1] memory cell array
- MCA[p] memory cell array
- PHL peripheral circuit
- MC memory cell
- MC[1,1] memory cell
- MC[m, 1] memory cell
- MC [1, n] memory cell
- MC [m, n] memory cell
- BD circuit
- WD circuit
- SD circuit
- CLC circuit
- OPC circuit
- M4 transistor
- MD resistance change device
- ME MTJ element
- IT1 terminal
- IT2 terminal
- OT terminal
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Abstract
Description
本発明の一態様は、第1導電体と、第2導電体と、第3導電体と、第1トランジスタと、第2トランジスタと、メモリ素子と、を有する、半導体装置である。第2導電体は、第1導電体の上方に位置し、メモリ素子は、第2導電体の上方に位置し、第1トランジスタ、及び第2トランジスタは、メモリ素子の上方に位置し、第3導電体は、第1トランジスタ、及び第2トランジスタの上方に位置する。また、平面視において、第3導電体は、第1導電体に重畳する領域に位置する。第1導電体は、第2導電体に電気的に接続され、第2導電体は、メモリ素子の第1端子と、第1トランジスタの第1端子と、に電気的に接続され、メモリ素子の第2端子は、第2トランジスタの第1端子に電気的に接続され、第1トランジスタの第2端子は、第2トランジスタの第2端子と、第3導電体と、に電気的に接続されている。また、第1トランジスタ、及び第2トランジスタのそれぞれは、チャネル形成領域に金属酸化物を含む。
又は、本発明の一態様は、上記(1)において、メモリ素子が、抵抗変化素子、強誘電キャパシタ、FTJ素子、又は相変化メモリのいずれか一を有する構成としてもよい。
本発明の一態様は、第1導電体と、第2導電体と、第3導電体と、第1トランジスタと、第2トランジスタと、メモリ素子と、を有する半導体装置である。なお、メモリ素子は、第1磁性層と、第2磁性層と、絶縁体と、を有する。第2導電体は、第1導電体の上方に位置し、第1磁性層は、第2導電体の上方に位置し、絶縁体は、第1磁性層の上方に位置し、第2磁性層は、絶縁体の上方に位置する。また、第1トランジスタ、及び第2トランジスタは、第2磁性層の上方に位置し、第3導電体は、第1トランジスタ、及び第2トランジスタの上方に位置する。特に、平面視において、第3導電体は、第1導電体に重畳する領域に位置する。第1導電体は、第2導電体に電気的に接続され、第2導電体は、第1磁性層と、第1トランジスタの第1端子と、に電気的に接続され、第2磁性層は、第2トランジスタの第1端子に電気的に接続され、第1トランジスタの第2端子は、第2トランジスタの第2端子と、第3導電体と、に電気的に接続されている。また、第1トランジスタ、及び第2トランジスタのそれぞれは、チャネル形成領域に金属酸化物を含む。
又は、本発明の一態様は、上記(3)において、メモリ素子は、MTJ素子として機能する構成としてもよい。特に、第1磁性層は、自由層として機能し、第2磁性層は、固定層として機能し、絶縁体は、トンネル絶縁体として機能することが好ましい。また、第2導電体が、電流が流れることでスピンホール効果が起きる金属材料を有する構成としてもよい。
又は、本発明の一態様は、上記(3)の構成と異なる、第1導電体と、第2導電体と、第3導電体と、第1トランジスタと、第2トランジスタと、メモリ素子と、を有する半導体装置である。なお、メモリ素子は、第1磁性層と、第2磁性層と、絶縁体と、を有する。第1トランジスタ、及び第2トランジスタは、第3導電体の上方に位置し、第2磁性層は、第1トランジスタ、及び第2トランジスタの上方に位置する。絶縁体は、第2磁性層の上方に位置し、第1磁性層は、絶縁体の上方に位置し、第2導電体は、第1磁性層の上方に位置し、第1導電体は、第2導電体の上方に位置する。特に、平面視において、第1導電体は、第3導電体に重畳する領域に位置する。第1導電体は、第2導電体に電気的に接続され、第2導電体は、第1磁性層と、第1トランジスタの第1端子と、に電気的に接続され、第2磁性層は、第2トランジスタの第1端子に電気的に接続され、第1トランジスタの第2端子は、第2トランジスタの第2端子と、第3導電体と、に電気的に接続されている。また、第1トランジスタ、及び第2トランジスタのそれぞれは、チャネル形成領域に金属酸化物を含む。
又は、本発明の一態様は、上記(5)において、メモリ素子は、MTJ素子として機能する構成としてもよい。特に、第1磁性層は、自由層として機能し、第2磁性層は、固定層として機能し、絶縁体は、トンネル絶縁体として機能することが好ましい。また、第2導電体が、電流が流れることでスピンホール効果が起きる金属材料を有する構成としてもよい。
又は、本発明の一態様は、上記(1)乃至(6)のいずれか一の半導体装置と、周辺回路を含む層と、を有する記憶装置である。なお、層は、半導体装置の下方に位置する。また、周辺回路は、半導体装置へのデータの書き込み、及び半導体装置からのデータの読み出しを行う機能を有する。
又は、本発明の一態様は、上記(7)の記憶装置と、筐体と、を有する電子機器である。
図2A、及び図2Bは、トランジスタの構成例を示す断面模式図である。
図3A、及び図3Bは、トランジスタの構成例を示す断面模式図である。
図4A乃至図4Dは、メモリセルの構成例を示す回路図である。
図5は、メモリセルに含まれているメモリ素子の構成例を説明する模式図である。
図6Aは、メモリセルの構成例を示す平面模式図であり、図6Bは、メモリセルの構成例を示す断面模式図である。
図7は、メモリセルの構成例を示す断面模式図である。
図8は、メモリセルの構成例を示す断面模式図である。
図9は、複数のメモリセルの接続構成を示すブロック図である。
図10Aは、メモリセルの構成例を示す平面模式図であり、図10Bは、メモリセルの構成例を示す断面模式図である。
図11Aは、メモリセルの構成例を示す平面模式図であり、図11Bは、メモリセルの構成例を示す断面模式図である。
図12Aは、メモリセルの構成例を示す平面模式図であり、図12Bは、メモリセルの構成例を示す断面模式図である。
図13は、メモリセルの構成を模式的に示した斜視図である。
図14は、メモリセルの構成を模式的に示した斜視図である。
図15Aは、メモリセルの構成例を示す平面模式図であり、図15Bは、メモリセルの構成例を示す断面模式図である。
図16A、及び図16Bは、メモリセルの構成例を示す断面模式図である。
図17は、記憶装置の構成例を示すブロック図である。
図18A、及び図18Bは、記憶装置の構成例を示すブロック図である。
図19は、記憶装置の構成例を示す断面模式図である。
図20は、トランジスタの構成例を示す断面模式図である。
図21は、記憶装置の構成例を示す断面模式図である。
図22は、記憶装置の構成例を示すブロック図である。
図23Aは半導体ウェハの一例を示す斜視図であり、図23Bはチップの一例を示す斜視図であり、図23C、及び図23Dは電子部品の一例を示す斜視図である。
図24は、CPUを説明するブロック図である。
図25A乃至図25Jは、電子機器の一例を説明する斜視図、又は、模式図である。
図26A乃至図26Dは、電子機器の構成例を示す図である。
図27A乃至図27Eは、電子機器の一例を説明する斜視図、又は、模式図である。
本実施の形態では、本発明の一態様の半導体装置である、メモリセルについて説明する。
図4Aは、記憶装置に備えることができるメモリセルの一例を示している。なお、図4Aに示すメモリセルMCは、3端子メモリ素子であるSOT−MRAM(Spin Orbit Torque−Magnetoresistive Random Access Memory)の一例ということができる。
図1A、及び図1Bは、本発明の一態様の半導体装置である、メモリセルの構成例を示している。具体的には、図1Aは、メモリセル600Aの構成例を模式的に示した平面図であって、図1Bは、層OSLに含まれるメモリセル600Aの構成例を模式的に示した断面図である。特に、図1Bは、図1Aに示している一点鎖線A1−A2における断面図である。また、図1Aは、導電体590、導電体540、導電体560A、導電体560B、導電体542a、導電体542b、導電体542c、酸化物530bA、酸化物530bB、メモリ素子400、導電体458、導電体450、導電体448、及び導電体440のみを抜粋して示している。
本発明の一態様の半導体装置は、上述した構成に限定されず、適宜変更がなされていてもよい。
又は、本発明の一態様の半導体装置は、図10A、及び図10Bに示す構成としてもよい。図10A、及び図10Bに示すメモリセル600Aは、図1A、及び図1Bのメモリセル600Aの変更例であって、トランジスタ500Aとトランジスタ500Bの構成において、図1A、及び図1Bのメモリセル600Aと異なる。
又は、本発明の一態様の半導体装置は、図11A、及び図11Bに示す構成としてもよい。図11A、及び図11Bに示すメモリセル600Aは、図10A、及び図10Bのメモリセル600Aの変更例であって、トランジスタ500Aとトランジスタ500Bの構成において、図10A、及び図10Bのメモリセル600Aと異なる。
図4Cに示すメモリセルMCは、図4AのメモリセルMCの変更例であって、図4CのメモリセルMCも記憶装置に備えることができる。図4CのメモリセルMCは、配線SLを2本の配線WBL、及び配線RBLに変更している点と、配線BLを配線SLに変更している点で、図4AのメモリセルMCと異なる。
図12A、及び図12Bは、本発明の一態様の半導体装置である、図4CのメモリセルMCの構成例を示している。具体的には、図12Aは、メモリセル600Cの構成例を模式的に示した平面図であって、図12Bは、層OSLに含まれるメモリセル600Cの構成例を模式的に示した断面図である。
図4Dは、図4A乃至図4Cとは異なる、記憶装置に備えることができるメモリセルの一例を示している。なお、図4Dに示すメモリセルMCも、図4Aに示すメモリセルMCと同様にSOT−MRAMの一例である。
図15A、及び図15Bは、本発明の一態様の半導体装置である、図4DのメモリセルMCの構成例を示している。具体的には、図15Aは、メモリセル600Dの構成例を模式的に示した平面図であって、図15Bは、層OSLに含まれるメモリセル600Dの構成例を模式的に示した断面図である。
本実施の形態では、上述したメモリセルを適用できる記憶装置の構成例について説明する。
図17は、本発明の一態様の記憶装置の構成を示している。記憶装置MDVは、周辺回路PHL、及びメモリセルアレイMCAを有する。周辺回路PHLは、ローデコーダ2621、ワード線ドライバ回路2622、ビット線ドライバ回路2630、及び出力回路2640、コントロールロジック回路2660を有する。
次に、図19のメモリセル600を、図18Aの記憶装置MDVに適用した構成例を図22に示す。なお、図22では、見易くするために各構成要素を平面上に図示しているが、メモリセルアレイMCAは、図22と同様に、図18Aの記憶装置MDVのとおり、周辺回路PHLの上方に設けられているものとする。また、図22に示すメモリセルMC[1,1]乃至メモリセルMC[m,n]のいずれか一は、図19のメモリセル600に相当する。
本実施の形態では、上記の実施の形態で説明したOSトランジスタに用いることができる金属酸化物(以下、酸化物半導体ともいう)について説明する。
酸化物半導体の結晶構造としては、アモルファス(completely amorphousを含む)、CAAC(c−axis−aligned crystalline)、nc(nanocrystalline)、CAC(cloud−aligned composite)、単結晶(single crystal)、及び多結晶(poly crystal)等が挙げられる。
なお、酸化物半導体は、構造に着目した場合、上記とは異なる分類となる場合がある。例えば、酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体として、例えば、上述のCAAC−OS、およびnc−OSがある。また、非単結晶酸化物半導体には、多結晶酸化物半導体、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)、非晶質酸化物半導体、等が含まれる。
CAAC−OSは、複数の結晶領域を有し、当該複数の結晶領域はc軸が特定の方向に配向している酸化物半導体である。なお、特定の方向とは、CAAC−OS膜の厚さ方向、CAAC−OS膜の被形成面の法線方向、またはCAAC−OS膜の表面の法線方向である。また、結晶領域とは、原子配列に周期性を有する領域である。なお、原子配列を格子配列とみなすと、結晶領域とは、格子配列の揃った領域でもある。さらに、CAAC−OSは、a−b面方向において複数の結晶領域が連結する領域を有し、当該領域は歪みを有する場合がある。なお、歪みとは、複数の結晶領域が連結する領域において、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を指す。つまり、CAAC−OSは、c軸配向し、a−b面方向には明らかな配向をしていない酸化物半導体である。
nc−OSは、微小な領域(例えば、1nm以上10nm以下の領域、特に1nm以上3nm以下の領域)において原子配列に周期性を有する。別言すると、nc−OSは、微小な結晶を有する。なお、当該微小な結晶の大きさは、例えば、1nm以上10nm以下、特に1nm以上3nm以下であることから、当該微小な結晶をナノ結晶ともいう。また、nc−OSは、異なるナノ結晶間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、nc−OSは、分析方法によっては、a−like OSおよび非晶質酸化物半導体と区別が付かない場合がある。例えば、nc−OS膜に対し、XRD装置を用いて構造解析を行うと、θ/2θスキャンを用いたOut−of−plane XRD測定では、結晶性を示すピークが検出されない。また、nc−OS膜に対し、ナノ結晶よりも大きいプローブ径(例えば50nm以上)の電子線を用いる電子線回折(制限視野電子線回折ともいう)を行うと、ハローパターンのような回折パターンが観測される。一方、nc−OS膜に対し、ナノ結晶の大きさと近いかナノ結晶より小さいプローブ径(例えば1nm以上30nm以下)の電子線を用いる電子線回折(ナノビーム電子線回折ともいう)を行うと、ダイレクトスポットを中心とするリング状の領域内に複数のスポットが観測される電子線回折パターンが取得される場合がある。
a−like OSは、nc−OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。a−like OSは、鬆または低密度領域を有する。即ち、a−like OSは、nc−OSおよびCAAC−OSと比べて、結晶性が低い。また、a−like OSは、nc−OSおよびCAAC−OSと比べて、膜中の水素濃度が高い。
次に、上述のCAC−OSの詳細について、説明を行う。なお、CAC−OSは材料構成に関する。
CAC−OSとは、例えば、金属酸化物を構成する元素が、0.5nm以上10nm以下、好ましくは、1nm以上3nm以下、またはその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、一つまたは複数の金属元素が偏在し、該金属元素を有する領域が、0.5nm以上10nm以下、好ましくは、1nm以上3nm以下、またはその近傍のサイズで混合した状態をモザイク状、またはパッチ状ともいう。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
ここで、酸化物半導体中における各不純物の影響について説明する。
本実施の形態は、上記実施の形態に示す記憶装置などが形成された半導体ウェハ、及び当該記憶装置が組み込まれた電子部品の一例を示す。
初めに、記憶装置などが形成された半導体ウェハの例を、図23Aを用いて説明する。
図23Cに電子部品4700および電子部品4700が実装された基板(実装基板4704)の斜視図を示す。図23Cに示す電子部品4700は、モールド4711内にチップ4800aを有している。なお、図23Cに示すチップ4800aには、回路部4802が積層された構成を示している。つまり、回路部4802として、上記の実施の形態で説明した記憶装置を適用することができる。図23Cは、電子部品4700の内部を示すために、一部を省略している。電子部品4700は、モールド4711の外側にランド4712を有する。ランド4712は電極パッド4713と電気的に接続され、電極パッド4713はチップ4800aとワイヤ4714によって電気的に接続されている。電子部品4700は、例えばプリント基板4702に実装される。このような電子部品が複数組み合わされて、それぞれがプリント基板4702上で電気的に接続されることで実装基板4704が完成する。
本実施の形態では、上記の実施の形態の記憶装置を備えることができるCPUについて説明する。
本実施の形態では、上記実施の形態で説明した記憶装置を有する電子機器の一例について説明する。なお、図25A乃至図25J、図27A乃至図27Eには、当該記憶装置を有する電子部品4700が各電子機器に含まれている様子を図示している。
図25Aに示す情報端末5500は、情報端末の一種である携帯電話(スマートフォン)である。情報端末5500は、筐体5510と、表示部5511と、を有しており、入力用インターフェースとして、タッチパネルが表示部5511に備えられ、ボタンが筐体5510に備えられている。
また、図25Bには、ウェアラブル端末の一例である情報端末5900が図示されている。情報端末5900は、筐体5901、表示部5902、操作ボタン5903、操作子5904、バンド5905などを有する。
また、図25Cには、デスクトップ型情報端末5300が図示されている。デスクトップ型情報端末5300は、情報端末の本体5301と、ディスプレイ5302と、キーボード5303と、を有する。
また、図25Dには、電化製品の一例として電気冷凍冷蔵庫5800が図示されている。電気冷凍冷蔵庫5800は、筐体5801、冷蔵室用扉5802、冷凍室用扉5803等を有する。
また、図25Eには、ゲーム機の一例である携帯ゲーム機5200が図示されている。携帯ゲーム機5200は、筐体5201、表示部5202、及びボタン5203を有する。
上記実施の形態で説明した記憶装置は、移動体である自動車、及び自動車の運転席周辺に適用することができる。
上記実施の形態で説明した記憶装置は、カメラに適用することができる。
上記実施の形態で説明した記憶装置は、ビデオカメラに適用することができる。
上記実施の形態で説明した記憶装置は、植え込み型除細動器(ICD)に適用することができる。
上記実施の形態で説明した記憶装置は、AR(拡張現実)、又はVR(仮想現実)といったXR(Extended Reality、又はCross Reality)向けの電子機器に適用することができる。
上記実施の形態で説明した記憶装置は、PC(Personal Computer)などの計算機、情報端末用の拡張デバイスに適用することができる。
上記実施の形態で説明した記憶装置は、情報端末、デジタルカメラなどの電子機器に取り付けが可能なSDカードに適用することができる。
上記実施の形態で説明した記憶装置は、情報端末など電子機器に取り付けが可能なSSD(Solid State Drive)に適用することができる。
Claims (8)
- 第1導電体と、第2導電体と、第3導電体と、第1トランジスタと、第2トランジスタと、メモリ素子と、を有し、
前記第2導電体は、前記第1導電体の上方に位置し、
前記メモリ素子は、前記第2導電体の上方に位置し、
前記第1トランジスタ、及び前記第2トランジスタは、前記メモリ素子の上方に位置し、
前記第3導電体は、前記第1トランジスタ、及び前記第2トランジスタの上方に位置し、
平面視において、前記第3導電体は、前記第1導電体に重畳する領域に位置し、
前記第1導電体は、前記第2導電体に電気的に接続され、
前記第2導電体は、前記メモリ素子の第1端子と、前記第1トランジスタの第1端子と、に電気的に接続され、
前記メモリ素子の第2端子は、前記第2トランジスタの第1端子に電気的に接続され、
前記第1トランジスタの第2端子は、前記第2トランジスタの第2端子と、前記第3導電体と、に電気的に接続され、
前記第1トランジスタ、及び前記第2トランジスタのそれぞれは、チャネル形成領域に金属酸化物を含む、
半導体装置。 - 請求項1において、
前記メモリ素子は、抵抗変化素子、強誘電キャパシタ、FTJ素子、又は相変化メモリのいずれか一を有する、
半導体装置。 - 第1導電体と、第2導電体と、第3導電体と、第1トランジスタと、第2トランジスタと、メモリ素子と、を有し、
前記メモリ素子は、第1磁性層と、第2磁性層と、絶縁体と、を有し、
前記第2導電体は、前記第1導電体の上方に位置し、
前記第1磁性層は、前記第2導電体の上方に位置し、
前記絶縁体は、前記第1磁性層の上方に位置し、
前記第2磁性層は、前記絶縁体の上方に位置し、
前記第1トランジスタ、及び前記第2トランジスタは、前記第2磁性層の上方に位置し、
前記第3導電体は、前記第1トランジスタ、及び前記第2トランジスタの上方に位置し、
平面視において、前記第3導電体は、前記第1導電体に重畳する領域に位置し、
前記第1導電体は、前記第2導電体に電気的に接続され、
前記第2導電体は、前記第1磁性層と、前記第1トランジスタの第1端子と、に電気的に接続され、
前記第2磁性層は、前記第2トランジスタの第1端子に電気的に接続され、
前記第1トランジスタの第2端子は、前記第2トランジスタの第2端子と、前記第3導電体と、に電気的に接続され、
前記第1トランジスタ、及び前記第2トランジスタのそれぞれは、チャネル形成領域に金属酸化物を含む、
半導体装置。 - 請求項3において、
前記メモリ素子は、MTJ素子として機能し、
前記第1磁性層は、自由層として機能し、
前記第2磁性層は、固定層として機能し、
前記絶縁体は、トンネル絶縁体として機能し、
前記第2導電体は、電流が流れることでスピンホール効果が起きる金属材料を有する、
半導体装置。 - 第1導電体と、第2導電体と、第3導電体と、第1トランジスタと、第2トランジスタと、メモリ素子と、を有し、
前記メモリ素子は、第1磁性層と、第2磁性層と、絶縁体と、を有し、
前記第1トランジスタ、及び前記第2トランジスタは、前記第3導電体の上方に位置し、
前記第2磁性層は、前記第1トランジスタ、及び前記第2トランジスタの上方に位置し、
前記絶縁体は、前記第2磁性層の上方に位置し、
前記第1磁性層は、前記絶縁体の上方に位置し、
前記第2導電体は、前記第1磁性層の上方に位置し、
前記第1導電体は、前記第2導電体の上方に位置し、
平面視において、前記第1導電体は、前記第3導電体に重畳する領域に位置し、
前記第1導電体は、前記第2導電体に電気的に接続され、
前記第2導電体は、前記第1磁性層と、前記第1トランジスタの第1端子と、に電気的に接続され、
前記第2磁性層は、前記第2トランジスタの第1端子に電気的に接続され、
前記第1トランジスタの第2端子は、前記第2トランジスタの第2端子と、前記第3導電体と、に電気的に接続され、
前記第1トランジスタ、及び前記第2トランジスタのそれぞれは、チャネル形成領域に金属酸化物を含む、
半導体装置。 - 請求項5において、
前記メモリ素子は、MTJ素子として機能し、
前記第1磁性層は、自由層として機能し、
前記第2磁性層は、固定層として機能し、
前記絶縁体は、トンネル絶縁体として機能し、
前記第2導電体は、電流が流れることでスピンホール効果が起きる金属材料を有する、
半導体装置。 - 請求項1乃至請求項6のいずれか一の半導体装置と、周辺回路を含む層と、を有し、
前記層は、前記半導体装置の下方に位置し、
前記周辺回路は、前記半導体装置へのデータの書き込み、及び前記半導体装置からのデータの読み出しを行う機能を有する、
記憶装置。 - 請求項7の記憶装置と、筐体と、を有する電子機器。
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JP2014220376A (ja) * | 2013-05-08 | 2014-11-20 | ソニー株式会社 | 半導体装置およびその製造方法 |
JP2015228493A (ja) * | 2014-05-08 | 2015-12-17 | 株式会社半導体エネルギー研究所 | 半導体装置 |
WO2019073333A1 (ja) * | 2017-10-13 | 2019-04-18 | 株式会社半導体エネルギー研究所 | 記憶装置、電子部品、及び電子機器 |
US20190334080A1 (en) * | 2017-01-17 | 2019-10-31 | Agency For Science, Technology And Research | Memory cell, memory array, method of forming and operating memory cell |
US20200075670A1 (en) * | 2018-08-31 | 2020-03-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Magnetic tunnel junction structures and related methods |
WO2021014810A1 (ja) * | 2019-07-24 | 2021-01-28 | ソニーセミコンダクタソリューションズ株式会社 | 不揮発性メモリセル、不揮発性メモリセルアレイ、及び、不揮発性メモリセルアレイの情報書き込み方法 |
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US9177872B2 (en) | 2011-09-16 | 2015-11-03 | Micron Technology, Inc. | Memory cells, semiconductor devices, systems including such cells, and methods of fabrication |
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JP2014220376A (ja) * | 2013-05-08 | 2014-11-20 | ソニー株式会社 | 半導体装置およびその製造方法 |
JP2015228493A (ja) * | 2014-05-08 | 2015-12-17 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US20190334080A1 (en) * | 2017-01-17 | 2019-10-31 | Agency For Science, Technology And Research | Memory cell, memory array, method of forming and operating memory cell |
WO2019073333A1 (ja) * | 2017-10-13 | 2019-04-18 | 株式会社半導体エネルギー研究所 | 記憶装置、電子部品、及び電子機器 |
US20200075670A1 (en) * | 2018-08-31 | 2020-03-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Magnetic tunnel junction structures and related methods |
WO2021014810A1 (ja) * | 2019-07-24 | 2021-01-28 | ソニーセミコンダクタソリューションズ株式会社 | 不揮発性メモリセル、不揮発性メモリセルアレイ、及び、不揮発性メモリセルアレイの情報書き込み方法 |
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