WO2023042536A1 - 炭化珪素半導体装置 - Google Patents

炭化珪素半導体装置 Download PDF

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Publication number
WO2023042536A1
WO2023042536A1 PCT/JP2022/027572 JP2022027572W WO2023042536A1 WO 2023042536 A1 WO2023042536 A1 WO 2023042536A1 JP 2022027572 W JP2022027572 W JP 2022027572W WO 2023042536 A1 WO2023042536 A1 WO 2023042536A1
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Prior art keywords
region
gate
silicon carbide
semiconductor device
pad
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PCT/JP2022/027572
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English (en)
French (fr)
Japanese (ja)
Inventor
光亮 内田
健良 増田
雄 斎藤
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Priority to CN202280051428.1A priority Critical patent/CN117693823A/zh
Priority to DE112022004405.5T priority patent/DE112022004405T5/de
Priority to JP2023548145A priority patent/JPWO2023042536A1/ja
Priority to US18/580,785 priority patent/US20240339499A1/en
Publication of WO2023042536A1 publication Critical patent/WO2023042536A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs

Definitions

  • the present disclosure relates to silicon carbide semiconductor devices.
  • Patent Document 1 A silicon carbide semiconductor device aimed at suppressing dielectric breakdown between a gate electrode and a source electrode during switching has been disclosed (for example, Patent Document 1).
  • a silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface, and a gate pad and a source pad provided above the first main surface. a first region including a plurality of unit cells; a second region overlapping with the gate pad; Each of the plurality of unit cells includes: a drift region having a first conductivity type; a body region having a second conductivity type different from the first conductivity type; a source region separated from the drift region and having the first conductivity type; a contact region provided on the first main surface and electrically connected to the body region and having the second conductivity type; and the gate pad. and a gate insulating film provided between the drift region, the body region and the source region, and the gate electrode, wherein the second region is the second region.
  • first semiconductor region having two conductivity types
  • third region having a second semiconductor region having the second conductivity type
  • an interlayer insulating film provided between the first semiconductor region and the gate pad, the source region, the contact region, and the second semiconductor region being electrically connected to the source pad; Connected.
  • FIG. 1 is a top view showing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 2 is a diagram showing respective regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 3 is a top view showing the region 221 in FIG. 2 through the passivation film, the gate pad and the source pad.
  • FIG. 4 is a top view showing the configuration of the first main surface of the silicon carbide substrate in region 221 in FIG.
  • FIG. 5 is a top view showing the region 222 in FIG. 2 through the passivation film, the gate pad and the source pad.
  • FIG. 6 is a top view showing the region 223 in FIG. 2 through the passivation film, the gate pad and the source pad.
  • FIG. 7 is a top view showing the region 224 in FIG.
  • FIG. 8 is a cross-sectional view (part 1) showing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 9 is a cross-sectional view (Part 2) showing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 10 is a cross-sectional view (part 3) showing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 11 is a cross-sectional view (part 4) showing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 12 is a cross-sectional view (No. 5) showing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 13 is a cross-sectional view (No. 6) showing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 14 is a cross-sectional view showing the configuration of a unit cell.
  • FIG. 15 is a diagram showing respective regions in the silicon carbide substrate in the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 16 is a top view showing the region 222 in FIG. 15 through the passivation film, gate pad and source pad.
  • FIG. 17 is a top view showing the region 223 in FIG. 15 through the passivation film, gate pad and source pad.
  • FIG. 18 is a cross-sectional view showing a silicon carbide semiconductor device according to the second embodiment.
  • FIG. 19 is a top view showing a silicon carbide semiconductor device according to the third embodiment.
  • FIG. 20 is a diagram showing respective regions in the silicon carbide substrate in the silicon carbide semiconductor device according to the third embodiment.
  • FIG. 21 is a diagram showing respective regions within a silicon carbide substrate in a silicon carbide semiconductor device according to a fourth embodiment.
  • FIG. 22 is a diagram showing respective regions in the silicon carbide substrate in the silicon carbide semiconductor device according to the fifth embodiment.
  • FIG. 23 is a diagram showing respective regions in the silicon carbide substrate in the silicon carbide semiconductor device according to the sixth embodiment.
  • FIG. 24 is a diagram showing respective regions in the silicon carbide substrate in the silicon carbide semiconductor device according to the seventh embodiment.
  • FIG. 25 is a top view showing the silicon carbide semiconductor device according to the eighth embodiment.
  • FIG. 26 is a diagram showing each region in the silicon carbide substrate in the silicon carbide semiconductor device according to the eighth embodiment.
  • FIG. 27 is a diagram showing each region in the silicon carbide substrate in the silicon carbide semiconductor device according to the ninth embodiment.
  • FIG. 28 is a top view showing the silicon carbide semiconductor device according to the tenth embodiment.
  • FIG. 29 is a diagram showing respective regions in the silicon carbide substrate in the silicon carbide semiconductor device according to the tenth embodiment.
  • FIG. 30 is a top view showing the silicon carbide semiconductor device according to the eleventh embodiment.
  • FIG. 31 is a diagram showing each region in the silicon carbide substrate in the silicon carbide semiconductor device according to the eleventh embodiment.
  • FIG. 32 is a top view showing a modification of the first region.
  • An object of the present disclosure is to provide a silicon carbide semiconductor device capable of alleviating electric field concentration in an interlayer insulating film.
  • a silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface, and a gate pad and a source pad provided above the first main surface, and the A silicon carbide substrate, in plan view from a direction perpendicular to the first main surface, includes a first region including a plurality of unit cells, a second region overlapping with the gate pad, and a third region continuous with the second region.
  • each of the plurality of unit cells includes: a drift region having a first conductivity type; a body region having a second conductivity type different from the first conductivity type; a source region separated from the drift region by the body region and having the first conductivity type; and a source region provided on the first main surface and electrically connected to the body region and having the second conductivity type.
  • the second region has a first semiconductor region having the second conductivity type
  • the third region has a second semiconductor region having the second conductivity type
  • the first semiconductor region and the second semiconductor region have the second conductivity type.
  • the semiconductor regions are connected to each other on the first main surface and have an interlayer insulating film provided between the first semiconductor region and the gate pad, and the source region, the contact region and the second semiconductor region are electrically connected to the source pad;
  • a third region is provided that is continuous with the second region, and the first semiconductor region and the second semiconductor region are continuous with each other on the first main surface. Therefore, the contact resistance between the source pad and the second semiconductor region is reduced, and even if a surge occurs, electric field concentration on the interlayer insulating film in the second region can be alleviated.
  • the contact region and the second semiconductor region may be connected to each other on the first main surface. In this case, it is easy to control the contact region and the second semiconductor region to have the same potential.
  • the plurality of unit cells extend in a first direction in plan view and are arranged side by side in a second direction perpendicular to the first direction at a first pitch, A dimension of the second semiconductor region in a direction away from the second region may be equal to or greater than the first pitch. In this case, it is easy to reduce the contact resistance between the source pad and the second semiconductor region.
  • the dimension of the second semiconductor region in the direction away from the second region may be twice or more the first pitch. In this case, it is easier to further reduce the contact resistance between the source pad and the second semiconductor region.
  • the third region has a fourth region located between the first region and the second region in plan view, and may be equal to or larger than the first pitch in the second direction. In this case, it is easy to reduce the contact resistance between the source pad and the second semiconductor region.
  • the dimension of the second semiconductor region in the fourth region in the second direction may be twice or more the first pitch. In this case, it is easier to further reduce the contact resistance between the source pad and the second semiconductor region.
  • the third region has a fifth region positioned on the first direction side with respect to the second region and the fourth region,
  • the area of the second semiconductor region within the fifth region may be equal to or larger than the area of the second semiconductor region within the fourth region. In this case, it is easier to further reduce the contact resistance between the source pad and the second semiconductor region.
  • the third region is located on the side opposite to the first direction with respect to the second region and the fourth region.
  • 6 regions, and the area of the second semiconductor region in the sixth region may be equal to or larger than the area of the second semiconductor region in the fourth region. In this case, it is easier to further reduce the contact resistance between the source pad and the second semiconductor region.
  • the interlayer insulating film is also formed between the first region and the third region, and in the first region, the A first contact hole reaching the source region and the contact region is formed in the interlayer insulating film, a second contact hole reaching the second semiconductor region is formed in the interlayer insulating film in the third region, and the first contact hole reaches the second semiconductor region.
  • the contact holes and the second contact holes may be arranged side by side in the second direction at a constant pitch. In this case, microloading is suppressed when forming the first contact hole and the second contact hole, and variation in characteristics is suppressed.
  • the silicon carbide substrate has a first side and a second side parallel to each other and a side perpendicular to the first side and the second side.
  • a first gate runner extending along the first side, a second gate runner extending along the second side, and the first gate having a rectangular shape with a third side and a fourth side.
  • a runner and a third gate runner continuous with the second gate runner and extending along the third side, wherein the gate pad is continuous with the first gate runner, and the second gate runner is It may be separated from the gate pad in a direction parallel to the third side.
  • the gate pad may include an intersection point between the first gate runner and the third gate runner, and may be continuous with the first gate runner and the third gate runner.
  • the gate pads can be arranged near the corners of the silicon carbide substrate.
  • the third gate runner may be separated from the gate pad in a direction parallel to the first side.
  • the gate pad can be arranged away from the corner of the silicon carbide substrate.
  • the third region has a seventh region arranged along the third side of the gate pad in plan view, and the seventh region includes the It may continue to the third gate runner. In this case, it is easier to further reduce the contact resistance between the source pad and the second semiconductor region.
  • the third region has an eighth region arranged along the second side of the gate pad in plan view,
  • the eighth region may be remote from the second gate runner. In this case, it is easier to further reduce the contact resistance between the source pad and the second semiconductor region.
  • the third region has an eighth region arranged along the second side of the gate pad in plan view,
  • the eighth region may be continuous with the second gate runner. In this case, it is easier to further reduce the contact resistance between the source pad and the second semiconductor region.
  • the third region has a ninth region arranged along the fourth side of the gate pad in plan view. good too. In this case, it is easier to further reduce the contact resistance between the source pad and the second semiconductor region.
  • the silicon carbide substrate has a first side and a second side parallel to each other and a side perpendicular to the first side and the second side.
  • a first gate runner having a rectangular shape with a third side and a fourth side, the third region surrounding the gate pad and extending along the first side in a plan view;
  • a second gate runner extending along a second side;
  • a third gate runner continuous with the first gate runner and the second gate runner and extending along the third side; the third gate runner and the gate and a fourth gate runner connecting with the pad.
  • the degree of freedom in arranging the gate pads can be increased.
  • a plane including the X1-X2 direction and the Y1-Y2 direction is referred to as the XY plane
  • a plane including the Y1-Y2 direction and the Z1-Z2 direction is referred to as the YZ plane
  • a plane including the Z1-Z2 direction and the X1-X2 direction. is described as the ZX plane.
  • the Z1-Z2 direction is the vertical direction
  • the Z1 side is the upper side
  • the Z2 side is the lower side.
  • the term "planar view” refers to viewing the object from the Z1 side
  • the term "planar shape” refers to the shape of the object viewed from the Z1 side.
  • FIG. 1 is a top view showing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 2 is a diagram showing respective regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 3 is a top view showing the region 221 in FIG. 2 through the passivation film, the gate pad and the source pad.
  • FIG. 4 is a top view showing the configuration of the first main surface of the silicon carbide substrate in region 221 in FIG.
  • FIG. 5 is a top view showing the region 222 in FIG. 2 through the passivation film, the gate pad and the source pad.
  • FIG. 1 is a top view showing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 2 is a diagram showing respective regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 3 is a top view showing the region 221 in FIG. 2 through the passivation film, the gate pad and the source pad.
  • FIG. 4 is a top view showing the configuration of the
  • FIG. 6 is a top view showing the region 223 in FIG. 2 through the passivation film, the gate pad and the source pad.
  • FIG. 7 is a top view showing the region 224 in FIG. 2 through the passivation film, gate pad and source pad.
  • 8 to 13 are cross-sectional views showing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIG.
  • FIG. 9 corresponds to a cross-sectional view taken along line IX-IX in FIG.
  • FIG. 10 corresponds to a cross-sectional view taken along line XX in FIG.
  • FIG. 11 corresponds to a cross-sectional view taken along line XI-XI in FIG.
  • FIG. 12 corresponds to a cross-sectional view taken along line XII-XII in FIG.
  • FIG. 13 corresponds to a cross-sectional view taken along line XIII-XIII in FIG.
  • FIG. 14 is a cross-sectional view showing the configuration of a unit cell. 8 to 14 omit the passivation film.
  • a MOSFET 201 includes a silicon carbide substrate 10, a gate insulating film 63, a gate electrode 51, an interlayer insulating film 44, a contact electrode 52, and a passivation film 80. , and a drain electrode 53 .
  • the MOSFET 201 further has a gate pad 61, a source pad 62, a gate runner (gate wiring) 61A, a gate runner 61B, a gate runner 61C, a gate runner 61D, and a source runner (source wiring) 62C.
  • Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 20 and a silicon carbide epitaxial layer 30 on silicon carbide single crystal substrate 20 .
  • Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1 .
  • Silicon carbide epitaxial layer 30 forms first main surface 1
  • silicon carbide single-crystal substrate 20 forms second main surface 2 .
  • Silicon carbide single-crystal substrate 20 and silicon carbide epitaxial layer 30 are made of, for example, polytype 4H hexagonal silicon carbide.
  • Silicon carbide single-crystal substrate 20 contains an n-type impurity such as nitrogen (N) and has n-type (first conductivity type).
  • the first main surface 1 is a plane in which the ⁇ 0001 ⁇ plane or the ⁇ 0001 ⁇ plane is inclined in the off direction by an off angle of 8° or less.
  • the first main surface 1 is the (000-1) plane or a plane in which the (000-1) plane is inclined in the off direction by an off angle of 8° or less.
  • the off direction may be, for example, the ⁇ 11-20> direction or the ⁇ 1-100> direction.
  • the off angle may be, for example, 1° or more, or may be 2° or more.
  • the off angle may be 6° or less, or may be 4° or less.
  • silicon carbide substrate 10 has a rectangular shape with first side 91 and second side 92 parallel to each other, and third side 93 and fourth side 94 perpendicular to first side 91 and second side 92 .
  • has the shape of The first side 91 and the second side 92 are parallel to the Y1-Y2 direction, and the third side 93 and the fourth side 94 are parallel to the X1-X2 direction.
  • the first side 91 is on the X2 side of the second side 92
  • the second side 92 is on the X1 side of the first side 91 .
  • the third side 93 is on the Y1 side of the fourth side 94
  • the fourth side 94 is on the Y2 side of the third side 93 .
  • the silicon carbide substrate 10 has an active region 41 and a termination region 42 provided around the active region 41 in plan view.
  • the active region 41 has a first region 101 , a second region 102 and a third region 103 .
  • a first area 101 is an area in which a plurality of unit cells are arranged.
  • the second region 102 is a region that overlaps the gate pad 61 in plan view.
  • a third area 103 is an area in which a plurality of dummy cells are arranged.
  • the unit cells are arranged in the Y1-Y2 direction with the X1-X2 direction as the longitudinal direction. The dimensions in the Y1-Y2 direction of each unit cell are common.
  • Each unit cell has a pair of gate trenches and gate electrodes.
  • the unit cells are arranged at a constant pitch P1 in the Y1-Y2 direction.
  • the dummy cell has the X1-X2 direction as its longitudinal direction.
  • a plurality of dummy cells may be arranged at a constant pitch P1 in the Y1-Y2 direction.
  • the dimension of the dummy cell in the Y1-Y2 direction matches the dimension of the unit cell in the Y1-Y2 direction.
  • a dummy cell may have a gate electrode, but the dummy cell does not have a gate trench.
  • the X1-X2 direction is an example of the first direction
  • the Y1-Y2 direction is an example of the second direction.
  • the silicon carbide epitaxial layer 30 includes a drift region 31, a body region 32, a source region 33, a contact region 34, a buried region 35, a buried junction termination extension (JTE) region 36, a surface It mainly has a JTE region 37 .
  • Drift region 31 is provided over active region 41 and termination region 42 .
  • Body region 32 , source region 33 , contact region 34 and buried region 35 are provided within active region 41 .
  • Buried JTE region 36 and surface JTE region 37 are provided in termination region 42 .
  • a portion of the contact region 34 and the buried region 35 may also be provided in the termination region 42 .
  • Drift region 31 is provided on silicon carbide single crystal substrate 20 .
  • Drift region 31 is located closer to first main surface 1 than silicon carbide single-crystal substrate 20 is.
  • Drift region 31 may continue to silicon carbide single-crystal substrate 20 .
  • Drift region 31 contains n-type impurities such as nitrogen or phosphorus (P), and has n-type conductivity.
  • the body region 32 is provided on the drift region 31.
  • Body region 32 contains a p-type impurity such as aluminum (Al) and has a p-type conductivity (second conductivity type).
  • Body region 32 is located closer to first main surface 1 than drift region 31 is.
  • Drift region 31 is located closer to second main surface 2 than body region 32 .
  • Body region 32 is in contact with drift region 31 .
  • a source region 33 is provided on the body region 32 .
  • Source region 33 is separated from drift region 31 by body region 32 .
  • the source region 33 contains an n-type impurity such as nitrogen or phosphorus and has n-type conductivity.
  • Source region 33 is located closer to first main surface 1 than body region 32 is.
  • Body region 32 is located closer to second main surface 2 than source region 33 is.
  • Source region 33 is in contact with body region 32 .
  • Source region 33 constitutes first main surface 1 .
  • Source region 33 is covered with gate insulating film 43 .
  • Source region 33 is in direct contact with gate insulating film 43 .
  • the contact region 34 contains p-type impurities such as aluminum and has p-type conductivity.
  • the p-type impurity concentration of the contact region 34 is higher than the p-type impurity concentration of the body region 32, for example.
  • Contact region 34 penetrates source region 33 and body region 32 .
  • Contact region 34 contacts body region 32 .
  • Contact region 34 constitutes first main surface 1 .
  • a gate trench 5 defined by the side surface 3 and the bottom surface 4 is provided on the first main surface 1 .
  • Side surface 3 reaches drift region 31 through source region 33 and body region 32 .
  • the bottom surface 4 is continuous with the side surfaces 3 .
  • a source region 33 , a body region 32 and a drift region 31 are in contact with the side surface 3 .
  • Bottom surface 4 is located in drift region 31 .
  • the bottom surface 4 is, for example, a plane parallel to the second main surface 2 .
  • An angle ⁇ 1 of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 45° or more and 65° or less.
  • the angle ⁇ 1 may be, for example, 50° or more.
  • the angle ⁇ 1 may be, for example, 60° or less.
  • Side 3 preferably has a ⁇ 0-33-8 ⁇ plane.
  • the ⁇ 0-33-8 ⁇ plane is a crystal plane that provides excellent mobility.
  • the gate trench 5 extends in the X1-X2 direction parallel to the first main surface 1 in plan view. Also, in plan view, a plurality of gate trenches 5 are provided at regular intervals in the Y1-Y2 direction. Gate trenches 5 are not provided in the second region 102 and the third region 103 .
  • the embedded region 35 contains a p-type impurity such as aluminum and has a p-type conductivity. Embedded region 35 is located closer to second main surface 2 than contact region 34 . Contact region 34 is located closer to first main surface 1 than buried region 35 . Buried region 35 is in contact with contact region 34 . Embedded region 35 is formed at a position deeper than gate trench 5 . The top surface of embedded region 35 is positioned closer to second main surface 2 than bottom surface 4 of gate trench 5 .
  • the embedded JTE region 36 contacts the embedded region 35 in a direction parallel to the first main surface 1 .
  • the embedded JTE region 36 is formed in an annular shape in plan view. Buried JTE region 36 contains p-type impurities, such as aluminum, and has p-type conductivity.
  • the embedded JTE region 36 is spaced from the first major surface 1 and the second major surface 2 .
  • the upper end surface of embedded JTE region 36 contacts the lower end surface of contact region 34 .
  • the surface JTE region 37 contacts the contact region 34 in a direction parallel to the first main surface 1 .
  • the surface JTE region 37 is formed in an annular shape in plan view.
  • Surface JTE region 37 contains p-type impurities such as aluminum and has p-type conductivity.
  • Surface JTE region 37 is provided above buried JTE region 36 .
  • Surface JTE region 37 is spaced from buried JTE region 36 .
  • Surface JTE region 37 is located closer to first main surface 1 than buried JTE region 36 .
  • Embedded JTE region 36 is located closer to second main surface 2 than surface JTE region 37 .
  • Surface JTE region 37 constitutes first main surface 1 .
  • a portion of drift region 31 is between surface JTE region 37 and buried JTE region 36 .
  • the gate insulating film 43 is, for example, an oxide film.
  • the gate insulating film 43 is made of a material containing silicon dioxide, for example.
  • the gate insulating film 43 is in contact with the side surfaces 3 and the bottom surface 4 .
  • Gate insulating film 43 is in contact with drift region 31 at bottom surface 4 .
  • Gate insulating film 43 is in contact with each of source region 33 , body region 32 and drift region 31 at side surface 3 .
  • Gate insulating film 43 may be in contact with source region 33 , contact region 34 and surface JTE region 37 on first main surface 1 .
  • the gate electrode 51 is provided on the gate insulating film 43 .
  • the gate electrode 51 is made of, for example, polysilicon (poly-Si) containing conductive impurities. A portion of the gate electrode 51 is arranged inside the gate trench 5 . A portion of gate electrode 51 is arranged above first main surface 1 .
  • the interlayer insulating film 44 is provided in contact with the gate electrode 51 and the gate insulating film 43 .
  • the interlayer insulating film 44 is, for example, an oxide film.
  • the interlayer insulating film 44 is made of a material containing silicon dioxide, for example.
  • the interlayer insulating film 44 electrically insulates the gate electrode 51 from the contact electrode 52 and the source pad 62 .
  • a contact hole 71 for a gate is formed in the interlayer insulating film 44 .
  • Gate electrode 51 is exposed from interlayer insulating film 44 through contact hole 71 .
  • the gate pad 61 is provided on the interlayer insulating film 44 and is in contact with the gate electrode 51 within the contact hole 71 .
  • the gate pad 61 is made of a material containing aluminum, for example.
  • a source contact hole 72 is formed in the interlayer insulating film 44 and the gate insulating film 43 .
  • the source region 33 and the contact region 34 in the first region 101 are exposed from the interlayer insulating film 44 and the gate insulating film 43 through the contact hole 72 .
  • Contact hole 72 is an example of a first contact hole.
  • a contact hole 73 for a dummy cell is formed in the interlayer insulating film 44 and the gate insulating film 43 .
  • the contact region 34 in the third region 103 is exposed from the interlayer insulating film 44 and the gate insulating film 43 through the contact hole 73 .
  • Contact hole 73 is an example of a second contact hole.
  • the contact electrode 52 is in contact with the source region 33 and the contact region 34 within the contact hole 72 .
  • the contact electrode 52 is made of a material containing nickel silicide (NiSi), for example.
  • Contact electrode 52 may be made of a material containing titanium, aluminum, and silicon.
  • the contact electrode 52 is in ohmic contact with the source region 33 and contact region 34 .
  • the source pad 62 is provided on the interlayer insulating film 44 and is in contact with the contact electrode 52 within the contact hole 72 .
  • the source pad 62 is made of a material containing aluminum, for example.
  • Source pad 62 may include a barrier metal film (not shown) covering the surface of interlayer insulating film 44 .
  • source pads 62 may include source pads 62A and 62B.
  • source pad 62A is on the X2 side of the center of silicon carbide substrate 10 in the X1-X2 direction
  • source pad 62B is on the X1 side of the center of silicon carbide substrate 10 in the X1-X2 direction.
  • the gate pad 61 is located on the Y1 side of the source pad 62, and the planar shape of the gate pad 61 is rectangular.
  • the dimension of the gate pad 61 in the X1-X2 direction is larger than the dimension in the Y1-Y2 direction.
  • the source pad 62 is located on the Y2 side of the gate pad 61 and has a rectangular planar shape.
  • the distance of the gate pad 61 from the first side 91 and the distance from the second side 92 are approximately the same.
  • the distance of gate pad 61 from third side 93 is smaller than the distance from fourth side 94 .
  • the distance of the source pad 62 from the first side 91 and the distance from the second side 92 are approximately the same.
  • the distance of source pad 62 from third side 93 is greater than the distance from fourth side 94 .
  • the dimension in the X1-X2 direction of the gate pad 61 may be smaller than the dimension in the X1-X2 direction of the source pad 62, and the dimension in the Y1-Y2 direction of the gate pad 61 may be smaller than the dimension in the Y1-Y2 direction of the source pad 62.
  • Source pad 62 is arranged so as to include a center line that bisects silicon carbide substrate 10 in the Y1-Y2 direction in plan view.
  • the gate runner 61A extends along the first side 91 in the Y1-Y2 direction.
  • the gate runner 61B extends along the second side 92 in the Y1-Y2 direction.
  • the gate runner 61C extends along the third side 93 in the X1-X2 direction.
  • the Y1 side end of the gate runner 61A and the X2 side end of the gate runner 61C are connected.
  • the Y1 side end of the gate runner 61B and the X1 side end of the gate runner 61C are connected.
  • Gate runner 61 A is on the X2 side of source pad 62 A
  • gate runner 61 B is on the X1 side of source pad 62 B
  • gate runner 61 C is on the Y1 side of gate pad 61
  • a gate runner 61C is connected to the gate pad 61 .
  • the gate pad 61 is continuous with the gate runner 61C
  • the gate runners 61A and 61B are continuous with the gate runner 61C.
  • Gate runners 61A and 61B are spaced apart from gate pad 61 in the X1-X2 direction.
  • a gate runner 61D is connected to the gate pad 61 and extends in the Y1-Y2 direction between the source pads 62A and 62B.
  • Gate runners 61 A, 61 B, 61 C and 61 D are made of the same material as gate pad 61 .
  • the source runner 62C is annularly provided outside the source pad 62 and the gate runners 61A, 61B and 61C in plan view.
  • Source runner 62C is connected to source pad 62 and is continuous.
  • Source runner 62C is made of the same material as source pad 62.
  • a contact hole for the source runner 62C is annularly formed in the interlayer insulating film 44 and the gate insulating film 43, and the source runner 62C is electrically connected to the contact region 34 through the annular contact hole.
  • Contact hole 73 is part of the contact hole for source runner 62C.
  • a passivation film 80 covers the gate pad 61 , source pad 62 and interlayer insulating film 44 .
  • the passivation film 80 is in contact with the gate pad 61 , the source pad 62 and the interlayer insulating film 44 .
  • the passivation film 80 also covers the gate runners 61A, 61B, 61C and 61D and the source runner 62C.
  • the passivation film 80 is also in contact with the gate runners 61A, 61B, 61C and 61D and the source runner 62C.
  • the passivation film 80 is made of a material containing, for example, silicon nitride or polyimide.
  • the passivation film 80 is formed with an opening 81 exposing a portion of the upper surface of the gate pad 61 and an opening 82 exposing a portion of the upper surface of the source pad 62 .
  • the drain electrode 53 is in contact with the second main surface 2 . Drain electrode 53 is in contact with silicon carbide single-crystal substrate 20 at second main surface 2 . Drain electrode 53 is electrically connected to drift region 31 .
  • the drain electrode 53 is made of a material containing nickel silicide, for example. Drain electrode 53 may be made of a material containing titanium, aluminum, and silicon. Drain electrode 53 is in ohmic contact with silicon carbide single crystal substrate 20 .
  • a buffer layer containing an n-type impurity such as nitrogen and having n-type conductivity may be provided between silicon carbide single-crystal substrate 20 and drift region 31 .
  • the second region 102 is on the Z2 side of the gate pad 61.
  • the third area 103 continues to the second area 102 .
  • the third region 103 includes a fourth region 104 on the Y2 side of the second region 102, a fifth region 105 on the X2 side of the second region 102 and the fourth region 104, and an X1 region of the second region 102 and the fourth region 104. and a tenth region 110 on the Y1 side of the second region 102 .
  • the planar shapes of the fourth region 104, the fifth region 105, the sixth region 106, and the tenth region 110 are rectangular, for example.
  • the first area 101 is on the Y2 side of the fourth area 104, the fifth area 105 and the sixth area .
  • the first region 101 is provided in the X1-X2 direction from the vicinity of the gate runner 61A to the vicinity of the gate runner 61B.
  • the first region 101 is also provided between the fifth region 105 and the gate runner 61A in plan view and between the sixth region 106 and the gate runner 61B in plan view. Part or all of the tenth region 110 may be within the termination region 42 .
  • the gate trench 5 is provided in the first region 101 but not provided in the second region 102 and the third region 103 .
  • a source region 33 is also provided in the first region 101 but not provided in the second region 102 and the third region 103 . Therefore, in the second region 102 and the third region 103 , the first main surface 1 is formed by the contact regions 34 .
  • Contact region 34 in first region 101 , contact region 34 in second region 102 , and contact region 34 in third region 103 are connected to each other on first main surface 1 .
  • the source regions 33 are provided between the gate trenches 5 adjacent in the Y1-Y2 direction.
  • Each unit cell includes a pair of gate trenches 5 and gate electrodes 51, and a plurality of unit cells are arranged in the Y1-Y2 direction at a constant pitch P1 in the first region 101.
  • the contact region 34 within the second region 102 is an example of the first semiconductor region 121
  • the contact region 34 within the third region 103 is an example of the second semiconductor region 122 .
  • the gate electrode 51 may be provided on the contact region 34 on the Z1 side of the fifth region 105 and the sixth region 106 with the gate insulating film 43 interposed therebetween.
  • the plurality of source contact holes 72 formed in the interlayer insulating film 44 are arranged at a constant pitch P2 equal to the pitch P1 in the Y1-Y2 direction. Further, on the Z1 side of the third region 103, the plurality of dummy cell contact holes 73 formed in the interlayer insulating film 44 are arranged at a pitch P2 in the Y1-Y2 direction. The pitch between the contact holes 72 and 73 adjacent in the Y1-Y2 direction is also P2.
  • a gate contact hole 71 is formed in the interlayer insulating film 44, but a source contact hole 72 and a dummy cell contact hole 73 are not formed.
  • Gate contact holes 71 are also formed in the interlayer insulating film 44 between the gate runners 61 A, 61 B, 61 C and 61 D and the gate electrode 51 .
  • the contact hole 71 is provided for each gate electrode 51 in FIG. In this case, electrical resistance between the gate electrode 51 and the gate runner 61D can be reduced. The same applies to gate runners 61A, 61B and 61C.
  • the contact hole 73 is also formed in a portion between the interlayer insulating film 44 and the tenth region 110 of the gate insulating film 43 and the source runner 62C.
  • the contact electrode 52 is in contact with the contact region 34 within the contact hole 73 .
  • the contact electrode 52 is in ohmic contact with the contact region 34 .
  • the source pad 62 and the source runner 62 ⁇ /b>C are in contact with the contact electrode 52 even inside the contact hole 73 .
  • a third region 103 is provided which is continuous with the second region 102 , and the contact regions 34 are continuous in the second region 102 and the third region 103 . Therefore, the contact resistance between the source pad 62 and the contact region 34 is reduced, and even if a surge occurs, electric field concentration on the interlayer insulating film 44 in the second region 102 can be alleviated.
  • the contact holes 73 for dummy cells formed in the interlayer insulating film 44 are formed at the same pitch P2 as the contact holes 72 for the source of the unit cells. Therefore, microloading is suppressed when the contact holes 72 and 73 are formed, and variations in characteristics are suppressed.
  • the contact region 34 in the first region 101 and the contact region 34 in the third region 103 are connected to each other, it is easy to control them to have the same potential.
  • the dimension of the contact region 34 in the fourth region 104 in the Y1-Y2 direction is preferably equal to or greater than the unit cell pitch P1, and more preferably equal to or greater than twice the pitch P1. This is because the contact resistance can be further reduced.
  • the area of the contact region 34 within the fifth region 105 is preferably equal to or greater than the area of the contact region 34 within the fourth region 104 .
  • the area of the contact region 34 within the sixth region 106 is preferably greater than or equal to the area of the contact region 34 within the fourth region 104 . This is because both can further reduce the contact resistance.
  • the third area 103 does not have to include the tenth area 110 .
  • FIG. 15 is a diagram showing respective regions in the silicon carbide substrate in the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 16 is a top view showing the region 222 in FIG. 15 through the passivation film, gate pad and source pad.
  • FIG. 17 is a top view showing the region 223 in FIG. 15 through the passivation film, gate pad and source pad.
  • FIG. 18 is a cross-sectional view showing a silicon carbide semiconductor device according to the second embodiment.
  • FIG. 18 corresponds to a cross-sectional view taken along line XVIII-XVIII in FIG. A passivation film is omitted in FIG.
  • the first region 101 is only on the Y2 side of the fourth region 104, fifth region 105 and sixth region .
  • the fifth region 105 extends to the vicinity of the gate runner 61A
  • the sixth region 106 extends to the vicinity of the gate runner 61B.
  • the entire top surface (Z1 side surface) of the gate insulating film 43 is in contact with the bottom surface (Z2 side surface) of the interlayer insulating film 44.
  • the gate electrode 51 is not provided on the Z1 side of the fifth region 105 and the sixth region 106 .
  • the same effect as the first embodiment can be obtained by the second embodiment. Moreover, according to the second embodiment, since the gate electrode 51 is not provided on the Z1 side of the fifth region 105 and the sixth region 106, the parasitic capacitance between the gate electrode 51 and the source pad 62 can be reduced.
  • FIG. 19 is a top view showing a silicon carbide semiconductor device according to the third embodiment.
  • FIG. 20 is a diagram showing respective regions in the silicon carbide substrate in the silicon carbide semiconductor device according to the third embodiment.
  • the gate pad 61 is connected to the gate runners 61A and 61C.
  • Gate pad 61 is continuous with gate runner 61A and gate runner 61C and includes the intersection of gate runner 61A and gate runner 61C.
  • Gate runner 61B is separated from gate pad 61 in the X1-X2 direction.
  • the source pad 62 is not divided into two source pads 62A and 62B, and the gate runner 61D is not provided.
  • the third region 103 has an eighth region 108 instead of the fourth region 104, the fifth region 105 and the sixth region 106.
  • the planar shape of the eighth region 108 is, for example, a rectangular shape.
  • the eighth region 108 is arranged along the side of the gate pad 61 on the side of the second side 92 and is separated from the gate runner 61B.
  • the eighth region 108 has the same configuration as the sixth region 106 in the first embodiment.
  • the first region 101 is on the Y2 side of the second region 102 and the eighth region 108 .
  • the first region 101 is provided in the X1-X2 direction from the vicinity of the gate runner 61A to the vicinity of the gate runner 61B.
  • the first region 101 is also provided between the eighth region 108 and the gate runner 61B in plan view.
  • the third embodiment the degree of freedom in arranging the gate pads 61 can be increased.
  • FIG. 21 is a diagram showing respective regions within a silicon carbide substrate in a silicon carbide semiconductor device according to a fourth embodiment.
  • the first region 101 is only on the Y2 side of the second region 102 and the eighth region .
  • the eighth region 108 extends to the vicinity of the gate runner 61B (see FIG. 19).
  • the entire upper surface of the gate insulating film 43 (the surface on the Z1 side) is in contact with the lower surface of the interlayer insulating film 44 (the surface on the Z2 side). That is, the gate electrode 51 is not provided on the Z1 side of the eighth region 108 .
  • the same effect as the third embodiment can be obtained by the fourth embodiment. Further, according to the fourth embodiment, since the gate electrode 51 is not provided on the Z1 side of the eighth region 108, the parasitic capacitance between the gate electrode 51 and the source pad 62 can be reduced.
  • FIG. 22 is a diagram showing respective regions in the silicon carbide substrate in the silicon carbide semiconductor device according to the fifth embodiment.
  • the third region 103 has a ninth region 109 in place of the eighth region 108 .
  • the ninth region 109 is arranged along the side of the gate pad 61 on the fourth side 94 side.
  • the ninth region 109 has the same configuration as the fourth region 104 in the first embodiment.
  • the first region 101 is also provided between the second region 102 and the ninth region 109 and the gate runner 61B (see FIG. 19).
  • the contact resistance can be further reduced because the third region 103 is connected to the second region 102 in a wider range than the third embodiment.
  • FIG. 23 is a diagram showing respective regions in the silicon carbide substrate in the silicon carbide semiconductor device according to the sixth embodiment.
  • the third region 103 includes the eighth region 108 in addition to the tenth region 110 and the ninth region 109 .
  • the eighth region 108 is arranged along the second side 92 side of the gate pad 61 and the ninth region 109, and is separated from the gate runner 61B as in the third embodiment.
  • the same effect as the fifth embodiment can be obtained by the sixth embodiment.
  • the third region 103 is connected to the second region 102 in a wider range than in the fifth embodiment, so the contact resistance can be further reduced.
  • FIG. 24 is a diagram showing respective regions in the silicon carbide substrate in the silicon carbide semiconductor device according to the seventh embodiment.
  • the first region 101 is located only on the Y2 side of the second region 102 and the eighth region 108 .
  • the eighth region 108 extends to the vicinity of the gate runner 61B (see FIG. 19).
  • the entire upper surface of the gate insulating film 43 (the surface on the Z1 side) is in contact with the lower surface of the interlayer insulating film 44 (the surface on the Z2 side). That is, the gate electrode 51 is not provided on the Z1 side of the eighth region 108 .
  • the same effect as the sixth embodiment can be obtained by the seventh embodiment. Further, according to the seventh embodiment, since the gate electrode 51 is not provided on the Z1 side of the eighth region 108, the parasitic capacitance between the gate electrode 51 and the source pad 62 can be reduced.
  • the entire top surface of the gate insulating film 43 (Z1 side surface) may be in contact with the bottom surface of the interlayer insulating film 44 (Z2 side surface). In this case, the parasitic capacitance between the gate electrode 51 and the source pad 62 can be further reduced.
  • FIG. 25 is a top view showing the silicon carbide semiconductor device according to the eighth embodiment.
  • FIG. 26 is a diagram showing each region in the silicon carbide substrate in the silicon carbide semiconductor device according to the eighth embodiment.
  • the gate pad 61 is separated from the gate runner 61C to the Y2 side.
  • the gate pad 61 is connected to the gate runner 61A.
  • Third region 103 includes seventh region 107 between second region 102 and gate runner 61C.
  • the third area 103 also includes a tenth area 110 and an eighth area 108 as in the fourth embodiment.
  • the eighth region 108 is also on the X1 side of the seventh region 107 .
  • the seventh area 107 has the same configuration as the ninth area 109 in the seventh embodiment.
  • FIG. 27 is a diagram showing each region in the silicon carbide substrate in the silicon carbide semiconductor device according to the ninth embodiment.
  • the third region 103 includes a ninth region 109 in addition to the tenth region 110, eighth region 108 and seventh region 107.
  • the eighth region 108 is also located on the X1 side of the ninth region 109 .
  • the same effect as the eighth embodiment can be obtained by the ninth embodiment.
  • the third region 103 is connected to the second region 102 in a wider range than the eighth embodiment, so the contact resistance can be further reduced.
  • FIG. 28 is a top view showing the silicon carbide semiconductor device according to the tenth embodiment.
  • FIG. 29 is a diagram showing respective regions in the silicon carbide substrate in the silicon carbide semiconductor device according to the tenth embodiment.
  • MOSFET 210 has gate runner 61E that connects gate runner 61C and gate pad 61 .
  • the third region 103 includes an eleventh region 111 between the second region 102 and the gate runner 61C on the X2 side of the gate runner 61E, and an eleventh region 111 between the second region 102 and the gate runner 61C on the X1 side of the gate runner 61E. and a twelfth region 112 .
  • Gate runner 61E is made of the same material as gate pad 61 .
  • the eleventh region 111 and the twelfth region 112 have the same configuration as the seventh region 107 in the eighth embodiment.
  • Gate runner 61E is an example of a fourth gate runner.
  • the eleventh area 111 and the twelfth area 112 are examples of the seventh area.
  • the tenth embodiment can also provide the same effect as the first embodiment. Further, according to the tenth embodiment, the degree of freedom in arranging the gate pads 61 can be increased.
  • FIG. 30 is a top view showing the silicon carbide semiconductor device according to the eleventh embodiment.
  • FIG. 31 is a diagram showing each region in the silicon carbide substrate in the silicon carbide semiconductor device according to the eleventh embodiment.
  • the MOSFET 211 has gate runners 61D.
  • Gate runner 61D is connected to gate runner 61C.
  • the source pad 62 includes source pads 62A and 62B.
  • the eighth region 108 is provided closer to the gate runner 61A (X2 side) than the gate runner 61D in plan view.
  • the eleventh embodiment can also provide the same effect as the eighth embodiment.
  • FIG. 32 is a top view showing a modification of the first region. Similar to FIG. 4, FIG. 32 shows the configuration of the first main surface of the silicon carbide substrate.
  • a plurality of gate trenches 5 are formed between two gate runners adjacent in the X1-X2 direction.
  • the contact region 34 is provided between the gate trenches 5 adjacent in the X1-X2 direction and extends in the Y1-Y2 direction.
  • first main surface 2 second main surface 3 side surface 4 bottom surface 5 gate trench 10 silicon carbide substrate 20 silicon carbide single crystal substrate 30 silicon carbide epitaxial layer 31 drift region 32 body region 33 source region 34 contact region 35 buried region 36 buried embedded JTE region 37 surface JTE region 41 active region 42 termination region 43 gate insulating film 44 interlayer insulating film 51 gate electrode 52 contact electrode 53 drain electrode 61 gate pad 61A, 61B, 61C, 61D, 61E gate runner 62, 62A, 62B source Pad 62C Source runner 63 Gate insulating film 71, 72, 73 Contact hole 80 Passivation film 81, 82 Opening 91 First side 92 Second side 93 Third side 94 Fourth side 101 First region 102 Second region 103 Third Region 104 4th region 105 5th region 106 6th region 107 7th region 108 8th region 109 9th region 110 10th region 111 11th region 112 12th region 121 1st semiconductor region 122 2nd semiconductor region 201 , 202

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JP2015095578A (ja) * 2013-11-13 2015-05-18 三菱電機株式会社 半導体装置及びその製造方法
JP2020520092A (ja) * 2017-05-16 2020-07-02 ゼネラル・エレクトリック・カンパニイ 半導体デバイスのレイアウトおよびその形成方法
JP2021108400A (ja) * 2019-10-07 2021-07-29 ローム株式会社 半導体装置

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JP5321377B2 (ja) * 2009-09-11 2013-10-23 三菱電機株式会社 電力用半導体装置
DE112017007186B4 (de) * 2017-03-07 2024-06-27 Mitsubishi Electric Corporation Halbleitereinheit und leistungswandler
JP7276691B2 (ja) 2020-03-18 2023-05-18 トヨタ自動車株式会社 セパレータ一体型電極の製造方法
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JP2015095578A (ja) * 2013-11-13 2015-05-18 三菱電機株式会社 半導体装置及びその製造方法
JP2020520092A (ja) * 2017-05-16 2020-07-02 ゼネラル・エレクトリック・カンパニイ 半導体デバイスのレイアウトおよびその形成方法
JP2021108400A (ja) * 2019-10-07 2021-07-29 ローム株式会社 半導体装置

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