WO2023035432A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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Publication number
WO2023035432A1
WO2023035432A1 PCT/CN2021/135640 CN2021135640W WO2023035432A1 WO 2023035432 A1 WO2023035432 A1 WO 2023035432A1 CN 2021135640 W CN2021135640 W CN 2021135640W WO 2023035432 A1 WO2023035432 A1 WO 2023035432A1
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substrate
conductive
inductance
dielectric layer
forming
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PCT/CN2021/135640
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to US18/149,182 priority Critical patent/US20230141481A1/en
Publication of WO2023035432A1 publication Critical patent/WO2023035432A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/04—Fixed inductances of the signal type  with magnetic core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • the present disclosure relates to but is not limited to a method for forming a semiconductor structure and the semiconductor structure.
  • Integrated circuit (integrated circuit, IC) packaging technology is a technology that realizes the interconnection of multiple chips through silicon vias (Through Silicon Via, TSV). Redistribution Layer (RDL) is used to realize the electrical interconnection between different chips.
  • IC integrated circuit
  • RDL Redistribution Layer
  • the existing through-silicon via technology usually integrates passive devices (Integrated Passive Device, IPD) on the semiconductor substrate.
  • IPD Integrated Passive Device
  • the integrated passive device is to integrate the resistance (Resistor), capacitance (Capacitance) and technology into a chip.
  • resistor resistor
  • Capacitance capacitance
  • the inductance generated by passive devices is difficult to meet the application requirements of integrated circuits.
  • the disclosure provides a method for forming a semiconductor structure and the semiconductor structure.
  • a first aspect of the present disclosure provides a method for forming a semiconductor structure, the method for forming the semiconductor structure comprising:
  • An initial structure includes a substrate and a dielectric layer disposed on the substrate, the dielectric layer is disposed on the first side of the substrate, the bottom surface of the dielectric layer and the substrate first side connection;
  • the conductive trench extends from the top of the dielectric layer to the second side of the substrate, the conductive trench exposes part of the dielectric layer and part of the substrate, and the a first distance between the bottom surface of the conductive trench and the second side surface of the substrate;
  • the inductance structure filling the conductive trench, wherein the projection of the inductance structure on the substrate is set to take the projection of the conductive pillar on the substrate as the inductance center, and surround the helical structure of the inductive center;
  • An inductance lead-out structure is formed, and the inductance lead-out structure covers the conductive column and the inductance structure exposed on the top surface of the dielectric layer.
  • the forming the conductive trench includes:
  • first mask layer on the top surface of the dielectric layer, the first mask layer comprising a first pattern, the first pattern exposing part of the top surface of the dielectric layer;
  • the forming the conductive hole includes:
  • the first mask layer further includes a second pattern, the second pattern exposes part of the top surface of the dielectric layer, wherein the projection of the first pattern on the substrate is set in the manner of the The projection of the second pattern on the substrate is a helix center and a helix pattern arranged around the helix center;
  • the substrate is removed according to the initial conductive hole to form the conductive hole.
  • the removing part of the substrate according to the initial conductive hole to form the conductive hole includes:
  • the shielding layer covering the conductive trench and the top surface of the dielectric layer
  • the forming the conductive hole includes:
  • a second mask layer is formed on the second side of the substrate, the second mask layer includes a third pattern, the third pattern exposes part of the second side of the substrate, and the first pattern
  • the projection on the substrate is set as a spiral pattern with the projection of the third pattern on the substrate as a spiral center and arranged around the spiral center;
  • the spiral pattern is configured to include a multi-turn annular pattern, and the plurality of turns of the annular pattern are arranged outwardly around the center of the spiral.
  • the helical structure includes a starting end close to the center of the inductance and a terminal end far away from the center of the inductance, and the helical structure surrounds the center of the inductance radially outward from the starting end An annular structure extending to said terminal end.
  • the forming the inductance lead-out structure includes:
  • the first metal pad is disposed on the top surface of the dielectric layer, and the first metal pad covers the conductive column exposed on the top surface of the dielectric layer;
  • the second metal pad is disposed on the top surface of the dielectric layer, and the second metal pad covers the exposed inductance structure on the top surface of the dielectric layer;
  • first inductance lead-out part forming a first inductance lead-out part, the first inductance lead-out part covering part of the top surface of the second metal pad;
  • a second inductance lead-out part is formed, and the second inductance lead-out part covers part of the top surface of the second metal pad.
  • the projection formed by the first inductance lead-out part on the substrate is located at the starting end of the spiral structure
  • the projection formed by the second inductance lead-out part on the substrate is located at the termination end of the spiral structure.
  • a second aspect of the present disclosure provides a semiconductor structure comprising:
  • a substrate comprising a first side and a second side
  • the dielectric layer is disposed on the first side of the substrate, and the bottom surface of the dielectric layer is connected to the first side of the substrate;
  • the conductive trench extends from the top of the dielectric layer to the second side of the substrate, the conductive trench exposes part of the dielectric layer and part of the substrate, and the conductive trench a first distance between the bottom surface of the groove and the second side surface of the substrate;
  • Conductive pillars the conductive pillars are filled with conductive holes
  • An inductance structure the inductance structure filling the conductive trench, wherein the projection of the inductance structure on the substrate is set to take the projection of the conductive pillar on the substrate as the center of inductance and surround all The helical structure of the inductor center;
  • An inductance lead-out structure covers the conductive column and the inductance structure exposed on the top surface of the dielectric layer.
  • the spiral structure includes a plurality of spiral parts sequentially connected in a clockwise direction or in a counterclockwise direction, and according to the connection sequence, the distance between the plurality of spiral parts and the center of the inductor Gradually increase.
  • the spiral structure includes a starting end close to the center of the inductor and a terminal end far away from the center of the inductor, the spiral structure surrounds the center of the inductor radially outward from the starting end and extends to the terminus.
  • the distance between the starting end of the helical structure and the center of the inductor is a first distance
  • connection sequence the distance between the plurality of spiral parts and the center of the inductor increases with a first distance step.
  • the inductance drawing structure further includes:
  • the first metal pad is disposed on the top surface of the dielectric layer, and the first metal pad covers the conductive pillar exposed on the top surface of the dielectric layer;
  • the second metal pad is disposed on the top surface of the dielectric layer, and the second metal pad covers the exposed inductance structure on the top surface of the dielectric layer;
  • first inductance lead-out part a first inductance lead-out part, the first inductance lead-out part is disposed on the second metal pad;
  • a second inductance lead-out part, the second inductance lead-out part is disposed on the second metal pad.
  • the projection formed by the first inductance lead-out part on the substrate is located at the starting end of the spiral structure
  • the projection formed by the second inductance lead-out part on the substrate is located at the termination end of the spiral structure.
  • Fig. 1 is a flowchart showing a method for forming a semiconductor structure according to an exemplary embodiment.
  • Fig. 2 is a flowchart showing a method for forming a semiconductor structure according to an exemplary embodiment.
  • Fig. 3 is a flowchart showing a method for forming a semiconductor structure according to an exemplary embodiment.
  • Fig. 4 is a flow chart of forming an inductor lead-out structure in a method for forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 5 is a schematic diagram of forming a first mask layer on an initial structure in a method for forming a semiconductor structure according to an exemplary embodiment
  • Fig. 6 is a schematic projection of a first pattern and a second pattern formed on a substrate in a method for forming a semiconductor structure according to an exemplary embodiment
  • FIG. 7 is a schematic diagram of forming a conductive trench and an initial conductive hole in a method for forming a semiconductor structure according to an exemplary embodiment
  • Fig. 8 is a schematic diagram of a shielding layer in a method for forming a semiconductor structure according to an exemplary embodiment
  • FIG. 9 is a schematic diagram of forming a conductive hole in a method for forming a semiconductor structure according to an exemplary embodiment
  • FIG. 10 is a schematic diagram of forming a first mask layer on an initial structure in a method for forming a semiconductor structure according to an exemplary embodiment
  • Fig. 11 is a schematic diagram of forming a conductive trench in a method for forming a semiconductor structure according to an exemplary embodiment
  • Fig. 12 is a schematic diagram of forming a second mask layer on the initial structure in a method for forming a semiconductor structure according to an exemplary embodiment
  • Fig. 13 is a schematic projection view of the formation of the first pattern and the third pattern formed on the substrate in a method for forming a semiconductor structure according to an exemplary embodiment
  • Fig. 14 is a schematic diagram of forming a conductive hole in a method for forming a semiconductor structure according to an exemplary embodiment
  • Fig. 15 is a schematic diagram of forming a first barrier layer and a second barrier layer in a method for forming a semiconductor structure according to an exemplary embodiment
  • Fig. 16 is a schematic diagram of forming a conductive column and an inductor structure in a method for forming a semiconductor structure according to an exemplary embodiment
  • Fig. 17 is a schematic projection of a conductive column and an inductor structure formed on a substrate in a method for forming a semiconductor structure according to an exemplary embodiment
  • Fig. 18 is a schematic diagram of forming a first metal pad and a second metal pad in a method for forming a semiconductor structure according to an exemplary embodiment
  • Fig. 19 is a schematic diagram of forming a first inductance lead-out part and a second inductance lead-out part in a method for forming a semiconductor structure according to an exemplary embodiment
  • Fig. 20 is a schematic diagram of forming a redistribution layer in a method for forming a semiconductor structure according to an exemplary embodiment.
  • 110 initial structure; 110, substrate; 120, dielectric layer; 130, isolation layer; 140, conductive trench; 150, conductive hole; 151, initial conductive hole; 160, first mask layer; 161a, first pattern ; 162a, the second pattern; 170, the shielding layer; 180, the second mask layer; 181a, the third pattern;
  • 210 conductive column; 211, first shielding layer; 212, first conductive layer; 220, inductive structure; 221, second shielding layer; 222, second conductive layer; 220a, spiral structure; 2200a, spiral part; 2201, The initial end of the helical structure; 2202, the terminal end of the helical structure;
  • Inductance lead-out structure 310. First metal pad; 320. Second metal pad; 331. First inductance lead-out part; 332. Second inductance lead-out part;
  • L1 the first distance
  • L2 the first distance
  • FIG. 1 shows a flow chart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIG. 5 - FIG. 20 is a schematic diagram of various stages of a method for forming a semiconductor structure. The method for forming a semiconductor structure will be described below in conjunction with FIGS. 5-20 .
  • This embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be described below as an example of a dynamic random access memory (DRAM). However, this embodiment is not limited to this.
  • the semiconductor structure in this embodiment can also be other structures. .
  • a method for forming a semiconductor structure includes the following steps:
  • Step S110 providing an initial structure, the initial structure includes a substrate and a dielectric layer disposed on the substrate, the dielectric layer is disposed on the first side of the substrate, and the bottom surface of the dielectric layer is connected to the first side of the substrate.
  • the substrate 110 includes a semiconductor material, and the semiconductor material layer may be any one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.
  • the substrate 110 may be a silicon-on-insulator (Silicon-On-Onsulator, SOI) substrate or a germanium-on-insulator (Germanium-on-Insulator, GOI) substrate.
  • the dielectric layer 120 may include a dielectric material.
  • the dielectric layer 120 may include silicon oxide.
  • the substrate 110 and the dielectric layer 120 may also be provided with an isolation layer 130 , and the isolation layer 130 is provided to isolate the substrate 110 from being in direct contact with the dielectric layer 120 .
  • the isolation layer 130 may include insulating materials, and the isolation layer 130 may include insulating materials such as silicon nitride and silicon oxide.
  • Step S120 forming a conductive trench, the conductive trench extends from the top of the dielectric layer to the second side of the substrate, the conductive trench exposes part of the dielectric layer and part of the substrate, and the bottom surface of the conductive trench is a distance from the second side of the substrate Side first spacing.
  • the conductive trench 140 can be formed by removing part of the dielectric layer 120 and part of the substrate 110 through dry etching or wet etching.
  • the conductive trench 140 extends from the top of the dielectric layer 120 to the second side of the substrate 110 , and the bottom of the conductive trench 140 is at a first distance L1 from the second side of the substrate 110 .
  • the thickness of the initial structure 100 is 3 ⁇ m to 10 ⁇ m
  • the thickness of the dielectric layer 120 is 0.05 ⁇ m to 0.3 ⁇ m
  • the depth of the conductive trench 140 is 1 ⁇ m to 10 ⁇ m
  • the bottom surface of the conductive trench 140 is the first distance from the second side surface of the substrate 110.
  • the distance L1 is larger than 1 ⁇ m.
  • Step S130 forming a conductive hole extending from the top surface of the dielectric layer to the second side surface of the substrate.
  • the conductive hole 150 can be formed by removing part of the dielectric layer 120 and part of the substrate 110 by etching, and the conductive hole 150 penetrates the initial structure 100 .
  • the conductive hole 150 is disposed in the middle of the conductive trench 140 and the conductive hole 150 is surrounded by the conductive trench 140 .
  • the projection of the conductive trench 140 on the substrate 110 is a spiral pattern centered on the projection of the conductive hole 150 on the substrate 110 .
  • Step S140 forming a conductive column, and the conductive column fills the conductive hole.
  • Forming the conductive column 210 includes: as shown in FIG. 15, referring to FIG. 9, an atomic layer deposition process (Atomic Layer Deposition, ALD) can be used to deposit tantalum (Ta) or tantalum compound to form a first barrier layer 211, the first barrier layer covers the conductive The sidewall of the hole 150.
  • the material of the first barrier layer 211 is tantalum (Ta).
  • conductive metal is deposited by electroplating process, the conductive metal fills the conductive hole 150 to form the first conductive layer 212 , and the first barrier layer 211 and the first conductive layer 212 form the conductive column 210 .
  • the conductive metal may be copper or copper compound.
  • Step S150 forming an inductance structure, which fills the conductive trench, and the projection of the inductance structure on the substrate is set as a spiral structure surrounding the center of the inductance with the projection of the conductive pillar on the substrate as the center of the inductance.
  • the process of forming the inductance structure 220 is roughly the same as the process of forming the conductive pillar 210, depositing tantalum or tantalum compound to form the second barrier layer 221 covering the conductive trench 140, and depositing conductive metal to fill the conductive trench 140 by electroplating process.
  • the trench 140 forms the second conductive layer 222 , and the second barrier layer 221 and the second conductive layer 222 form the inductor structure 220 .
  • the conductive metal may be copper or copper compound.
  • the projection of the inductor structure 220 on the substrate 110 in this embodiment is set as a helical structure 220 a surrounding the inductor center with the projection of the conductive pillar 210 on the substrate 110 as the center of the inductor.
  • Step S160 forming an inductor lead-out structure, the inductor lead-out structure covers the exposed conductive columns and the inductor structure on the top surface of the dielectric layer.
  • the inductance lead-out structure 300 at least includes a first inductance lead-out part 331 and a second inductance lead-out part 332 connected to the inductance structure 220, and the inductance structure 220 is drawn out through the first inductance lead-out part 331 and the second inductance lead-out part 332.
  • the portion 332 is connected to an external terminal, so that when a current passes through the conductive column 210, the inductance structure 220 is affected by the induced current and can generate inductance.
  • a winding coil with the conductive pillar as the magnetic core and the inductance structure as the winding coil surrounding the conductive pillar is formed in the semiconductor structure embedded inductive devices.
  • the conductive pillars of the semiconductor structure formed in this embodiment not only serve as through-silicon via structures for interconnection, but also serve as the magnetic core of the inductance device.
  • the current induced into the conductive posts creates inductance.
  • the semiconductor structure formed in this embodiment can generate inductance to meet the demand for inductance when energized, and no passive devices need to be integrated in the semiconductor structure, which can further reduce the size of the semiconductor structure.
  • An exemplary embodiment of the present disclosure provides a method for forming a semiconductor structure, as shown in FIG. 2 , which shows a flow chart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • a method for forming a semiconductor structure includes the following steps:
  • Step S210 providing an initial structure, the initial structure includes a substrate and a dielectric layer disposed on the substrate, the dielectric layer is disposed on the first side of the substrate, and the bottom surface of the dielectric layer is connected to the first side of the substrate.
  • Step S220 forming a first mask layer on the top surface of the dielectric layer, the first mask layer including a first pattern and a second pattern.
  • the first mask layer 160 includes a first pattern 161a and a second pattern 162a, the first pattern 161a exposes part of the top surface of the dielectric layer 120, and the second pattern 162a exposes a part of the top surface of the dielectric layer 120. noodle.
  • the projection of the first pattern 161a on the substrate 110 is set as a spiral pattern with the projection of the second pattern 162a on the substrate 110 as the center of the spiral and arranged around the center of the spiral.
  • the spiral pattern formed by the projection of the first pattern 161a is configured to include a multi-turn annular pattern, and the multi-turn annular pattern is arranged outwardly around the center of the spiral.
  • Step S230 removing part of the initial structure according to the first pattern and the second pattern to form conductive trenches and initial conductive holes.
  • the dielectric layer 120 and the substrate 110 exposed by the first pattern 161a and the second pattern 162a are removed by a dry or wet etching process, etched to a predetermined depth, and formed The conductive trench 140 and the initial conductive hole 151 .
  • the conductive trench 140 is arranged around the initial conductive hole 151 centered on the initial conductive hole 151 , and the bottom surface of the conductive trench 140 and the initial conductive hole 151 is at a first distance L1 from the second side surface of the substrate 110 .
  • Step S240 removing the substrate exposed by the initial conductive hole to form a conductive hole.
  • a shielding layer 170 is formed.
  • the shielding layer 170 covers the conductive trench 140 and the top surface of the dielectric layer 120 .
  • the material of the shielding layer 170 is photoresist. Then, the substrate 110 exposed by the initial conductive hole 151 is removed by a photolithography process to form the conductive hole 150 penetrating through the initial structure 100 .
  • Step S250 forming a conductive column, and the conductive column fills the conductive hole.
  • Step S260 forming an inductance structure, which fills the conductive trench, and the projection of the inductance structure on the substrate is set as a spiral structure surrounding the center of the inductance with the projection of the conductive pillar on the substrate as the center of the inductance.
  • Step S270 forming an inductor lead-out structure, the inductor lead-out structure covers the exposed conductive column and the inductor structure on the top surface of the dielectric layer.
  • step S210 in this embodiment is the same as the implementation of step S110 in the above-mentioned embodiment, and the implementation of steps S250-S270 is the same as that of steps S140-S160 in the above-mentioned embodiment, and will not be repeated here.
  • the inductance structure 220 is arranged around the conductive pillar 210, and the projection formed by the inductive structure 220 on the substrate 110 is set to be formed by the conductive pillar 210 on the substrate 110.
  • the projection of is the inductance center, and the helical structure 220a surrounding the inductance center.
  • the spiral structure 220a is a spiral ring structure that surrounds the center of the inductor and is away from the center of the inductor along the radial direction.
  • the spiral structure 220a formed by the projection of the inductor structure 220 on the substrate 110 includes a starting end 2201 close to the center of the inductor and a terminal end 2202 away from the center of the inductor, and the spiral structure 220a is radially outward from the starting end 2201.
  • the center of the inductor extends to the terminal end 2202 to form a spiral ring structure.
  • the inductance structure 220 surrounds the conductive column 210 for multiple turns around the outer circumference of the conductive column 210, and the inductive structure can be connected to the external terminal through the inductance lead-out structure 300.
  • the inductive structure 220 is electrically conductive Influenced by the current conducted in the column 210, an inductance is generated.
  • the projection of the first pattern on the substrate is set to take the projection of the second pattern on the substrate as a spiral
  • the spiral pattern arranged around the center of the spiral center only needs to be patterned once on the first mask layer, and both the first pattern and the second pattern are patterned on the top surface of the dielectric layer, which reduces the difficulty of patterning and has high patterning accuracy.
  • An exemplary embodiment of the present disclosure provides a method for forming a semiconductor structure, as shown in FIG. 3 , which shows a flowchart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • a method for forming a semiconductor structure includes the following steps:
  • Step S310 providing an initial structure, the initial structure includes a substrate and a dielectric layer disposed on the substrate, the dielectric layer is disposed on the first side of the substrate, and the bottom surface of the dielectric layer is connected to the first side of the substrate.
  • Step S320 forming a first mask layer on the top surface of the dielectric layer, the first mask layer including a first pattern.
  • a first mask layer 160 is formed on the initial structure 100.
  • the first mask layer 160 covers the top surface of the dielectric layer 120.
  • the first mask layer 160 includes a first pattern 161a. Referring to FIG. 13, The projection of the first pattern 161a formed on the substrate 110 is a spiral pattern.
  • Step S330 removing part of the initial structure according to the first pattern to form a conductive trench.
  • a conductive trench 140 is formed in the initial structure 100 , and the bottom surface of the conductive trench 140 is at a first distance L1 from the second side surface of the substrate.
  • the implementation manner of forming the conductive trench 140 is the same as the implementation manner of forming the conductive trench 140 in step S230 in the above embodiment.
  • Step S340 forming a second mask layer on the second side of the substrate, the second mask layer includes a third pattern, and the third pattern exposes part of the second side of the substrate.
  • a second mask layer 180 is formed, and the second mask layer 180 covers the second side surface of the substrate 100 .
  • the film layer 180 is patterned to form a third pattern 181 a on the second mask layer 180 , and the third pattern 181 a exposes part of the second side surface of the substrate 110 .
  • the projection image formed by the conductive groove 140 on the substrate 110 is acquired by illumination, and the third pattern 181a is patterned according to the projection formed by the conductive groove 140 on the substrate 110, as shown in FIG. 13 , the The projection of the third pattern 181 a formed on the substrate 110 is set as the spiral center of the projection of the conductive trench 140 formed on the substrate 110 .
  • the spiral pattern formed by the projection of the first pattern 161a on the substrate 110 is configured to include a multi-turn annular pattern, and the multi-turn annular pattern is arranged outwardly around the center of the spiral.
  • Step S350 removing the substrate and the dielectric layer exposed by the third pattern to form conductive holes.
  • the substrate 110 exposed by the third pattern 181a is etched and removed by dry etching or wet etching process, and the third pattern 181a is transferred to the dielectric layer 120,
  • the dielectric layer 120 is then etched according to the third pattern 181 a to form a conductive hole 150 penetrating through the initial structure 110 .
  • the conductive hole 150 is disposed at the center of the conductive trench 140 , and the conductive trench 140 is centered on the conductive hole 150 and spirally surrounds the conductive hole 150 in a direction away from the conductive hole 150 .
  • Step S360 forming a conductive column, and the conductive column fills the conductive hole.
  • Step S370 forming an inductance structure, which fills the conductive trench, and the projection of the inductance structure on the substrate is set as a spiral structure surrounding the center of the inductance with the projection of the conductive pillar on the substrate as the center of the inductance.
  • Step S380 forming an inductance lead-out structure, the inductance lead-out structure covers the exposed conductive column and the inductance structure on the top surface of the dielectric layer.
  • step S310 in this embodiment is the same as that of step S210 in the above-mentioned embodiment, and the implementation of steps S360-S380 is the same as that of steps S250-S270 in the above-mentioned embodiment, and will not be repeated here.
  • the first pattern is patterned on the first mask layer, and the initial structure is etched from the top of the dielectric layer to the bottom surface of the substrate according to the first pattern to form a conductive trench.
  • a second mask layer is formed on the second side, and a third pattern is patterned on the second mask layer according to the projection diagram formed by the conductive trench on the substrate, and a conductive hole is formed according to the third pattern, without forming a shielding layer to shield the conductive trench
  • the groove reduces the steps of forming and removing the shielding layer, and further simplifies the forming process of the semiconductor structure.
  • this embodiment is a further description of step S380 in the above embodiment.
  • forming the inductance lead-out structure includes:
  • Step S381 forming a first metal pad, the first metal pad is disposed on the top surface of the dielectric layer, and the first metal pad covers the exposed conductive pillars on the top surface of the dielectric layer.
  • Step S382 forming a second metal pad, the second metal pad is disposed on the top surface of the dielectric layer, and the second metal pad covers the exposed inductor structure on the top surface of the dielectric layer.
  • Steps S381 and S382 can be performed at the same time.
  • a dielectric material is deposited on the top surface of the dielectric layer 120 to form an auxiliary layer, and the auxiliary layer is patterned by a light development process and a dry etching or wet etching process to form an auxiliary pattern on the auxiliary layer.
  • the projection of the auxiliary pattern on the substrate 110 coincides with the projection of the conductive pillar 210 and the inductive structure 220 on the substrate 110, depositing conductive metal to fill the auxiliary pattern to form the first metal pad 310 and the second metal pad 320, and then The auxiliary layer is removed, as shown in FIG.
  • the first metal pad 310 covers the exposed conductive column 210 on the top surface of the dielectric layer 120
  • the second metal pad 320 covers the exposed inductor structure 220 on the top surface of the dielectric layer 120 .
  • the first metal pad 310 and the second metal pad 320 may also be formed separately.
  • Step S383 forming a first inductance lead-out portion, the first inductance lead-out portion covers part of the top surface of the second metal pad.
  • Step S384 forming a second inductance lead-out part, the second inductance lead-out part covers part of the top surface of the second metal pad.
  • Steps S383 and S384 can be performed at the same time.
  • the first inductor lead-out portion 331 and the second inductor lead-out portion 332 are formed on the top surface of the second metal pad 320 by immersion tin welding.
  • the projection of the first inductance lead-out part 331 on the substrate 110 is located at the starting end 2201 of the helical structure 220a; the projection of the second inductance lead-out part 332 on the substrate 110 is located at Terminating end 2202 of 220a.
  • the first inductance lead-out portion 331 and the second inductance lead-out portion 332 may also be formed separately.
  • the first inductance lead-out part is arranged at the end of the inductance structure closest to the conductive pillar
  • the second inductance lead-out part is arranged at the end of the inductance structure farthest from the conductive pillar
  • the first inductance lead-out structure and the second inductance lead-out The structures are arranged oppositely, and the semiconductor structure formed in this embodiment can be connected to an external terminal through the first inductance lead-out portion and the second inductance lead-out portion to form a complete inductance device.
  • the method for forming a semiconductor structure in this embodiment further includes:
  • Step S390 forming a redistribution layer, the redistribution layer is disposed on the second side of the substrate, and the redistribution layer covers the exposed conductive pillars on the second side of the substrate.
  • forming the redistribution layer 400 includes: forming an insulating layer on the second side of the substrate 110, patterning the insulating layer through an exposure process, a development process, and a dry etching or wet etching process, and forming a pattern on the insulating layer A redistribution pattern is formed, the redistribution pattern exposes part of the second side of the substrate 110, and a redistribution layer 400 is formed according to the redistribution pattern. As shown in FIG. 20 , the redistribution layer 400 covers the exposed part of the second side of the substrate 110 Conductive column 210 .
  • a redistribution layer electrically connected to the conductive column is formed on the second side of the substrate of the semiconductor structure, and the position of the interconnection contacts of the semiconductor structure is changed through the redistribution layer, so that the semiconductor structure can be applied to different packaging forms .
  • the semiconductor structure includes: a substrate 110, a dielectric layer 120 connected to the substrate 110, and a The conductive groove 140 and the conductive hole 150 in 110, the substrate 110 includes a first side and a second side, the dielectric layer 120 is arranged on the first side of the substrate 110, the bottom surface of the dielectric layer 120 and the first side of the substrate 110 Connection; the conductive trench 140 extends from the top of the dielectric layer 120 to the second side of the substrate 110, the conductive trench 140 exposes part of the dielectric layer 120 and part of the substrate 110, and the bottom surface of the conductive trench 140 is far from the bottom surface of the substrate 110
  • the second side surface has a first distance L1, and the conductive hole 150 extends from the top surface of the dielectric layer 120 to the second side surface of the substrate 110 .
  • the semiconductor structure further includes a conductive column 210 filling the conductive hole 150 , an inductor structure 220 filling the conductive trench 140 , and an inductor extraction structure 300 covering the exposed conductive column 210 and the inductor structure 220 on the top surface of the dielectric layer 120 .
  • the projection of the inductance structure 220 on the substrate 110 is set as a helical structure 220 a surrounding the center of the inductance with the projection of the conductive pillar 210 on the substrate 110 as the center of the inductance.
  • the inductance structure 220 that spirally coils the conductive column 210 is arranged around the conductive column 210, and the inductance lead-out structure 300 connected with the inductance structure 220 is also provided on the top surface of the dielectric layer 120, the conductive column 210, the inductor
  • the structure 220 and the inductance lead-out structure 300 jointly form an inductance device with the conductive pillar 210 as a magnetic core and the inductive structure 220 as a winding coil surrounding the conductive pillar 210 .
  • the conductive column 210 in the semiconductor structure of this embodiment not only serves as a TSV structure for interconnection, but also serves as the magnetic core of the inductance device.
  • a current flows through the conductive column 210 , the inductance structure 220 induces the current in the conductive column 210 to generate an inductance.
  • the semiconductor structure does not need to provide inductance by integrating passive devices, which can further reduce the size of the semiconductor structure.
  • the spiral structure 2200a is a ring structure surrounding the center of the inductor in a predetermined shape clockwise or counterclockwise.
  • the helical structure 2200a may surround the center of the inductor in a rectangular or circular manner in a clockwise or counterclockwise direction.
  • the helical structure 2200a is a ring structure with a rectangular shape surrounding the center of the inductor in a counterclockwise direction.
  • the inductance structure 220 includes a multi-turn structure surrounding the outer circumference of the conductive pillar 210 . When a current flows through the conductive pillar 210 , each turn of the inductor structure 220 around the conductive pillar 210 is equivalent to a coil around the conductive pillar 210 .
  • the inductance structure 220 and the conductive column 210 form an inductance device with the conductive column 210 as the magnetic core and the inductive structure 220 as an inductance coil surrounding the magnetic core.
  • the inductive structure 220 is affected by the induced current of the magnetic core to generate inductance.
  • the helical structure 220a is arranged to surround the center of the inductor radially outward from the start end 2201 and extend to the termination end.
  • the distance between the starting end 2201 of the spiral structure 220a and the center of the inductor is the first distance L2; according to the connection sequence, the distance between the plurality of spiral parts 220a and the center of the inductor increases stepwise by the first distance L2.
  • the first distance L2 is 0.2um ⁇ 1um.
  • the first distance L2 may be 0.3um, 0.4um, 0.5um, 0.6um, 0.7um, 0.8um or 0.9um.
  • the distance between the coils of the inductance structure 220 and the minimum distance between the inductance structure 220 and the conductive pillars 210 are set to 0.2 um to 1 um, which is smaller than the current spacing rules for TSV structures, so that the conductive pillars 210 are energized , the inductance structure 220 generates greater inductance under the influence of the current of the conductive pillar 210 .
  • most of the content of this embodiment is the same as the above-mentioned embodiment, the difference is that, as shown in FIG. 20, referring to FIG. 18 and FIG.
  • the first metal pad 310 covers the exposed conductive column 210 on the top surface of the dielectric layer 120
  • the second metal pad 320 covers the exposed inductor structure 220 on the top surface of the dielectric layer 120 .
  • the projection of the first inductance lead-out part 331 on the substrate 110 is located in the projection range of the initial end 2201 of the spiral structure 220a on the substrate 110; the second inductance lead-out part 332 is formed on the substrate The projection of is located in the projection range formed on the substrate 110 by the terminal end of the helical structure 220a.
  • the semiconductor structure provided by the embodiment of the present disclosure uses the conductive pillar 210 as the magnetic core, and spirally surrounds the inductance structure 220 arranged around the periphery of the conductive pillar.
  • the semiconductor structure does not need to integrate passive devices to provide inductance, which can further reduce the size of the semiconductor structure.
  • the inductance structure can induce the current in the conductive column to generate inductance, without integrating passive devices in the semiconductor structure, which can further reduce the semiconductor structure. size.

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Abstract

本公开公布一种半导体结构的形成方法及半导体结构，半导体结构的形成方法包括，提供初始结构，初始结构包括衬底及介质层；形成导电沟槽，导电沟槽的底面距离衬底的第二侧面第一间距；形成导电孔，导电孔自介质层的顶面延伸到衬底的第二侧面；形成导电柱，导电柱填充导电孔；形成电感结构，电感结构填充导电沟槽，电感结构在衬底上的投影被设置为以导电柱在衬底上的投影为电感中心，环绕电感中心的螺旋结构；形成电感引出结构。

Description

半导体结构的形成方法及半导体结构
本公开基于申请号为202111060919.6，申请日为2021年09月10日，申请名称为“半导体结构的形成方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的形成方法及半导体结构。
背景技术
集成电路(integrated circuit，IC)封装技术是通过硅穿孔(Through Silicon Via，TSV)实现多个芯片堆栈互联的技术，通过在多个芯片上分别形成出垂直互连的硅穿孔结构，并通过后续重布线(Redistribution Layer，简称RDL)来实现不同芯片之间的电互连。
现有的硅通孔技术通常在半导体衬底上集成无源器件(Integrated Passive Device，IPD)，集成无源器件是将电路中的电阻(Resistor)、电容(Capacitance)以及电感(Inductance)均集成到一个芯片中的技术。但是随着集成电路的集成度不断提高，集成电路尺寸减小，集成无源器件的特征尺寸随之减小，集成无源器件的尺寸减小导致集成无源器件中电感的品质因数降低，集成无源器件产生的电感难以满足集成电路的应用需求。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种半导体结构的形成方法及半导体结构。
本公开的第一方面提供一种半导体结构的形成方法，所述半导体结构的形成方法包括：
提供初始结构，所述初始结构包括衬底以及设置在所述衬底上的介质层，所述介质层设置在所述衬底的第一侧，所述介质层的底面和所述衬底的第一侧面连接；
形成导电沟槽，所述导电沟槽自所述介质层的顶面向所述衬底的第二侧面延伸，所述导电沟槽暴露出部分所述介质层以及部分所述衬底，且所述导电沟槽的底面距离所述衬底的第二侧面第一间距；
形成导电孔，所述导电孔自所述介质层的顶面延伸到所述衬底的第二侧面；
形成导电柱，所述导电柱填充所述导电孔；
形成电感结构，所述电感结构填充所述导电沟槽，其中，所述电感结构在所述衬底上的投影被设置为以所述导电柱在所述衬底上的投影为电感中心，环绕所述电感中心的螺旋结构；
形成电感引出结构，所述电感引出结构覆盖所述介质层的顶面暴露出的所述导电柱和所述电感结构。
根据本公开的一些实施例，所述形成导电沟槽，包括：
在所述介质层的顶面形成第一掩膜层，所述第一掩膜层包括第一图案，所述第一图案暴露出所述介质层的部分顶面；
去除所述第一图案暴露出的所述介质层以及部分所述衬底，形成所述导电沟槽。
根据本公开的一些实施例，所述形成导电孔，包括：
所述第一掩膜层还包括第二图案，所述第二图案暴露出所述介质层的部分顶面，其中，所述第一图案在所述衬底上的投影被设置为以所述第二图案在所述衬底上的投影为螺旋中心，并环绕所述螺旋中心设置的螺旋图案；
去除所述第二图案暴露出的所述介质层以及部分所述衬底，形成初始导电孔；
根据所述初始导电孔去除所述衬底，形成所述导电孔。
根据本公开的一些实施例，所述根据所述初始导电孔去除部分所述衬底，形成所述导电孔，包括：
形成遮挡层，所述遮挡层覆盖所述导电沟槽以及所述介质层的顶面；
去除所述初始导电孔暴露出的所述衬底，形成所述导电孔。
根据本公开的一些实施例，所述形成导电孔，包括：
在所述衬底的第二侧面形成第二掩膜层，所述第二掩膜层包括第三图案，所述第三图案暴露出所述衬底的部分第二侧面，所述第一图案在所述衬底上 的投影被设置为以所述第三图案在所述衬底上的投影为螺旋中心，并环绕所述螺旋中心设置的螺旋图案；
去除所述第三图案暴露出的所述衬底以及所述介质层，形成导电孔。
根据本公开的一些实施例，所述螺旋图案被设置为包括多圈环形图案，多圈所述环形图案环绕所述螺旋中心依次向外设置。
根据本公开的一些实施例，所述螺旋结构包括靠近所述电感中心的起始端和远离所述电感中心的终止端，所述螺旋结构为自所述起始端径向向外环绕所述电感中心延伸至所述终止端形成的环形结构。
根据本公开的一些实施例，所述形成电感引出结构包括：
形成第一金属焊盘，所述第一金属焊盘设置在所述介质层的顶面，所述第一金属焊盘覆盖所述介质层的顶面暴露出的所述导电柱；
形成第二金属焊盘，所述第二金属焊盘设置在所述介质层的顶面，所述第二金属焊盘覆盖所述介质层的顶面暴露出的所述电感结构；
形成第一电感引出部，所述第一电感引出部覆盖所述第二金属焊盘的部分顶面；
形成第二电感引出部，所述第二电感引出部覆盖所述第二金属焊盘的部分顶面。
根据本公开的一些实施例，所述第一电感引出部在所述衬底上形成的投影位于所述螺旋结构的起始端；
所述第二电感引出部在所述衬底上形成的投影位于所述螺旋结构的终止端。
本公开的第二方面提供了一种半导体结构，所述半导体结构包括：
衬底，所述衬底包括第一侧和第二侧；
介质层，所述介质层设置在所述衬底的第一侧，所述介质层的底面和所述衬底的第一侧面连接；
导电沟槽，所述导电沟槽自所述介质层的顶面向所述衬底的第二侧面延伸，所述导电沟槽暴露出部分所述介质层以及部分所述衬底，且所述导电沟槽的底面距离所述衬底的第二侧面第一间距；
导电孔，所述导电孔自所述介质层的顶面延伸到所述衬底的第二侧面；
导电柱，所述导电柱填充导电孔；
电感结构，所述电感结构填充所述导电沟槽，其中，所述电感结构在所述衬底上的投影被设置为以所述导电柱在所述衬底上的投影为电感中心，环绕所述电感中心的螺旋结构；
电感引出结构，所述电感引出结构覆盖所述介质层的顶面暴露出的所述导电柱和所述电感结构。
根据本公开的一些实施例，所述螺旋结构包括沿着顺时针方向或沿着逆时针方向依次连接的多个螺旋部，且按照连接顺序，多个所述螺旋部距离所述电感中心的间距逐渐增大。
根据本公开的一些实施例，所述螺旋结构包括靠近所述电感中心的起始端和远离所述电感中心的终止端，所述螺旋结构自所述起始端径向向外环绕所述电感中心并延伸至所述终止端。
根据本公开的一些实施例，所述螺旋结构的起始端距离所述电感中心的间距为第一距离；
按照连接顺序，多个所述螺旋部距离所述电感中心的间距以第一距离阶梯递增。
根据本公开的一些实施例，所述电感引出结构还包括：
第一金属焊盘，所述第一金属焊盘设置在所述介质层的顶面，所述第一金属焊盘覆盖所述介质层的顶面暴露出的所述导电柱；
第二金属焊盘，所述第二金属焊盘设置在所述介质层的顶面，所述第二金属焊盘覆盖所述介质层的顶面暴露出的所述电感结构；
第一电感引出部，所述第一电感引出部设置在所述第二金属焊盘上；
第二电感引出部，所述第二电感引出部设置在所述第二金属焊盘上。
根据本公开的一些实施例，所述第一电感引出部在所述衬底上形成的投影位于所述螺旋结构的起始端；
所述第二电感引出部在所述衬底上形成的投影位于所述螺旋结构的终止端。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施 例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的一种半导体结构的形成方法的流程图。
图2是根据一示例性实施例示出的一种半导体结构的形成方法的流程图。
图3是根据一示例性实施例示出的一种半导体结构的形成方法的流程图。
图4是根据一示例性实施例示出的一种半导体结构的形成方法中形成电感引出结构的流程图。
图5是根据一示例性实施例示出的一种半导体结构的形成方法中在初始结构上形成第一掩膜层的示意图；
图6是根据一示例性实施例示出的一种半导体结构的形成方法中形成的第一图案和第二图案在衬底上形成的投影示意图；
图7是根据一示例性实施例示出的一种半导体结构的形成方法中形成导电沟槽和初始导电孔的示意图；
图8是根据一示例性实施例示出的一种半导体结构的形成方法中遮挡层的示意图；
图9是根据一示例性实施例示出的一种半导体结构的形成方法中形成导电孔的示意图；
图10是根据一示例性实施例示出的一种半导体结构的形成方法中在初始结构上形成第一掩膜层的示意图；
图11是根据一示例性实施例示出的一种半导体结构的形成方法中形成导电沟槽的示意图；
图12是根据一示例性实施例示出的一种半导体结构的形成方法中在初始结构上形成第二掩膜层的示意图；
图13是根据一示例性实施例示出的一种半导体结构的形成方法中形成的第一图案和第三图案在衬底上形成的投影示意图；
图14是根据一示例性实施例示出的一种半导体结构的形成方法中形成导电孔的示意图；
图15是根据一示例性实施例示出的一种半导体结构的形成方法中形成第一阻挡层和第二阻挡层的示意图；
图16是根据一示例性实施例示出的一种半导体结构的形成方法中形成导电柱和电感结构的示意图；
图17是根据一示例性实施例示出的一种半导体结构的形成方法中导电柱和电感结构在衬底上形成的投影示意图；
图18是根据一示例性实施例示出的一种半导体结构的形成方法中形成第一金属焊盘和第二金属焊盘的示意图；
图19是根据一示例性实施例示出的一种半导体结构的形成方法中形成第一电感引出部和第二电感引出部的示意图；
图20是根据一示例性实施例示出的一种半导体结构的形成方法中形成再分布层的示意图。
附图标记：
110、初始结构；110、衬底；120、介质层；130、隔离层；140、导电沟槽；150、导电孔；151、初始导电孔；160、第一掩膜层；161a、第一图案；162a、第二图案；170、遮挡层；180、第二掩膜层；181a、第三图案；
210、导电柱；211、第一遮挡层；212、第一导电层；220、电感结构；221、第二遮挡层；222、第二导电层；220a、螺旋结构；2200a、螺旋部；2201、螺旋结构的起始端；2202、螺旋结构的终止端；
300、电感引出结构；310、第一金属焊盘；320、第二金属焊盘；331、第一电感引出部；332、第二电感引出部；
400、再分布层；
L1、第一间距；L2、第一距离。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显 然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开示例性的实施例中提供一种半导体结构的形成方法，如图1所示，图1示出了根据本公开一示例性的实施例提供的半导体结构的形成方法的流程图，图5-图20为半导体结构的形成方法的各个阶段的示意图，下面结合图5-图20对半导体结构的形成方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图1所示，本公开一示例性的实施例提供的一种半导体结构的形成方法，包括如下的步骤：
步骤S110：提供初始结构，初始结构包括衬底以及设置在衬底上的介质层，介质层设置在衬底的第一侧，介质层的底面和衬底的第一侧面连接。
如图5所示，衬底110包括半导体材料，半导体材料层可以为硅、锗、硅锗化合物以及硅碳化合物中的任意一种或者多种。衬底110可以是绝缘体上硅(Silicon-On-Onsulator，SOI)衬底或绝缘体上锗(Germanium-on-Insulator，GOI)衬底。
介质层120可以包括介电材料。介质层120可以包括氧化硅。
在本实施例中，衬底110和介质层120还可以设置隔离层130，隔离层130设置为隔离衬底110和介质层120直接接触。隔离层130可以包括绝缘材料，隔离层130可以包括氮化硅、氧化硅等绝缘材料。
步骤S120：形成导电沟槽，导电沟槽自介质层的顶面向衬底的第二侧面延伸，导电沟槽暴露出部分介质层以及部分衬底，且导电沟槽的底面距离衬底的第二侧面第一间距。
如图7所示，参照图5，导电沟槽140可以通过干法刻蚀或湿法刻蚀工艺刻蚀去除部分部分介质层120和部分衬底110形成。导电沟槽140自介质层120的顶面向衬底110的第二侧面延伸，且导电沟槽140的底面距离衬底110的第二侧面第一间距L1。
初始结构100的厚度为3μm～10μm，介质层120的厚度为0.05μm～0.3μm，导电沟槽140的深度为1μm～10μm，导电沟槽140的底面距离衬底110的第二侧面的第一间距L1大于1μm。
步骤S130：形成导电孔，导电孔自介质层的顶面延伸到衬底的第二侧面。
如图9所示，参照图7，导电孔150可以通过刻蚀去除部分介质层120和部分衬底110形成，导电孔150贯穿初始结构100。在本实施例中，导电孔150设置在导电沟槽140中间且导电孔150被导电沟槽140环绕。导电沟槽140在衬底110上形成的投影为以导电孔150在衬底110上形成的投影为中心的螺旋图案。
步骤S140：形成导电柱，导电柱填充导电孔。
形成导电柱210包括：如图15所示，参照图9，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积钽(Ta)或钽化物形成第一阻挡层211，第一阻挡层覆盖导电孔150的侧壁。在本实施例中，第一阻挡层211的材料为钽(Ta)。如图16所示，参照图15，通过电镀工艺沉积导电金属，导电金属填充导电孔150形成第一导电层212，第一阻挡层211和第一导电层212形成导电柱210。在本实施例中，导电金属可以为铜或铜化物。
步骤S150：形成电感结构，电感结构填充导电沟槽，电感结构在衬底上的投影被设置为以导电柱在衬底上的投影为电感中心，环绕电感中心的螺旋结构。
如图15、图16所示，形成电感结构220的过程和形成导电柱210的过程大致相同，沉积钽或钽化物形成第二阻挡层221覆盖导电沟槽140，通过电镀工艺沉积导电金属填充导电沟槽140形成第二导电层222，第二阻挡层221和第二导电层222形成电感结构220。在本实施例中，导电金属可以为铜或铜化物。如图17所示，本实施例中的电感结构220在衬底110上的投影被设置为以导电柱210在衬底110上的投影为电感中心，环绕电感中心的螺旋结构220a。
步骤S160：形成电感引出结构，电感引出结构覆盖介质层的顶面暴露出的导电柱和电感结构。
参照图18、图19所示，电感引出结构300至少包括与电感结构220连接的第一电感引出部331和第二电感引出部332，电感结构220通过第一电 感引出部331和第二电感引出部332与外接端子连接，以使导电柱210中有电流通过时，电感结构220收到感应电流影响能够产生电感。
本实施例的半导体结构的形成方法，通过形成环绕导电柱的电感结构以及与电感结构连接的电感引出结构，在半导体结构中形成了以导电柱作为磁芯、电感结构作为环绕导电柱的绕组线圈的嵌入式的电感器件。本实施例形成的半导体结构的导电柱不仅作为用于互连的硅穿孔结构，还作为电感器件的磁芯，在导电柱与其它互联结构形成电连接时，导电柱中有电流通过，电感结构感应到导电柱中的电流产生电感。本实施例形成的半导体结构在通电时可产生电感满足对电感的需求，无需在半导体结构中集成无源器件，可以进一步减小半导体结构的尺寸。
本公开示例性的实施例中提供一种半导体结构的形成方法，如图2所示，图2示出了根据本公开一示例性的实施例提供的半导体结构的形成方法的流程图。
如图2所示，本公开一示例性的实施例提供的一种半导体结构的形成方法，包括如下的步骤：
步骤S210：提供初始结构，初始结构包括衬底以及设置在衬底上的介质层，介质层设置在衬底的第一侧，介质层的底面和衬底的第一侧面连接。
步骤S220：在介质层的顶面形成第一掩膜层，第一掩膜层包括第一图案和第二图案。
如图5所示，第一掩膜层160同时包括第一图案161a和第二图案162a，第一图案161a暴露出介质层120的部分顶面，第二图案162a暴露出介质层120的部分顶面。如图6所示，第一图案161a在衬底110上的投影被设置为以第二图案162a在衬底110上的投影为螺旋中心，并环绕螺旋中心设置的螺旋图案。在本实施例中，第一图案161a投影形成的螺旋图案被设置为包括多圈环形图案，多圈环形图案环绕螺旋中心依次向外设置。
步骤S230：根据第一图案和第二图案去除部分初始结构形成导电沟槽和初始导电孔。
如图7所示，参照图5、图6，通过干法或湿法刻蚀工艺去除第一图案161a和第二图案162a暴露出的介质层120和衬底110，刻蚀到预定深度，形成导电沟槽140和初始导电孔151。导电沟槽140以初始导电孔151为中心 环绕初始导电孔151设置，导电沟槽140和初始导电孔151的底面距离衬底110的第二侧面第一间距L1。
步骤S240：去除初始导电孔暴露出的衬底，形成导电孔。
如图8所示，参照图7，形成遮挡层170，遮挡层170覆盖导电沟槽140以及介质层120的顶面，在本实施例中，遮挡层170的材料为光刻抗试剂。然后，通过光刻工艺去除初始导电孔151暴露出的衬底110，形成贯穿初始结构100的导电孔150。
步骤S250：形成导电柱，导电柱填充导电孔。
步骤S260：形成电感结构，电感结构填充导电沟槽，电感结构在衬底上的投影被设置为以导电柱在衬底上的投影为电感中心，环绕电感中心的螺旋结构。
步骤S270：形成电感引出结构，电感引出结构覆盖介质层的顶面暴露出的导电柱和电感结构。
本实施例中步骤S210的形成方法和上述实施例中步骤S110的实现方式相同，步骤S250-S270和上述实施例步骤S140-S160的实现方式相同，在此，不再赘述。
本实施例形成的半导体结构，如图16所示，参照图17，电感结构220环绕导电柱210设置，电感结构220在衬底110上形成的投影被设置为以导电柱210在衬底110上的投影为电感中心，环绕电感中心的螺旋结构220a。本实施例中，螺旋结构220a为环绕电感中心并沿着径向方向远离电感中心的螺旋环状结构。
如图17所示，电感结构220在衬底110上投影形成的螺旋结构220a包括靠近电感中心的起始端2201和远离电感中心的终止端2202，螺旋结构220a为自起始端2201径向向外环绕电感中心延伸至终止端2202形成的螺旋环形结构。如图18所示，参照图19，电感结构220在导电柱210外周环绕导电柱210多圈，电感结构可通过电感引出结构300与外接端子连接，在导电柱210通电时，电感结构220受到导电柱210中导通的电流影响，产生电感。
本实施例在形成半导体结构时，通过在第一掩膜层上构图第一图案和第二图案，将第一图案在衬底上的投影设置为以第二图案在衬底上的投影为螺旋中心，并环绕螺旋中心设置的螺旋图案，只需要在第一掩膜层上构图一次， 而且第一图案和第二图案均在介质层的顶面构图，减小了构图难度，构图精度高。
本公开示例性的实施例中提供一种半导体结构的形成方法，如图3所示，图3示出了根据本公开一示例性的实施例提供的半导体结构的形成方法的流程图。
如图3所示，本公开一示例性的实施例提供的一种半导体结构的形成方法，包括如下的步骤：
步骤S310：提供初始结构，初始结构包括衬底以及设置在衬底上的介质层，介质层设置在衬底的第一侧，介质层的底面和衬底的第一侧面连接。
步骤S320：在介质层的顶面形成第一掩膜层，第一掩膜层包括第一图案。
如图10所示，在初始结构100上形成第一掩膜层160，第一掩膜层160覆盖在介质层120的顶面，第一掩膜层160包括第一图案161a，参照图13，第一图案161a在衬底110上形成的投影为螺旋图案。
步骤S330：根据第一图案去除部分初始结构形成导电沟槽。
如图11所示，参照图10，在初始结构100中形成导电沟槽140，导电沟槽140的底面距离衬底的第二侧面第一间距L1。形成导电沟槽140的实施方式和上述实施例中步骤S230中形成导电沟槽140的实施方式相同。
步骤S340：在衬底的第二侧面形成第二掩膜层，第二掩膜层包括第三图案，第三图案暴露出部分衬底的第二侧面。
如图12所示，参照图11，形成第二掩膜层180，第二掩膜层180覆盖衬底100的第二侧面，根据导电沟槽140在衬底110上形成的投影对第二掩膜层180进行构图，在第二掩膜层180上形成第三图案181a，第三图案181a暴露出衬底110的部分第二侧面。在本实施例中，通过光照获取导电沟槽140在衬底110上形成的投影图，根据导电沟槽140在衬底110上形成的投影对第三图案181a构图，如图13所示，将第三图案181a在衬底110上形成的投影设置为导电沟槽140在衬底110上形成的投影的螺旋中心。如图13所示，第一图案161a在衬底110上投影形成的螺旋图案被设置为包括多圈环形图案，多圈环形图案环绕螺旋中心依次向外设置。
步骤S350：去除第三图案暴露出的衬底以及介质层，形成导电孔。
如图14所示，参照图12、图13，通过干法刻蚀或湿法刻蚀工艺刻蚀去 除第三图案181a暴露出的衬底110，将第三图案181a转移到介质层120上，再根据第三图案181a刻蚀介质层120，形成贯穿初始结构110的导电孔150。导电孔150设置在导电沟槽140的中心位置，导电沟槽140以导电孔150为中心并向远离导电孔150的方向螺旋环绕导电孔150。
步骤S360：形成导电柱，导电柱填充导电孔。
步骤S370：形成电感结构，电感结构填充导电沟槽，电感结构在衬底上的投影被设置为以导电柱在衬底上的投影为电感中心，环绕电感中心的螺旋结构。
步骤S380：形成电感引出结构，电感引出结构覆盖介质层的顶面暴露出的导电柱和电感结构。
本实施例中步骤S310的形成方法和上述实施例中步骤S210的实现方式相同，步骤S360-S380和上述实施例步骤S250-S270的实现方式相同，在此，不再赘述。
本实施例在形成半导体结构时，通过在第一掩膜层上构图第一图案，根据第一图案自介质层的顶面向衬底的底面刻蚀初始结构形成导电沟槽，然后在衬底的第二侧面形成第二掩膜层，根据导电沟槽在衬底上形成的投影图在在第二掩膜层上构图第三图案，根据第三图案形成导电孔，无需形成遮挡层遮挡导电沟槽，减少了遮挡层的形成和去除的步骤，进一步简化半导体结构的形成工艺。
根据本公开一个示例性的实施例，本实施例是对上述实施例中步骤S380的进一步说明。
如图4所示，形成电感引出结构包括：
步骤S381：形成第一金属焊盘，第一金属焊盘设置在介质层的顶面，第一金属焊盘覆盖介质层的顶面暴露出的导电柱。
步骤S382：形成第二金属焊盘，第二金属焊盘设置在介质层的顶面，第二金属焊盘覆盖介质层的顶面暴露出的电感结构。
步骤S381、S382可以同时进行，在介质层120顶面沉积介电材料形成辅助层，通过光照显影工艺以及干法刻蚀或湿法刻蚀工艺对辅助层进行构图，在辅助层上形成辅助图案。辅助图案在衬底110上形成的投影与导电柱210和电感结构220在衬底110上形成的投影重合，沉积导电金属填充辅助图案 形成第一金属焊盘310和第二金属焊盘320，然后去除辅助层，如图18所示，第一金属焊盘310覆盖介质层120的顶面暴露出的导电柱210，第二金属焊盘320覆盖介质层120的顶面暴露出的电感结构220。在本公开其它实施例中，第一金属焊盘310和第二金属焊盘320也可以分别形成。
步骤S383：形成第一电感引出部，第一电感引出部覆盖第二金属焊盘的部分顶面。
步骤S384：形成第二电感引出部，第二电感引出部覆盖第二金属焊盘的部分顶面。
步骤S383、S384可以同时进行，如图19所示，通过浸锡焊接在第二金属焊盘320的顶面形成第一电感引出部331和第二电感引出部332。在本实施例中，参照图17，第一电感引出部331在衬底110上形成的投影位于螺旋结构220a的起始端2201；第二电感引出部332在衬底110上形成的投影位于螺旋结构220a的终止端2202。在本公开其它实施例中，第一电感引出部331和第二电感引出部332也可以分别形成。
本实施例的形成方法，第一电感引出部设置在电感结构距离导电柱最近的一端，第二电感引出部设置在电感结构距离导电柱最远的一端，第一电感引出结构和第二电感引出结构相对设置，本实施例形成的半导体结构可以通过第一电感引出部和第二电感引出部与外接端子连接，形成完整的电感器件。
根据本公开一个示例性的实施例，本实施例的大部分内容和上述实施例相同，区别之处在于，如图3所示，本实施例中半导体结构的形成方法还包括：
步骤S390：形成再分布层，再分布层设置在衬底的第二侧，再分布层覆盖衬底的第二侧面暴露出的导电柱。
在本实施例中，形成再分布层400包括：在衬底110的第二侧形成绝缘层，通过曝光工艺和显影工艺以及干法刻蚀或湿法刻蚀工艺对绝缘层构图，在绝缘层中形成再分布图案，再分布图案暴露衬底110的部分第二侧面，根据再分布图案形成再分布层400，如图20所示，再分布层400覆盖衬底110的第二侧面暴露出的导电柱210。
本实施例中，在半导体结构的衬底的第二侧形成与导电柱电性连接的再分布层，通过再分布层改变半导体结构的互联触点位置，使半导体结构能适 用于不同的封装形式。
本公开示例性的实施例中提供一种半导体结构，如图20所示，参照图14，半导体结构包括：衬底110、和衬底110连接的介质层120、设置在介质层120和衬底110中的导电沟槽140以及导电孔150，衬底110包括第一侧和第二侧，介质层120设置在衬底110的第一侧，介质层120的底面和衬底110的第一侧面连接；导电沟槽140自介质层120的顶面向衬底110的第二侧面延伸，导电沟槽140暴露出部分介质层120以及部分衬底110，且导电沟槽140的底面距离衬底110的第二侧面第一间距L1，导电孔150自介质层120的顶面延伸到衬底110的第二侧面。半导体结构还包括填充导电孔150的导电柱210、填充导电沟槽140的电感结构220以及覆盖介质层120的顶面暴露出的导电柱210和电感结构220的电感引出结构300。如图17所示，电感结构220在衬底110上的投影被设置为以导电柱210在衬底110上的投影为电感中心，环绕电感中心的螺旋结构220a。
本实施例的半导体结构，在导电柱210周围设置螺旋式盘绕导电柱210的电感结构220，并且还在介质层120的顶面设置与电感结构220连接的电感引出结构300，导电柱210、电感结构220和电感引出结构300共同形成了以导电柱210作为磁芯、以电感结构220作为环绕导电柱210的绕组线圈的电感器件。
本实施例的半导体结构中的导电柱210不仅作为用于互连的硅穿孔结构，还作为电感器件的磁芯，在导电柱210与其它互联结构形成电连接时，导电柱210中有电流通过，电感结构220感应到导电柱210中的电流产生电感。本实施例半导体结构无需通过集成无源器件的方式提供电感，可以进一步减小半导体结构的尺寸。
根据本公开一个示例性的实施例，本实施例的大部分内容和上述实施例相同，区别之处在于，如图17所示，螺旋结构220a包括沿着顺时针方向或沿着逆时针方向依次连接的多个螺旋部2200a，且按照连接顺序，多个螺旋部2200a距离电感中心的间距逐渐增大。
螺旋结构2200a是沿着顺时针或逆时针以预定形状环绕电感中心的环形结构。螺旋结构2200a可以沿着顺时针或逆时针方向矩形环绕或圆形环绕电感中心。在本实施例中，螺旋结构2200a是沿着逆时针方向矩形环绕电感中 心的环形结构。电感结构220包括环绕导电柱210外周的多圈结构，在导电柱210中有电流通过时，电感结构220环绕导电柱210的每一圈相当于环绕导电柱210的一圈线圈。电感结构220和导电柱210形成了以导电柱210为磁芯，电感结构220作为环绕磁芯的电感线圈的电感器件，电感结构220受到磁芯的感应电流的影响产生电感。
根据本公开一个示例性的实施例，本实施例的大部分内容和上述实施例相同，区别之处在于，如图17所示，螺旋结构220a包括靠近电感中心的起始端2201和远离电感中心的终止端2202，螺旋结构220a被设置为自起始端2201径向向外环绕电感中心并延伸至终止端。
在本实施例中，螺旋结构220a的起始端2201距离电感中心的间距为第一距离L2；按照连接顺序，多个螺旋部220a距离电感中心的间距以第一距离L2阶梯递增。
在本实施例中，第一距离L2为0.2um～1um。第一距离L2可以为0.3um、0.4um、0.5um、0.6um、0.7um、0.8um或0.9um。
本实施例中，将电感结构220的线圈之间的间距以及电感结构220和导电柱210的最小距离设置为0.2um～1um，小于当前对硅穿孔结构设计的间距规则，以使导电柱210通电时，电感结构220在导电柱210的电流影响下产生电感更大。
根据本公开一个示例性的实施例，本实施例的大部分内容和上述实施例相同，区别之处在于，如图20所示，参照图18、图19，电感引出结构300包括：设置在介质层120的顶面的第一金属焊盘310和第二金属焊盘320，以及设置在第二金属焊盘320上的第一电感引出部331和第二电感引出部332。第一金属焊盘310覆盖介质层120的顶面暴露出的导电柱210，第二金属焊盘320覆盖介质层120的顶面暴露出的电感结构220。
在本实施例中，第一电感引出部331在衬底110上形成的投影位于螺旋结构220a的起始端2201在衬底110上形成的投影范围中；第二电感引出部332在衬底上形成的投影位于螺旋结构220a的终止端在衬底110上形成的投影范围中。
本公开实施例提供的半导体结构，利用导电柱210作为磁芯，螺旋环绕导电柱外周设置的电感结构220，导电柱210通电时电感结构220受到导电 柱210中电流感应可以产生电感，实施例的半导体结构无需集成无源器件提供电感，可以进一步减小半导体结构的尺寸。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使 相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开通过形成环绕导电柱的电感结构，在导电柱中有电流通过时，电感结构感应到导电柱中的电流能够产生电感，无需在半导体结构中集成无源器件，可以进一步减小半导体结构的尺寸。

Claims (15)

  1. 一种半导体结构的形成方法，所述半导体结构的形成方法包括：
    提供初始结构，所述初始结构包括衬底以及设置在所述衬底上的介质层，所述介质层设置在所述衬底的第一侧，所述介质层的底面和所述衬底的第一侧面连接；
    形成导电沟槽，所述导电沟槽自所述介质层的顶面向所述衬底的第二侧面延伸，所述导电沟槽暴露出部分所述介质层以及部分所述衬底，且所述导电沟槽的底面距离所述衬底的第二侧面第一间距；
    形成导电孔，所述导电孔自所述介质层的顶面延伸到所述衬底的第二侧面；
    形成导电柱，所述导电柱填充所述导电孔；
    形成电感结构，所述电感结构填充所述导电沟槽，其中，所述电感结构在所述衬底上的投影被设置为以所述导电柱在所述衬底上的投影为电感中心，环绕所述电感中心的螺旋结构；
    形成电感引出结构，所述电感引出结构覆盖所述介质层的顶面暴露出的所述导电柱和所述电感结构。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，所述形成导电沟槽，包括：
    在所述介质层的顶面形成第一掩膜层，所述第一掩膜层包括第一图案，所述第一图案暴露出所述介质层的部分顶面；
    去除所述第一图案暴露出的所述介质层以及部分所述衬底，形成所述导电沟槽。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，所述形成导电孔，包括：
    所述第一掩膜层还包括第二图案，所述第二图案暴露出所述介质层的部分顶面，其中，所述第一图案在所述衬底上的投影被设置为以所述第二图案在所述衬底上的投影为螺旋中心，并环绕所述螺旋中心设置的螺旋图案；
    去除所述第二图案暴露出的所述介质层以及部分所述衬底，形成初始导电孔；
    根据所述初始导电孔去除所述衬底，形成所述导电孔。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，所述根据所述初始导电孔去除部分所述衬底，形成所述导电孔，包括：
    形成遮挡层，所述遮挡层覆盖所述导电沟槽以及所述介质层的顶面；
    去除所述初始导电孔暴露出的所述衬底，形成所述导电孔。
  5. 根据权利要求2所述的半导体结构的形成方法，其中，所述形成导电孔，包括：
    在所述衬底的第二侧面形成第二掩膜层，所述第二掩膜层包括第三图案，所述第三图案暴露出所述衬底的部分第二侧面，所述第一图案在所述衬底上的投影被设置为以所述第三图案在所述衬底上的投影为螺旋中心，并环绕所述螺旋中心设置的螺旋图案；
    去除所述第三图案暴露出的所述衬底以及所述介质层，形成导电孔。
  6. 根据权利要求4或5所述的半导体结构的形成方法，其中，所述螺旋图案被设置为包括多圈环形图案，多圈所述环形图案环绕所述螺旋中心依次向外设置。
  7. 根据权利要求1所述的半导体结构的形成方法，其中，所述螺旋结构包括靠近所述电感中心的起始端和远离所述电感中心的终止端，所述螺旋结构为自所述起始端径向向外环绕所述电感中心延伸至所述终止端形成的环形结构。
  8. 根据权利要求7所述的半导体结构的形成方法，其中，所述形成电感引出结构包括：
    形成第一金属焊盘，所述第一金属焊盘设置在所述介质层的顶面，所述第一金属焊盘覆盖所述介质层的顶面暴露出的所述导电柱；
    形成第二金属焊盘，所述第二金属焊盘设置在所述介质层的顶面，所述第二金属焊盘覆盖所述介质层的顶面暴露出的所述电感结构；
    形成第一电感引出部，所述第一电感引出部覆盖所述第二金属焊盘的部 分顶面；
    形成第二电感引出部，所述第二电感引出部覆盖所述第二金属焊盘的部分顶面。
  9. 根据权利要求8所述的半导体结构的形成方法，其中，所述第一电感引出部在所述衬底上形成的投影位于所述螺旋结构的起始端；
    所述第二电感引出部在所述衬底上形成的投影位于所述螺旋结构的终止端。
  10. 一种半导体结构，所述半导体结构包括：
    衬底，所述衬底包括第一侧和第二侧；
    介质层，所述介质层设置在所述衬底的第一侧，所述介质层的底面和所述衬底的第一侧面连接；
    导电沟槽，所述导电沟槽自所述介质层的顶面向所述衬底的第二侧面延伸，所述导电沟槽暴露出部分所述介质层以及部分所述衬底，且所述导电沟槽的底面距离所述衬底的第二侧面第一间距；
    导电孔，所述导电孔自所述介质层的顶面延伸到所述衬底的第二侧面；
    导电柱，所述导电柱填充导电孔；
    电感结构，所述电感结构填充所述导电沟槽，其中，所述电感结构在所述衬底上的投影被设置为以所述导电柱在所述衬底上的投影为电感中心，环绕所述电感中心的螺旋结构；
    电感引出结构，所述电感引出结构覆盖所述介质层的顶面暴露出的所述导电柱和所述电感结构。
  11. 根据权利要求10所述的半导体结构，其中，所述螺旋结构包括沿着顺时针方向或沿着逆时针方向依次连接的多个螺旋部，且按照连接顺序，多个所述螺旋部距离所述电感中心的间距逐渐增大。
  12. 根据权利要求11所述的半导体结构，其中，所述螺旋结构包括靠近所述电感中心的起始端和远离所述电感中心的终止端，所述螺旋结构自所述起始端径向向外环绕所述电感中心并延伸至所述终止端。
  13. 根据权利要求12所述的半导体结构，其中，所述螺旋结构的起始端 距离所述电感中心的间距为第一距离；
    按照连接顺序，多个所述螺旋部距离所述电感中心的间距以第一距离阶梯递增。
  14. 根据权利要求12所述的半导体结构，其中，所述电感引出结构包括：
    第一金属焊盘，所述第一金属焊盘设置在所述介质层的顶面，所述第一金属焊盘覆盖所述介质层的顶面暴露出的所述导电柱；
    第二金属焊盘，所述第二金属焊盘设置在所述介质层的顶面，所述第二金属焊盘覆盖所述介质层的顶面暴露出的所述电感结构；
    第一电感引出部，所述第一电感引出部设置在所述第二金属焊盘上；
    第二电感引出部，所述第二电感引出部设置在所述第二金属焊盘上。
  15. 根据权利要求14所述的半导体结构，其中，所述第一电感引出部在所述衬底上形成的投影位于所述螺旋结构的起始端；
    所述第二电感引出部在所述衬底上形成的投影位于所述螺旋结构的终止端。
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US20150255529A1 (en) * 2014-03-07 2015-09-10 International Business Machines Corporation Silicon process compatible trench magnetic device
CN112151496A (zh) * 2020-09-10 2020-12-29 复旦大学 一种内嵌电感的tsv结构及其制备方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1420716A (zh) * 2001-10-10 2003-05-28 St微电子公司 单片电路中电感和通孔的形成方法
US20150255529A1 (en) * 2014-03-07 2015-09-10 International Business Machines Corporation Silicon process compatible trench magnetic device
CN112151496A (zh) * 2020-09-10 2020-12-29 复旦大学 一种内嵌电感的tsv结构及其制备方法

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